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L-Edit Dev-Gen

Device Layout Generator

Tanner EDA Division Tanner Research, Inc. 825 South Myrtle Avenue Monrovia, CA 91016-3424 USA: (626) 471-9700

version 14

copyright 2009

TABLE OF CONTENTS
Section 1 Introduction .............................................................................. 4 Section 1.1 Running Dev-Gen ........................................................... 4 Section 2 Device Setup............................................................................. 4 Section 2.1 Using the Setup Dialogs.................................................. 5 Section 2.2 Importing and Exporting Device Settings ........................ 6 Section 2.3 Device Setup Wizards ..................................................... 7 Section 2.4 Modifying Device Parameters ......................................... 8 Section 2.5 Cell Info Placement Wizard ............................................. 8 Section 3 Capacitors................................................................................. 9

Section 4 Inductors................................................................................. 12 Section 4.1 Square Layout............................................................... 13 Section 4.2 Circular Layout .............................................................. 13 Section 5 Resistors................................................................................. 15 Section 5.1 Calculating Resistance.................................................. 16
Section 5.1.1 Section 5.1.2 Segmented Resistor.........................................................17 Continuous Resistor .........................................................17

Section 6 MOSFETs ................................................................................ 19 Section 6.1 Device Parameters........................................................ 20 Section 6.2 Layout Patterns ............................................................. 20 Section 6.3 Additional Options ......................................................... 21 Section 7 Setup Reference..................................................................... 21 Section 7.1 Capacitors ..................................................................... 22
Section 7.1.1 Section 7.1.2 Section 7.1.3 Section 7.1.4 Section 7.1.5 Section 7.1.6 Text Formats ....................................................................22 Single Capacitor Layer Setup...........................................22 Single Capacitor Design Rules.........................................23 Capacitor Array Layer Setup ............................................25 Capacitor Array Design Rules ..........................................26 Default Parameters ..........................................................28 Text Formats ....................................................................29 Inductor Layer Setup ........................................................29 Inductor Design Rules ......................................................30 Default Parameters ..........................................................31

Section 7.2

Inductor Setup Wizard................................................... 29

Section 7.2.1 Section 7.2.2 Section 7.2.3 Section 7.2.4

Dev-Gen User Guide

Section 7.3

Resistor Setup Wizard................................................... 32


Text Formats ....................................................................32 Continuous Resistor Layer Setup.....................................33 Continuous Resistor Design Rules...................................34 Segmented Resistor Layer Setup ....................................35 Segmented Resistor Design Rules ..................................36 Default Parameters ..........................................................37 Text Formats ....................................................................38

Section 7.3.1 Section 7.3.2 Section 7.3.3 Section 7.3.4 Section 7.3.5 Section 7.3.6

Section 7.4 Section 7.5 Section 7.6

N- and P-Channel MOSFET Setup ............................... 38 MOSFET Layer Setup ................................................... 38 MOSFET Design Rules ................................................. 40
Default Parameters ..........................................................43

Section 7.4.1

Section 7.6.1

Dev-Gen User Guide

Section 1 Introduction
Dev-Gen is an integrated set of macros that provides parameterizable device layout generation in L-Edit, allowing ASIC designers to generate analog device layout quickly and accurately. For each device, you can specify layout configurations, design rules, and electrical parameters. The current macro set includes four device generators: Capacitor Generator constructs a single capacitor or a capacitor array. Optional dimension control allows you to constrain one dimension to a fixed value or create a square capacitor. Inductor Generator constructs inductor cells in either rectangular or circular coils. Parameters include the width of inductor segments and the total number of wraps in the coil. Resistor Generator constructs continuous (simple) or segmented (precision) resistor cells. Dimension control allows you to specify the width and number of resistive layout segments. MOSFET Generator constructs n- or p-channel MOSFET cells using specified transistor parameters and layout options. Optional dimension control allows you to constrain one dimension of the device to a fixed value.

Section 1.1

Running Dev-Gen

The suite of macros is accessible from the L-Edit menu by selecting Draw > Layout Generators > Dev-Gen. You can map Dev-Gen to a shortcut key by selecting Setup > Application from the L-Edit menu. On the Keyboard tab, choose the Macro category and select Dev-Gen from the list of available macros. Press the new shortcut key and click Assign. Dev-Gen device generation is highly dependent on the process technology. A series of dialogs is provided on the Setup tab of the Dev-Gen interface to guide you through the process technology setup. The first time Dev-Gen is launched on a layout database file, you will be prompted to begin setup by completing the Setup dialogs, importing settings from a text file, or accepting the default settings. After the initial setup, Dev-Gen device parameters are stored in the layout database file.

Section 2 Device Setup


The first step in using Dev-Gen is initializing the generator for the current layout database file (*.tdb). If you load Dev-Gen in a layout file that has not been initialized for Dev-Gen, a Missing Information dialog will prompt you to load or create the missing Dev-Gen setup parameters:

Dev-Gen User Guide

Choose one of the following options: Import Dev-Gen information from a file Allows you to load a text file containing a list of Dev-Gen option values. Text files are discussed in Importing and Exporting Device Settings on page 6. Launches the Dev-Gen Setup dialog. From the main setup dialog, you can launch individual wizards to specify parameters for each Dev-Gen device. When you have completed setup, click Cancel to close the Setup dialog and launch the standard Dev-Gen interface. Launches Dev-Gen with the default parameter values loaded.

Start editing Dev-Gen information by using the Dev-Gen setup wizard

Initialize Dev-Gen Information with default values

Once setup is complete, Dev-Gen device parameters are saved in the current .tdb file.

Section 2.1

Using the Setup Dialogs

Dev-Gen includes a set of device setup wizards that allow you to create custom Dev-Gen device setups, each containing a set of saved parameter values. Tanner Research also includes Dev-Gen device setups in its popular Mixed-Signal Design Kits. To create or modify a set of device parameters, click the Setup tab of the Dev-Gen interface and select one of the device setup wizards. The Setup tab contains wizards for capacitor, inductor, resistor, and n- or p-channel MOSFET devices.

Dev-Gen User Guide

Section 2.2

Importing and Exporting Device Settings

The Setup dialog includes Import and Export buttons that allow you to read and save setup information in a text file. Using the import and export functions, you can easily save parameters to share with other L-Edit/Dev-Gen users. To export setup information, click Export on the Setup tab. In the Export Dev-Gen Information To dialog, type or select the text file (*.txt) in which to save setup information and click Save. If you select an existing file, Dev-Gen will automatically overwrite its contents with the most recent setup data. The exported text file contains all parameters and configurations that have been specified in setup wizards for the current layout database (.tdb) file. The text file also contains the most recently used values in each cell generator dialog. To import setup information, click Import on the Setup tab. In the Import Dev-Gen Information From dialog, select a text file containing Dev-Gen setup information and click Open.

Dev-Gen User Guide

The easiest way to edit setup information is using the device setup wizards, described below. However, you can also create a text file for import or edit an exported text file directly. Text file formats are described for each set of device parameters in Setup Reference on page 21.

Section 2.3

Device Setup Wizards

Clicking a device setup wizard button launches the Setup Wizard dialog for that device:

The Setup Wizard allows you to create or modify device names. Each Device Name corresponds to a device class, a saved set of device parameters. You can specify several different setup configurations using different device names. Current Device Name Displays the currently selected device name. This field also specifies the name of the default setup configuration, which is automatically loaded into the corresponding device generator dialogs Device Name field. Launches the device setup wizard for the selected device name. The device setup wizard is a series of dialogs that will guide you through the selection of layer assignments, design rules, and default electrical and geometric parameters.

Modify

Dev-Gen User Guide

Create

Launches the Create New Device Class dialog to create a new device name.

Type the device name in the field provided and click OK. The device class will be created with Dev-Gen default values and saved in the current .tdb file. Click Modify to edit the default settings. Remove Copy To Rename To Deletes the selected Device Name and its associated setup configuration from the current .tdb file. Creates a new device class using the same setup configuration as the selected device name. Renames the selected device class.

Section 2.4

Modifying Device Parameters

When you select a device name in the Setup Wizard and click Modify, Dev-Gen launches a series of setup dialogs for the selected device class. Device setup wizard dialogs specify layer assignments, design rules for constructing cells, and default parameters. A complete list of setup parameters for capacitors, inductors, resistors, and n- and p-channel MOSFETs is given in the Setup Reference on page 21.

Section 2.5

Cell Info Placement Wizard

The Cell Info Placement Wizard launches a setup dialog to specify the location and appearance of information ports in a generated cell. Information ports are optional text ports that report electrical and geometric parameters used to generate a device.

Dev-Gen User Guide

Note that information port settings apply to all device types. Cell Information Text Layer Cell Information Text Size Cell Information Text Orientation Specifies the layer on which Dev-Gen places information ports in the generated cell. Point size of the port text. Select the placement of text within a port. Text can be right- or left- justified in the top, center, or bottom of a port.

Section 3 Capacitors
To generate a capacitor, select the Capacitor tab in the Device Layout Generator dialog.

Dev-Gen User Guide

Device Name shows the name of the currently active device class. The capacitor generator constructs capacitor cells using the layer assignments, design rules, and electrical parameters specified for the active device class. To change the device class, open the Capacitor Setup Wizard in the Setup tab. In the Capacitor Type field, select either Capacitor Array or Single Capacitor from the dropdown list. The Capacitor Array generator builds large and precision capacitors from evenly distributed arrays of small and accurate unit capacitor elements. Capacitor arrays are widely used in demanding analog circuit implementations such as switch-cap circuitry in filter applications. The advantages of such structures include precision value and uniform parasitic conditions on unit capacitor elements. Capacitor parameters include: Total Capacitance Unit Capacitance (Array only) The total capacitance of the cell to be built. The capacitance of each component of the array. This field is not available for a single capacitor.

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Dimension

Choose one of the following options: Fixed Height Capacitor is constructed with the specified height. Capacitor width is varied to achieve the correct area. Fixed Width Capacitor is constructed with the specified width. Height is varied to achieve the correct area. Square The capacitor is built with equal height and width. The size of the square depends upon the calculated area. If Fixed Height or Fixed Width is selected, specify a corresponding height or width value in the Dimension Length field. Height and width are specified in technology units.

Place cell information into generated cell

When checked, writes capacitor parameters to text ports in the generated cell. (Use the Cell Info Placement Wizard on the Setup tab to specify the layer for information ports.)

The default values of Total Capacitance, Unit Capacitance, and Dimension Length are specified in the Capacitor device setup wizard. Click Build to create the new capacitor cell. All cells built by Dev-Gen are locked; to unlock the capacitor cell, choose Cell > Info from the L-Edit menu and uncheck the Locked (no edits) option.

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Section 4 Inductors
To generate an inductor, select the Inductor tab in the Device Layout Generator dialog.

Device Name shows the name of the currently active device class. The inductor generator constructs capacitor cells using the layer assignments, design rules, and electrical parameters specified for the active device class. To change the device class, open the Inductor Setup Wizard in the Setup tab. Choose either a Square or Circular layout style. The parameters for each layout type are described below. The option Place cell information into generated cell causes Dev-Gen to write inductor parameters to port text in the generated cell. Use the Cell Info Placement Wizard on the Setup tab to specify the layer for information ports.

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Click Build to generate the inductor cell. All cells built by Dev-Gen are locked; to unlock the inductor cell, choose Cell > Info from the L-Edit menu and uncheck the Locked (no edits) option.

Section 4.1

Square Layout

When Square is selected as the Layout Style, the following Inductor parameters apply: Generation Direction The direction in which the inductor will be generated, beginning at the inside of the coil. Options are Clockwise and Counter Clockwise. Width, in technology units, of the wire used to generate the inductor. Length of the first straight segment of the inductor. Subsequent segments increase in length as the coil increases in size. The number of times the coil makes a complete revolution around the first inductor segment. This value is one fourth the number of right angles in the inductor.

Inductor width

Initial Segment Length

Number of turns

The following figure illustrates inductor parameters for a square coil with two turns:
Inductor Width

Generation Direction

Initial Segment Length

End of Turn 1

End of Turn 2

Section 4.2

Circular Layout

To generate a circular coil layout, select Circular in the Layout Style pull-down menu. When Circular is selected as the Layout Style, the following Inductor Parameters apply: Generation Direction The direction in which the inductor will be generated, beginning at the inside of the coil. Options are Clockwise and Counter Clockwise.

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Inductor width Initial Radius Length Number of turns Segments Per Ring

Width, in technology units, of the wire used to generate the inductor. Length, in technology units, of the radius of the innermost circle in the inductor coil. The number of times the inductor coil completes a 360 degree revolution around its center. The number of linear segments used to approximate each circular revolution of the inductor coil.

The following figure illustrates inductor parameters for a circular coil with two turns:
Inductor width

Generation Direction

Initial Radius Length

End of Turn 1

End of Turn 2

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Section 5 Resistors
To generate a resistor, select the Resistor tab in the Device Layout Generator dialog.

Device Name shows the name of the currently active device class. The resistor generator constructs capacitor cells using the layer assignments, design rules, and electrical parameters specified for the active device class. To change the device class, open the Resistor Setup Wizard in the Setup tab. In the Resistor Type field, select either a Continuous Resistor or a Segmented Resistor from the drop-down list. Continuous resistors are simple resistors in which the resistive layer segments are connected by unit cell arrays on the resistive layer. Continuous resistors are the simpler of the two resistor types, and they generally have higher accuracy as the device increases in size. For best resistance approximation, a continuous resistor should have an odd number of segments (or an even number of turns).

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Unit Cell Array for Inter-connecting Resistor Segments

Continuous
Segmented resistors are constructed from individual resistor segments connected by metal. Segmented resistors are preferable for small-value and high-accuracy devices, especially when the ratio between resistors is critical to circuit performance.
Resistor Inter-Connect

Segmented Resistor

Additional resistor parameters include: Resistor Width Resistance Dimension of resistor cell determined by The width, in technology units, of subsegments on the resistor layer. Resistance value of the completed device. Enter an integer value in the Number Of Segments field to select the number of equal-length resistor subsegments that will be used to construct the device. The height of the segments is then calculated from the number of segments, width of each segment, and the desired resistance. Note: The Vertical Dimension option has not yet been implemented. Place cell information into generated cell When checked, writes resistor parameters to port text in the generated cell. Use the Cell Info Placement Wizard on the Setup tab to specify the layer for information ports.

Section 5.1

Calculating Resistance

The layout for a Dev-Gen resistor is calculated using the specified resistor parameters and the following formula for total sheet resistance:

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R=
where

L W

is the Resistivity value (in ohms per square) of the resistor device. You can
specify this parameter in the last step of the Resistor Setup Wizard. L is the total calculated length of all resistor segments, in microns. The relationship between total length and segment length is described in the next section. W is the user-specified width of the resistor segments, converted to microns. R is the user-specified total resistance. Total resistor length is determined from the resistance equation above. From this calculation, Dev-Gen then determines the lengths of resistor segments according the type of resistor and total number of segments. Note: Contact and Metal Inter-Connect layers are generally add negligible resistance to the primary resistive layer. Therefore, these values are ingored in resistance calculations. Section 5.1.1 Segmented Resistor

In a segmented resistor, inter-connection paths between adjacent segments do not contribute to the total length. In this case, segment length (dL) is equal to the total length divided by the user-specified number of segments (N):

dL =

TotalLengt h N

The height of the final resistor cell is equal to the sum of the segment length and the contact cell heights (h), as shown below.

H = dL + 2h
H

d
h

Section 5.1.2

Continuous Resistor

The total length of a continuous resistor is calculated as the length of the central line of the primary resistive layer geometry. In this case, two different segment lengths are included in the calculation:

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dL2

dL is the length of a main segment of the resistor body. dL2 is the length of the interconnection between two resistor segments. This value is derived from the minimum spacing rule for the primary resistive layer (SP).
dL

Each main segment of the resistor is paired with a corresponding interconnection segment. The length of a single main segment and interconnection pair is equal to the TotalLength divided by the specified number of resistor segments.

dL + dL 2 =

TotalLength N

The length of the interconnection, dL2, is equal to the sum of the resistor width (W) and the minimum spacing between resistor segments (SP). Minimum spacing on the primary resistive layer is specified in the Resistor Setup Wizard.

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Section 6 MOSFETs
To generate a MOSFET, select the MOSFET tab in the Device Layout Generator dialog:

Device Name shows the name of the currently active device class corresponding to the selected Device Type (n-channel or p-channel). The MOSFET generator constructs MOSFET cells using the layer assignments, design rules, and electrical parameters specified for the active device class. To change the active n-channel or p-channel device class, open either the N-Channel MOSFET Setup Wizard or the P-Channel MOSFET Setup Wizard in the Setup tab. Select either a P-Channel or N-Channel MOSFET in the Device Type field.

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Section 6.1

Device Parameters

The Restricted by Cell Dimension field allows you to select one of three ways to determine the dimensions of the MOSFET device: Manual Allows you to specify the length and width of a single channel, and the total number of channels included in the device. Horizontal Allows you to constrain the MOSFET device to a maximum horizontal size. Using the specified values for channel length and total transistor width, Dev-Gen calculates the maximum allowed number of channels and their corresponding widths. Vertical Constrains the MOSFET to a specified vertical size. Using the specified values for channel length and total transistor width, Dev-Gen calculates the minimum allowed number of channels and their corresponding widths. When Manual is selected, the available parameters are: Channel Length Single Channel Width Total Transistor Width The length of an individual channel (technology units). The width of an individual channel (technology units).

The combined width of all transistor channels (technology units). When Horizontal or Vertical is selected, the available parameters are: Channel Length Multiple Channel Count Restricted Cell Dimension The length of an individual channel (technology units). The total number of transistor channels. The fixed horizontal or vertical size of the completed MOSFET device (technology units).

Section 6.2

Layout Patterns

Dev-Gen supports the following layout patterns: S/D Inter-Connection Gate Inter-Connection Allows optional metal connection between source and drain. Specifies the pattern of interconnection between gate layer segments. You can choose no connection, parallel connections along the top and/or bottom of the segments, or snaked connection paths beginning at the upper or lower end of the leftmost segment. Specifies the desired arrangement of optional bulkcontact elements.

Bulk Contact Arrangement

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Section 6.3

Additional Options
When checked, writes MOSFET parameters to port text in the generated cell. Use the Cell Info Placement Wizard on the Setup tab to specify the layer for information ports. Allows SPICE parameters such as source/drain areas and perimeters to be extracted to an L-Edit Extract file. Click Browse EXT File to choose the extract definition file.

Place cell information into generated cell

SPICE Parameter Back Annotation

Section 7 Setup Reference


Every device generated by Dev-Gen is a member of a device class. A device class is a predefined set of parameters that specify layer assignments, design rules, and default parameters for a device type. A device type can have multiple device classes; see Device Setup Wizards on page 7 for information about creating device classes. You can define and modify Dev-Gen device classes using the device setup wizards, which are available from the Setup tab. Alternatively, you can edit setup information in a text file that contains all of the Dev-Gen device class definitions that will be used with your layout database file. Setup for each device class includes the following information: Layer assignments that map Dev-Gen layer names to existing layers in your LEdit database file. Some Dev-Gen layers are optional (e.g., a dielectric implant in a capacitor); to omit an optional layer, assign it a value of NULL. Design rules for constructing the device cell. It is important that you define design rules to be consistent with the rules saved in Tools > Setup DRC for the current layout database file, or those specified by your foundry. For example, if the capacitor top plate layer is mapped to Poly, then the minimum width of the top plate should be greater than or equal to the minimum width of Poly. Otherwise, Dev-Gen devices may generate DRC errors and/or fail to fabricate properly. Default Parameters that define the default values of device generator parameters. In some cases, default parameters also include internal electrical parameters, such as resistivity. Additional setup information includes: The names of the default device classes for capacitor, inductor, resistor, and Nand P-Channel MOSFET devices. Information port parameters, including the layer on which ports are placed and the size and alignment of text.

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The following sections describe setup parameters for each device. At the beginning of each section, the text format for parameter definitions is shown.

Section 7.1

Capacitors
Text Formats

Section 7.1.1

Capacitor setup information consists of the following sections of text.


// Default device name tCell_Info.Capacitor.ClassDefault::5::ActiveClass // Single Capacitor Layer Setup tCell_Info.Capacitor.ClassName.Type1.LayerInfo.LayerName::5::MapLayer ... // Single Capacitor Design Rules tCell_Info.Capacitor.ClassName.Type1.DesignRules.Name::3::Value

... // Capacitor Array Layer Setup tCell_Info.Capacitor.ClassName.Type2.LayerInfo.LayerName::5::MapLayer ... // Capacitor Array Design Rules tCell_Info.Capacitor.ClassName.Type2.DesignRules.Name::3::Value ... // Default Parameters tCell_Info.Capacitor.ClassName.InitalValue.Parameter::3::Value ... Section 7.1.2 Single Capacitor Layer Setup

The first two dialogs of the Capacitor Setup Wizard allow you to assign elements of the Dev-Gen single capacitor to layers defined in your L-Edit layout database:

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To assign a Target Layer, select from the drop-down list. The first entry in each most lists is NULL. To omit a capacitor feature from the generated cell, set the Target Layer to NULL. (If NULL does not appear on the list, you can enter it manually in the Target Layer field.) Dev-Gen Layer (Text Format Name) C TOP PLATE (C_TopPlate) C BOTTOM PLATE (C_BottomPlate) C MASK (C_Mask) C SUBS (C_Subs) C ID (C_Id) 1st METAL (1stMetal) Definition Layer that forms the top plate of the capacitor. Layer that forms the bottom plate of the capacitor. Dedicated dielectric implant for special capacitive performance (such as Thin Oxide).* Well or substrate below the capacitor. This layer is not electrically connected to the capacitor.* ID layer to extract device to netlist components.* Metal connecting to the capacitor. Recommended Target Layers Poly2 Mim-Cap Poly1 Metal4 Thin Oxide

Well Metal3 Capacitor ID Metal1

CONTACT Contact Cut Contact (Contact) * Optional layers may be omitted from the capacitor by mapping them to NULL. Section 7.1.3 Single Capacitor Design Rules

Steps 3 and 4 of the Capacitor Setup Wizard contain design rule values for constructing a single capacitor:

The Value for each rule is defined in technology units.

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# 1

Rule (Text Format Name) Top Plate: Min Top Plate Width (Rule1)

Description Includes three rules that comprise the capacitor width: Minimum width of the top plate. Minimum width of the bottom plate. Minimum width of the capacitor ID layer, if one is defined. Minimum width of the bottom plate area surrounding the capacitors top plate. If a dielectric implant (mask) layer is defined, specifies the minimum width of mask layer required to surround the capacitors bottom plate. Minimum width of the substrate layer area surrounding the capacitors bottom plate. Exact width of contact cuts. Minimum spacing allowed between contact cuts. Minimum width of the metal layer area surrounding each contact cut. Minimum width of the top plate area surrounding each contact cut. Minimum width of the bottom plate area surrounding each contact cut. Minimum spacing between contact cuts on the bottom plate and the edge of the capacitor top plate.

Top Plate: Min Top Plate surrounded by Bottom Plate (Rule2) Bottom Plate: Min Bottom Plate Surrounded by C Mask (Rule3) Bottom Plate: Min Bottom Plate Surround by C Subs (Rule4) Contact: Exact Contact Cut Size (Rule5) Contact: Min Contact Spacing (Rule6) Contact: Min Contact Surround by Metal (Rule7) Contact: Min Contact Surround by Top Plate (Rule8) Contact: Min Contact Surround by Bottom Plate (Rule9) Contact: Min (Bottom Plate) Contact Spacing to Top Plate (Rule10)

5 6 7

10

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Section 7.1.4

Capacitor Array Layer Setup

Steps 5 and 6 of the Capacitor Setup Wizard allow you to assign elements of the Dev-Gen capacitor array to layers defined in your L-Edit layout database:

To assign a Target Layer, select from the drop-down list. The first entry in each most lists is NULL. To omit a capacitor feature from the generated cell, set the Target Layer to NULL. (If NULL does not appear on the list, you can enter it manually in the Target Layer field.) Dev-Gen Layer (Text Format Name) C TOP PLATE (C_TopPlate) C BOTTOM PLATE (C_BottomPlate ) C MASK (C_Mask) C SUBS (C_Subs) C ID (C_Id) 1st METAL (1stMetal) CONTACT (Contact) 2nd METAL Recommende d Target Layers Poly2 Mim-Cap Poly1 Metal4

Definition Layer that forms the top plate of the capacitor. Layer that forms the bottom plate of the capacitor.

Dedicated dielectric implant for special capacitive performance (such as Thin Oxide).* Well or substrate below the capacitor. This layer is not electrically connected to the capacitor.* ID layer to extract device to netlist components.* Metal connecting to the capacitor. Contact cut. Metal connecting the 1st Metal and Via layers.*

Thin Oxide Well Metal3 Capacitor ID Metal1 Contact Metal2

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Dev-Gen Layer (Text Format Name) (2ndMetal)

Definition

Recommende d Target Layers

VIA Via cut.* Via1 (Via) * Optional layers may be omitted from the capacitor by mapping them to NULL. Section 7.1.5 Capacitor Array Design Rules

Steps 7, 8, and 9 of the Capacitor Setup Wizard contain design rule values for constructing a capacitor array:

The Value for each rule is defined in technology units.

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# 1

Rule (Text Format Name) Top Plate: Min Top Plate Width (Rule1)

Description Includes three rules that comprise the capacitor width: Minimum width of the top plate. Minimum width of the bottom plate. Minimum width of the capacitor ID layer, if one is defined. Minimum width of the bottom plate area surrounding the capacitors top plate. If a dielectric implant (mask) layer is defined, specifies the minimum width of mask layer required to surround the capacitors bottom plate. Minimum width of the substrate layer area surrounding the capacitors bottom plate. Exact width of contact cuts. Minimum spacing allowed between contact cuts. Minimum width of the metal layer area surrounding each contact cut. Minimum width of the top plate area surrounding each contact cut. Minimum width of the bottom plate area surrounding each contact cut. Minimum spacing between contact cuts on the bottom plate and the edge of the capacitor top plate. Exact width of Via. Minimum spacing between the via layer and contact cuts. Minimum width of the 1st metal layer area surrounding each via cut. Minimum width of the 2nd metal layer area

Top Plate: Min Top Plate Surrounded by Bottom Plate (Rule2) Bottom Plate: Min Bottom Plate Surrounded by C Mask (Rule3) Bottom Plate: Min Bottom Plate Surround by C Subs (Rule4) Contact: Exact Contact Cut Size (Rule5) Contact: Min Contact Spacing (Rule6) Contact: Min Contact Surround by Metal (Rule7) Contact: Min Contact Surround by Top Plate (Rule8) Contact: Min Contact Surround by Bottom Plate (Rule9) Contact: Min (Bottom Plate) Contact Spacing to Top Plate (Rule10) Via: Exact Via Size (Rule11) Via: Min Via Spacing to Contact (Rule12) Via: Min Via Surround by 1st Metal (Rule13) Via: Min Via Surround by 2nd Metal

5 6 7

10

11 12 13 14

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Rule (Text Format Name) (Rule14)

Description surrounding each via cut.

Section 7.1.6

Default Parameters

Step 10 of the Capacitor Setup Wizard specifies default input values for the Capacitor generator dialog. This step also includes two internal values used to calculate capacitance area capacitance and fringe capacitance.

Options include: Parameter (Text Format Name) Area Capacitance (AreaCapacitance) Fringe Capacitance (FringeCapacitance) Total Capacitance (TotalCapacitance) Unit Capacitance (UnitCapacitance) Dimension Length (CapHeight) Units aF/2 fF/ pF pF tech. units Description Capacitance per square micron of the device. Capacitance per linear micron of the devices perimeter. Default total capacitance in the Capacitor dialog. Default unit capacitance for capacitor arrays in the Capacitor dialog. Default value for the fixed dimension length in the Capacitor dialog.

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Section 7.2

Inductor Setup Wizard


Text Formats

Section 7.2.1

Inductor setup information consists of the following sections of text.


// Default device name tCell_Info.Inductor.ClassDefault::5::ActiveClass // Inductor Layer Setup tCell_Info.Inductor.ClassName.Sprial.LayerInfo.LayerName::5::MapLayer ... // Inductor Design Rules tCell_Info.Inductor.ClassName.Sprial.DesignRules.Name::3::Value ... // Default Parameters tCell_Info.Inductor.ClassName.Sprial.InitalValue.Parameter::3::Value ...

Section 7.2.2

Inductor Layer Setup

Steps 1 and 2 of the Inductor Setup Wizard allow you to assign elements of a Dev-Gen inductor to layers defined in your L-Edit layout database. Layer assignments apply to both square and circular inductors:

To assign a Target Layer, select from the drop-down list. The first entry in each most lists is NULL. To omit an inductor feature from the generated cell, set the Target Layer to NULL. (If NULL does not appear on the list, you can enter it manually in the Target Layer field.) Dev-Gen Layer (Text Format Name) L LAYER (L_Layer) Recommended Target Layers Poly Metal1

Definition Layer that forms the inductor.

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Dev-Gen Layer (Text Format Name) L MASK (L_Mask) L SUBS (L_Subs) L ID (L_Id) METAL (Metal)

Definition Mask of dedicated material for special inductive performance (such as Silicide Block).* Well or substrate beneath the inductor. This layer is not electrically connected to the inductor.* ID layer to extract device to netlist components.* Metal connecting directly to the center of the inductor.

Recommended Target Layers Silicide Block

Well

Inductor ID Metal1 Metal2

CONTACT Contact cut. Contact (Contact) Via * Optional layers may be omitted from the capacitor by mapping them to NULL. Section 7.2.3 Inductor Design Rules

Steps 3 and 4 of the Inductor Setup Wizard contain design rule values for constructing a square or circular inductor:

The Value for each rule is defined in technology units. # 1 Rule (Text Format Name) L Layer (&ID Layer): Min L Layer (& ID Layer) Width (Rule1) L Layer (& ID Layer): Min L Layer (& Description Defines the minimum width of the inductive layer (the layer that forms the inductor coil). This rule also specifies the minimum width of the inductor ID layer, if one is defined. Minimum spacing between consecutive

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Rule (Text Format Name) ID Layer) Spacing (Rule2)

Description turns in the inductor coil. The same rule is applied to the inductor ID layer, if one is applied. Minimum width of mask (if defined) required to surround the inductive layer. Minimum width of well or substrate (if defined) required to surround the inductive layer. Exact width of a contact cut. Minimum width of metal surrounding a contact cut. Minimum width of inductive layer surrounding a contact cut.

L Layer: Min L Layer Surrounded by L Mask (Rule3) L Layer: Min L Layer Surround by L Subs (Rule4) Contact: Exact Contact Size (Rule5) Contact: Min Contact Surround by Metal (Rule6) Contact: Min Contact Surround by L Layer (Rule7) Default Parameters

5 6

Section 7.2.4

Step 5 of the Inductor Setup Wizard specifies default input parameters for the Inductor generator dialog.

Options include: Parameter (Text Format Name) Generation Direction (GenerateDirection) Units Description The direction in which the inductor is generated, beginning at the inside of the

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Parameter (Text Format Name)

Units

Description coil and growing outward. Options are Clockwise and Counter Clockwise.

Initial Inner Radius/Length (InnerSegmentDiameter)

Tech. units

Length of the first straight segment of the inductor. For a circular inductor, this segment defines the radius of the first turn in the inductor coil. The number of times the inductor coil completes a 360 degree turn with respect to its center point. For circular inductors, the number of linear segments used to complete a single turn.

Number of Turns (NTurns) Segment Per Ring (circular) (SegmentPerRing)

Section 7.3

Resistor Setup Wizard


Text Formats

Section 7.3.1

Resistor setup information consists of the following sections of text.


// Default device name tCell_Info.Resistor.ClassDefault::5::ActiveClass // Continuous Resistor Layer Setup tCell_Info.Resistor.ClassName.Type1.LayerInfo.LayerName::5::MapLayer ... // Continuous Resistor Design Rules tCell_Info.Resistor.ClassName.Type1.DesignRules.Name::3::Value ... // Segmented Resistor Layer Setup tCell_Info.Resistor.ClassName.Type2.LayerInfo.LayerName::5::MapLayer ... // Segmented Resistor Design Rules tCell_Info.Resistor.ClassName.Type2.DesignRules.Name::3::Value

... // Default Parameters tCell_Info.Resistor.ClassName.Sprial.InitalValue.Parameter::3::Value ...

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Section 7.3.2

Continuous Resistor Layer Setup

Steps 1 and 2 of the Resistor Setup Wizard allow you to assign elements of a continuous resistor to layers defined in your L-Edit layout database.

To assign a Target Layer, select from the drop-down list. The first entry in each most lists is NULL. To omit a resistor feature from the generated cell, set the Target Layer to NULL. (If NULL does not appear on the list, you can enter it manually in the Target Layer field.) Dev-Gen Layer (Text Format Name) R LAYER (R_Layer) R MASK (R_Mask) R SUBS (R_Subs) R ID (R_ID) METAL (Metal) CONTACT (Contact) Recommended Values Poly Active Well Silicide Block

Description Resistive layer that forms the resistor body. Mask of dedicated material for special resistive performance (such as Hi-Res or Silicide Block).* Well or substrate beneath the resistor. This layer is not electrically connected to the resistor.* ID layer to extract device to netlist components.* Metal connecting directly to the resistor. Contact cut.

Well

Resistor ID Metal1 Contact

* Optional layers may be omitted from the capacitor by mapping them to NULL.

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Section 7.3.3

Continuous Resistor Design Rules

Steps 3 and 4 of the Resistor Setup Wizard contain design rule values for constructing a continuous resistor:

The Value for each rule is defined in technology units. # 1 Rule (Text Format Name) R Layer (&ID Layer): Min R Layer (& ID Layer) Width (Rule1) R Layer (&ID Layer): Min R Layer (& ID Layer) Spacing (Rule2) R Layer: Min R Layer Surrounded by R Mask (Rule3) R Layer: Min R Layer Surround by R Subs (Rule4) Contact: Min Contact Spacing to R Mask (Rule5) Contact: Exact Contact Size (Rule6) Contact: Min Contact Spacing (Rule7) Description Defines the minimum width of the resistive layer. This rule also specifies the minimum width of the resistor ID layer, if one is defined. Minimum spacing between segments of the resistor. The same rule is applied to the resistor ID layer, if one is applied. Minimum width of mask (if defined) required to surround the resistive layer. Minimum width of well or substrate (if defined) required to surround the resistive layer. Minimum spacing between the mask layer and a contact cut. Exact width of a contact cut. Minimum spacing between contact cuts.

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# 8

Rule (Text Format Name) Contact: Min Contact Surround by Metal (Rule8) Contact: Min Contact Surround by R Layer (Rule9)

Description Minimum width of metal surrounding a contact cut. Minimum width of resistive layer surrounding a contact cut.

Section 7.3.4

Segmented Resistor Layer Setup

Steps 5 and 6 of the Resistor Setup Wizard allow you to assign elements of a segmented resistor to layers defined in your L-Edit layout database.

To assign a Target Layer, select from the drop-down list. The first entry in each most lists is NULL. To omit a resistor feature from the generated cell, set the Target Layer to NULL. (If NULL does not appear on the list, you can enter it manually in the Target Layer field.) Dev-Gen Layer (Text Format Name) R LAYER (R_Layer) R MASK (R_Mask) R SUBS (R_Subs) R ID Recommended Values Poly Active Well Silicide Block

Description Resistive layer that forms the resistor body. Mask of dedicated material for special resistive performance (such as Hi-Res or Silicide Block).* Well or substrate beneath the resistor. This layer is not electrically connected to the resistor.* Identification layer for extracting the

Well

Resistor ID

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Dev-Gen Layer (Text Format Name) (R_Id) METAL (Metal)

Description device into a netlist component.* Metal connecting directly to the resistor.

Recommended Values

Metal1

CONTACT Contact cut. Contact (Contact) * Optional layers may be omitted from the capacitor by mapping them to NULL. Section 7.3.5 Segmented Resistor Design Rules

Steps 7 and 8 of the Resistor Setup Wizard contain design rule values for constructing a segmented resistor:

The Value for each rule is defined in technology units. # 1 Rule (Text Format Name) R Layer (&ID Layer): Min R Layer (& ID Layer) Width (Rule1) R Layer (&ID Layer): Min R Layer (& ID Layer) Spacing (Rule2) R Layer: Min R Layer Surrounded by R Mask (Rule3) R Layer: Min R Layer Surround by R Subs Description Defines the minimum width of the resistive layer. This rule also specifies the minimum width of the resistor ID layer, if one is defined. Minimum spacing between segments of the resistor. The same rule is applied to the resistor ID layer, if one is applied. Minimum width of mask (if defined) required to surround the resistive layer. Minimum width of well or substrate (if defined) required to surround the resistive

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Rule (Text Format Name) (Rule4)

Description layer. Minimum spacing between the mask layer and a contact cut. Exact width of a contact cut. Minimum spacing between contact cuts. Minimum width of metal surrounding a contact cut. Minimum width of resistive layer surrounding a contact cut. Minimum width of the metal layer.

Contact: Min Contact Spacing to R Mask (Rule5) Contact: Exact Contact Size (Rule6) Contact: Min Contact Spacing (Rule7) Contact: Min Contact Surround by Metal (Rule8) Contact: Min Contact Surround by R Layer (Rule9) Metal: Min Metal Width (Rule10) Default Parameters

6 7 8

10

Section 7.3.6

Step 9 of the Resistor Setup Wizard specifies default input parameters for the Resistor generator dialog.

Options include: Parameter (Text Format Name) Resistivity Units Ohms/square Description

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Parameter (Text Format Name) (RollValue) Resistor Width (InitWidth) Resistance Value (InitResistanceValue) Resistor Segments (InitSegment)

Units

Description

Tech. units Ohms

Default width of a single resistor segment. Default resistance of a new resistor device. Default number of subsegments used to build a resistor.

Section 7.4

N- and P-Channel MOSFET Setup

N- and P-Channel MOSFETs are initialized using the corresponding setup wizards. Because the parameters for N- and P- channel MOSFETs are identical, only the N-Channel MOSFET dialogs are shown below. Section 7.4.1 Text Formats

MOSFET setup information consists of the following sections of text.


tCell_Info.npType.ClassDefault::5::ActiveClass // MOSFET Layer Setup tCell_Info.npType.ClassName.Regular.LayerInfo.LayerName::5::MapLayer ... // MOSFET Bulk Generation tCell_Info.npType.ClassName.Regular.BulkGeneration::4::Value // MOSFET Design Rules tCell_Info.npType.ClassName.Regular.DesignRules.RuleType.Name::3::Value ... // Default Parameters tCell_Info.npType.ClassName.InitalValue.Parameter::3::Value ...

Section 7.5

MOSFET Layer Setup

Steps 1 and 2 of each MOSFET setup wizard allow you to assign elements of an n- or pchannel MOSFET to layers defined in your L-Edit layout database.

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To assign a Target Layer, select from the drop-down list. The first entry in each most lists is NULL. To omit a resistor feature from the generated cell, set the Target Layer to NULL. (If NULL does not appear on the list, you can enter it manually in the Target Layer field.) Dev-Gen Layer (Text Format Name) GATE (Poly) BULK (BulkL) 1st METAL (Metal1) CONTACT (Contact) S/D DIFF (SD_Diff) S/D SELECT (SD_Select) BULK DIFF (Bulk_Diff) BULK SELECT (Bulk_Select) Recommended Values N-Channel P-Channel Description Gate and field poly. Well or substrate.* The metal layer closest to the substrate surface. Contact cut. Source/drain diffusion layer. (Select source or drain in Diffusion options.) Implant mask that specifies the polarities of sources and drains.* Diffusion layer for bulk connections. Implant Mask that specifies the polarities of bulk connections.* Poly P-Well P-Substrate Metal1 Contact N+ Diffusion Active N+ Implant P+ Diffusion Active P+ Implant Poly N-Well N-Substrate Metal1 Contact P+ Diffusion Active P+ Implant N+ Diffusion Active N+ Implant

* Optional layers may be omitted from the capacitor by mapping them to NULL.

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Section 7.6

MOSFET Design Rules

MOSFET design rules are grouped into the following categories: 1. Gate Design Rules Step 3 of each MOSFET setup wizard specifies gate-related design rules:

# 1 2

Rule (Text Format Name) Gate: Min Gate Length (GatePoly.Rule1) Gate: Min Gate Poly Extension out of Diffusion (GatePoly.Rule2) Field Poly: Min Field Poly Width (GatePoly.Rule3) Field Poly: Min Field Poly Spacing to Diffusion

Description Minimum width of the gate layer. Minimum extension of the gate layer beyond the source/drain diffusion layer. Minimum width of the field poly. Minimum spacing between field poly and diffusion layers.

3 4

2. Source/Drain and Bulk Design Rules Steps 4 and 5 of each MOSFET setup wizard specify design rules for source/drain and bulk diffusion and implant layers.

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# 1

Rule (Text Format Name) S/D Diffusion: Min S/D Diffusion Surround by Implant Select (SD_Implant.Rule1) S/D Diffusion: Min S/D Diffusion Surround by Well (SD_Implant.Rule2) Bulk Diffusion: Min Bulk Diffusion Surround by Implant Select (SD_Implant.Rule3) Bulk Diffusion: Min Bulk Diffusion Surround by Well (SD_Implant.Rule4) S/D Diffusion: Min S/D Diffusion Spacing to Bulk Diffusion (SD_Implant.Rule5) Bulk Diffusion: Min Bulk Diffusion Spacing to S/D Select (SD_Implant.Rule6)

Description Minimum width of source/drain implant mask surrounding the source/drain diffusion layer. Minimum width of well surrounding the source/drain diffusion layer. Minimum width of source/drain implant mask surrounding the bulk diffusion layer. Minimum width of well surrounding the bulk diffusion layer. Minimum spacing between the source/drain and bulk diffusion layers. Minimum spacing between the bulk diffusion layer and the source/drain implant mask. Minimum spacing between the source/drain diffusion layer and the bulk implant mask.

S/D Diffusion: Min S/D Diffusion Spacing to Bulk Select (SD_Implant.Rule7) 3. Contact Design Rules

Steps 6 and 7 of each MOSFET setup wizard specify design rules involving the contact layer.

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# 1 2 3

Rule (Text Format Name) Contact: Exact Contact Size (Contact.Rule1) Contact: Min Contact Spacing (Contact.Rule2) Contact: Min Contact Surround by Metal (Contact.Rule3) Bulk Contact: Min Contact Surround by Bulk Diffusion (Contact.Rule4) S/D Contact: Min Contact Surround by S/D Diffusion (Contact.Rule5) Butting Contact: Min Contact Spacing to Opposite Implant Sel/Diff (Contact.Rule6) S/D Contact: Min Contact Spacing to Gate (Contact.Rule7)

Description Exact width of a contact cut. Minimum spacing between contact cuts. Minimum width of metal surrounding a contact cut. Minimum width of bulk diffusion layer surrounding a contact cut. Minimum width of source/drain diffusion layer surrounding a contact cut. Minimum spacing between a contact cut and either the S/D implant mask or bulk implant mask layer. Minimum spacing between contact cuts and the gate layer.

4. Metal Design Rules Step 8 of each MOSFET setup wizard specifies design rules for the metal layer.

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# 1 2

Rule (Text Format Name) Metal: Min Metal Width (Metal.Rule1) Metal: Min Metal Spacing (Metal.Rule2) Default Parameters

Description Minimum width of the metal layer. Minimum metal-to-metal spacing.

Section 7.6.1

Step 9 of the n- and p-channel MOSFET setup wizards specify default input parameters for the MOSFET generator dialog when the selected device type is N-Channel or P-Channel, respectively.

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Parameter (Text Format Name) Channel Length (ChannelLength) Single Channel Width (OneChannelWidth) Total Transistor Width (AllTransWidth) Restricted Dimension (RestricDimension) Multiple Channel Count (MultChannel)

Units Tech. units Tech. units Tech. units Tech. units Tech. units

Description Default channel length. Default width of a single channel in the MOSFET. Default total width of a completed MOSFET device. Default value of the restricted dimension in the MOSFET dialog. Default number of channels used to build a MOSFET.

Copyright 1999-2009 Tanner Research, Inc.

All Rights Reserved.

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