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Reference Design

SLUA269 - July 2002

UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design
Michael O’Loughlin ABSTRACT This paper reviews the benefits of a boost follower topology and the design of a 250-W PFC boost follower preregulator. System Power

Contents 1 2 3 4 5 6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power Stage Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 VAI Output Sensing Circuit with Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slower Voltage Loop Small Signal Transient Response at High Line . . . . . . . . . . . . . . . . . . . . 11 Reference Design Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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Introduction
Conventionally PFC off-line power converters are designed with two power stages. The first stage is typically a boost converter. This is because the boost converter topology has continuous input current that can be shaped through the use of a multiplier and average current mode control to achieve near-unity power factor (PF). However the boost converter requires a higher output voltage than the input and requires a second converter to step this voltage down to a useable level. The boost converter is traditionally designed to have a fixed output voltage greater than the maximum peak line voltage. However, the boost voltage does not have to be well regulated or fixed because the step down converter can be designed to handle the variations in voltage. As long as the boost voltage is above the peak input voltage the converter will regulate properly. There are actually some benefits that can be gained by having the boost voltage vary with variations in peak line voltage (i.e. boost follower preregulator). One is reduced inductor size and the other is lower switch loss at low line operation. This paper reviews the benefits of a boost follower topology and the design of a 250-W PFC boost follower preregulator. NOTE: The reference design was generated using typical parameters rather than worst-case values. Please refer to the table in Figure 1 and Figure 2 for design specifications and component placement. Refer to Table 1 for all variable definitions.

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Functional Block Diagram Table 1.7 409 275 5. POUT = 250 W POUT = 250 W 100 VIN = 85 VRMS VIN = 265 VRMS 195 370 0 93% 5% 7% kHz ms V W A TEST CONDITIONS MIN 85 60 205 390 215 410 250 3% V W TYP MAX 265 UNITS VRMS Hz 2 UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design . VIN = 265 VRMS. Design Specifications PARAMETER VIN fIN VOUT dc POUT VRIPPLE η THD fOSC tHOLDUP VOVP PLIM ILIM Input offset voltage Input frequency Output oltage O tp t voltage Output power Output voltage ripple Efficiency Total harmonic distortion Operating frequency Hold-up time Overvoltage protection threshold voltage Power limit Peak current limit VOUT = 400 V VIN = 85 VRMS 16.335 416 360 5.665 VIN = 85 VRMS POUT = 250 W VIN = 85 VRMS.SLUA269 STAGE 1 STAGE 2 + VOUT VLINE 85 VAC TO 265 VAC – PFC CONTROLLER PWM CONTROLLER UDG–02075 Figure 1.500 422 385 5.

Reference Design Schematic + UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design 3 .SLUA269 + Figure 2.

SLUA269 Table 2. Variable Definitions VARIABLE CDIODE COSS GVEA D fS GPID GPID (f) GPS(f) IMO_MAX(high_line) IRMS_DIODE IRMS_FET IRMS_L Osc_Amplitude PSEMI PCON_FET PCOND_DIODE PCOSS PDIODE PDIODE_CAP PDIODE_TR PFET_TR PGATE POUT PQ1 QGATE RDS(on) RθCS RθJC RθSA TA tHOLDUP TJ(max) tF tR tRR TS(f) VAI(max) VAI(min) VCLAMP VEA(max) VEA(min) VGATE VDROP VIN(max) Boost diode capacitance FET Drain to source capacitance Gain of the voltage amplifier Duty cycle PWM switching frequency Control to output gain of the current loop at the desired crossover frequency Control to output gain of the current loop Voltage loop control to output gain Peak IMO current at high-line input Boost diode current RMS current in the FET RMS inductor current Typical oscillator ramp amplitude Power dissipated by a semiconductor device Conduction losses in the FET Diode conduction losses Power dissipated by the FET’s drain to source capacitance Total loss in the boost diode Loss due to boost diode capacitance Boost diode transition loss FET transition losses Power dissipated by the FET gate Maximum output power Total FET losses FET gate charge On resistance of the FET Thermal impedance case to sink Thermal impedance junction to case Thermal impedance sink to air Ambient temperature Boost capacitor holdup time Maximum semiconductor temperature FET fall time FET rise time Reverse recover time for a boost diode Voltage loop frequency response Maximum voltage amplifier reference Minimum voltage amplifier reference voltage Voltage reference clamp to ensure the boost voltage is not exceeded Maximum voltage amplifier output. Maximum RMS input voltage DEFINITIONS 4 UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design . Minimum voltage amplifier output Gate drive voltage Amount of voltage the boost capacitor is allowed to drop during holdup.

To calculate the loss in Q1: I RMS_FET + P OUT V IN (min) 2 fS 2 2* 16 3 V IN(min) p 2 V OUT(min) I RMS_L + P OUT V OUT (min) (4) (5) P GATE + Q GATE P COSS + 1 C OSS 2 V GATE V OUT(min) fS (6) UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design 5 . The calculated inductance for this design was roughly 570 µH. To make the design process easier the inductor was designed by Cooper Electronics. To meet the power budget for this design an IRFP450 HEX FET and HFA08TB60 fast recovery diode from International Rectifier were chosen for this design to meet the power constraints. Equations (4).2 Boost Switch Selection (D1) and Boost Diode Selection (Q1) To properly select D1 and Q1 a power budget is generally set for these devices to maintain the desired efficiency goal. The following equations can be used to calculate the required inductor for the power stage with ripple current that is 20% of the peak input current. For the same power levels and input conditions for the traditional boost converter would require and inductance of roughly 1 mH. In traditional application the boost voltage (VOUT(min)) would be fixed at roughly 390 V.SLUA269 VARIABLE VIN(min) VOUT(max) VOUT(min) VPP VREF_TL431 ∆I η %THD Minimum RMS input voltage Maximum dc output voltage Minimum dc output voltage Output peak-to-peak ripple voltage Reference voltage of the TL431 Change in boost inductor ripple current Efficiency Percentage of allowable total harmonic distortion DEFINITIONS 2 2. (5). and (6) are used to estimate power loss in the switching devices.2 V IN (min) V OUT (min) * V IN (min) V OUT (min) 2 fS D DI (3) 2 (1) D+1* L1 + (2) V IN (min) 2.1 Power Stage Design Inductor Selection The boost inductor is selected based on the maximum allowed ripple current at maximum duty cycle at the peak of minimum line voltage. DI + P OUT 2 0.

The calculated losses for Q1 and D1 in the traditional topology were approximately 25 W and the calculated losses for switch and diode for the boost follower was approximately 17.3 Benefits of the Boost Follower Topology on the Power Stage at Low-Line The more traditional PFC preregulator topology has a fixed output voltage that is greater than the peak line voltage. The fixed boost voltage for a universal input is typically set at 390 V. The boost follower is designed so that the output voltage is greater than the peak input voltage.SLUA269 P COND_FET + R DS(on) P FET_TR + 1 V OUT(min) 2 2 I RMS_FET I RMS_L 0. From the equations for transition loss and capacitance loss for the boost switch (Q1).4 W. The boost follower topology should be at least 3% more efficient at low line than the traditional topology.9 tR ) tF fS (7) (8) (9) P Q1 + P GATE ) P COSS ) P COND_FET ) P FET_TR To calculate the loss in D1: I RMS_DIODE + P OUT V OUT (min) 3 16 p V OUT(min) V IN(min) 2 (10) (11) P COND_DIODE + V F P DIODE_CAP + C DIODE 2 I RMS_DIODE 2 V OUT(min) I RMS_DIODE fS t RR fS (12) (13) (14) P DIODE_TR + 1 V OUT(min) 2 P DIODE + P COND_DIODE ) P DIODE_CAP ) P COND_TR 2.) 6 UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design . When compared to that of a traditional converter with the same power levels. For this design the output tracks the input from 206 V to 390 V. (See Figure 3. the finished converter’s low-line efficiency is approximately 5% more efficient. it can be observed that these losses should be less at lower line voltages for the boost follower topology as compared to the traditional preregulator.

SLUA269 EFFICIENCY vs OUTPUT POWER 100 98 96 Efficiency – (%) 94 92 90 88 86 84 82 25 50 75 100 125 150 175 200 225 250 POUT – Output Power – W 85 VRMS of Boost-Follower PFC 85 VRMS of Traditional PFC Figure 3. C12 w 2 P OUT V OUT(min) t HOLDUP 2 2 (16) * V OUT(min) * V DROP UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design 7 . This is one of the negative aspects of using a boost follower topology.5 Holdup Capacitor Selection Equation (16) is used to estimate the size of the hold-up capacitor and the maximum allowable RMS current through the boost capacitor. This minimum calculated capacitance value is roughly double of what is required in the traditional design. The heat sink required for Q1 using the traditional topology required an AVVID heat sink part number 53002 that is approximately 4.38 cubic inches which is about 66% smaller than the heat sink used in the traditional design.7 ms of holdup time (tHOLDUP) allowing the output 85 V of drop (VDROP).4 Heat Sinks Equation (15) calculates the minimum required thermal impedances of the heat sinks (RθSA) required for this design. Rq SA + T J(max) * T A * P SEMI P SEMI Rq CS ) Rq JC (15) 2. The hold-up capacitor was designed for 16. The heat sinks require a fan capable of forcing 40°C air at 150 LFPM.125 cubic inches. 2. The heat sink for the boost follower topology required an AVVID heat sink part number 531202 of approximately 1. For this design the calculated minimum hold-up capacitance was approximately 330 µF requiring roughly 1.7 A of RMS current at low-line operation. The heat sinks are designed to ensure that the junction tempature stays below 75% of the rated maximum.

To meet the current THD requirements.SLUA269 I RMS_C12 + P OUT V OUT (min) 3 16 p V OUT(min) V IN(min) 2 *1 (17) 2. contribute to input current total harmonic distortion (THD).9 2 (18) 1.5% (%THD) of the VFF pin’s voltage range. R14. The voltage feedforward (VFF) of the multiplier is one that contribute to THD.4 V V IN(min) R13)R21 Three voltage signals in this circuit. having a 120-Hz ripple component. This comparator limits only the current through the switch and not the current drawn by the output. C6 is set to attenuate the 120-Hz voltage ripple present on the VFF input of the multiplier to 1. R12 and R11 are selected to have the peak limit comparator trip at 110% of the maximum output power to protect Q1.7 Peak Current Limit The UCC3819 has a peak current limit comparator that can be set up with a voltage divider using the VREF pin of the PWM controller. C6 + 1 2 p %THD 66% 120 Hz R6 (20) 2. To meet the design goal of less than 5% THD. R13 ) R21 + R6 + V IN(max) 500 mA (19) 2 0. Equations (18) and (19) are used to set up the multiplier.6 Multiplier Setup The multiplier is used to shape the input current waveform and must be set up correctly to get proper PFC. 8 UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design .5% allowable 120-Hz distortion (%THD). each signal is allowed to contribute only 1.

Resistor R8 and capacitor C9 form a zero at the desired crossover frequency that gives an added 45 degrees of phase margin for circuit stability. This reference voltage is then used to make the output voltage track the input voltage. C9 + G PID 1 2 p fS 10 . P OUT 2 h V IN(max) R14 R9 + I MO_MAX(high_line) . With a few external components. UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design 9 .9 Current Amplifier Equations (22) and (23) are used to compensate the current loop with a desired crossover frequency at 1/10 of the switching frequency. It is this feature that allows the designer to use an integrated PWM controller with a boost follower topology.8 Power Limiting Resistor R9 is selected to achieve soft power limiting at maximum output power[1]. Capacitor C8 and and resistor R8 form a high-frequency pole to attenuate any high-frequency noise that may be present in the system. C8 + R8 2 p 1 fS 2 R8 (23) 3 VAI Input Sensing Circuit with Clamp The UCC3819 PWM controller allows the user to set the reference voltage (VAI) externally.SLUA269 2. G PID + 2 p V OUT(max) fS 10 L1 R14 (22) Osc_Amplitude R8 + 1 . a circuit can be constructed that sets VAI proportional to the input voltage. R9 + R10 (21) 2. Figure 4 shows the external components that are required to generate the VAI voltage.

R35.1 kΩ R36 2 kΩ UDG–02076 Figure 4.5% THD. and D13 form a VAI clamp to ensure the boost voltage does not exceed the design specification of 390 V. VAI Output Sensing Schematic R31. C17 + 2 p 1 V AI(max) %THD V IN(max) 2 66% 120 Hz R33 (26) Setting up the clamp voltage requires that the divider to the VSENSE pin be set up first.7 µF 4 6 5 R35 3. Capacitor C17 is selected to keep its contribution to less than 1. R33 and C17 form a voltage divider with a single-pole filter that is used to monitor the line voltage.3 kΩ D13 TLV431CLP VFF C18 1 µF 1 2 R32 499 kΩ R33 22. Equations (24) and (25) can be used to select the proper components for the circuit.9 * V AI(min) V AI(min) V IN(min) (25) The VAI signal includes a 120-Hz component that can contribute to THD. R3 + V AI(min) (R19 ) R2) V OUT(min) * V AI(min) V OUT(max) R3 R19 ) R29 ) R3 R36 (29) (27) V CLAMP + R35 + (28) V CLAMP * V REF_TL431 V REF_TL431 10 UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design . V AI(min) + R33 + V AI(max) 2 (24) (R31 ) R32) 0.SLUA269 C19 33 pF VREC R31 499 kΩ U2 OP–07 VCC 8 7 R34 432 Ω 3 C16 0. R36.01 µF C17 4. R32.

As the input voltage increases. s(f) + j G PS(f) + 2 p f P OUT V EA(max) * V EA(min) (s(f) S(f) T s(f) + * G PS(f) R9 (C9 ) C8) G EA(f) V OUT R8 s(f) C9 ) 1) S(f) R8 C9 C8 )1 C9)C8 (35) (36) C12 G EA(f) + (37) (38) Figures 5 and 6 show the measured voltage loop small-signal frequency response. These equations describe the power stage gain (GPS(f)) as inversely proportional to output voltage. which decreases the overall loop gain (TS(f)). The small signal transient response at low line is roughly twice as fast as it is at high line. which results in a fixed transient response.SLUA269 3. As TS(f) decreases the loop crosses over at a lower fC. The traditional topology has a fixed output voltage and a fixed TS(f). VOUT increases. V PP + P OUT h (30) V OUT(min) (31) p 120 Hz %THD C12 G VEA + C8 + fC + V EA(max) * V EA(min) V PP 100 G VEA R9 P OUT 1 R9 1 120 Hz 2 p (32) V EA(max) * V EA(min) 1 2 p fS 10 V OUT(min) 2 p C12 2 p C8 (33) R8 + C8 (34) 4 Slower Voltage Loop Small Signal Transient Response at High Line Another drawback to using a boost follower topology is the small signal transient response is slower at lower line voltages. In the boost-follower topology the voltage loop is compensated when the boost voltage is at its lowest to ensure circuit stability. UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design 11 . independent of line voltage. resulting in slower transient response. Equations (35) through (38) model the voltage loop frequency response of both a boost follower and traditional PFC offline voltage regulator.1 Voltage Amplifier The voltage amplifier is compensated to attenuate the 120-Hz boost-ripple voltage (VPP) in order to reduce it’s contribution to THD.

SLUA269 50 40 30 140 120 100 Phase 20 G – Gain – (dB) 10 0 –10 –20 –30 –40 –50 1 10 f – Frequency – Hz 80 60 40 20 Phase – (_) Phase – (_) Gain 0 –20 –40 –60 100 Figure 5. Voltage Loop Low-Line Frequency Response at Maximum Load 50 40 30 20 G – Gain – (dB) 10 0 –10 –20 –30 –40 –40 –50 1 10 f – Frequency – Hz –60 100 0 100 80 Phase 60 40 Gain –20 Figure 6. Voltage Loop High-Line Frequency Response at Maximum Load 12 UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design .

POWER FACTOR vs OUTPUT POWER 100 Figure 8. UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design 13 . TOTAL HARMONIC DISTORTION (THD) vs OUTPUT POWER 10 9 100 98 96 Efficiency – (%) 94 92 90 88 3 2 86 EFFICIENCY vs OUTPUT POWER THD – Total Harmonic Distortion – (%) 8 7 6 5 4 VRMS = 265 VRMS = 120 VRMS = 265 VRMS = 85 VRMS = 120 1 0 25 50 75 100 125 150 VRMS = 85 84 82 175 200 225 250 25 50 75 100 125 150 175 200 225 250 POUT – Output Power – W POUT – Output Power – W Figure 7. VRMS = 85 90 PF – Power Factor – (%) 80 70 VRMS = 120 60 50 VRMS = 265 40 25 50 75 100 125 150 175 200 225 250 POUT – Output Power – W Figure 9.SLUA269 5 Reference Design Performance Curves The following graphs show the performance of the reference design.

HIGH-LINE OPERATION VIN = 265 V POUT = 25 W VIN = 265 V POUT = 25 W Figure 11. Figure 13. HIGH-LINE OPERATION Rectified Line Voltage (100 V / div) Rectified Line Voltage (100 V / div) Input Current (200 mA / div) t – Time – 5 ms / div Input Current (2 A / div) t – Time – 5 ms / div Figure 12.SLUA269 LOW-LINE OPERATION VIN = 85 V POUT = 25 W Rectified Line Voltage (100 V / div) VIN = 85 V POUT = 250 W Rectified Line Voltage (100 V / div) LOW-LINE OPERATION Input Current (500 mA / div) Input Current (5 A / div) t – Time – 5 ms / div t – Time – 5 ms / div Figure 10. 14 UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design .

Practical Considerations in Current Mode Power Supplies.SLUA269 6 References 1. POWER CONVERSION. Texas Instruments Literature No. ” Unitrode Power Supply Design Seminar SEM–700. SLUA110.” Texas Instruments Literature No. ”High Power Factor Switching Prergulator Design Optimization. Lloyd Dixon. (LIST PUBLICATION HERE) p. 3. SLUP093. UCC3819 250-W Power Factor Corrected (PFC) Boost Follower Preregulator Design 15 . 1990. 2. September 1992 Proceedings. Application Note. SLUA196. Laszlo Balogh. Topic 7. Texas Instruments Literature No. 67 4. ”UCC3854A/B and UCC3855A/B Provide Power Limiting With Sinusoidal Input Current.

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