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# Digital Systems Mini-Project Number Comparisons and Structural Modelling in VHDL

Surajkumar.H. , Senel Herenj EE11B075, EE11B074 November 5, 2012

Abstract
The Mini-Project was to familiarize oneself with the concepts taught in the classes, namely the synchronous logic, state equations, graphs, assignment and reduction. Deriving next state equations and circuit level modelling. It is also a way to learn, and get comfortable with coding in HDL languages. below. It was implemented in VHDL with Structural Modelling This pro ject has a problem statement as given

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Problem Statement
X2 )
represent a 2-bit binary number, N. If the

The problem statement was question 14.12b as given in the text book . It is the following :A sequential network has two inputs and two outputs. The inputs (X1 , the previous value of N is greater than 2, then the value of of inputs are recieved, use 0 as the previous value of N Find a Moore State Table for the network ( minimum number of states is 10 ). Implement the above with Structural Modelling  present value of N plus the previous value of N is greater than 2, then the value of

Z1
and

is 1.If the present value of N times

Z2

is 1. Otherwise

Z1

Z2 are

both 0. When the rst pair

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State Tables and Graphs

The rst part of the question was to derive the State table. This was necessry, as it is required to obtain the next state equations to describe the Flip-Flop next state inputs and the Output - Flip-Flop state equations. For this, the state graph was obtained by giving several inputs and arriving at the next states of the current state, while dening new states for new input combnations / outputs. Since the circuit is Moore, the output is a function of the State, and not the input. This ensures that the output changes only at the rising edge of the clock. A minimal solution of 10 states was arrived at, and it was cinverted into an equivalent state Table The State Table Obtained was thus :Previous Input Next State, Input 00 01 10

X1 X2
00 01 10 11 10 11 01 10 00 01

Current State

X1 X2
11

Output

Z1 Z2
00 00 00 10 10 11 10 11 10 11

S0 S1 S2 S3 S4 S5 S6 S7 S8 S9

S0 S0 S0 S8 S0 S8 S0 S0 S0 S0

S1 S1 S6 S9 S6 S9 S1 S6 S1 S1

S2 S4 S7 S7 S7 S7 S4 S7 S2 S4

S3 S5 S5 S5 S5 S5 S5 S5 S3 S5

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Input 00 01 10 X1 X2 00 00 01 01 01 10 10 10 11 11 Current State X1 X2 11 Output Z1 Z2 00 10 00 10 11 00 10 11 10 11 S0 S8 S1 S6 S9 S2 S4 S7 S3 S5 S0 S0 S0 S0 S0 S0 S0 S0 S8 S8 S1 S1 S1 S1 S1 S6 S6 S6 S9 S9 S2 S2 S4 S4 S4 S7 S7 S7 S7 S7 S3 S3 S5 S5 S5 S5 S5 S5 S5 S5 We can already see that this provides a more optimal State Assignment Solution.Now we shall rearrange the table to group the states with similar previous state together. This is one of the major criteria for State assignment. S2 = 0101. S6 = 0011. but dierent Output Thus from this table a State Assignment was done. and that this civers the entire range of inputs. S8 = 0001. The optimized State Table is given as below :Previous Input Next State. S9 = 1001 2 . S9 = 0100. After several state equivalences. S7 = 0111. S3 = 1000. S4 = 0110. obtained by subjecting to the range of outputs. S1 = 0010. as several adjacent states have the Same Next State.Figure 1: State Graph of Sequenecer The following it the state graph obtained for the question. this was the nal 10 state graph :- We see that has 10 states. and thus this is the modication used before obtaining the optimized State Table. as S0 = 0000 .

We see that 4 such sets exist. So instead. one for each input value. Hence. for A and B :Previous Input State ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 A+ Input X1 X2 00 0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 11 1 1 1 1 1 1 1 1 1 1 B + Input X1 X2 00 0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 1 1 10 1 1 1 1 1 1 1 1 1 1 11 0 0 0 0 0 0 0 0 0 0 C + Input X1 X2 00 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1 0 0 10 0 0 1 1 1 1 1 1 1 1 11 0 0 0 0 0 0 0 0 0 0 D+ Input X1 X2 00 0 0 0 0 0 0 0 0 1 1 01 0 0 0 0 0 1 1 1 0 0 10 1 1 0 0 0 1 1 1 1 1 11 0 0 1 1 1 1 1 1 1 1 Output X1 X2 00 00 01 01 01 10 10 10 11 11 Z1 Z2 00 10 00 10 11 00 10 11 10 11 From here it is possible to derive the next state equations of the Flip-Flop variables from here.11 E2 = A (B C + BC D ) E3 = A (B(C + D)) E4 = AB C From here. The state assignment was done such that sets of adjacent states have the same next state. 01 0010 0010 0010 0010 0010 0011 0011 0011 0100 0100 Input 10 0101 0101 0110 0110 0110 0111 0111 0111 0111 0111 X1 X2 11 1000 1000 1001 1001 1001 1001 1001 1001 1001 1001 Output X1 X2 00 00 01 01 01 10 10 10 11 11 Z1 Z2 00 10 00 10 11 00 10 11 10 11 Writing The Next State as a function of input and current state gives us. which would be dicult to solve with the current techniques. and also the output. so that would give a 6 variable K-Map. a small trick was done with the current state assignment. there are 4 bits and 2 inputs. These. For example we dened X1 and X2 will give E1 = A B C as a combination of the rst two terms which have the same output ( previou output 00 ) Analogously. for previous input 01.The New State Table with the State Assignments is as follows:Previous Input Current State ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Next State 00 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 A+ B + C + D + . and used in all the next state equations. when ANDed and ORer with combinations of the required next state.10. Hence these 4 values were taken computed early in the VHDL code. we can write : A+ = (E1 + E2 + E3 + E4 )X1 X2 B + = (E1 + E2 + E3 )X1 X2 + E4 (X1 X2 + X1 X2 ) C + = E1 (X1 X2 ) + (E2 + E3 )(X1 X2 + X1 X2 ) + E4 (X1 X2 ) D+ = E1 (X1 X2 ) + E2 (X1 X2 ) + E3 (X1 + X2 ) + E4 (X1 + X2 ) Also from a simple 4-variable K-Map we arrive at the equations for Z1 and Z2 Z1 = A + BD + B D + CD 3 . each of these can be represented by an expression in terms of the 4 state variables. Ordinarily fot the Next-State we would do a K-Map or a QM Reduction. But here.

50 NS 90 NS . but since here the same expression is recycled several times. a K-Map could have been done and the expressions simplied. Table 1: Input Testbench The clock was choen as period 40 NS. so it was convenient to change the input values at intervals of 40 NS starting from 10. 3 TestBench and I/O In the testbench. so they were left as attachments. Ideally.e 10 NS. especially in terms of gate minimization.. a clock sequence was chosen with Time period 40 NS. And with that the following input sequence The 3 fragments of the code were too long to include in the report. Also a rising edge Flip-Flop was designed.Z2 = BC D + BCD + AD We can very easily see that this may not be the optimal solution. The input combinations are given below. 2nd is the circuits and 3rd the testbench. this works as a great solution too. The testbench output is as shown below was applied. etc. so as to see what gets taken in the Next-State Equation Time ( NS ) 20 60 100 140 180 220 260 300 340 380 420 460 Input X1 ( MSB of 2 digit number) 0 0 1 1 0 1 0 1 1 1 1 1 Input X2 0 1 0 0 1 0 0 0 1 0 1 1 ( LSB ) Output Z1 0 0 1 1 1 1 0 0 1 1 1 1 expected Output Z2 0 0 0 1 0 0 0 0 1 1 1 1 expected 4 . The rst is for the denitions of gates. i. These have been referenced at the rising edge of the clock.

not of variable. it will most likely stand the test. as this more accurately describes the real design of DFF's We see that for the given Inputs. which was simulated by assigning a 2 NS delay to the Flip-Flops. 5 . the output does agree with the requirement as per question. Note that there is a slight delay in the output. A more rigorous testbench would always be better as is would point errors much beter.Figure 2: Sample I/O for the given testbench This is the expected output for the given testbench. but since this was designed with assignment and reduction of state.