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Digital CMOS Logic Circuits

Sedra & Smith, Chapter 10

Digital CMOS Logic Circuits Sedra & Smith, Chapter 10 Inverter Circuit

Inverter Circuit

CMOS Logic Gate Circuit

Similar structure to inverter:

CMOS Logic Gate Circuit Similar structure to inverter: Network of PMOS transistors Network of NMOS transistors

Network of PMOS transistors

Network of NMOS transistors

PUN & PDN Basic Structure

Parallel OR

Series AND

PUN & PDN Basic Structure Parallel → OR Series → AND

Combinations of Basic Structures

Combinations of Basic Structures

Alternative (Digital) Symbols

Alternative (Digital) Symbols PMOS Active Low: Transistor is conducting (activated) when input is low.

PMOS Active Low: Transistor is conducting (activated) when input is low.

2input NOR

2 ‐ input NOR Y is high (PUN conducting) when A AND B are Low. Y
2 ‐ input NOR Y is high (PUN conducting) when A AND B are Low. Y
2 ‐ input NOR Y is high (PUN conducting) when A AND B are Low. Y

Y is high (PUN conducting) when A AND B are Low.

Y is low (PDN conducting) when A OR B is High.

2 ‐ input NOR Y is high (PUN conducting) when A AND B are Low. Y
2 ‐ input NAND Y is high (PUN conducting) when A OR B are Low. Y
2 ‐ input NAND Y is high (PUN conducting) when A OR B are Low. Y

2input NAND

2 ‐ input NAND Y is high (PUN conducting) when A OR B are Low. Y

Y is high (PUN conducting) when A OR B are Low.

Y is low (PDN conducting) when A AND B are High.

2 ‐ input NAND Y is high (PUN conducting) when A OR B are Low. Y

A Complex Gate

A Complex Gate For PUN expression must be of Y in terms of the variables complements:

For PUN expression must be of Y in terms of the variables complements:

By DeMorgan’s Law:

A Complex Gate For PUN expression must be of Y in terms of the variables complements:
A Complex Gate For PUN expression must be of Y in terms of the variables complements:

A Complex Gate

A Complex Gate For PDN expression must be of in terms of the variables:

For PDN expression must be of

A Complex Gate For PDN expression must be of in terms of the variables:

in terms of the variables:

A Complex Gate For PDN expression must be of in terms of the variables:
A Complex Gate For PDN expression must be of in terms of the variables:

Complete Complex Gate

Complete Complex Gate Note: Two transistors per variable.
Complete Complex Gate Note: Two transistors per variable.
Complete Complex Gate Note: Two transistors per variable.

Note: Two transistors per variable.

PUN/PDN Duality

PUN/PDN Duality

Design by Duality

Design by Duality
Design by Duality
Design by Duality
Design by Duality

PUN

PUN XOR PUN
PUN XOR PUN

XOR PUN

PUN XOR PUN
PUN XOR PUN

XOR PDN

XOR PDN
XOR PDN

Complete XOR

Complete XOR Number of transistors is 12!
Complete XOR Number of transistors is 12!

Number of transistors is 12!

Transistor Sizing

Define:

I PUN = I PDN = I Inverter

Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and

and

Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and

recall

Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and
Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and
Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and
Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and
Similarly If
Similarly
If
Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and

then for two transistors

Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and

and

Transistor Sizing Define: PUN PDN Inverter and recall Similarly If then for two transistors and

Transistor Sizing Example1

Transistor Sizing Example ‐ 1 Design with worst case in mind.
Transistor Sizing Example ‐ 1 Design with worst case in mind.
Transistor Sizing Example ‐ 1 Design with worst case in mind.

Design with worst case in mind.

Transistor Sizing Example2

Let Calculate W/L for all transistors. PDN worst case: Q NB and (Q NC or Q
Let
Calculate W/L for all transistors.
PDN worst case:
Q NB and (Q NC or Q ND ) ON. → 2 transistors in series.

Transistor Sizing Example2

PUN worst case: Q PA and Q PC and Q PD ON. → 3 transistors in
PUN worst case:
Q PA and Q PC and Q PD ON. → 3 transistors in series.
Q PA and Q PB ON. → 2 transistors in series.
Q PA fixed:

Fanin & Fanout VS. Propagation Delay

Fan-in

additional input 2 extra transistors

chip area C EQ ↑ → t P

Fan-out

additional output C load ↑ → C EQ ↑ → t P

Also more complex circuits for both cases.

PseudoNMOS Inverter

Pseudo ‐ NMOS Inverter Advantages: - One gate per input. - Less loading capacitance. - Smaller

Advantages:

- One gate per input. -Less loading capacitance. - Smaller Area.

Pseudo ‐ NMOS Inverter Advantages: - One gate per input. - Less loading capacitance. - Smaller

PseudoNMOS Logic Static Characteristics

Pseudo ‐ NMOS Logic Static Characteristics Point E Q saturation: Q triode: Point A Q triode:

Point E Q P saturation:

Pseudo ‐ NMOS Logic Static Characteristics Point E Q saturation: Q triode: Point A Q triode:

Q N triode:

Q triode: Point A Q triode:

Point A Q P triode:

Pseudo ‐ NMOS Logic Static Characteristics Point E Q saturation: Q triode: Point A Q triode:

Ratioed Type

Pseudo ‐ NMOS Logic Static Characteristics Point E Q saturation: Q triode: Point A Q triode:

Q N saturation (cutoff):

Pseudo ‐ NMOS Logic Static Characteristics Point E Q saturation: Q triode: Point A Q triode:
Pseudo ‐ NMOS Logic Static Characteristics Point E Q saturation: Q triode: Point A Q triode:

PseudoNMOS Logic V OH and V OL

For v I =0 (point A)

Q P triode, Q N cutoff

Pseudo ‐ NMOS Logic V and V For v = 0 (point A) Q triode, Q
Pseudo ‐ NMOS Logic V and V For v = 0 (point A) Q triode, Q

For v I =V DD (point E)

Q P saturation, Q N triode

Pseudo ‐ NMOS Logic V and V For v = 0 (point A) Q triode, Q
Pseudo ‐ NMOS Logic V and V For v = 0 (point A) Q triode, Q

Gate conducts (static) current I stat !

Pseudo ‐ NMOS Logic V and V For v = 0 (point A) Q triode, Q

PseudoNMOS Logic VTC

Region I (AB) Q P triode, Q N cutoff

Region II (BC) Q P triode, Q N saturation

Region III (CD) Q P triode, Q N triode

Region IV(DE) Q P saturation, Q N triode

Pseudo ‐ NMOS Logic VTC Region I ( AB ) Q triode, Q cutoff Region II

PseudoNMOS Logic VTC Regions I & II

Pseudo ‐ NMOS Logic VTC Regions I & II Region I Q triode, Q cutoff Region

Region I Q P triode, Q N cutoff

Region II Q P triode, Q N saturation Setting
Region II
Q P triode, Q N saturation
Setting

PseudoNMOS Logic VTC Regions III & IV

Region III Q P triode, Q N triode Not significant.

Point C: Set v O =v I –V t in region II v O formula. Point
Point C: Set v O =v I –V t in region II
v O formula.
Point D: v O =V t
Region IV
Q P saturation, Q N triode
Setting
Pseudo ‐ NMOS Logic VTC Regions III & IV Region III Q triode, Q triode Not

PseudoNMOS Logic V OL & I stat

Set v I =V DD in region IV v O formula:

Pseudo ‐ NMOS Logic V & I Set v =V in region IV v formula: Static

Static current is Q P current in saturation

Pseudo ‐ NMOS Logic V & I Set v =V in region IV v formula: Static
Pseudo ‐ NMOS Logic V & I Set v =V in region IV v formula: Static

Noise Margins for PseudoNMOS Logic

Noise Margins for Pseudo ‐ NMOS Logic By controlling the ratio r=k /k we can adjust
Noise Margins for Pseudo ‐ NMOS Logic By controlling the ratio r=k /k we can adjust

By controlling the ratio r=k n /k p we can adjust the noise margins and V OL .

Noise Margins for Pseudo ‐ NMOS Logic By controlling the ratio r=k /k we can adjust

PseudoNMOS Dynamic Operation

t PLH

 

t PHL

Similar to CMOS.

Not so similar to CMOS.

Must subtract i from i .
Must subtract i from i .

Must subtract i DP from i DN .

PLH PHL Similar to CMOS. Not so similar to CMOS. Must subtract i from i
PLH PHL Similar to CMOS. Not so similar to CMOS. Must subtract i from i

If r is large the formulas will look identical but:

Pseudo ‐ NMOS Dynamic Operation PLH PHL Similar to CMOS. Not so similar to CMOS. Must

So t PLH will be r times t PHL . Asymmetrical delay.

PseudoNMOS Logic Design Considerations

Design of either P or N MOSFET ratio r and W/L is chosen. The design of the counterpart is determined by the ratio r.

Ratio r

Pseudo ‐ NMOS Logic Design Considerations Design of either P or N MOSFET ratio r and

V OL NML & NMH Asymmetry of t P (W/L) P (size)

 

C

Size

W/L

I Stat

 

P D t P

PseudoNMOS Logic Circuit

PDN same as for CMOS.

Pseudo ‐ NMOS Logic Circuit PDN same as for CMOS. Less transistors than CMOS. Most used

Less transistors than CMOS. Most used in RAMs, memory decoders, and when output is mostly high.

PassTransistor Logic (PTL)

TransmissionGate Logic

Use logic variables to connect another input variable to output.

Used with CMOS gates.

Pass ‐ Transistor Logic (PTL) Transmission ‐ Gate Logic Use logic variables to connect another input

PTL Switch Types

PTL Switch Types Single NMOS Two complimentary CMOS Transistors. CMOS Transmission Gate

Single NMOS Transistor

PTL Switch Types Single NMOS Two complimentary CMOS Transistors. CMOS Transmission Gate

Two complimentary CMOS Transistors.

CMOS Transmission Gate

PTL Needs Path to V DD /Ground

Y=AB

PTL Needs Path to V /Ground Y=AB B S 1 A Y High Closed Low Low

B

S 1

 

A

Y

High

Closed

 

Low

Low

Y=A

High

High

     

Was Low

Low

Low

Open

Y=?

 

Slow

Was High

Discharge!

Not a static combinational logic circuit!

PTL Path to V DD /Ground Solved

PTL Path to V /Ground Solved S low resistance path to ground. Every node must always

S 2 low resistance path to ground. Every node must always have a low resistance path to V DD or ground.

Single NMOS & Body Effect

Single NMOS & Body Effect When v goes high Q will be in saturation. Body Effect:

When v I goes high Q will be in saturation.

Body Effect:

Single NMOS & Body Effect When v goes high Q will be in saturation. Body Effect:
Single NMOS & Body Effect When v goes high Q will be in saturation. Body Effect:

Body connected to source at v O .

1- As v O V t and i D Charging will be slowed. 2- When v O =V DD -V t the current i D =0 V OH = V DD -V t (poor 1). 3- Because V OH = V DD -V t load Q P will conduct P D 0.

Restoration of V DD

v

O1

v

O1

Q R

Low

High

Off

Poor High

Low

On

When Q R is on it will charge C up to V DD (good High). Warning: Positive feedback!

Restoration of V O1 O1 Q R Low High Off Poor High Low On When Q

Or use special transistors with small V t preferably V t =0V.

CMOS Transmission Gates

CMOS Transmission Gates Switch=On V =V & V =V Q in saturation. & i is going

Switch=On V DSN =V DD & V GSN =V DD Q N in saturation.

CMOS Transmission Gates Switch=On V =V & V =V Q in saturation. & i is going
CMOS Transmission Gates Switch=On V =V & V =V Q in saturation. & i is going

& i DN is going down again!

What about Q P ? V DSP =-V DD & V GSP =-V DD Q P also in saturation.

CMOS Transmission Gates Switch=On V =V & V =V Q in saturation. & i is going

No body effect. Why?

Q P will continue to conduct after v O =|V tp | until v O =V DD = V OH .

Transmission Gate Vs. Single Transistor

Pros:

Improved t p because two transistors conduct giving higher current. Good V OH .

Cons:

Increased capacitance C because of two transistors. More complex circuit. More area.

PTL Example 1

PTL Example 1 2 to 1 MUX

2 to 1 MUX

PTL Example 2

PTL Example 2 XOR 8 transistors vs. 12 for CMOS.

XOR

8 transistors vs. 12 for CMOS.

Complementary PTL Example

AND NAND
AND
NAND

Use small V t or V t =0V.

Dynamic Logic Circuits

Basic principle: Storage of voltages on capacitors. Capacitors lose charge over time. Need refresh (clock).

Why dynamic logic?

1- Small number of transistors. 2- Static power dissipation is zero.

Dynamic Logic Operation Principle

Dynamic Logic Operation Principle Precharge: Q on, Q off → C charged to V =Y =V

Precharge: Q p on, Q e off C L charged to V DD =Y =V OH . Inputs settle.

Evaluate: Q p off, Q e on

F(A,B,C) high PDN off Y high,

t PLH =0

F(A,B,C) low PDN on Y low, V OL =0, t PHL 0

Q p W/L to fully charge C L during T Precharge

Dynamic Logic Characteristics 1

Noise Margins:

V IL V IH V tn

NML= V tn

NMH= V DD - V tn

NMLNMH

NML small

C L will discharge into the load gate. Clock cycle must be small to limit discharge.

Dynamic Logic Characteristics 1 Noise Margins: IL IH tn NML= V NMH= V - V NML

Dynamic Logic Characteristics 2

Dynamic Logic Characteristics 2 Charge Sharing Evaluation phase If Q on and Q off. C loses

Charge Sharing

Evaluation phase If Q 1 on and Q 2 off. C L loses some charge to C 1 v O decay.

Dynamic Logic Characteristics 2 Charge Sharing Evaluation phase If Q on and Q off. C loses

Solution

Dynamic Logic Characteristics 3

Dynamic Logic Circuits in Cascade

Evaluation phase In theory: A high Y 1 low Y 2 high In reality: Y 1 at V DD and discharging Q 2 will stay on until Y 1 drops to V t In the mean time Y 2 is discharging! v O < V DD (Poor One)

It doesnt work properly!

Dynamic Logic Characteristics 3 Dynamic Logic Circuits in Cascade Evaluation phase In theory: A high →

Domino CMOS Logic Circuits

(Dynamic Logic Circuits In Cascade)

Precharge Phase: Y low

Evaluation

Phase:

X high Y low,

t PHL =0

  • X low Y high,

t PLH 0

Will it work?

Domino CMOS Logic Circuits (Dynamic Logic Circuits In Cascade) Precharge Phase: Y low Evaluation Phase: X

Domino CMOS Logic Circuits 2

Precharge Phase:

X 1 high(V DD ) Y 1 low(0V) X 2 high(V DD ) Y 2 low(0V)

Evaluation Phase:

A high, φ C L1 discharges pulling X 1 down Wait until v X1 V t then Y 1 high(V DD )

C L2 discharges pulling X 2 down Wait until v X2 V t then Y 2 high(V DD )

Domino CMOS Logic Circuits 2 Precharge Phase: X high( V ) → Y low(0V) X high(

Delay

Small size + high speed + zero static power dissipation Difficult in design