Digital CMOS Logic Circuits
Sedra & Smith, Chapter 10
Inverter Circuit
CMOS Logic Gate Circuit
Similar structure to inverter:
Network of PMOS transistors
Network of NMOS transistors
PUN & PDN Basic Structure
Parallel → OR
Series → AND
Combinations of Basic Structures
Alternative (Digital) Symbols
PMOS Active Low: Transistor is conducting (activated) when input is low.
2‐input NOR
Y is high (PUN conducting) when A AND B are Low.
Y is low (PDN conducting) when A OR B is High.
2‐input NAND
Y is high (PUN conducting) when A OR B are Low.
Y is low (PDN conducting) when A AND B are High.
A Complex Gate
For PUN expression must be of Y in terms of the variables complements:
By DeMorgan’s Law:
A Complex Gate
For PDN expression must be of
in terms of the variables:
Complete Complex Gate
Note: Two transistors per variable.
Complete XOR
Number of transistors is 12!
Transistor Sizing
Define:
^{I} PUN ^{=} ^{I} PDN ^{=} ^{I} Inverter
and
recall
then for two transistors
and
Transistor Sizing Example‐1
Design with worst case in mind.
Transistor Sizing Example‐2
Let
Calculate W/L for all transistors.
PDN worst case:
Q NB and (Q NC or Q ND ) ON. → 2 transistors in series.
Transistor Sizing Example‐2
PUN worst case:
Q PA and Q PC and Q PD ON. → 3 transistors in series.
Q PA and Q PB ON. → 2 transistors in series.
Q PA fixed:
Fan‐in & Fan‐out VS. Propagation Delay
Fanin ↑
additional input → 2 extra transistors
^{→} ^{c}^{h}^{i}^{p} ^{a}^{r}^{e}^{a} ^{↑} → C _{E}_{Q} ↑ → t _{P} ↑
Fanout ↑
additional output → C _{l}_{o}_{a}_{d} ↑ → C _{E}_{Q} ↑ → t _{P} ↑
Also more complex circuits for both cases.
Pseudo‐NMOS Inverter
Advantages:
 One gate per input. Less loading capacitance.  Smaller Area.
Pseudo‐NMOS Logic Static Characteristics
Point E Q _{P} saturation:
Q _{N} triode:


Point A Q _{P} triode:

Ratioed Type
Q _{N} saturation (cutoff):
Pseudo‐NMOS Logic V _{O}_{H} and V _{O}_{L}
For v _{I} =0 (point A)
Q _{P} triode, Q _{N} cutoff
For v _{I} =V _{D}_{D} (point E)
Q _{P} saturation, Q _{N} triode
Gate conducts (static) current I _{s}_{t}_{a}_{t} !
Pseudo‐NMOS Logic VTC
Region I (AB) Q _{P} triode, Q _{N} cutoff
Region II (BC) Q _{P} triode, Q _{N} saturation
Region III (CD) Q _{P} triode, Q _{N} triode
Region IV(DE) Q _{P} saturation, Q _{N} triode
Region I Q _{P} triode, Q _{N} cutoff
Region II
Q P triode, Q N saturation
Setting
Pseudo‐NMOS Logic VTC Regions III & IV
Region III Q _{P} triode, Q _{N} triode Not significant.
Point C: Set v O =v I –V t in region II
v O formula.
Point D: v O =V t
Region IV
Q P saturation, Q N triode
Setting
Pseudo‐NMOS Logic V _{O}_{L} & I _{s}_{t}_{a}_{t}
Set v _{I} =V _{D}_{D} in region IV v _{O} formula:
Static current is Q _{P} current in saturation
Noise Margins for Pseudo‐NMOS Logic
By controlling the ratio r=k _{n} /k _{p} we can adjust the noise margins and V _{O}_{L} .
Pseudo‐NMOS Dynamic Operation
^{t} PLH


^{t} PHL

Similar to CMOS.

Not so similar to CMOS.



Must subtract i _{D}_{P} from i _{D}_{N} .



If r is large the formulas will look identical but:
So t _{P}_{L}_{H} will be r times t _{P}_{H}_{L} . → Asymmetrical delay.
Pseudo‐NMOS Logic Design Considerations
Design of either P or N MOSFET ratio r and W/L is chosen. The design of the counterpart is determined by the ratio r.
Ratio r ↑
V OL ↓ NML & NMH ↑ Asymmetry of t _{P} ↑ (W/L) _{P} (size) ↑

C ↓

Size ↓

W/L

↓

^{I} Stat ^{↓}


P D ↓ t P ↑

Pseudo‐NMOS Logic Circuit
PDN same as for CMOS.
Less transistors than CMOS. Most used in RAMs, memory decoders, and when output is mostly high.
Pass‐Transistor Logic (PTL)
Transmission‐Gate Logic
Use logic variables to connect another input variable to output.
Used with CMOS gates.
PTL Switch Types
Single NMOS _{T}_{r}_{a}_{n}_{s}_{i}_{s}_{t}_{o}_{r}
Two complimentary CMOS Transistors.
CMOS Transmission Gate
PTL Needs Path to V _{D}_{D} /Ground
Y=AB
B

S 1


A

Y

High

Closed


Low

Low

Y=A

High

High




Was Low

Low

Low

Open

Y=?


Slow

Was High

Discharge!

Not a static combinational logic circuit!
PTL Path to V _{D}_{D} /Ground Solved
S _{2} low resistance path to ground. Every node must always have a low resistance path to V _{D}_{D} or ground.
Single NMOS & Body Effect
When v _{I} goes high Q will be in saturation.
Body Effect:
Body connected to source at v _{O} .
1 As v _{O} ↑ → V _{t} ↑ and i _{D} ↓ → Charging will be slowed. 2 When v _{O} =V _{D}_{D} V _{t} the current i _{D} =0 → V _{O}_{H} = V _{D}_{D} V _{t} (poor 1). 3 Because V _{O}_{H} = V _{D}_{D} V _{t} load Q _{P} will conduct → P _{D} ≠0.
Restoration of V _{D}_{D}
^{v}


^{v}


Q R

Low

High

Off

Poor High

Low

On

When Q _{R} is on it will charge C up to V _{D}_{D} (good High). Warning: Positive feedback!
Or use special transistors with small V _{t} preferably V _{t} =0V.
CMOS Transmission Gates
Switch=On V _{D}_{S}_{N} =V _{D}_{D} & V _{G}_{S}_{N} =V _{D}_{D} Q _{N} in saturation.
& i _{D}_{N} is going down again!
What about Q _{P} ? V _{D}_{S}_{P} =V _{D}_{D} & V _{G}_{S}_{P} =V _{D}_{D} Q _{P} also in saturation.
No body effect. Why?
Q _{P} will continue to conduct after v _{O} =V _{t}_{p}  until v _{O} =V _{D}_{D} = V _{O}_{H} .
Transmission Gate Vs. Single Transistor
Pros:
‐Improved t _{p} because two transistors conduct giving higher current. ‐Good V _{O}_{H} .
Cons:
‐Increased capacitance C because of two transistors. ‐ More complex circuit. ‐ More area.
PTL Example 2
XOR
8 transistors vs. 12 for CMOS.
Complementary PTL Example
Use small V _{t} or V _{t} =0V.
Dynamic Logic Circuits
Basic principle: Storage of voltages on capacitors. Capacitors lose charge over time. Need refresh (clock).
Why dynamic logic?
1 Small number of transistors. 2 Static power dissipation is zero.
Dynamic Logic Operation Principle
Precharge: Q _{p} on, Q _{e} off → C _{L} charged to V _{D}_{D} =Y =V _{O}_{H} . Inputs settle.
Evaluate: Q _{p} off, Q _{e} on
F(A,B,C) high → PDN off → Y high,
t _{P}_{L}_{H} =0
F(A,B,C) low → PDN on → Y low, V _{O}_{L} =0, t _{P}_{H}_{L} ≠0
Q _{p} W/L to fully charge C _{L} during T _{P}_{r}_{e}_{c}_{h}_{a}_{r}_{g}_{e}
Dynamic Logic Characteristics 1
Noise Margins:
^{V} IL ^{≈} ^{V} IH ^{≈} ^{V} tn
NML= V _{t}_{n}
NMH= V _{D}_{D}  V _{t}_{n}
NML≠NMH
NML small
C _{L} will discharge into the load gate. Clock cycle must be small to limit discharge.
Charge Sharing
Evaluation phase If Q _{1} on and Q _{2} off. C _{L} loses some charge to C _{1} → v _{O} decay.
Solution
Dynamic Logic Characteristics 3
Dynamic Logic Circuits in Cascade
Evaluation phase In theory: A high → Y _{1} low → Y _{2} high In reality: Y _{1} at V _{D}_{D} and discharging Q _{2} will stay on until Y _{1} drops to V _{t} In the mean time Y _{2} is discharging! v _{O} < V _{D}_{D} (Poor One)
It doesn’t work properly!
Domino CMOS Logic Circuits
(Dynamic Logic Circuits In Cascade)
Precharge Phase: Y low
Evaluation
Phase:
X high → Y low,
t _{P}_{H}_{L} =0
t _{P}_{L}_{H} ≠0
Will it work?
Domino CMOS Logic Circuits 2
Precharge Phase:
X _{1} high(V _{D}_{D} ) → Y _{1} low(0V) X _{2} high(V _{D}_{D} ) → Y _{2} low(0V)
Evaluation Phase:
A high, φ ↑ C _{L}_{1} discharges pulling X _{1} down Wait until v _{X}_{1} ≤V _{t} then Y _{1} high(V _{D}_{D} )
C _{L}_{2} discharges pulling X _{2} down Wait until v _{X}_{2} ≤V _{t} then Y _{2} high(V _{D}_{D} )
Delay
Small size + high speed + zero static power dissipation Difficult in design