EELE 367 – Logic Design Lab #7 – Introduction to Counters & Logic Analyzers

Lab Description This lab will introduce you to modeling counters in VHDL using the “+1” operation. You will be provided with a set of VHDL files that implement a 16-bit binary counter that is displayed on LEDR[15:0] on the DE2 project board. The clock that drives the counter is ran through a programmable clock divider with produces 32 different frequency selections by using SW[4:0]. The system clock is 50MHz and can be divided down as low as 23mHz (T=43s) This lab will also introduce you to a piece of test equipment called a logic analyzer. A logic analyzer is an instrument to debug digital systems. It is similar to an oscilloscope in that you passively observe signals on your system using a probe. The difference is that instead of measuring the analog voltage of your signal, it measures the digital value. A programmable threshold within the logic analyzer is used to determine whether your signal is a 0 or a 1. A logic analyzer contains many channels which make it useful for digital signals (i.e., 16+). The logic analyzer has trigger functions which can search for patterns or sequences of patterns in order to display data around events of interest. The logic analyzer has an adjustable sample rate and adjustable memory depth. Demo #1 – Running the Counter and Taking a Logic Analyzer Measurement Download the three vhd files from the course website: logic_analyzer_demo.vhd (top level) clock_div.vhd dflipflop.vhd

Create a Quartus project using these three files. The pin assignments in this design are given in the DE2_pin_assignments.csv file on the course website so you will need to import that. Once you get your project created, download the design to the FPGA board and make sure the counter is running. You should see a binary counter on the Red LEDs. You should be able to change the frequency of the count using the SW[4:0] switches. The SW[4:0] switches are also shown on the Green LEDs. You can reset the counter by pressing the KEY0 button. If all the Red LEDs are ON, the counter is probably running to0 fast. Slow it down using the SW[4:0] switches. If the counter is stuck at a certain value, it is probably running too slow. At the slowest setting, the counter will update every 43s. Speed it up using SW[4:0]. Now we want to take a logic analyzer measurement of the counter. If you look at the top level VHDL file for this design, you’ll notice that there is a signal vector called “Logic_Analyzer_Port[16:0]”. This vector is routed to the GPIO_0 pins on connector JP1 on the DE2 board. If you look at the DE2 board, you’ll notice that there are 17 logic analyzer probes connected to the board. We will leave these probes connected to these pins for the rest of the semester. That means you can use the “Logic_Analyzer_Port[16:0]” and the GPIO_0 assignments in this example as a “debug port” for your designs for the rest of the semester.

The TLA software will appear. Launch the Tektronix Logic Analyzer Software by double clicking on the TLA Application icon . The analyzer probes are plugged into the A2 and A3 inputs of the instrument. If you notice in the logic_analyzer_demo.You can simply assign whatever signals you want to observe to the Logic_Analyzer_Port[16:0] vector and they will be probed by the logic analyzer. 2. First.A TLA Connection dialog will appear. 1.vhd file. Setup the Signal Groups The analyzer probes are already plugged into the project board. This clock will have different frequencies based on the SW[4:0] settings. . If you notice in the logic_analyzer_demo. Signals can be included in multiple groups. You can create any arbitrary group of signals within the analyzer with descriptive names to make the measurement results more readable. You can log into the analyzer using your student account. You can also use Remote Desktop Connection on your workstation to login to the instrument. Using RDC gives a little larger display. we are going to create one signal group that contains 16 signals to observe the counter being displayed on LEDR[15:0]. There are 17 digital channels that are connected to the analyzer. the Clock is assigned to Logic_Analyzer_Port(16) in addition to being used by the counter process. the counter is assigned to both LEDR[15:0] and Logic_Analyzer_Port[15:0]. A2 has 8-channels and A3 has 8-Channels + a clock/bonus channel. We will also create a signal group that contains the clock that drives the counter. you need to log into the logic analyzer. For this lab.vhd file. Select “Local” and click “Connect”.

enter “Counter”.Highlight signals A3(7) through A2(0). right click and delete it.Highlight signal CK0(). .The 17 channels of the analyzer are probing the following signals on our DE2 board TLA Name A3-CK0() A3(7) A3(6) A3(5) A3(4) A3(3) A3(2) A3(1) A3(0) A2(7) A2(6) A2(5) A2(4) A2(3) A2(2) A2(1) A2(0) DE2 Signal GPIO_0(33) GPIO_0(31) GPIO_0(29) GPIO_0(27) GPIO_0(25) GPIO_0(23) GPIO_0(21) GPIO_0(19) GPIO_0(17) GPIO_0(15) GPIO_0(13) GPIO_0(11) GPIO_0(9) GPIO_0(7) GPIO_0(5) GPIO_0(3) GPIO_0(1) “Logic_Analyzer_Port” Vector Name Logic_Analyzer_Port(16) Logic_Analyzer_Port(15) Logic_Analyzer_Port(14) Logic_Analyzer_Port(13) Logic_Analyzer_Port(12) Logic_Analyzer_Port(11) Logic_Analyzer_Port(10) Logic_Analyzer_Port(9) Logic_Analyzer_Port(8) Logic_Analyzer_Port(7) Logic_Analyzer_Port(6) Logic_Analyzer_Port(5) Logic_Analyzer_Port(4) Logic_Analyzer_Port(3) Logic_Analyzer_Port(2) Logic_Analyzer_Port(1) Logic_Analyzer_Port(0) . A dialog will appear on the right side of the screen. There is a default field called “New Group”. put your mouse over this field. Give it the name “Clock”. Right Click and choose “Create Group from Selected Signals”. . Right Click and choose “Create Group from Selected Signals”. You can click-and-drag or use the CNTL key to select multiple signals.Click on the “Setup” button at the top of the window. . In the field that says <Enter Group Name>.

On the Easy Trigger tab.3v. For our first measurement. Set the storage to 1M. For this measurement. We tell the analyzer where the middle is using the Global Threshold. let’s set the trigger when Counter=0. you would need to alter the switching threshold.3v CMOS. Since a 50MHz count translates to a period of 20ns period. 6. A 16-bit counter will go from 0 to 65. we will run the counter at 50MHz. The signals on the GPIO_0 port are 3. Setup the Storage We also need to set how many samples we will take. We need to be aware of the sample rate of the measurement relative to the speed of the signal or we will take all our samples within one count value. the period of the counter will get larger and larger. . If you ever need to measure a digital signal with a different logic level.5v. . In order for the logic analyzer to tell when something is a 1 or a 0.5v. Setup the Threshold Voltage The logic analyzer can be used to measure digital signals of any voltage level. So if wanted to see the entire counter range. This means we want to sample fast enough to get multiple samples during each count. The default threshold is 1. it must know where the middle of the signal is. we can leave the default setting at 1. You can run the analyzer without specifying a trigger but the data that is collected might not be around the time of interest that you are looking for. We want to store a sufficient amount of samples so that we can see most of the counter values.535. This corresponds to 500M Samples/second.3. Note that as we slow down the counter. let’s set the sample rate to 2ns to get ~10 samples per count. meaning that they swing from 0v to 3. we would need to store >10x65k. You can configure how fast the analyzer samples in addition to how many samples the analyzer will store. it will store the digital value of each signal into memory. 5. choose Simple Events – Trigger on group value . Setup the Trigger The trigger in a logic analyzer represents the point at which the instrument will start storing data. 4. For our lab.Now choose the group as “Counter” and set the value to HEX 0000. Setup the Sampling (Asynchronous) Each time the logic analyzer samples the signal. .Click the “Trigger” button at the top of the window.

Click the “Run” button at the top of the window. Add the Counter and Clock group to the waveform window . You should now see waveform data. choose Counter and Clock and click “Add”. Run the Analyzer . Right-click on the waveform and select Zoom-All to see the entire measurement. You can change the base of the waveform by right-clicking on the signal name on the left.On the left under Waveform.Click on the Waveform button at the top of the window .buttons. . Click “Close” 8. right click and select “Add Waveform”.7. Put your counter into DECIMAL. Zoom in/out by clicking on the +/.

take a look at the counter process. you’ll see a set of pre-defined measurements. Turn in the check-off sheet at the end of lab.At the bottom of the waveform window. You will see the frequency of the clock now at the bottom of the waveform window.9. Demo #2 – Creating an UP/DOWN Counter and Taking a Logic Analyzer Measurement Now you are going to modify the counter design provided to add the functionality to count either UP or DOWN based on the value of SW17. Click RUN again and see if your measurement updates. Put it into DOWN mode and run the clock at 6. Measure the Frequency of the Clock . Change the clock frequency to 25MHz by switching SW0. You should have enough knowledge at this point to modify the code provided. . Show your waveform to the lab instructor for Demo #1. 11. Specifcally. Click on the “Save” icon and put the configuration file in your project directory. Setup the logic analyzer to trigger when it sees a pattern of 222 followed by 221. Show your waveform to the lab instructor for Demo#2. Drag the “Frequency” measurement onto the Clock waveform and drop it. 10.25MHz. Save your configuration file All of the setup you did can be saved so that next lab you will not need to redo it. Could you add an additional if/then statement to account for the UP/DOWN functionality? Will a “-1” also work with these date types? Once you get your counter going UP and DOWN. Put a Period measurement on your clock signal (it should be 160ns).

EELE 367 – Logic Design Instructor Verification Sheet Lab #7 Counters & Logic Analyzers Name(s) : _______________________ / ________________________ Show the lab instructor the following demos: Demo #1: Binary Counter and Logic Analyzer Measurement (5 points) Verified By: ___________________ Date: ______________ Demo #2: UP/DOWN Binary Counter and Logic Analyzer Measurement (5 points) Verified By: ___________________ Date: ______________ .

Sign up to vote on this title
UsefulNot useful