PART I

BASIC DIGITAL CIRCUITS

we cover the more sophisticated VHDL operators and constructs and examine module-level combinational circuits. By Pong P. The language is formally defined by IEEE Standard 1076. Detailed VHDL coverage may be explored through the sources listed in the Bibliography. The description uses only logical operators and represents a gate-level combinational circuit. we use a simple comparator to illustrate the skeleton of a VHDL program. The focus of this book is on hardware design rather than the language.Chu Copyright @ 2008 John Wiley & Sons.S. Department of Defense and later transferred to the IEEE (Institute of Electrical and Electronics Engineers).CHAPTER 1 GATE-LEVEL COMBINATIONAL CIRCUIT 1. In Chapter 3. we introduce the key VHDL synthesis constructs by examining a collection of examples. FPGA Prototyping by VHDL Examples. In this chapter. This book mainly follows the revision in 1993 (referred to as VHDL 93). which are composed of intermediate-sized components.” It was originally sponsored by the U. comparators. and multiplexers. Inc. The standard was ratified in 1987 (referred to as VHDL 87). 1 . VHDL is intended for describing and modeling a digital system at various levels and is an extremely complex language. such as adders. and revised several times. which is composed of simple logic gates.1 INTRODUCTION VHDL stands for “VHSIC (very high-speed integrated circuit) hardware description language. Instead of covering every aspect of VHDL.

il’ + One possible corresponding VHDL code is shown in Listing 1.a r c h .1 Gate-level implementation of a 1-bit comparator l i b r a r y ieee. and xor cells. One way to describe the circuit is to use a sum-of-products format. Listing 1. or. p i : std-logic. begin -. i l : in s t d . The truth table of this circuit is shown in Table 1.p r o d u c t t e r m s p 0 <= ( n o t i0) and ( n o t il). The eq signal is asserted when i0 and i l are equal. In this book. The logic expression is eq = iO . a r c h i t e c t u r e s o p . and an output. il iO’ . to implement the circuit.2 GATE-LEVEL COMBINATIONAL CIRCUIT Table 1.l o g i c .1 Basic lexical rules VHDL is case insensitive. 10 5 1.all. e n t i t y eql i s port ( i 0 .a r c h o f eql i s s i g n a l P O .2 GENERAL DESCRIPTION Consider a 1-bit equality comparator with two inputs. . which means that upper.and lowercase letters can be used interchangeably. 1s 1. use ieee. We examine the language constructs and statements of this code in the following subsections.s u m o f t w o p r o d u c t t e r m s eq <= PO or p l . which means that spaces and blank lines can be inserted freely. which include not. Assume that we want to use basic logic gates.std-logic-ll64. i 0 and ii. -. and free formatting.1 Truth table of a 1-bit equality comparator input iOil 00 01 10 11 output eq 1 0 0 1 1. It is good practice to add proper spaces to make the code clear and to associate special meaning with cases. p l <= i 0 and i l .1. end s o p . we reserve uppercase letters for constants. and. eq: ou t std-logic end e q l .2. eq.1.

logical 1. 1. The first line indicates that the name of the circuit is e q l . and ’ Z ’ . mainly the s t d . The two statements are needed because a special data type is used in the code.GENERAL DESCRIPTION 3 An identiJier is the name of an object and is composed of 26 letters. e q : out std-logic end e q l . The basic format for an I/O port declaration is signal-namel. which means that an object must have a data type and only the defined values and operations can be applied to the object. The comments start with -. which stand for “uninitialized” and “unknown” (e. digits. The other four values. ’U’ and ’X’. The mode term can be in or out. may be encountered in simulation. Three of the values.. i l : i n s t d . It can also be inout. The identifier must start with a letter.’ . and the underscore (-).. can be synthesized.l o g i c type and its variants. 1. ’ I ’ . : mode data-type. are not used in this book. and the port section specifies the I/O signals. invoke the std-logic-1164 package from the i e e e library. a l l .2. essentially outlines the I/O signals of the circuit. ’ H’. In this book. ’L ’ .and the text after it is ignored. use ieee.std-logic-1164. ’0 ’ . and high impedance.l o g i c type is defined in the std-logic-I164 package and consists of nine values.3 Entity declaration The entity declaration e n t i t y eql i s port ( i0. which indicates that the corresponding signals flow “into” or “out of” of the circuit. to VHDL. when signals with ’ 0’ and ’ 1’ values are tied together).2 this is a comment Library and package The first two lines. which stand for logical 0. our discussion is limited to a small set of predefined types that are suitable for synthesis. std-logic type The s t d .. The package and library allow us to add additional types. functions. and the comments are shown in italics type. Two values. and data-busl-enable. as in i0.i l . operators. etc.g. ). the VHDL keywords are shown in boldface type. signal-name2.4 Data type and operators VHDL is a strongly typed language. .2. .2. ’ . Although VHDL is rich in data types. as in __ 1. l i b r a r y ieee. and ’W ’. as in entity.l o g i c . for bidirectional signals.

which specifies constants. Two internal signals are declared in this program: s i g n a l PO.a r c h . It can be declared as a : i n s t d . When PO or p i changes its value. or.5 Architecture body The architecture body. The architecture body may include an optional declaration section. consider the statement eq <= PO or p l . and thus the body is identified by the name sop-arch (“sum-of-products architecture”). and. contains three concurrent statements. and so on. or. It is a circuit that performs the or operation. For example. a r c h i t e c t u r e s o p . Note that the and. p l : std-logic. . and xor. this statement is activated and the expression is evaluated. We generally avoid this format since it is more natural to associate the MSB with the leftmost position. The main description. in which the statements are executed sequentially.l o g i c . are defined over the std-logic-vector and s t d .a r c h of eql i s s i g n a l PO. which is defined as an array with elements of std-logic. internal signals. -. and the expression specifies the circuit function and corresponding input signals. The new value is assigned to eq after the default propagation delay. -- describes operation of the circuit. encompassed between begin and end. and xor operators have the same precedence and we need to use parentheses to specify the desired order of evaluation. let a be an 8-bit input port. p l <= i 0 and i l .p r o d u c t terms PO <= ( n o t i 0 ) and ( n o t il). The std-logic-vector data type. Unlike a program in C language.l o g i c data type. end s o p . The array can also be declared in ascending order: a : in std-logic-vector(0 to 7 ) . Logical operators Several logical operators.v e c t o r ( 7 downto 0 ) . VHDL allows multiple bodies associated with an entity. including not. We can use term like a (7 downto 4) to specify a desired range and term like a ( 1) to access a single element of the array.2. Bit-wise operation is used when an operator is applied to an object with the std-logic-vector data type. The signal on the left-hand side of a statement can be considered as the output of that part. p l : std-logic. as in ( a and b ) or (c and d) 1. For example. begin sum o f t w o p r o d u c t t e r m s eq <= PO or p l . can be used for this purpose. concurrent statements are like circuit parts that operate in parallel.4 GATE-LEVEL COMBINATIONAL CIRCUIT A signal in a digital circuit frequently contains multiple bits.

x p 3 <= ( a ( 1 ) and b ( 1 ) ) and ( a ( 0 ) and b ( 0 ) ) .p2.p3: s t d .l o g i c . p2.pl.sum of product terms a e q b <= P O or p l o r p 2 or p 3 . The order of the concurrent statements is clearly irrelevant and the statements can be rearranged arbitrarily. The graphical representation of this program is shown in Figure 1. The aeqb signal is asserted when both bits of a and b are equal. The code is shown in Listing 1. s t d . p 2 <= ( a ( 1 ) and b ( 1 ) ) and ( ( n o t a ( 0 ) ) and ( n o t b ( 0 ) ) ) . 1.a r c h . Derivation of the architecture body is similar to that of a 1-bit comparator.p r o d u c t terms P O < = ( ( n o t a ( 1 ) ) and ( n o t b ( 1 ) ) ) and ( ( n o t a ( 0 ) ) and ( n o t b ( 0 ) ) ) . aeqb. a l l .2 Gate-level implementation of a 2-bit comparator library i e e e . 10 downto 0 ) . p i . and the final result. I5 -. The connections among these parts are implicitly specified by the signal and port names.2.GENERAL DESCRIPTION 5 (not i0) and (not il) PO or p l Figure 1. .1. use i e e e . a r c h i t e c t u r e s o p . p l <= ( ( n o t a ( 1 ) ) and ( n o t b ( 1 ) ) ) and ( a ( 0 ) and b ( 0 ) ) .1 Graphical representation of a comparator program. e n t i t y eq2 i s port ( a . and p3 signals represent the results of the four product terms. ). The three circuit parts represent the three concurrent statements.1 1 6 4 .2.l o g i c . begin -. b : in s t d . end s o p . Listing 1. Let the input be a and b and the output be aeqb. is the logic expression in sum-of-products format.a r c h of eq2 i s signal pO. The PO.6 Code of a 2-bit comparator We can expand the comparator to 2-bit inputs.l o g i c end e q 2 .l o g i c .v e c t o r ( 1 a e q b : out s t d . The a and b ports are now declared as a two-element std-logic-vector.

formal-s i g n a l = > actual-s ignal . eql ( s o p . e q .6 is to utilize the previously constructed 1-bit comparators as the building blocks. This allows us to build a large system from simpler or predesigned components.2.b i t 0 .2.a a n d b a r e equal i f i n d i v i d u a l b i t s are equal a e q b <= eO and e l . ).3 STRUCTURAL DESCRIPTION A digital system is frequently composed of several smaller subsystems.i n s t a n t i a t e t w o 1 . e q = > e O ) . This type of code is called structural description.e. which library) the component resides. end s t r u c . entity-name (arch-name) p o r t map( formal-signal=>actual-signal. whose syntax is: unit-label : e n t i t y lib-name.a r c h . il=>b(O).u n i t : e n t i t y w o r k . eql ( s o p . The u n i t . Note that the entity declaration is the same and thus is not included. known as component instantiation.3 Structural description of a 2-bit comparator a r c h i t e c t u r e s t r u c . 1..a r c h of e q 2 i s s i g n a l eO. to perform this task. eq=>el).3. The diagram is shown in Figure 1. The first portion of the statement specifies which component is used.6 GATE-LEVEL COMBINATIONAL CIRCUIT Figure 1. An alternative to the design of the 2-bit comparator of Section 1. il=>b(i). The aeqb signal is asserted only when the two bits are equal. begin _.a r c h ) p o r t m a p ( i O = > a ( O ) . el: std-logic. and the e n t i t y n a m e and archname terms indicate the names of the .u n i t : e n t i t y w o r k . -. VHDL provides a mechanism. in which two 1-bit comparators are used to check the two individual bits and their results are fed to an and cell. The corresponding code is shown in Listing 1.b i t l . 5 KI The code includes two component instantiation statements. the l i b n a m e term indicates where (i.b i t comparators e q .a r c h ) p o r t m a p ( i O = > a ( l ) .2 Construction of a 2-bit comparator from 1-bit comparators.l a b e l term gives a unique id for an instance. Listing 1.

i l = > b ( O ) . Although it is a clumsy way for humans to comprehend a diagram. The code is essentially a textual description of a schematic. Listing 1.u n i t : e n t i t y work. e l : std-logic. and actual signals. in which a component must first be declared (i.8 7 .2.u s e t h e d e c l a r e d n a m e . signal eO. which are I/O ports declared in a component’s entity declaration. which are the signals used in the architecture body. 10 I5 Note that the original clause. The code in this format is shown in Listing 1. eq=>el). The port mapping reflects the connections shown in Figure 1.b i t comparators eq-bit0-unit : eql -. which indicates the connection between formal signals. The second portion is port mapping.l o g i c . eq=>eO). i l = > b ( l ) . This example demonstrates the close relationship between a block diagram and code. The Xilinx ISE package includes a simple schematic editor utility that can perform schematic Xilinx capture in graphic format and then convert the diagram into an HDL structural description. -.e.c o m p o n e n t d e c 1 a r a t i o n component e q l port ( i 0 . e q . end vhd-87-arch. i l = > b ( O ) .a a n d b a r e e q u a l if i n d i v i d u a l b i t s a r e e q u a l a e q b <= eO a n d e l . e q l port map(iO=>a(O).a r c h of e q 2 i s _.b i t 0 . The component instantiation statement is also a concurrent statement and represents a circuit that is encompassed in a “black box” whose function is defined in another module.a r c h ) is replaced by a clause with the declared component name eq-bit0-unit: eql . Older codes may use the mechanism in VHDL 87. The archname term is optional. If it is omitted. The first component instantiation statement is e q . made known) and then used. and eql and sop-arch are the names of the entity and architecture defined in Listing 1. e q l ( s o p .u n i t : e n t i t y work. specific The component instantiation statement is added in VHDL 93.u s e t h e d e c l a r e d n a m e .. i l : in s t d . eq: out std-logic end c o m p o n e n t . it puts all representations into a single HDL framework. e q l ( s o p . the last compiled architecture body will be used. e q = > e O ). The work library is the default library in which the compiled entity and architecture units are stored.4 Structural description with VHDL-87 a r c h i t e c t u r e v h d .4. begin __ i n s t a n t i a t e t w o 1 .b i t 0 .1. eq-bitl-unit : eql -.STRUCTURAL DESCRIPTION 7 entity and architecture. e q l port map(iO=>a(l). ).a r c h ) p o r t m a p ( i O = > a ( O ) .

__ t e s t v e c t o r 3 25 t e s t . __ t e s t v e c t o r g e n e r a t o r process 15 begin __ t e s t v e c t o r I t e s t . a l l . use i e e e .i n 1 <= " 0 0 " w a i t f o r 200 n s . known as a testbench. entity eq2-testbench is end e q 2 .3 Testbench for a 2-bit comparator. Listing 1.i n 0 <= " 0 0 " .a r c h o f e q 2 .i n s t a n t i a t e the c i r c u i t under t e s t u u t : e n t i t y work. signal test-out : std-logic.3. We create a special program. the t e s t v e c t o r g e n e r a t o r block generates testing input patterns.i n 0 <= " 0 1 " . aeqb=>test-out) . 5 a r c h i t e c t u r e t b. to mimic a physical lab bench. w a i t f o r 200 n s . e q 2 ( s t r u c _ a r c h ) port rnap(a=>test-inO.l o g i c .5. it can be simulated in a host computer to verify the correctness of the circuit operation and can be synthesized to a physical device.i n 0 . and the monitor block examines the output responses.i n 1 <= " 1 1 " . The sketch of a 2-bit comparator testbench program is shown in Figure 1.l o g i c .t e s t b e n c h .t e s t b e n c h i s s i g n a l t e s t . t e s t . The u u t block is the unit under test.v e c t o r (1 d o w n t o 0) . 20 __ t e s t v e c t o r 2 t e s t .4 TESTBENCH After code is developed.1 1 6 4 . A simple testbench for the 2-bit comparator is shown in Listing 1. t e s t . t e s t . b=>test-in1 . s t d . __ t e s t v e c t o r 4 .i n 1 <= " 0 0 " w a i t f o r 200 n s . 1.i n 1 : s t d . Simulation is usually performed within the same HDL framework.5 Testbench for a 2-bit comparator library ieee.i n 0 <= " 0 1 " t e s t . begin 10 -.8 GATE-LEVEL COMBINATIONALCIRCUIT test vector generator -test-in-0 test-in-l a b eq2 aeqb test-out - monitor Figure 1.

4s end p r o c e s s . The process statement is a special VHDL construct in which the operations are performed sequentially. and Scalability provides a comprehensive discussion on developing effective. __ test vector 2 test-in0 <= "01". The code consists of a component instantiation statement. The first two statements specify the values for the t e s t . and the third indicates that the two values will last for 200 ns. The Designer's Guide to VHDL by P. Ashenden provides detailed coverage of the language's syntax and constructs.i n 1 signals. by J. We can substitute the uut instance and modify the test patterns according to the new circuit. which can be treated as a "virtual logic analyzer. __ t e s t v e c t o r 7 test-in0 <= " 1 1 " test-in1 <= "01". The code has no monitor. We can observe the input and output waveforms on a simulator's display. A comprehensive bibliography is included at the end of the book. J.5 BIBLIOGRAPHIC NOTES A short bibliographic section appears at the end of each chapter to provide some of the most relevant references for further exploration. VHDL is a complex language. The author's RTL Hardware Design Using VHDL: Codingfor EfJiciency. which generates a sequence of test patterns." The simulated timing diagram of this testbench is shown in Figure 2. Each test pattern is generated by three statements. 2nd edition.BIBLIOGRAPHIC NOTES 9 30 35 10 test-in0 <= "10" test-in1 <= " 1 0 " w a i t for 200 ns. Writing code for a comprehensive test vector generator and a monitor requires detailed knowledge of VHDL and is beyond the scope of this book. which creates an instance of a 2-bit comparator. The derivation of the testbench for a large digital system is a difficult task. synthesizable codes. .i n 0 and t e s t . and a process statement. end tb-arch. w a i t f o r 2 0 0 ns. For example. w a i t for 200 ns. Bergeron focuses on this topic. Portability. test-in1 <= "00". __ t e s t v e c t o r 6 test-in0 <= " 1 1 " test-in1 <= " 1 1 " w a i t f o r 200 n s . Writing Testbenches: Functional VeriJicationof HDL Models. __ t e s t v e c t o r 5 test-in0 <= " 1 0 " test-in1 <= "00" w a i t for 200 n s . 1.16. This listing can serve as a testbench template for other combinational circuits.

The experiments help us to better understand the concepts and provide a hands-on opportunity to design and debug actual circuits. 1.6.9.2 Code for gate-level binary decoder Develop the HDL codes in Experiment 2. The code can be simulated and synthesized after we complete Chapter 2.6.1.9. some experiments are suggested as exercises. The code can be simulated and synthesized after we complete Chapter 2. .10 GATE-LEVELCOMBINATIONAL CIRCUIl 1.6 SUGGESTED EXPERIMENTS At the end of each chapter.2. 1.1 Code for gate-level greater-than circuit Develop the HDL codes in Experiment 2.

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