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Wired: Wire-Aware Circuit Design WireIntel custom project, funded by the Semiconductor Research Corporation (SRC) Corporation

Emil Axelsson Mary Sheeran and Koen Claessen

Chalmers University of Technology For CHARME 2005

Theres a whole world beneath the netlist

Physical design stage introduces wires

Only implicitly present in netlist Real physical objects with associated side-effects

Down-scaling chip technologies

Active devices gain performance Wires dont (on average) Non-ideal wire effects exposed
E.g. ratio of wire/gate delay increases

Wires already dominating

75% of path delays, and 50% of power consumption

Wire-aware design flow

Traditional models abstract away from wires
The designer looses important control over performance Sub-optimal solutions Higher time-to-market

Urgent need to take wires into account from start

Formal verification?
Broaden the view of formal verification to also include nonnon-functional properties FV community must realize the functional FV community must realize the functional design concerns are not enough enough design concerns are not enough enough
(Wolfgang Roesner (IBM) at CHARME03) (Wolfgang Roesner (IBM) at CHARME03)

Non-functional property checking

Our approach
Explicit wires! Requires detailed explicit layout low-level design?
Yes, but in a high-level, language-based system

Embedding in functional programming language Haskell raises abstraction level

Our approach
Connection patterns raise level further
bitMult = row bitMult1

Functional, non-functional and geometrical aspects all modeled Our system is called Wired

Related work
Behavior and layout

Adds meta-programming

Interconnect-aware synthesis of arithmetic modules Physically knowledgeable synthesis (PKS)

Automatic integration of logical and physical design stages Cadence, Synopsys, Magma

Wired in short I
A description is either
Primitive defined by a surface and a surface relation Compound defined by two subdescriptions and a combinator
R1 R


A surface is a structure of contact segments Relation propagates constraints across the surface
Both structural and behavioral constraints

Wired in short II
The surface structure may be partially unspecified Description surface and context surface must be equal
Context surface

Instantiation engine solves the unknown surfaces using this constraint and the surface relations Example stretchy wires:

Wired in short III

Generic description
Awaits surface info from context, and then instantiates

Instantiation encoded as a Haskell function
Allows clever choices

Used to describe recursive connection patterns

Most common row row:
row D D row D

Parallel prefix
Central component in CPUs
Carry computation in look-ahead adders Priority encoders
sklansky 0 sklansky 0 = thinEmptyX1 = thinEmptyX1 sklansky dep = join *=~ (subSklansky ~||~ subSklansky) sklansky dep = join *=~ (subSklansky ~||~ subSklansky) where where subSklansky = sklansky (dep-1) subSklansky = sklansky (dep-1) join = (row w1 ~||* w3) -||- (row d2 ~||* d) join = (row w1 ~||* w3) -||- (row d2 ~||* d) where (d,d2,w1,_,w3,_) = params2 where (d,d2,w1,_,w3,_) = params params2 params

sklansky 0 sklansky 0 = thinEmptyX1 = thinEmptyX1 sklansky dep = join *=~ (subSklansky ~||~ subSklansky) sklansky dep = join *=~ (subSklansky ~||~ subSklansky) where where subSklansky = sklansky (dep-1) subSklansky = sklansky (dep-1) join = (row w1 ~||* w3) -||- (row d2 ~||* d) join = (row w1 ~||* w3) -||- (row d2 ~||* d) where (d,d2,w1,_,w3,_) = params2 where (d,d2,w1,_,w3,_) = params2

New parallel prefix structure

New structure with low fanout (here 67 inputs) Non-trivial structure; 50 lines of code

(Non-)functional analysis
The user makes statements about connections, e.g.:
Signals s1 and s2 are connected over distance d :


The actual relation depends on signal interpretation (NSI)

Logical value (standard interpretation) Direction (in/out) Unit delay Drive resistance / load capacitance RC-delay

RC-delay; bi-directional analysis

r, c l
modeled as

R = rr ll R=

C = c ll C=c delay RC // 2 delay RC 2

Composition with fanout (Elmore approximation)

R1,C1 R0, C0
0 1


R3, C3

delay delay R00C00 // 2 + R33C33 // 2 RC 2+RC 2

+ R00 ((C1 + C22 + C33+ C44) + R C1 + C + C + C )

R4, C4


Bi-directional analysis
No magic
The primitives know how to propagate values locally Instantiation engine propagates values globally

Functional setting and symbolic evaluation

Forwards analysis

Relational setting
Bi-direcional analysis

Why not external analysis?

Quick evaluation of different alternatives Analysis can be used to guide instantiation adaptive descriptions
s1 s2 s3

delay s1 < delay s3

s1 s2 s3 s1 s2 s3

& &


& &

M. Sheeran. Generating fast multipliers using clever circuits. FMCAD 2004.

What has been done?

Instantiation engine Primitives, combinators, connection patterns Analysis (all of the above) Browser/debugger Output: currently postscript layout

Who should use Wired?

Low-level designers
Hide boring details in patterns Quick evaluation of different layout alternatives

Module designers
Wired descriptions can be made
Highly parameterized Context-sensitive


Future work
Examples: Adaptive circuits (low-power), Output
Real layout (VLSI project) Netlist (timed VHDL)

Analysis: Crosstalk, Semantics