Fundamentals of Digital Logic andhficrocomputer Design. M. Rafiquzzaman Copyright 02005 John Wiley & Sons, Inc.

APPENDIX

68000 INSTRUCTION SET
Instruction Size Length
1 1 1 1 2 for B, W

G

Operation

ABCD - (Ay), - (AX) ABCD Dy, Dx ADD ( E N , (EA) ADDA (EA), An ADD1 #data, (EA) ADDQ #data, (EA) ADDX - (AYL - ('4x1 ADDX Dy, Dx AND (EA), (EA) ANDI #data, (EA) ANDI #data& CCR ANDI #datal6, SR ASL Dx, Dy

3 for L 1 1 1
1

-[Ay] lo+-[Ax] I O + X + [ A x ] [DyllO + [DxIlO +X + Dx [EA] + [EA] EA [EA] + An -+ An data + [EA] EA

-

-

- [Ay]

2 for B, W 3 for L 2 2
1

data + [EA] + EA + - [AX]+ X Dy + Dx + X + Dx [EA] [EA] EA data A [EA] EA

--

+

[AX]

data8 A [CCR] + CCR data16 [SR] + SR if s = 1; else trap

numher of shifts dercmiincd by I l h ]

ASL #data, Dy

1

1)).

]

4

0

ASL (EA)

1

ASR Dx, Dy

B,W,L

1

ASR #data, Dy

B,W,L

1

ASR (EA)

B,W,L

I

695

(EA) BCHG #data. specified by Dn]’ + Z [bit of [EA] specified by Dn]’ +bit of [EA] Same as BCHG Dn. (EA) BSR d BTST Dn. L B. (EA) BCS d BEQ d BGE d BGT d BHl d BLE d BLS d BLT d BMI d BNE d BPL d BRA d BSET Dn. else next instruction Branch to PC + d if greater than.L W. (EA) B.[EA] + Attect all condition codes except X [EA] -data Affect all flags except X-bit + . L 2 1 for B 2 for W 1 for B 2 for W 1 1 1 1 2 for B. else next instruction Branch to PC + d if higher.[EA] + Affect all condition codes except X An . [EA] except the bit is specified by immediate data PC . [EA] except the bit is specified by data Branch to PC + d if V = 0. (EA) BSET #data. else next instruction - - CHK (EA). W Fundamentals of Digital Logic and Microcomputer Design Length (words) 1 for B 2 for W 1 Operation Branch to PC + d if carry = 0. else next instruction Branch to PC + d if less or equal. else next instruction Branch to PC + d if low or same.W. else next instruction If Dn < 0 or Dn > [EA]. then trap O+EA Dn . (EA) BCLR Dn (EA) BCLR #data. [bit of [EA]]’ . 2 1 2 1 forB 2 for W 1 for B 2 for W 1 for B 2 for W 1 forB 2 for W 1 for B 2 for W 1 for B 2 for W 1 forB 2 for W 1 forB 2 for W 1 for B 2 for W 1 forB 2 for W 1 forB 2 for W 1 forB 2 for W 1 2 1 forB 2 for W 1 else next instruction Branch always to PC + d [bit of [EA]]’ Z 1 + bit of [EA] specified by Dn Same as BSET Dn. W. else next instruction Branch to PC +d if N = I . An CMPI #data. else next instruction [bit of [EA]. W 3 for L - Branch to PC + d if V = 1. else next instruction Branch to PC +d if Z = 0: else next instruction Branch to PC + d if N = 0.[SP] PC + d + PC [bit of [EA] specified by Dn]’ 2 Same as BTST Dn. [EA] except the bit is specified by immediate data Branch to PC + d if carry = 1. Dn CMP (EA). (EA) BTST #data.Z 0 + bit of [EA] specified by Dn Same as BCLR Dn. else next instruction Branch to PC + d if less than.L B. else next instruction Branch to PC + d if greater than or equal. (EA) BVC d BVS d Size B. Dn CLR(EA) CMP (EA).W.696 Instruction BCC d BCHG Dn. else next instruction Branch to PC + d if 2 = 1. [EA] except bit number is specified by immediate data .

2 PC if Dn f . W data 0 [EA] EA 3 for L 2 d8 0 CCR CCR d16 0 SR SR if S = 1. (EA) E O N #data. SR EXG Rx. d DBVS Dn. d DBLS Dn. d DBGE Dn. W. else trap 2 1 Rx -Ry Extend sign bit of Dn from 8-bit to 16-bit or from 16-bit 1 to 32-bit depending on whether the operand size is B or W 1 [EAI. S P . [EA] -PC Jump to subroutine using address in operand [EA] An 1 An+-[SP].PC Unconditional jump using addres's in operand 1 PC--[SP]. then Dn .e. else PC + 2 Same as DBCC except condition is C = 1 2 2 Same as DBCC except condition is 2 = 1 2 Same as DBCC except condition is always false 2 Same as DBCC except condition is greater or equal 2 Same as DBCC except condition is greater than Same as DBCC except condition is high 2 2 Same as DBCC except condition is less than or equal 2 Same as DBCC except condition is low or same 2 Same as DBCC except condition is less than 2 Same as DBCC except condition is N = 1 2 Same as DBCC except condition Z = 0 2 Same as DBCC except condition N = 0 2 Same as DBCC except condition is always true Same as DBCC except condition is V = 0 2 2 Same as DBCC except condition is V = 1 1 Signed division [Dn]32/[EA]16 [Dn] 0-15 = quotient [Dn] 16-31 = remainder 1 Same as DIVS except division is unsigned 1 Dn 0 [EA] EA 2 for B. d DBMl Dn. Dy LSR #data. i. d DBT Dn. d DBHIDn. Dy except the right shift is performed only once . d DBGT Gn. d DBVC Dn. d DBLE Dn. Dn B. CCR E O N #d16. d DBPL Dn. Dy LSL (EA) LSR Dx. (Ax) + DBCC Dn. C = 1.[Ay]+ + Affect all flags except X.Appendix G: 68000 Instruction Set Instruction Sue Length (words) 1 Operation 697 CMPM (Ay) +. d DBF Dn. d DBCS Dn. d DBLT Dn. d DBEQ Dn. An LINK An. (EA) E O N #d8. Dy LSR (EA) 1 1 Same as LSL Dx.1 --> Dn. update Ax D I W (EA). Dx. Dy and AY If condition false. d DBNE Dn. Dn EOR Dn. # -d LSL Dx. L [Ax]+ .. d DIVS (EA).1. Ry EXTDn JMP (EA) JSR (EA) LEA (EA).d -+SP 2 1 - - - - + - + - LSL #data. Dy except left shift is performed only once 1 1 I Same as LSR except immediate data specifies the number of shifts from 0 to 7 Same as LSR. S P + A n . Dy except immediate data specify the number of shifts from 0 to 7 Same as LSL Dx. then PC + d PC.

Dy 1 Same as ROR Dx. W. (EA) MOVE (EA). else TRAP 2 1 [EA] 16 sign extend to 32 bits . CCR MOVE CCR. An MOVEM register list. USP MOVE USP. Dy B. L B.. - --+ - ROXL #data. then assert RESET line. Dy ROL (EA) ROR Dx.[EAIlO . (EA) MOVEM (EA). Dy B W L Unsized B. (Dn) 16 MULU(EA)16. Dy ROXL (EA) ROXR Dx. W. [EA] source + [EA] destination [EA] CCR CCR [EA] If S = I.. Dy ROR (EA) ROXL Dx. else TRAP If S = I. Dn MULS(EA)16. Dy except the number of rotates is specified by immediate data from 0 to 7 Same as ROR Dx. Dy except [EA] is rotated once .. W data V[EA] EA 3 for L 2 CCR d8VCCR If S = I. Dy I Same as ROL Dx.[EA] .X EA 1 No operation 1 [EA]' EA 1 [EA]V[EA] EA 2 for B. register list MOVEP Dx. . else TRAP If S = I. W.X EA 1 0-[EAI-EA 1 0 . L I 1 1 Same as ROXL Dx. then An USP. then dl6VSR -> SR. then SR [EA]. (EA) MOVE An.[SP] 1 If S = I. CCR O N #d16. Dy except immediate data specifies number of rotates from 0 to 7 Same as ROXL Dx.. then [EA] SR. Dy except immediate data specifies number of times to be rotated from 0 to 7 Same as ROL Dx. Dy except [EA] is rotated once ROR #data.--- - - - ~ 1 ROL #data.698 Instruction MOVE (EA). (Dn)16 W NBCD (EA) NEC (EA) NEGX (EA) NOP NOT (EA) OR F A ) . (EA) Fundamentals of Digital Logic and Microcomputer Design Size Length (words) 1 1 1 Operation 1 1 I 1 2 . W. SR MOVE SR. SR PEA (EA) RESET ROL Dx. d (Ay) MOVEP d (Ay). Dy except [EA] is rotated once . (EA) MOVE (EA). L Dx d[Ay] d[Ay] Dx 1 d8 sign extended to 32-bit Dn Signed 16 x 16 multiplication [EA]16 * [Dn]16 1 [Dn]32 1 Unsigned 16 x 16 multiplication [EA]16 * [Dn]16 + [Dn]32 1 0 . F A ) ORI #data. L B. Dx MOVEQ #dS. else TRAP . else TRAP [USP] An Register list [EA] [EA] register list 2 2 2 O N #d8..

W [EA] .X + DX 1 If C = 0.[EA] An 2 for B. else next instruction 1 [EA] . [EA] . L Unsized Unsized Unsized B B B B B B B B B B B B B B B B Unsized B.[EA] . Dx SCC (EA) SCS (EA) SEQ ( E N SF (EA) SGE (EA) SGT (EA) SHI (EA) SLE (EA) SLS(EA) SLT (EA) SMI (EA) SNE (EA) SPL(EA) ST (EA) STOP #data SUB ( W . Dy except [EA] is rotated once 1 If S = I. else TRAP 1 [SP] + c c .( A X ) SUBX Dy.W.Appendix G: 68000 Instruction Set Instruction Sue 699 Operation Length (words) 1 ROXR #data. Dy except immediate data specifies number of rotates from 0 to 7 1 Same as ROXR Dx.[SSP]. no result provided 1 - + + - + + x- - - - .X + Dx 1 Same as SCC except if V = 0 1 Same as SCC except if V = 1 1 Dn [31:16] Dn [15:0] [EA] tested. then [SP] + -P S R [SP] + PC.data + EA 3 for L 1 [EA] . SR .L B. W. L B.(Ay)lO . L B.[SSP]. (EA) SUBX . L B. TRAP if executed in user mode 1 .0 + condition codes affected. L W. then data + SR and stop.(AX)lO .Dy . L B B W B Unsized Unsized B. N and Z are affected accordingly. .[AYl"4x1 1 Dx . Dx SVC (EA) SVS (EA) SWAP Dn TAS (EA) TRAP #vector TRAPV TST (EA) Same as ROXR Dx. then TRAP. 1 TRAP If V = 1. An SUB1 #data. 1 -+ bit 1 7 of [EA] PC . W. (vector) PC.. (EA) B. [SP] + + PC 1 [SP] + PC 1 . ( E N SUBA (EA).[DyllO .(Ay).data + EA 1 . Dy ROXR (EA) RTE RTR RTS SBCD -(Ay). W. W. 16 ."4x1 .W.EA 1 An .W. L SUBQ #data.L B. W. -(AX) SBCD Dy.X (AX) 1 [Dx]lO . then Is [EA] else 0s -+ [EA] 1 Same as SCC except the condition is C = 1 1 Same as SCC except if Z = 1 1 Same as SCC except condition is always false 1 Same as SCC except if greater or equal 1 Same as SCC except if greater than 1 Same as SCC except if high Same as SCC except if less or equal 1 1 Same as SCC except if low or same 1 Same as SCC except if less than 1 Same as SCC except if N = 1 1 Same as SCC except if Z = 0 1 Same as SCC except if N = 0 1 Same as SCC except condition always true 2 If S= 1.