You are on page 1of 34

MSP430P325 MIXED SIGNAL MICROCONTROLLER

SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

D D D D D D D D

Low Supply Voltage Range, 2.7 V – 5.5 V Low Operation Current, 3 mA at 1 MHz, 3V Ultralow Power Consumption (Standby Mode Down to 0.1 mA) Five Power-Saving Modes Wakeup From Standby Mode in 6 ms 16-Bit RISC Architecture, 300 ns Instruction Cycle Time Single Common 32 kHz Crystal, Internal System Clock up to 3.3 MHz Integrated LCD Driver for up to 84 Segments

D D D D D D

Integrated 12+2 Bit A/D Converter Family Members Include: – MSP430P325, 16KB OTP, 512 Byte RAM EPROM Version Available for Prototyping: PMS430E325 Serial Onboard Programming Programmable Code Protection by Security Fuse Avaliable in 64 Pin Quad Flatpack (QFP), 68 Pin Plastic J-Leaded Chip Carrier (PLCC), 68 Pin J-Leaded Ceramic Chip Carrier (JLCC) Package (EPROM Version)

description
The Texas Instruments MSP430 is an ultralow-power mixed-signal microcontroller family consisting of several devices which feature different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digitallycontrolled oscillator, together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode to active mode in less than 6 ms.
PG Package (TOP VIEW)

64 63 6261 60 59 58 57 56 55 54 5352

DVSS AVSS A1 A0 XBUF RST/NMI TCK TMS TDI/VPP TDO/TDI COM3 COM2 COM1 AVCC DVCC SVCC Rext A2 A3 A4 A5 Xin Xout/TCLK CIN TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 P0.0 P0.1/RXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 2425 26 272829 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

COM0 S20/O20/CMPI S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/O7 S6/O6 S5/O5 S4/O4 S3/O3

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

P0.2/TXD P0.3 P0.4 P0.5 P0.6 P0.7 R33 R23 R13 R03 S0 S1 S2/O2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

1

MSP430P325 MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

description (continued)
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. The MSP430x32x offers an integrated 12+2 bit A/D converter with six multiplexed inputs.
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PG) MSP430P325IPG — PLASTIC 64-PIN QFP (PM) MSP430P325IPM — PLASTIC 68-PIN PLCC (FN) MSP430P325IFN — CERAMIC 68-PIN JLCC (FZ) — PMS430E325FZ

– 40°C to 85°C 25°C

functional block diagram
XIN Xout/TCLK XBUF RST/NMI P0.0 P0.7

Oscillator FLL System Clock TDI/VPP TDO/TDI

ACLK MCLK

8/16 kB ROM 16 kB OTP ’C’: ROM ’P’: OTP

256/512 B RAM

Power-onReset

8 b Timer/ Counter Serial Protocol Support

I/O Port TXD 8 I/O’s, All With Interr. Cap. 3 Int. Vectors RXD

MAB, 16 Bit

MAB, 4 Bit

CPU Incl. 16 Reg.

Test JTAG MDB, 16 Bit Bus Conv

MCB MDB, 8 Bit

TMS TCK ADC 12 + 2 Bit 6 Channels Current S. Watchdog Timer 15/16 Bit Timer/Port Applications: A/D Conv. Timer, O/P Basic Timer1 f LCD CMPI 6 6 LCD 84 Segments 1, 2, 3, 4 MUX Com0–3 S0–19/O2–19 S20/O20CMPI

A0–5 SVCC Rext

TP0.0–5 CIN

R33 R23

R13 R03

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

MSP430P325 MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000

Terminal Functions
TERMINAL NAME AVCC AVSS A0 A1 A2–A5 CIN COM0–3 DVCC DVSS P0.0 P0.1/RXD P0.2/TXD P0.3–P0.7 Rext RST/NMI R03 R13 R23 R33 SVCC S0 S1 S2–S5/O2–O5 S20/O20/CMPI S6–S9/O6–O9 S10–S13/O10–O13 S14–S17/O14–O17 S18-S19/O18-O19 TCK TDO/TDI TDI/VPP TMS TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 XBUF Xin Xout/TCLK NO. 1 63 61 62 5–8 11 51–54 2 64 18 19 20 21–25 4 59 29 28 27 26 3 30 31 32–35 50 36–39 40–43 44–47 48, 49 58 55 56 57 12 13 14 15 16 17 60 9 10 O O O I/O O O O O I I/O I I O O O O O I/O O I I/O I/O I/O I/O I/O I I I I I O I I I I O I/O Positive analog supply voltage Analog ground reference Analog-to-digital converter input port 0 or digital input port 0 Analog-to-digital converter input port 1 or digital input port 1 Analog-to-digital converter inputs ports 2–5 or digital inputs ports 2–5 Input used as enable of counter TPCNT1 – Timer/Port Common outputs, used for LCD backplanes – LCD Positive digital supply voltage Digital ground reference General-purpose digital I/O General-purpose digital I/O, receive digital input port, 8-Bit Timer/Counter General-purpose digital I/O, transmit data output port, 8-Bit Timer/Counter Five general-purpose digital I/Os, bit 3 to bit 7 Programming resistor input of internal current source Reset input or non-maskable interrupt input Input of fourth positive analog LCD level (V4) – LCD Input of third positive analog LCD level (V3) – LCD Input of second positive analog LCD level (V2) – LCD Output of first positive analog LCD level (V1) – LCD Switched AVCC to analog-to-digital converter Segment line S0 – LCD Segment line S1 – LCD Segment lines S2 to S5 or digital output ports O2–O5, group 1 – LCD Segment line S20 can be used as comparator input port CMPI – Timer/Port Segment lines S6 to S9 or digital output ports O6–O9, group 2 – LCD Segment lines S10 to S13 or digital output ports O10–O13, group 3 – LCD Segment lines S14 to S17 or digital output ports O14 to O17, group 4 – LCD Segment lines S18 and S19 or digital output port O18 and O19, group 5 – LCD Test clock, clock input terminal for device programming and test Test data output, data output terminal or data input during programming Test data input, data input terminal or input of programming voltage Test mode select, input terminal for device programming and test General-purpose 3-state digital output port, bit 0 – Timer/Port General-purpose 3-state digital output port, bit 1 – Timer/Port General-purpose 3-state digital output port, bit 2 – Timer/Port General-purpose 3-state digital output port, bit 3 – Timer/Port General-purpose 3-state digital output port, bit 4 – Timer/Port General-purpose digital input/output port, bit 5 – Timer/Port Clock signal output of system clock MCLK or crystal clock ACLK Input terminal of crystal oscillator Output terminal of crystal oscillator or test clock input DESCRIPTION

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

3

JNE R4 + R5 → R5 PC → (TOS). &MEM R5 4 POST OFFICE BOX 655303 • DALLAS. a stack pointer. Table 1. This design structure results in a RISC-like architecture. Instruction Word Formats Dual operands.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 short-form description processing unit The processing unit is based on a consistent and orthogonally-designed CPU and instruction set.g. instruction set The instruction set for this register-register architecture provides a powerful and easy-to-use assembler language.B PUSH. &MEM R5 R5 Instructions for byte operation MOV.g. un-/conditional e. Examples: Instructions for word operation MOV ADD PUSH SWPB EDE. highly transparent to the application development. and a constant generator. The remaining registers are available as general-purpose registers. providing reduced instruction execution time. Table 1 provides a summation and example of the three types of instruction formats. TONI #235h. TONI #35h. Peripherals are connected to the CPU using a data address and control bus and can be handled easily with all instructions for memory manipulation.B ADD. CALL R8 e. ADD R4. destination only Relative jump. This reduces a register-register operation execution time to one cycle of the processor frequency. a status register. The instruction set consists of 51 instructions with three formats and seven addressing modes. R8 → PC Jump-on equal bit = 0 Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register R14 R15 Each instruction that operates on word and byte data is identified by the suffix B. TEXAS 75265 . Four of the registers are reserved for special use as a program counter.g. Program Counter PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 CPU Sixteen registers are located inside the CPU. source-destination Single operands. All operations other than program-flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source and four modes for destination operand. and it is distinguished by ease of programming. R5 e.B — EDE. the addressing modes are listed in Table 2.

R10 + 2 → R10 #45 → M(TONI) OPERATION Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 Table 2. and the dc generator for the DCO is switched off. peripheral operation continues. The full use of this programming capability permits a program structure different from conventional 8. An interrupt event awakens the system from each of the various operating modes and returns with the RETI instruction to the mode that was selected before the interrupt event. Rd MOV X(Rn). MCLK and loop control for MCLK are inactive. Tab(R6) MOV @R10+. The clocks used are ACLK and MCLK. R11 MOV #45. TONI EXAMPLE MOV R10. some peripheral current-saving functions are accessed through the state of local register bits. POST OFFICE BOX 655303 • DALLAS. An example is the enable/disable of the analog voltage generator in the LCD peripheral. and the dc generator for the digital controlled oscillator (DCO) ( MCLK generator) is switched off. All registers of the peripherals may be accessed if the operational function is stopped or enabled. For example. ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock. ideally suited for computed branches and calls. ACLK signal is active. Low power mode 2 (LPM2). This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. Low power mode 1 (LPM1). However. These addressing modes provide indirect addressing. peripheral operation continues. MCLK and loop control for MCLK are inactive. The requirements are fully supported during interrupt event handling. The CPU is disabled. Low power mode 0 (LPM0). The software can configure five operating modes: D D D D D D Active mode (AM). 5(R6) R10 → R11 M(2 + R5) → M(6 + R6) M(EDE) → M(TONI) M(MEM) → M(TCDAT) M(R10) → M(Tab + R6) M(R10) → R11. The CPU is disabled. peripheral operation continues. and MCLK and loop control for MCLK are inactive. peripheral operation continues. and loop control for MCLK is active. which is turned on or off using one register bit. and loop control for MCLK is inactive. Address Mode Descriptions ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate NOTE: s = source s √ √ √ √ √ √ √ d = destination d √ √ √ √ SYNTAX MOV Rs.and 16-bit controllers. The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific peripheral module. TONI MOV @R10. Low power mode 3 (LPM3). TONI MOV &MEM. peripheral operation continues. ACLK signal is active. The CPU is enabled with different combinations of active peripheral modules. ACLK and MCLK signals are active. ³ Low power mode 4 (LPM4). The CPU is disabled. numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control. RM MOV #X. &TCDAT MOV @Rn. R11 MOV 2(R5). operation modes and interrupts The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy consumption. TEXAS 75265 5 . ACLK and MCLK signals are active. Y(Rm) MOV @Rn+. The CPU is disabled. ACLK signal is inactive (crystal oscillator stopped). The CPU is disabled. Y(Rm) MOV EDE.

1 or 8-Bit Timer/Counter RXD INTERRUPT FLAG WDTIFG (see Note1) NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 4) P0. (Non)-maskable: the individual interrupt enable bit can disable on interrupt event. OscOff. 3. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. EN1FG (see Note 2) Maskable Maskable 0FFEAh 0FFE8h 0FFE6h 0FFE4h Basic Timer1 I/O port 0.0 Dedicated I/O P0. oscillator fault Dedicated I/O P0. 2.0IFG P0. SCG0. external reset.27IFG (see Note 1) Maskable Maskable 0FFE2h 0FFE0h PRIORITY 15. (Non)-maskable Maskable Maskable WORD ADDRESS 0FFFEh 0FFFCh 0FFFAh 0FFF8h 0FFF6h Watchdog Timer WDTIFG Maskable 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh ADC Timer/Port ADCIFG RC1FG. but the general interrupt enable bit cannot. lowest Multiple source flags Timer/Port interrupt flags are located in the T/P registers Non-maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event. INTERRUPT SOURCE Power-up.1IFG SYSTEM INTERRUPT Reset Non-maskable. P0. 15 Reserved For Future Enhancements 9 8 V 7 SCG1 SCG0 OscOff CPUOff GIE N Z 0 C rw-0 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the ROM with an address range of 0FFFFh-0FFE0h.2–7 NOTES: 1. TEXAS 75265 . highest 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0. 6 POST OFFICE BOX 655303 • DALLAS. watchdog NMI. 4. and CPUOff. Four of these bits control the CPU and the system clock generator: SCG1.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 operation modes and interrupts (continued) The most general bits that influence current consumption and support fast turnon from low-power operating modes are located in the status register (SR). BTIFG P0. RC2FG.

0 P0.1IFG: NMIIFG: Address 03h rw 7 BTIFG Set on overflow or security key violation or Reset on VCC power on or reset condition at RST/NMI-pin Flag set on oscillator fault Dedicated I/O P0.1 or 8-Bit Timer/Counter. interrupt enable 1 and 2 Address 0h 7 6 5 4 3 P0IE. RXD Signal at RST/NMI-pin 6 5 4 3 2 ADIFG rw-0 1 0 BTIFG ADFIG Basic Timer1 flag Analog-to-digital converter flag POST OFFICE BOX 655303 • DALLAS.0 rw-0 1 OFIFG rw-1 0 WDTIFG rw-0 WDTIFG: OFIFG: P0.1 or 8-Bit Timer/Counter.1: Address 01h 7 BTIE rw-0 Watchdog Timer enable signal Oscillator fault enable signal Dedicated I/O P0. Simple SW access is provided with this arrangement. TEXAS 75265 7 .1 rw-0 2 P0IE.0IFG: P0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 operation modes and interrupts (continued) special function registers Most interrupt and module enable bits are collected into the lowest address space.1 rw-0 2 P0IFG.0 P0. Special function register bits that are not allocated to a functional purpose are not physically present in the device.0: P0IE.0 rw-0 1 OFIE rw-0 0 WDTIE rw-0 WDTIE: OFIE: P0IE. RXD 6 5 4 3 TPIE rw-0 2 ADIE rw-0 1 0 ADIE: TPIE: BTIE: A/D converter enable signal Timer/Port enable signal Basic Timer1 enable signal interrupt flag register 1 and 2 Address 02h 7 6 5 4 NMIIFG rw-0 3 P0IFG.

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 memory organization MSP430P325 PMS430E325 FFFFh FFE0h FFDFh Int. 8b Per. SFR 8 POST OFFICE BOX 655303 • DALLAS. Bit can be read and written. Vector 16 kB OTP or EPROM C000h 03FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h 512B RAM 16b Per.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 operation modes and interrupts (continued) module enable register 1 and 2 Address 04h Address 05h Legend rw: rw-0: Bit can be read and written. It is reset by PUC. SFR bit not present in device. TEXAS 75265 .

It can be stopped by setting the OscOff bit to a 1. address. peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog ADC Watchdog Timer control Data register Reserved Control register Input enable register Input register PERIPHERALS WITH BYTE ACCESS EPROM Crystal buffer System clock EPROM control Crystal buffer control SCG frequency control SCG frequency integrator SCG frequency integrator Timer/Port enable Timer/Port data Timer/Port counter2 Timer/Port counter1 Timer/Port control 8-Bit Timer/Counter data 8-Bit Timer/Counter preload 8-Bit Timer/Counter control Basic Timer counter2 Basic Timer counter1 Basic Timer control LCD memory 15 : LCD memory 1 LCD control & mode Port P0 interrupt enable Port P0 interrupt edge select Port P0 interrupt flag Port P0 direction Port P0 output Port P0 input SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 EPCTL CBCTL SCFQCTL SCFI1 SCFI0 TPE TPD TPCNT2 TPCNT1 TPCTL TCDAT TCPLD TCCTL BTCNT2 BTCNT1 BTCTL LCDM15 : LCDM1 LCDCTL P0IE P0IES P0IFG P0DIR P0OUT P0IN IFG2 IFG1 IE2 IE1 054h 053h 052h 051h 050h 04Fh 04Eh 04Dh 04Ch 04Bh 044h 043h 042h 047h 046h 040h 03Fh : 031h 030h 015h 014h 013h 012h 011h 010h 003h 002h 001h 000h WDTCTL ADAT ACTL AEN AIN 0120h 0118h 0116h 0114h o112h 0110h Timer/Port 8-Bit Timer/Counter Basic Timer1 LCD Port P0 Special function oscillator and system clock Two clocks are used in the system. or MCLK are accessible for use by external devices at output terminal XBUF. The ACLK runs with the crystal oscillator frequency. The MCLK is a multiple of the ACLK.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 peripherals Peripherals connect to the CPU through data. POST OFFICE BOX 655303 • DALLAS. The enabled clock signals ACLK. The special design of the oscillator supports the feature of low current consumption and the use of a 32 768 Hz crystal. ACLK/4. the system (master) clock (MCLK) and the auxiliary clock (ACLK). due to a reset of the control bit (OscOff) in the status register (SR). and control busses and can be handled easily with all instructions for memory manipulation. The oscillator starts after applying VCC. The crystal is connected across two terminals without any other external components being required. TEXAS 75265 9 . ACLK/2.

one for Port0. Provides read/write access to all registers with all instructions The six registers are: Input register Output register Direction register Interrupt flags Interrupt edge select Interrupt enable Contains information at the pins Contains output information Controls direction Indicates if interrupt(s) are pending Contains input signal change necessary for interrupt Contains interrupt enable pins All six registers contain eight bits except for the interrupt flag register and the interrupt enable register. real-time clock (RTC) Enable start-stop operation with a minimum of delay These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The frequency variation of the DCO with the FLL inactive is typically 330 ppm. The Port0. etc.2 pin function is shared with the 8-Bit Timer/Counter. Any combination of input. Three interrupt vectors are implemented. one for Port0. which is multiplied to achieve the desired nominal operating range: f(system) = (N+1) × f(crystal) The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. TEXAS 75265 . Six control registers give maximum flexibility of digital input/output to the application: D D D D D D D D D D All individual I/O bits are programmable independently. which means that with a cycle time of 1 µs the maximum possible variation is 0. the DCO is reset to its lowest possible frequency.g. output. Stable frequency for timer applications e. The compromise selected for the MSP430 uses a low-crystal frequency. digital I/O One 8-Bit I/O port (Port0) is implemented. For more precise timing.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 oscillator and system clock (continued) The controller system clock has to operate with different requirements according to the application and system conditions. in combination with a digital controlled oscillator (DCO) provides immediate start-up capability together with long term crystal stability. Requirements include: D D D D High frequency in order to react quickly to system hardware requests or events Low frequency in order to minimize current consumption. and interrupt conditions is possible. The control logic starts operation immediately after recognition of PUC. the FLL can be used forcing longer cycle times.7.1 and Port0.33 ns. This switching of cycle times makes it possible to meet the chosen system frequency over a long period of time.1. Interrupt processing of external events is fully implemented for all eight bits of port P0.2 to Port0.0. Connect operation of the FLL control logic requires the presence of a stable crystal oscillator. The two LSBs of the interrupt flag and interrupt enable registers are located in the special functions register (SFR). The FLL technique. During a power-up clear (PUC). EMI. and one commonly used for any interrupt event on Port0. if the previous cycle time was shorter than the selected one. 10 POST OFFICE BOX 655303 • DALLAS. The factor N is set to 31 after a power-up clear condition. The start-up operation of the system clock depends on the previous machine state.

to support low current applications. Both timers can be read and written by software. 3and 4-MUX operation. The user software usually configures the operational conditions on the BT1 during initialization. When the supply voltage is applied or when a reset of the device (RST/NMI pin). LCD memory is part of the LCD module. This minimizes accidental write operations to the WDTCTL register. a system reset is generated. The controller LCD logic operation is defined by software using memory-bit manipulation. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the Basic Timer1 interrupt enable (BTIE) bit. Writing to WDTCTL. The low-byte stores data written to the WDTCTL. In addition to the Watchdog Timer control bits. The current is adjusted by an external resistor and is enabled/disabled by bits located in the control registers. The current consumption and operation is stopped when it is set. It is a 12+2 bit converter with a software or automatically-controlled range select. If this watchdog function is not needed in an application. TEXAS 75265 11 . not part of data memory. Two bits in the SFR address range handle the system control interaction according to the function implemented in the Basic Timer1. A/D converter The analog-to-digital converter (ADC) is a cascaded converter type that converts analog signals from VCC to GND. which is an 8-Bit read/write register. A ratiometric current source can be used on four of the analog pins. 2-. Eight mode and control bits define the operation and current consumption of the LCD drive. in both operating modes (watchdog or timer) is only possible by using the correct password in the high-byte. Basic Timer1 The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK. Groups of the LCD segment lines can be selected for digital output signals. to provide low frequency control signals. The conversion is started by setting the start-of-conversion bit (SOC) in the control register and the end-of-conversions sets the interrupt flag. a system reset PUC is generated. Watchdog Timer The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a software upset has occurred. 3. the Basic Timer1. a watchdog overflow or a watchdog security key violation occurs. The power-down bit in the control register controls the operating mode of the ADC peripheral. This is done within the system by one central divider. and all bits in the register hold undefined or unchanged status. POST OFFICE BOX 655303 • DALLAS. The Watchdog Timer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software. If any value other than 05Ah is written to the high-byte of the WDTCTL. When the password is read its value is 069h. Five inputs can be selected for analog or digital function. If the selected time interval expires. The BTCTL control register contains the flags which control or select the different operational functions. The Basic Timer1 has two 8-Bit timers which can be cascaded to a 16-bit timer. The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL). The analog input signal is sampled starting with SOC during the next twelve MCLK clock pulses. The system reset PUC sets the power-down bit. The high-byte password is 05Ah.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 LCD drive Liquid crystal displays (LCDs) for static. The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-. which generates an interrupt after the selected time interval. two bits included in the WDTCTL configure the NMI pin. The segment information is stored in LCD memory using instructions for memory manipulation. The information for the individual digits can be easily obtained using table programming techniques combined with the correct addressing mode. as selected with the SSEL bit.and 4-MUX operations can be driven directly. The MSP430x32x configuration has four common signal lines and 21 segment lines. the module can work as an interval timer.

The two 8-Bit counters can be cascaded to a 16-bit counter. the counter will count-up each time a positive clock edge is applied to the clock input of the counter.1. Timer/Port The Timer/Port module has two 8-Bit counters. The 8-Bit counter counts up with an input clock which is selected by two control bits from the control register. Two counter inputs (load. When this function is activated. bit-by-bit. the start of a data transmission. overflow from the counters) or from two events in the 16-bit counter mode (gate signal. The hardware supports the output of the serial data stream. overflow from the MSB of the cascaded counter). and an input and output data latch.g. UART The serial communication uses software and the 8-Bit Timer/Counter hardware. or networks. The enable input enables the count operation. Both timers can be read from and written to by software. Start bit detection for asynchronous protocols). triggered by the carry-out-signal from the 8-Bit counter. need start-bit edge-detection to determine. enable) control the counter operation. When the enable signal is set to high. A write-access to the counter results in loading the content of the preload register into the counter. an edge detection (e. The interrupt flag can be set from three events in the 8-Bit counter mode (gate signal. and the signal from the logical AND of MCLK and terminal P0. The four possible clock sources are MCLK. which is programmed into the counter. systems. 12 POST OFFICE BOX 655303 • DALLAS. One of the counters has an extended control capability to halt. an input clock selector. or gate the counter by selecting one of two external signals. with the timing determined by the counter. The load input controls load operations. Both counters have an independent clock-selector for selecting an external signal or one of the internal clocks (ACLK or MCLK). the counter starts counting after the start-bit condition is detected. Two latches are used for input and output data (RXD_FF and TXD_FF) are clocked by the counter after the programmed timing interval has elapsed.1.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 8-Bit Timer/Counter The 8-Bit interval timer supports three major functions for the application: D D D Serial communication or data exchange Pulse counting or pulse accumulation Timer The 8-Bit Timer/Counter peripheral includes the following major blocks: an 8-Bit up-counter with preload register. at the receiver. and six 3-state digital outputs. The software writes or reads the preload register with all instructions. count continuously. the external signal from terminal P0. ACLK. TEXAS 75265 . The first signal level is sampled into the RXD input data-latch after completing the first timing interval. This gate signal sets the interrupt flag. if an external signal is selected. like UART protocol. Serial protocols. an 8-Bit control register. A common interrupt vector is implemented. The preload register acts as a buffer and can be written immediately after the load of the counter is completed. an input that triggers one counter. The software/hardware interface connects the mixed signal controller to external devices. and the gate stops the counter.

–0. Xout) High-level input voltage. . . . .3 V Diode current at any device terminal . . . . . . during programming OTP/EPROM (AVCC = DVCC = VCC) Supply voltage. . . . . f(XTAL) Processor frequency (signal MCLK). . . . . .8 VCC 0. . . . . . . . . . Xout) Low-level input voltage. . ± 2 mA Storage temperature. . . .2 3. . VSS Operating free-air temperature range. . . . . . . . . . . . . . . . . . . Tstg (unprogrammed device) . . . . VIH(Xin. . . . .2 1. . . . . . . . . . . . .8×VCC MSP430P325 PMS430E325 –40 25 32 768 2. . . . . . . . . Xout) High-level input voltage. . . . . VIH (excluding Xin. . . NOTE 5: All voltage values relative to VSS.7 VCC VSS 0. . . –0. . These are stress ratings only. .MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 absolute maximum ratings† Voltage applied at VCC to VSS (see Note 5) . .5 5. . . . . . TA free air range XTAL frequency. . . . . . . TEXAS 75265 13 . . . . . .7 5 0 85 NOM MAX 5. . . . . . . Figure 1. . . . . . . .7 3 5 5. . . . . . .5 Minimum 2.5 UNIT V V V °C Hz MHz V V f(system) – Maximum Processor Frequency – MHz f(MHz) 3. . . . . . –40°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. . . . . . . . . . . . VIL (excluding Xin. . . . . . . VCC (MSP430P/E325) Supply voltage. .7 2. . . . . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. .2×VCC VCC MSP430P325. . . . . . recommended operating conditions MIN Supply voltage.5 VCC (V) VCC – Supply Voltage – V NOTE: Minimum processor frequency is defined by system clock. . . . . . . . . . . . . . . . Xout) VCC = 3 V/5 V VCC = 3 V VCC = 5 V DC DC VSS 0. . . . f( MCLK) (system) t ) Low-level input voltage. . . . . . . . . . . . . . . and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.3 2. Processor Frequency vs Supply Voltage POST OFFICE BOX 655303 • DALLAS. .3 VSS+0. –55°C to 150°C Tstg (programmed device) . . . VIL(Xin. . .3 V to VCC + 0.3 V to 6 V Voltage applied to any pin (referenced to VSS) . . . . . . . . PMS430E325 2. .

2 4 0.x Timer/Port. CIN.1 3.3 1. P0.3 NOTE: All inputs are tied to 0 V or VCC. (LPM0.8 7 6. Outputs do not source or sink any current.1 MAX 5000 12000 110 200 12 25 2.1 0.3 1 1. TA = –40°C to 85°C. power-down Low power mode. TEXAS 75265 . The current consumption in LPM2. (LPM2) mode P325 P325 TEST CONDITIONS TA = –40°C to 85°C. TP 0. TA = –40°C to 85°C.2 4. A/D conversion in .6 TYP MAX 2. TA = –40°C to 85°C.5 1. TA = –40°C to 85°C.8 µA UNIT µA µA µA VCC = 3 V/5 V µA 0.2 2.4 0.3 0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) supply current into AVCC+DVCC excluding external current.6 5.4 1. TA = –40°C TA = 25°C I(LPM3) Low power mode. 4 MUX).4 1. (LPM3) mode TA = 85°C TA = –40°C TA = 25°C TA = 85°C I( (LPM4) ) Low power mode.35 2.5 1.8 TA = 85°C 0. LPM1) mode (LPM0 Low power mode. fsystem = 1 MHz PARAMETER I(AM) I(CPUOff) I(LPM2) Active mode.4 2 2.4 V UNIT 14 POST OFFICE BOX 655303 • DALLAS. (LPM4) TA = –40°C TA = 25°C VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V MIN TYP 3000 10000 70 150 6 15 1.5 PARAMETER VIT IT+ VIT IT– Vh hys Positive going input threshold voltage Positive-going Negative-going Negative going input threshold voltage Hysteresis (VIT+–VIT ) IT VIT– TEST CONDITIONS VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V MIN 1. current consumption of active mode versus system frequency IAM = IAM[1 MHz] × fsystem [MHz] current consumption of active mode versus supply voltage IAM = IAM[3 V] + 200 µA/V × (VCC–3 V) Schmitt-trigger inputs Port 0.3 0.5 7 0. LPM3 and LPM4 are measured with active Basic Timer1 (ACLK selected) and LCD module (f(LCD)=1024 Hz. TA = –40°C to 85°C.

for all outputs combined. port 0 Leakage current.5 are connected together during leakage current measurement. 7. The input voltage is V(IN) = VSS to VCC . See Note 6 See Note 7 See Note 6 See Note 7 See Note 6 See Note 7 See Note 6 See Note 7 MIN VCC–0.5 mA.2 mA. TEXAS 75265 15 . IOH = –3. IOH = –4.CIN) (see Note 9) Port 0: V(P0. 10. The port pin must be selected for input and there must be no optional pullup or pulldown resistor. 9. leakage current (see Note 8) PARAMETER Ilkg(TP) Ilkg(P0x) Ilkg(S20) Ilkg(Ax) Leakage current.4 VCC–1 VCC–0. The input voltage is VSS or VCC. CIN. IOHmax and IOLmax. the current source is off. VCC = 3 V.1. VCC = 5 V.5 mA. VCC = 3 V. pF VCC = 3 V/5 V TEST CONDITIONS CL = 20 pF fMCLK = 1. should not exceed ±20 mA to satisfy the maximum voltage drop specified.0 to TP0.2 mA.x bit is normally reset to stop throughput current flowing from VCC to VSS terminal. for all outputs combined.5. RST/NMI ±50 nA NOTES: 8. IOL = 3. IOHmax and IOLmax.x. S20 Leakage current. The maximum total current.x) (see Note 10) V(S20) = VSS to VCC ADC: Ax. VCC = 3 V. 11. Timer/Port: CIN. IOH = –1. AEN. VCC = 5 V. VCC = 3 V.. ADC TEST CONDITIONS Timer/Port: V(TP0.0 to TP0.5 are Hi-Z.0. IOL = 1. IOL = 1. XBUF. TP.1 MHz fXBUF = fACLK fXBUF = fACLK/n 40% 35% 50% MIN TYP MAX f(system) 60% 65% UNIT MHz POST OFFICE BOX 655303 • DALLAS. Pins CIN and TP.5 mA.x. Timer/Port Leakage current. All Timer/Port pins TP0. In the leakage measurement the input CIN is included. x= 0 to 5 (see Note 11) VCC = 3 V/5 V MIN TYP MAX ±50 ±50 ±50 ±30 UNIT nA nA nA nA Ilkg(RST/NMI) Leakage current.4 VCC–1 VSS VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS+0. input frequency – Port 0: P0.4 VSS+1 VSS+0. The leakage current is measured with VSS or VCC applied to the corresponding pin(s). TP0. should not exceed ±9.5 mA.5 mA. LCD: Sxx/Oxx. VCC = 5 V. XBUF CL = 20 pF. IOL = 4. The maximum total current. VCC = 5 V.6 mA to satisfy the maximum voltage drop specified.5 mA.x.4 VSS+1 UNIT VOH High-level High level output current V VOL Low-level out ut voltage output V NOTES: 6. unless otherwise noted. (see Note 6) PARAMETER TEST CONDITIONS IOH = –1..5 3V 5V TEST CONDITIONS MIN DC 300 125 TYP MAX f(system) UNIT MHz ns ns output frequency PARAMETER fXBUF tXdc Duty cycle of O/P frequency XBUF. Timer/Port: TP0. XBUF.5 PARAMETER f(IN) t(H) or t(L) Input frequency High level or low level time P0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) outputs – Port 0: P0.

3 17.4 13. FN_2=X NDCO = 00 0110 0000 FN 4 =1. FN 4=FN 3=0 FN_2=1 0000 FN_4=FN_3=0.5 1. FN_4=FN_3=FN_2=0 NDCO = 00 0110 0000. TEXAS 75265 .5 1. FN_4=0.7 4.8 6 A0h 1.1 9. RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRAMh CPU halted (see Note 14) 1. FN_4= 0. Input frequency (t(int)) is defined in MCLK cycles.8 1.15 0.5 0.07 1A0h TYP 1 0.62 4.9 1.5 TYP MAX UNIT cycle NOTES: 12. DCO PARAMETER f(NOM) DCO fDCO3 f(NOM) fDCO26 fDCO3 2xf(NOM) fDC26 fDCO3 3xf(NOM) fDCO26 fDCO3 4xf(NOM) fDCO26 NDCO S NDCO = 11 0100 0000.8 11 13. FN_2=X NDCO = 11 0100 0000 FN 4=FN 3=FN 2=0 FN_4=FN_3=FN_2=0 NDCO = 00 0110 0000.7 0. FN_4=FN_3=FN_2=0 0000 FN 4=FN 3=FN 2=0 VCC = 3 V/5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V/5 V VCC = 3 V/5 V MIN 0. FN_4=FN_3=FN_2=0 fNDCO+1 = S × fNDCO NDCO = 11 0100 0000 FN 4= 0 FN 3=1 FN 2=X 0000. No program execution should take place during this supply voltage condition.45 0. 13. FN 4=FN 3=0 FN_2=1 0000 FN_4=FN_3=0. FN_3=FN_2=X FN_4 =1 FN 3=FN 2=X NDCO = 11 0100 0000.13 MHz MHz MHz MHz MAX UNIT MHz 16 POST OFFICE BOX 655303 • DALLAS.5 0.2 8. FN_3= 1.5 3 0. FN 2=1 TEST CONDITIONS NDCO = 1A0h. FN 2=1 NDCO = 00 0110 0000 FN 4=0 FN 3= 1 FN 2=X 0000.05 1.7 5.7 340h 1. The external signal needs additionally a timing resulting from the maximum input frequency constraint.36 0. It may be set even with trigger signals shorter than t(int).MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) external interrupt timing PARAMETER t(int) TEST CONDITIONS Port P0: External trigger signal for the interrupt flag (see Notes 12 and 13) MIN 1. The conditions to set the flag must be met independently of this timing constraint. The external signal sets the interrupt flag every time t(int) is met. FN 4=1 FN_3=FN_2=X 0000 FN_4=1.8 V NOTE 14: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. FN_3=1.6 3.8 4.6 0.39 2.25 1. FN 3=FN 2=X fMCLK = fNOM .85 2.18 1.

2 0.4 UNIT µs V V V V µs V(POR) POR No POR POR V(min) t Figure 3.9 0 2 TEST CONDITIONS MIN NOM 150 MAX 250 2. TEXAS 75265 17 .4 2.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) f(DCO26) 4xfNOM f(DCO26) f(DCO3) 3xfNOM f(DCO26) f(DCO3) Legend Tolerance at Tap 26 f(DCO3) DCO Frequency Adjusted by Bits 2∧9–2∧5 in SCFI1 Tolerance at Tap 3 FN_2 = 1 FN_3 = 0 FN_4 = 0 FN_2 = X FN_3 = 1 FN_4 = 0 FN_2 = X FN_3 = X FN_4 = 1 2xfNOM f(DCO26) fNOM f(DCO3) FN_2 = 0 FN_3 = 0 FN_4 = 0 Figure 2 crystal oscillator PARAMETER C(Xin) C(Xout) Integrated capacitance at input Integrated capacitance at output TEST CONDITIONS VCC = 3 V/5 V VCC = 3 V/5 V MIN NOM 12 12 MAX UNIT pF pF PUC/POR PARAMETER t(POR_delay) V(POR) ( ) V(min) t(reset) V VCC POR TA = –40°C TA = 25°C TA = 85°C PUC/POR Reset is accepted internally 1.8 0. Power-On Reset (POR) vs Supply Voltage POST OFFICE BOX 655303 • DALLAS.1 1.5 VCC = 3 V/5 V 1.

4 2. No load at all seg and com pins R13 = VCC/ 3.26×VCC 37 42 UNIT µA V mV wake-up LPM3 PARAMETER TEST CONDITIONS f = 1 MHz t( (LPM3) ) Delay time f = 2 MHz f = 3 MHz VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 5 V MIN TYP MAX 6 6 6 µs UNIT 18 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 .2 MIN 0.5 25°C 0 –40 –20 0 20 Temperature [°C] 40 60 80 2.25×VCC 5 10 MAX 350 600 0.23×VCC MIN TYP 250 450 0.9 Figure 4. V(POR) vs Temperature LCD PARAMETER VO(HLCD) VO(LLCD) II(R03) II(R13) II(R23) ro(Rx3 to Sxx) Resistance Input leakage Output 1 (HLCD) Output 0 (LLCD) TEST CONDITIONS I(HLCD) <= 10 nA I(LLCD) <= 10 nA R03 = VSS.125 VSS TYP MAX VCC VSS+0. No load at all seg and com pins R23 = 2 VCC/ 3.5 V POR [V] 2 1.5 1 0.5 1. No load at all seg and com pins I(SXX) = –3 µA.8 MAX 1. VCC = 3 V/5 V 50 kΩ VCC = 3 V/5 V ±20 nA VCC = 3 V/5 V MIN VCC–0.1 1.125 UNIT V comparator (Timer/Port) PARAMETER I(com) ( ) Vref(com) Vhys(com) Comparator (Timer/Port) Internal reference voltage at (–) terminal In ut Input hysteresis (comparator) (com arator) TEST CONDITIONS CPON = 1 CPON = 1 CPON = 1 VCC = 3 V VCC = 5 V VCC = 3 V/5 V VCC = 3 V VCC =5 V 0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) 3 2.

2 V NOM MAX VCC ±0.2 –1.A3 = 0 . VCC = 5 V. 0. TEXAS 75265 19 .2 1.246 × V(SVCC) 95 –1 –3.4 × V(SVCC).5 –3. VCC = 3 V/5 V.A3 = 0 .1 100 UNIT V µA kΩ current source (ADC) PARAMETER V(Rext) R(ext) Voltage..5 × V(SVCC) IS = V(Rext)/R(ext)= 1 mA VA0. VCC = 3 V VCC = 5 V MIN NOM 200 300 MAX 400 740 UNIT µA µA SVCC (switched AVCC) PARAMETER V(SVCC) I(SVCC) Z(SVCC) Input impedance SVCC on.4 × V(SVCC).MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) ADC supply current (f(ADCLK) = 1 MHz) PARAMETER I(ADC) I(ADC) ADC current TEST CONDITIONS SVCC on. VCC = 5 V. current source off.. IS = V(Rext)/R(ext) = 6 mA VA0. current source off. IS = V(Rext)/R(ext) = 1 mA ∆IS VA0. SVCC off. 0. VCC = 3 V/5 V VCC = 2. I(RI) = 6 mA.252 × V(SVCC) 1600 1 3.249 × V(SVCC) MAX 0.2 TYP 0..2 UNIT V Ω µA µA µA µA Load compliance POST OFFICE BOX 655303 • DALLAS.A3 = 0 .A3 = 0 .. SVCC = 0 V. MIN 0. VCC = 3 V. 0. TEST CONDITIONS I(SVCC) = –8 mA. 0. SVCC off..5 × V(SVCC) IS = V(Rext)/R(ext)= 6 mA TEST CONDITIONS V(Rext) = V(SVCC) – V(RI). SVCC on..5 V VCC = 5 V 40 MIN VCC–0. VCC = 3 V/5 V VCC = 3 V.5 3.. (Rext) External resistor VA0..

000061×VSVCC –2 –3 –7 –10 –1 0.5 1.015 1.9925 0.14 96 132 0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) A/D converter (f(ADCLK) = 1 MHz) PARAMETER Resolution f( ) (con) f( (concyc) ) LSB Voltage INL1 INL2 INL3 INL4 DNL dN/dT dN/dV(SVCC) 0 ≤ DDV ≤ 127 Integral nonlinearity g y (see Note 15) 128 ≤ DDV ≤ 255 256 ≤ DDV ≤ 2047 2048 ≤ DDV ≤ 4095 Differential nonlinearity (see Note 16) Temperature stability V(SVCC)rejection ratio V(Rext)/R(ext) = 6mA. Range A Range B Range A. DDV is short form of delta digital value. 17. 16. The DDV is a span of conversion results.6 0.1 0.49 0.6 0.8 –1.6 –0.49 –0. TEXAS 75265 .7 –0. It is assumed that the conversion is of 12 bit not 12+2 bit. separate for the four 12-bit ranges and the 14-bit (12+2) range.24 0.9982 –0.13 1.0018 45 pF kΩ 2 3 7 10 1 TEST CONDITIONS MIN TYP 12 + 2 1.27 0.49 0. Offset referred to full scale 12/14 bit 18. FSRx: full scale range. SVCC ±10% Range A Range B Range C Range D Conversion offset 14 bit analog input to digital value (see Note 17) Slope 12 bit Slope 14 bit C(IN) R(SIN) Input capacitance Serial input resistance Range ABCD Conversion frequency Conversion cycles f( ) (con) = f(ADCLK) f(ADCLK) = f(MCLK)/N 12-bit conversion 12+2-bit conversion 12-bit conversion 12+2-bit conversion VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V 0.0075 1.5 MAX UNIT bits MHz cycles of y ADCLK V LSB LSB LSB LSB LSB LSB/°C LSB/V % FSRA (see Note 18) % FSRB (see Note 18) % FSRC (see Note 18) % FSRD (see Note 18) %FSRABCD (see Note 18) VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V VCC = 3 V/5 V g Conversion offset 12 bit analog input to digital value (see Note 17) NOTES: 15.2 –1.008 0.6 –0. V(Rext)/R(ext) = 1 mA. DNL is valid for all 12-bit ranges and the 14-bit (12+2) range.7 –1. B.06 1 1 40 2 0.25 –1. 20 POST OFFICE BOX 655303 • DALLAS.

P-. and E-versions. TCK. no further access to the MSP430 JTAG/test feature is possible. The JTAG block switches to by-pass mode.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) JTAG PARAMETER f(TCK) JTAG/test R(TEST) V(FB) I(FB) t(FB) V(PP) I(PP) t(pps) t(ppf) Pn EPROM ( ) and OTP(P) – (E) ( ) versions only JTAG/fuse ( JTAG/f (see N t 20) Note Pullup resistors on TMS. single pulse Programming time. 21. applied to TDI/VPP Current from programming voltage source Programming time. POST OFFICE BOX 655303 • DALLAS. The TMS and TCK pullup resistors are implemented in all C-. 20. E/P versions (see Note 21) Supply current on TDI to blow fuse Time to blow the fuse Programming voltage. TEXAS 75265 21 . fast algorithm Number of pulses for successful programming Data retention TJ < 55°C t(erase) y EPROM ( ) versions only (E) Erase time wave length 2537 Å at 15 Ws/cm2 (UV lamp of 12 mW/ cm2) Write/Erase cycles 4 10 30 1000 5 100 100 11 11. The voltage supply to blow the JTAG fuse is applied to TDI/VPP pin when fuse blowing is desired. TDI (see Note 19) Fuse blow voltage.5 TCK frequency TEST CONDITIONS VCC = 3 V VCC = 5 V VCC = 3 V/ 5 V VCC = 3 V/ 5 V MIN DC DC 25 11 60 TYP MAX 5 10 90 12 100 1 13 70 UNIT MHz kΩ V mA ms V mA ms µs Pulses year min cycles NOTES: 19. Once the JTAG fuse is blown.

5 f (DCO) / f (DCO@ 25°C ) f (DCO) / f (DCO@ 3 V) –20 0 20 40 60 80 T – Operating Free-Air Temperature – °C 90 1 1.8 DIGITAL CONTROLLED OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE 1.6 0.2 1.4 0.3 0.8 0.6 0.2 0 –40 0 0 4 2 VCC – Supply Voltage – V 6 Figure 5 Figure 6 22 POST OFFICE BOX 655303 • DALLAS.9 0. TEXAS 75265 .MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS DIGITAL CONTROLLED OSCILLATOR FREQUENCY vs OPERATING FREE-AIR TEMPERATURE 1.2 0.

TEXAS 75265 23 . XBUF) TDO_Internal VCC 60 k TYP TDO_Control TDI_Control TDI_Internal MSP430P/E325: TMS. B. TP5) CMOS 3-STATE OUTPUT (TP0–4.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS typical input/output schematics VCC (see Note A) (see Note B) (see Note B) VCC (see Note A) (see Note B) (see Note A) GND CMOS INPUT (RST/NMI) (see Note B) (see Note A) GND CMOS SCHMITT-TRIGGER INPUT (CIN) VCC (see Note A) (see Note B) (see Note B) (see Note A) GND I/O WITH SCHMITT-TRIGGER INPUT (P0. Optional selection of pullup or pulldown resistors with ROM (masked) versions.x. Anti-parallel diodes are connected between AVSS and DVSS. POST OFFICE BOX 655303 • DALLAS. TCK MSP430P/E325: TDO/TDI NOTES: A. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory.

TDO/TDI 24 POST OFFICE BOX 655303 • DALLAS. Figure 7. S1 VB Segment control VA VB Segment control LCDCTL (LCDM5.6. The ’P325 and ’E325 needs a pullup or a pulldown resistor to avoid floating a node which could increase the current consumption of the device. C. VB. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry. The TDI/VPP terminal of the ’P325 and ’E325 does not have an internal pullup resistor. MSP430P325/E325: TDI/VPP. An external pulldown resistor is recommended to avoid a floating node which could increase the current consumption of the device.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS typical input/output schematics VC COM 0–3 VD Control COM0–3 VA S0. Sn/On) NOTE: The signals VA. Sn. TEXAS 75265 . VPP_ Internal TDI_ Internal TDI/VPP JTAG Fuse TDO/TDI_Control TDO/TDI TMS JTAG Fuse Blow Control TDO_ Internal From/To JTAG_CBT_SIG_REG NOTES: A.7) S2/O2–Sn/On Data (LCD RAM bits 0–3 or bits 4–7) LCD OUTPUT (COM0–4. and VD come from the LCD module analog voltage generator. During programming activity and when blowing the JTAG enable fuse. VC. The TDO/TDI terminal is in a high-impedance state after POR. B. the TDI/VPP terminal is used to apply the correct voltage source.

Activation of the fuze check mode occurs with the first negative edge on the TMS pin after power-up or if TMS is being held low during power-up. pulldown Open Open POST OFFICE BOX 655303 • DALLAS. Fuse Check Mode Current. TCK. P/E3xx TDI TDO TMS TCK 68k.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned. MSP430P/E325 Care must be taken to avoid accidentally activating the fuse check mode. Configuration of TMS. TEXAS 75265 25 . ITF . of 1 mA at 3 V. a fuse check current. The second positive edge on the TMS pin deactivates the fuse check mode. pulldown 68k. Time TMS Goes Low After POR TMS ITDI ITF Figure 8. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. including guarding against EMI/ESD spikes that could cause signal edges on the TMS pin. the fuse check mode remains inactive until another POR occurs. TDI/VPP and TDO/TDI pins in applications. When activated.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 TYPICAL CHARACTERISTICS JTAG fuse check mode MSP430 devices that have the fuse on the TDI/VPP terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). After deactivation. 2. After each POR the fuse check mode has the potential to be activated.

10 MAX 0. All linear dimensions are in millimeters.10 0.80 24.60 19 0. B.70 TYP 0. 0°– 10° 26 POST OFFICE BOX 655303 • DALLAS.10 4040101 / B 03/95 NOTES: A.00 17.10 MIN 1. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.20 64 20 1 18.25 33 0.15 NOM Gage Plane 0. TEXAS 75265 . This drawing is subject to change without notice.20 M PLASTIC QUAD FLATPACK 1.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 MECHANICAL DATA PG (R-PQFP-G64) 0.80 18.45 0.00 TYP 14.20 19.25 2. C.40 23.70 Seating Plane 3.00 TYP 20.00 51 52 32 12.20 13.

1/RXD P0.5 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 AVCC DVSS AVSS A1 A0 XBUF RST/NMI TCK TMS TDI/V PP TDO/TDI COM3 COM2 COM1 COM0 S20/O20/CMPI S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/O7 S6/O6 S5/O5 S4/O4 10 11 12 13 14 15 33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0.3 TP0.4 TP0. TEXAS 75265 27 .1 TP0.2 TP0.2/TXD P0.5 P0.0 TP0.7 R33 R32 R13 R03 S0 S1 S2/O2 S3/O3 POST OFFICE BOX 655303 • DALLAS.6 P0.3 P0.0 P0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 MECHANICAL DATA MSP430P325 (PM package) PM PACKAGE (TOP VIEW) DVCC SVCC Rext A2 A3 A4 A5 Xin Xout/TCLK CIN TP0.4 P0.

D.50 TYP 10.60 MAX 0.25 0.80 1.50 0.08 M 49 32 64 17 0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 MECHANICAL DATA PM (S-PQFP-G64) 0.27 0.45 1.08 4040152 / C 11/96 NOTES: A. B.35 16 Gage Plane 0.75 0.05 MIN 0°– 7° 0.45 Seating Plane 1. TEXAS 75265 .20 SQ 11. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads.20 SQ 9.80 12. 28 POST OFFICE BOX 655303 • DALLAS. This drawing is subject to change without notice.17 48 33 PLASTIC QUAD FLATPACK 0. C. All linear dimensions are in millimeters.13 NOM 1 7.

7 R33 R23 R13 R03 S0 S1 S2/O2 S3/O3 NC POST OFFICE BOX 655303 • DALLAS.4 P0.0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVCC NC DVSS AVSS A1 A0 XBUF RST/NMI TCK TMS TDI/VPP TDO/TDI COM3 COM2 COM1 COM0 NC 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 S20/O20/CMPI S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/O7 S6/O6 S5/O5 S4/O4 NC – No internal connection NC P0. TEXAS 75265 29 .5 P0.0 TP0.2 TP0.1 TP0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 MECHANICAL DATA MSP430P325 (FN package) FN PACKAGE (TOP VIEW) DVCC SVCC Rext A2 A3 A4 A5 Xin Xout/TCLK CIN TP0.2/TXD P0.4 TP0.5 P0.6 P0.3 TP0.1/RXD P0.3 P0.

369 (9.78) 0.74) NOTES: A.008 (0.007 (0.169 (4.58) 0.32) 0.319 (8.13) 1.20) NOM 0.10) 0. C.85) 0.51) 0.020 (0.33) 1.750 (19.05) 0.04) 0.27) 1.191 (4.43) 0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 MECHANICAL DATA FN (S-PQCC-J**) 20 PIN SHOWN Seating Plane 0.65) 0.21) 0.57) 0.958 (24.56) 0.05) 0.541 (13.20) 0.495 (12.57) MAX 0.695 (17.35) MIN D1 / E1 MAX 0.685 (17. All linear dimensions are in inches (millimeters).58) 0.450 (11.41) MIN D2 / E2 MAX 0.29) 0.40) 0.10) D D1 3 1 19 0.219 (5.94) 0. OF PINS ** 20 28 44 52 68 84 D/E MIN 0.650 (16.10) MAX 0.02) 1.180 (4.026 (0.785 (19.350 (8.456 (11. Falls within JEDEC MS-018 30 POST OFFICE BOX 655303 • DALLAS.53) 0.51) MIN PLASTIC J-LEADED CHIP CARRIER E E1 D2 / E2 8 14 0.395 (10.195 (30.795 (20.341 (8.19) 0.91) 0.985 (25.03) 0.66) 4 18 D2 / E2 0.89) 0.33) 0.291 (7.158 (29. This drawing is subject to change without notice.66) 0.385 (9. TEXAS 75265 .120 (3.356 (9.090 (2.656 (16.29) 0.66) 0.485 (12.013 (0.756 (19.39) 0.032 (0.569 (14.20) 0.27) 9 13 0.150 (29.45) 4040005 / B 03/95 0.185 (30.021 (0.441 (11.995 (25.050 (1.950 (24.81) 0.18) M NO. B.469 (11.141 (3.004 (0.37) 0.

0 TP0. TEXAS 75265 31 .2/TXD P0.1 TP0.2 TP0.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 PMS430E325 (FZ package) FZ PACKAGE (TOP VIEW) DVCC SVCC rext A2 A3 A4 A5 Xin Xout/TCLK CIN TP0.1/RXD P0.4 TP0.0 AV CC NC DVSS AVSS A1 A0 XBUF RST/NMI TCK TMS TDI/ Vpp TDO/TDI COM3 COM2 COM1 COM0 NC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 S20/O20/CMPI S19/O19 S18/O18 S17/O17 S16/O16 S15/O15 S14/O14 S13/O13 S12/O12 S11/O11 S10/O10 S9/O9 S8/O8 S7/O7 S6/O6 S5/O5 S4/O4 NC – No internal connection NC P0.5 P0.3 TP0.3 P0.6 P0.5 P0.4 P0.7 R33 R23 R13 R03 S0 S1 S2/O2 S3/O3 NC POST OFFICE BOX 655303 • DALLAS.

730 (18.MSP430P325 MIXED SIGNAL MICROCONTROLLER SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000 MECHANICAL DATA FZ (S-CQCC-J**) 28 LEAD SHOWN 0. TEXAS 75265 .455 (11.930 (23. 32 POST OFFICE BOX 655303 • DALLAS.66) C (at Seating Plane) 0.025 (0.040 (1.910 (23.94) 0.765 (19. C.955 (24.610 (15.56) 0.11) C MAX 0.120 (3.985 (25.630 (16.655 (16.32) 0.155 (3.485 (12. All linear dimensions are in inches (millimeters). OF PINS** 28 44 52 68 4040219 / B 03/95 NOTES: A.43) 0.090 (2.180 (4.050 (1.62) JEDEC OUTLINE MO-087AA MO-087AB MO-087AC MO-087AD NO.695 (17.55) 0.79) 0.02) MAX 0.64) 0.680 (17.27) A B 0.430 (10.040 (1.92) 0.795 (20.430 (10.120 (3.930 (23.785 (19.00) 0.02) J-LEADED CERAMIC CHIP CARRIER  45° A B 4 1 26 0.014 (0.026 (0.54) 0.685 (17. This package can be hermetically sealed with a ceramic lid using glass frit.51) 0. B.020 (0.05) Seating Plane 5 25 0.00) 0.19) 0.26) MIN 0.995 (25.81) 0.032 (0.28) 0.57) 0.57) 0.495 (12.36) 11 19 12 18 0.94) 0.29) A MIN 0. This drawing is subject to change without notice.05) 0.630 (16.27) MIN 0.65) 0.140 (3.64) R TYP 0.49) 0.92) 0.41) 0.02) MIN 0.40) 0.62) B MAX 0.410 (10.740 (18.

or process in which such semiconductor products or services might be or are used. Copyright © 2000. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. is granted under any patent right. adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. and limitation of liability. and advise customers to obtain the latest version of relevant information to verify. except those mandated by government requirements. before placing orders. mask work right. patent infringement. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. including those pertaining to warranty. that information being relied on is current and complete. copyright. either express or implied. or other intellectual property right of TI covering or relating to any combination. TI does not warrant or represent that any license. machine. TI assumes no liability for applications assistance or customer product design. warranty or endorsement thereof. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval. Texas Instruments Incorporated .IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice. Specific testing of all parameters of each device is not necessarily performed. In order to minimize risks associated with the customer’s applications. Customers are responsible for their applications using TI components.

This datasheet has been download from: www.datasheetcatalog. .com Datasheets for electronics components.