Michael DePasquale

ECE 3450
Digital Notebook
Practica 1 - 9

....... Discussion of Results............................................. Diagrams and Figures .... Procedure ..............1 ii....... Procedure ..............25 Practicum III: Field Programmable Logic Devices ..................................................... and Graphs.......................................................................................... Discussion of Results.................................................... Pre-Lab.... Conclusions......................................................................................... Data.................................................................................................................... Calculations..Table of Contents page Practicum I: Properties of Digital Devices ........................ Discussion of Results........... Calculations.............................................7 i.....................................................18 iii....2 iv...............24 v..................................................17 Practicum II: Layout of a CMOS Circuit.................................................... Purpose......................................7 ii.............................................................................. Purpose.........................................................................1 Part i: Voltage Transfer Characteristics....................13 iv............................................................. Discussion of Results.............................. Discussion of Results.......................6 Part ii: Power Supply Current and Power Dissipation......................................18 i......14 v...............9 v.........................................28 iv................................. Diagrams.................................... Procedure ............................................................. Procedure ................................................ Conclusions.......... Figures................. Purpose................ Purpose... Conclusions...32 ............... and Graphs..............................................................................................................12 ii................................................................................................................................ Data............................ Pre-Lab.................................................................. and Code...........................................................................................4 v....27 iii........................................................ Pre-Lab..............................................11 Part iii: Average Propagation Delay Time and Power-Delay Product ...............1 iii....................12 iii....................12 i................. Calculations.............. Data...........................7 iii. and Graphs........................................................................................................ Procedure ......................1 i..............................................................................5 vi.................10 vi.................26 ii.......26 i...........16 vi................. Conclusions...................... Pre-Lab......................... Purpose....................8 iv...........30 v.18 ii............................................19 iv................31 vi............................................................................................ Conclusions..................................

we must establish thresholds so that we can answer the question “how high must the voltage be to be counted as ‘logic high’ and how low must the voltage be to be counted as ‘logic low?’” II. Part i Monday. and VOL.” with nothing in-between. Procedure To answer the above-stated question about voltage thresholds. January 23 2006 Michael DePasquale Practicum I: Properties of Digital Devices Part i: Voltage Transfer Characteristics I. 1 of 155 . We will capture all measured data from the oscilloscope. Purpose Ideally. In both cases we will ground all of the five remaining inputs to reduce the amount of noise. VIH. We will begin by setting up the function generator to give us a sawtooth waveform with an amplitude of 5V and a frequency of 1KHz. the input of a logic gate should always be either clearly “high” or clearly “low. and mark up the graph with the values for VIL. We will use this as the input to both a 74LS04 inverter and a CMOS 4069 inverter.Practicum I. VOH. Thus. we will observe the behavior of two inverters at all voltages between and including 0 and 5V.

Data. VOL High level Voltage Output. VIL High level Voltage Input. VIH Low level Voltage Output.Practicum I. VOH Hence calculated Noise Margin CMOS 4069 Parameter Low level Voltage Input. VOL High level Voltage Output. VOH Hence calculated Noise Margin Min Typical Max Measured Units Min Typical Max Measured Units 2 of 155 . VIL High level Voltage Input. VIH Low level Voltage Output. Calculations. and Graphs Data Tables 74LS04 Parameter Low level Voltage Input. January 23 2006 III. Part i Monday.

Part i Monday.Practicum I. January 23 2006 Graphs TTL (74LS04) 5V VO 4V VOH 3V VLS 2V 1V V OL VIL1V VIH 2V VTW CMOS (CD4069) VO 5V VOH 4V 3V VLS 2V 1V VOL 1V 2V VIL VIH 3V VTW 3 of 155 4V VI .

CMOS Results For the CMOS inverter. and very close to the manufacturer’s extreme conditions. we found that VIL is approximately 19% greater than manufacturer’s specification for VILmax. and they were approximately a factor of 2 away from the manufacturer’s extreme conditions. we feel that these are reasonable calculations because the manufacturer specifications deal with the worst case scenario. Again.5% less than the manufacturer’s specification for VIHmin. All of this resulted in the following noise margins: NMH = NML = NM = Thus. Again. we found that VIL and VOH were near the typical manufacturer’s specifications. our calculated noise margin of was slightly greater than the manufacturer’s value of . January 23 2006 IV. Our measurement for VOL was also approximately 20% greater than the manufacturer’s specification for VOLmax. Again. Some of this error can be attributed to noise in the system. Discussion of Results TTL Results For the TTL inverter. Part i Monday. We feel that these are reasonable calculations because the manufacturer specifications deal with the worst case scenario (with a large load on the inverter). this makes sense because our test did not involve such stringent conditions as the manufacturer’s test. our calculated noise margin of was nearly two times greater than the manufacturer’s value of . our measurement for VIH was approximately 12.Practicum I. and as a result it performed better. while our test was done under close to ideal conditions (with very little load on the inverter). this makes sense because our test did not involve such stringent conditions as the manufacturer’s test. Our measured value for VOH was above the manufacturer’s specification for a typical VOH. Our measurements for VOL and VOH were exactly the same as the manufacturer’s typical measurements. but it was still in the normal operating range. All of this resulted in the following noise margins: NMH = NML = NM = Thus. 4 of 155 . Also.

Part i Monday. we learned more about how to use all of the lab equipment. and the different features of the wave generator) work. that manufacturer’s spec sheets are designed to show the worst case conditions of a product. VOH. Conclusions From this part of this practicum. Also. and that it may be in a designer’s benefit to test a component to get performance data for a particular application. VOL. we learned the distinct differences between CMOS and TTL gates: specifically that TTL gates have different specification definitions (ie: VOH and VOL) because TTL gates do not perform as well. and both noise margins for both a TTL inverter and a CMOS inverter. 5 of 155 . Finally.Practicum I. VLs. we were able to accurately determine the values for VIL. In comparing this to the manufacturer’s data sheets. In this lab. we learned a few things: first. January 23 2006 V. we found that our results were near the expected values in all cases. VIH. VTW. and gained a general understanding of how different things (such as the data capture on the oscilloscope.

VOL High level Voltage Output. VIL High level Voltage Input.Practicum I. VIH Low level Voltage Output. VOL High level Voltage Output. January 23 2006 ECE 3450 Practicum I. Part i Monday. Part i: Pre-Lab Circuit Diagram 74LS04 Parameter Low level Voltage Input. VOL High level Voltage Output. VOH Hence calculated Noise Margin Min 6 of 155 Typical Max Measured Units Max Measured Units Max Measured Units . VIH Low level Voltage Output. VOH Hence calculated Noise Margin Min Typical CMOS 4069 (Texas Instruments and National Semiconductor) Parameter Min Typical Low level Voltage Input. VIL High level Voltage Input. VIL High level Voltage Input. VIH Low level Voltage Output. VOH Hence calculated Noise Margin CMOS 4069(Motorola) Parameter Low level Voltage Input.

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