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Clock Strategy

VLSI System Design

Clocked Systems Latch and Flip-flops System timing Clock skew High speed latch design Phase locked loop Dynamic logic Multiple phase clock Clock distribution
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Clocked Systems
Most VLSI systems are a combination of
pipelines and finite state machines(FSM) Pipelined systems
Input D Q Logic D Q ... Logic D Q output

CLK

CLK

Finite state machine

Comb. Logic

QD CLK or CLKS
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Single-phase clock timing waveforms


Cycle Time (Tc) Clock Setup Time (Ts) CLK

Tc: clock cycle time (period)

D Q

data

Hold Time (Th)

Q Clock-to-Q Delay (Tq)

Ts: setup time -- the time before the clock edge during which the data input (D) has to be stable Th: hold time -- the time after the clock edge during which the data input (D) has to remain stable Tq: clock-to-Q delay -- The delay from the clock edge to the Q output
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Latches and flip-flops


D 0 Q 1 s CLK

clk D Q

(a) Negative Latch (Level sensitive)

clk
0 Q D 1 s CLK

D Q

(b) Positive Latch (Level sensitive)

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Latches and flip-flops


clk

0 0 1 s CLK master QM Q 1 s CLK

D QM Q

slave

(c) Positive edge-triggered register(single-phase clock)

clk=0

clk=1 master slave

(d) Pass transistor/inverter implementation

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System timing
(A) Positive-edge triggered
Tc

clock

Register A

Tq

Combinational Logic Td

Ts

Register B
Tq Td Ts

Tc >Tq + Td + Ts

(B) Alternatively, one may use latches as storage elements to save area.

clock

Latch A

Tq

Combinational Logic Td

Ts

Latch B

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System timing (cont)


(C)
A Latch A Tq Combinational Logic Tda Ts Latch B B Combinational Logic Tdb Latch c

clock

Tc1

Tco

Tc1>Tqa+Tda+Tsb Tsb=Tsc
Tqa
Tda Tsb Tqb Tdb Tsc

Tco>Tqb+Tdb+Tsc

If Tc=Tc1+Tco and Tc1=Tco, Tqa=Tqb, => The limit is Tc = Tda + Tdb + 2(Tq+Ts)

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Racing due to clock skew


1 REG 1-bit d q Logic Td 2 0 REG 1-bit d q

1. If Tc2 > Tc1 + tq1 + td2


M2 may sample a wrong data (current data) Transparency problem

M1 clk delay Tc1 delay Tc2

M2

2. If Tc1 + tq1 + td2 >Tc (cycle time)


clk Tc1 Td 2 Old Data Tc2 New Data

M2 cannot sample the previous data

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Single-phase clock using D-FF


C1 L1 C2 L2

1) C2=C1

C2

C1

C1 C2 Wrong data in L2 2) C1=C2 C1 C2 Correct data

C1 = C2
C2 C1

or

C2 = C1
C1 C2

L1

L2

Comb
Wrong only if Comb.

CLK

Logic

FSM --> "feedback" or Pipeline --> "feedthrough"

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To eliminate (reduce) time skew (clock skew)


1.Balanced delay clock driver
clk-in clk

2.Use buffers where necessary


clk clk
Large Load

clk

clk

clk

clk-in

clk

3.Very careful simulation(HSPICE) 4.Very small rise and fall time on the clock-- large buffer for large load 5.Multiple clocking strategies

clk

usually slightly smaller than the inverter

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Some Implementations of clocked latches


Use a weak trickle inverter
-ck D ck
small inverter (low-gain, smaller W or large L)

D clk clk Q clk clk

eliminate a metal connection smaller area

or
D c lk c lk c lk

Transmission-gate latch
Q D

c lk

buffered input
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compared with a tri-state buffer


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Typical symbolic layouts for latches


(a)
V

(b)
DD
V

(c)
DD
V

DD

Q D

clk

-clk

SS

clk

-clk

clk

-clk

SS

SS

-clk
D clk clk clk Q clk

-clk

clk D -clk

clk Q

clk D -clk

clk Q

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logic gate based latches


(a) Level sensitive
D Q
clk

-Q clk
D

(b) Edge triggered


D Q

-Q clk

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Asynchronously settable and resettable F/Fs


-clk -reset Q clk D -clk -clk clk -reset
Q clk D -clk
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(a)

clk

-clk

clk

-clk

(b)

clk

-clk

clk

clk

-set -clk
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Dynamic single clock latches


The feedback inverter and transmission gate are eliminated. The latched value is stored on the capacitance of the input to
the inverter (mainly gate capacitance) Clock-to-Q (Tq) is very small need to be very careful to prevent transparency problem. Internal inversion of the clock is often necessary. Dynamic nodes should be always refreshed or clamped to a known state when in stand-by or low-power mode.
clk D -clk -Q
D -clk clk

(a)

(b)

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Dynamic single clock latches (cont)

clk D
D

clk

-clk Q

clk D -clk

-clk Q clk

-clk
-clk clk

(c)Tristate inverter

(d)master-slave F/F

(e)

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Refreshing for Dynamic latches


Dynamic storage nodes are
usually a gate capacitance. Assume the leakage current= 1 nA and the storage capacitance = 0.02PF
C V 5 = 0.02 10 12 9 = 100s i 10

Even if the storage of the


correct state is unimportant, the leakage may cause the storage node to assume a level that causes the inverter to draw significant current.
large current 5V -> 2.5V

must refresh every 100s

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Phase locked loop (PLL) clock techniques


(1) To synchronize internal and external clocks. (2) To synchronize data transfers between chips. (3) To operate the internal clock at a higher rate.
(1)
clock clock pad clock route dclk output pad dclk+dpad clock dclk data out chip PLL clock clock pad clock route dclk output pad dclk+dpad clock dclk data out

(a) Without PLL

(a) With PLL

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PLL techniques
(2)
bus high speed tristate bus

(3)
chip PLL /4

clock clock pad clock route dclk output pad dclk+dpad clock d clk

clock PLL PLL

clock

system clock

To ensure the output of chips are synchronized with each other.

Clock rate at d clk 4 = clock d clk = 4 clock


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Block diagram of a PLL circuit


n Ffb Phase Detector reference clock(F ) in
Phase detector: detect the difference between Ffb and Fin.
If Ffb > Fin =>D pulse If Ffb > Fin =>U pulse

U D Charge pump Filter VCO n*Fin

Charge pump: charge or Discharge a capacitor according to D and U. Filter: filter the capacitor output (smoother). VCO: Change the oscillation frequency depending on the control voltage. (Voltage Control Oscillator)

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Phase Detector
F1
F1 16/8 16/8 16/8 16/8 16/8 UP 16/8

F2
16/8 16/8

If F1 falls before F2 => UP=1


16/8

If F2 falls before F1 => DN=1


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F2 16/8

16/8 16/8

16/8 16/8 DN

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Charge Pump
40/2 P1 P-REF CHGUP N2 40/2 CHGDN N4 N-REF P-REF P1 40/2

SW0

2/5 2/5

N1

P-SWITCHSW0 SW1 CAP P-SWITCH SW0 SW1 N-REF N5 40/2

N3 10/2

IN

8/1 16/1 10/2 10/2 SW1

Bias circuit

CAP charges when CHGUP=1 discharge when CHGDN=1

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Filter
VCO
in 2/6 4/6
32/1
13stages

out

32/1

32/1

32/1 32/1 32/1 16xFsc 16/1

2400/6

2400/6

control voltage 16/1

16/1 16/1
VCO

16/1 16/1

in

out

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Metastability Problem
D clk clk Q Q
clock 4ns delay 2ns Q -Q No Problem data

delay=2.2ns

If the setup or hold time is not satisfied, I.e., D changes at the activation edge of the clock, then the output Q will have a state depending on the timing relation between D and CLK

delay=2.3ns

Q metastable Long delay point -Q

Q metastable point -Q delay=2.4ns

Output error

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Metastable state in a pair of inverters


Inv1 A B
To Solve the metastability problem:
Setup time is shorter than the clock-to-Q delays in a synchronization system. For asynchronous input : need a special circuit called synchronizer.

VB

Inv2

Inv1 metastable point Inv2 VA 5V

0V
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2.5V

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Single-phase N-P CMOS dynamic logic


Combine N-P section of domino logic with clocked CMOS (C2MOS) latch as the output stage.
to n-logic blocks to p-logic blocks clk -clk -clk Inputs from -clk stages clk to -clk section to p-logic blocks to n-logic blocks

clk

-clk -clk clk to -clk section

(b)

n-logic block n-p CMOS -clk logic stage

p-logic block

C2MOS latch

n-logic block (a)


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p-logic C2MOS latch block From n or buffered p-logic n-p CMOS clk logic stage

-clk logic

clk logic

-clk logic evaluation Precharge

evaluation Precharge Precharge evaluation (c)

clk -clk 0 1 1 0

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Design rules for N-P CMOS dynamic logic


Two problems to be solved
1.Each section must be internally race free. 2.When different section are cascaded to from pipelined system, clock skew should not cause a problem.
clk clk

R1: During precharge, logicblocks must be switched off. R2: During evaluation, internal inputs can make only one transition. When a static logic is used in a N-P CMOS dynamic logic, it should be placed after dynamic logic (I.e., one should keep the static logic up to the C2MOS latch. Reason: static logic after creates a glitch at its output.

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R3: There exists in each logic block Reason: at least one dynamic gate that is separated from 1 1 or the previous C2MOS 2 output stage by an even number C MOS of inventions. clk or clk C2MOS R4: The total number of inversions or Domino between two consecutive C2MOS stage is even.
-clk clk clk -clk

clk

clk

The same evaluation phase in a section

even number of inversions C2MOS latch output stage (-clk section)

at least one dynamic stage

C2MOS latch (clk section)

OR

even umber of inversions


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Two phase clocking


phi1 phi 2 -phi1 D phi (a) 1

phi1 phi2
-phi2 phi2 DFF1 Q

phi1 logic phi2 logic overlap

skewed clokcs

(c) small dealy

phi1=1 phi2=0 phi =0 1 phi =1 2 (b) C1 C2

slow rise time overlap phi1=1 phi2=0 (d)

C1

C2

C2

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Two phase clock generation


Two-phase clock generator 1. Globally distribute two clocks with or without their 1 clk complements. 3. A single global clock and locally generated two-phase clocks

Delay for non-overlap period

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Two phase registers


-phi1 D DEF1
-phi 2
high level =V

-phi 2
D

DD

-V

tn Q DEF1A

Q
(a) phi1 phi 2

phi1
-phi1 D phi1

phi2
-phi 1

p leakers

-phi

2 n

D phi

n 1 phi2

D (b) phi D 1 phi 2 DEF1B

phi2

DEF2 Both of these dynamic registers have to drive a local storage gate.
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DEF3

clk (c)

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Two phase logic


1. Static logic with two phase registers
Logic 1 Logic 2

2. Dynamic logic
-phi1 from phi2 stage -phi1 phi1 n-logic -phi2 -phi2 phi1 n-logic to phi 1 phi2 stage phi2

phi1 phi1

phi1

evaluate phi1 logic precharge phi1 logic latch phi data 2 evaluate phi2 logic precharge phi2 logic latch phi1 data latch phi2 data

precharge phi1 logic

phi2

evaluate phi2 logic

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Four-Phase clock
11 12 nonoverlapping 23 24
clk 1 clk 2 D clk 1 clk 3 n 1 clk 4 clk 3 in v2 clk 3 clk 34 clk 3 clk 1 Q clk 2 clk 3 clk 4
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Four-Phase logic clocking method

Slave Latch

Logic

Master Latch

Logic

clk 1 Q clk 2 clk 3 clk 4

clk1

clk2

clk3

clk4

(a) in v1 clk 1 clk 12 D clk 1 (b )


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Clock distribution
n-bit datapath

1. A single large buffer 2. A distributed-clock-tree approach

n-bit datapath n-bit datapath n-bit datapath n-bit datapath n-bit datapath clock n-bit datapath delays have to match between stages n-bit datapath n-bit datapath n-bit datapath n-bit datapath n-bit datapath

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Trends in clock strategy


For first-time designer, use static logic, single-phase
static registers. For standard cell and gate-array design, single-phase may be the only choice. Two phase clocking make timing design of RAMs, ROMs and PLAs easier. In modern process and circuits, cycle time is the main concern => single phased Processes are extremely dense => single phase

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