Microprocessor Complete | Read Only Memory | Central Processing Unit

MICROPROCESSOR & INTERFACES (CSE & IT SEM -V) Prepared By: SUDHA NAIR LECTURER(E&TC) R.C.E.T,BHILAI.

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UNIT- I Microprocessor Architecture

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Introduction to Microprocessors

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What is a microprocessor?
 A microprocessor is a programmable digital electronic

component that incorporates the functions of a central processing unit or CPU on a single semi conducting integrated circuit.

 One or more typically serve as the CPU in computer

systems, embedded devices, or handheld devices.

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What is a microprocessor?
 That means your laptop at home and the PC in your

computer lab!
 The advent of the microprocessor astounded many

people.
 It was an entire computation engine on one tiny chip.

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Going from the ENIAC which filled an entire room and used over 18,000 vacuum tubes to a 1/8th by 1/6th of an inch (fingernail size) mega chip!

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The First Microprocessor: Intel 4004
 Transistor count  Today's Intel® Core™2 Duo processors contain over

291 million transistors.

 This is 100,000 times the number of transistors than

were in the 4004, which had 2,300 transistors when it was introduced in 1971.

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The First Microprocessor: Intel 4004
 A human hair

The Intel 4004 microprocessor circuit line width was 10 microns or 10,000 nanometers.  Today Intel's microprocessors have circuit line widths of .065 microns or 65 nanometers.  A nanometer is one billionth of a meter.  By comparison, a human hair is approximately 100 microns or 100,000 nanometers.

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The First Microprocessor: Intel 4004
 Manufacturing  The Intel 4004 microprocessor was produced on 2" wafers

initially and then on 3" wafers.  Today's microprocessors are produced on 12" or 300mm wafers.

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The First Microprocessor: Intel 4004
 The Intel 4004 microprocessor is unique in that, if it is

not the smallest, it is one of the smallest microprocessor designs that ever went into commercial production.
 The 4004 microprocessor is composed of 5 layers.

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Intel 4004

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Who invented the microprocessor and when?
 In November 1971, a company called Intel, which we

are all familiar with today, is given most of the credit for inventing the first microprocessor (Intel 4004).

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Ted Hoff and Stan Mazor are said to be the brilliant minds behind the microprocessor.Who invented the microprocessor and when?  Three Intel engineers named Federico Faggin. & Technology 13 .  MYcsvtu Notes Rungta College of Engg.

 Before the microprocessor.Why was the microprocessor invented?  The microprocessor reduced the word size of the CPU from 32 bits to 4 bits so that the transistors of its logic circuits would fit onto a single part. electronic CPUs were typically made of big discrete switching devices containing only a few transistors. MYcsvtu Notes Rungta College of Engg. & Technology 14 .

& Technology 15 . doubles every 24 months.Why was the microprocessor invented?  The microprocessor greatly reduced the cost of processor power and the physical size of the CPU. with respect to minimum component cost.  The evolution of microprocessors has been known to MYcsvtu Notes Rungta College of Engg. follow Moore‟s Law which states that the complexity of an integrated circuit.

Why was the microprocessor invented?  This has held true throughout the years………………. ………………………. & Technology 16 . ever since the microprocessor was created. MYcsvtu Notes Rungta College of Engg.

MYcsvtu Notes Rungta College of Engg. & Technology 17 .  This breakthrough invention powered the calculator and paved the way for embedding intelligence in inanimate objects as well as the personal computer.The “building block”  Microprocessors forever changed the way that computing systems are made.

& Technology 18 .  Embedded intelligence brought by microprocessors MYcsvtu Notes Rungta College of Engg. we would not be as technologically advanced in computers as we have become today.Applications of microprocessors  Without this amazing invention.

Microprocessor’s interference in day to day life…… MYcsvtu Notes Rungta College of Engg. & Technology 19 .

& Technology 20 .Automation MYcsvtu Notes Rungta College of Engg.

Communication MYcsvtu Notes Rungta College of Engg. & Technology 21 .

MYcsvtu Notes Rungta College of Engg.Brief history of microprocessor  Intel i4004 processor  Identification  Model name: i4004. Component class: CPU. & Technology 22 . Supplier: Intel.

& Technology 23 .Intel i4004 processor  Architecture  4 bit data bus. 12 bit address bus (multiplexed). Separate address space for instructions and data (Harvard architecture). MYcsvtu Notes Rungta College of Engg.

MYcsvtu Notes Rungta College of Engg.  Dates  Introduction date: 1970.Intel i4004 processor  Physics  Manufacturing technology: PMOS.  Number of transistors: 2250.  Die size: 24 mm2.  First microprocessor ever built.  Packaging: 16 pin CerDIP. & Technology 24 .

Component class: CPU. & Technology 25 . Supplier: Intel.     Compatibility Intel i4004 CPU with extra features: more instructions. MYcsvtu Notes Rungta College of Engg. interrupt support.Intel i4040 processor  Identification  Model name: i4040.

MYcsvtu Notes Rungta College of Engg.Intel i4040 processor  Architecture  4 bit data bus. Separate address space for instructions and data (Harvard architecture). 12 bit address bus (multiplexed). & Technology 26 .

 Dates  Introduction date: 1972 MYcsvtu Notes Rungta College of Engg. & Technology 27 .Intel i4040 processor  Physics  Manufacturing technology: PMOS  Packaging: 24 pin CerDIP.

Intel i8008 processor  Identification  Model name: i8008. & Technology 28 . MYcsvtu Notes Rungta College of Engg. Supplier: Intel. Component class: CPU.

14 bit address bus (multiplexed). Separate address space for instructions and data (Harvard architecture).  Clock speed300 kHz MYcsvtu Notes Rungta College of Engg. & Technology 29 .Intel i8008 processor  Architecture  8 bit data bus.

 Number of transistors: 3300.  Packaging: 18 pin CerDIP. & Technology 30 .  Dates  Introduction date: April 1972.Intel i8008 processor  Physics  Manufacturing technology: PMOS. MYcsvtu Notes Rungta College of Engg.

Component class: CPU. & Technology 31 .Intel i8080/i8080A processor  Identification  Model name: i8080/i8080A.  Compatibility  Intel i8008 CPU with stack. MYcsvtu Notes Rungta College of Engg.  Generation  Generation: 8080. Supplier: Intel.

Intel i8080/i8080A processor  Architecture  8 bit data bus. Separate address space for instructions and data (Harvard architecture). & Technology 32 . MYcsvtu Notes Rungta College of Engg.  Introduction date: April 1974.  Physics  Packaging: 40 pin CerDIP. 16 bit address bus.

& Technology 33 .     Generation Generation: 8080.Intel i8085A/i8085AH processor  Identification  Model name: i8085A/i8085AH. Compatibility Intel i8080 CPU upward instruction compatible. Component class: CPU. MYcsvtu Notes Rungta College of Engg. Supplier: Intel.

including NMI (Non-Maskable Interrupt). & Technology 34 . MYcsvtu Notes Rungta College of Engg.Intel i8085A/i8085AH processor     Extra instructions: SIM (Set Interrupt Mask) RIM (Read Interrupt Mask) Extra interrupt lines.

& Technology 35 . 16 bit address bus. Separate address space for instructions and data .Intel i8085A/i8085AH processor  Architecture  8 bit data bus. Data and address bus are multiplexed. MYcsvtu Notes Rungta College of Engg.

& Technology 36 . Intel I8085a Intel iM8085A Intel i8085AH-2 Intel i8085AH-1 Intel iM8085AH 5 MHz 6 MHz MYcsvtu Notes Rungta College of Engg.Intel i8085A/i8085AH processor  Clock speed  Physics  Number of transistors: Clock speed Model Manufactu ring technolog y NMOS NMOS HMOS HMOS HMOS 3 MHz 6200.  Packaging: 40 pin CerDIP.

& Technology 37 .Major designers       Intel Advanced Micro Devices (AMD) IBM Microelectronics AMCC Freescale Semiconductor ARM Holdings MYcsvtu Notes Rungta College of Engg.

& Technology 38 .Major designers         MIPS Technologies Texas Instruments Semiconductors Renesas Technology VIA Technologies Western Design Center STMicroelectronics Sun Microsystems CPU Tech MYcsvtu Notes Rungta College of Engg.

& Technology 39 .Microprocessor based system MYcsvtu Notes Rungta College of Engg.

Microprocessor based system  The typical processor system consists of:    CPU (central processing unit)  ALU (arithmetic-logic unit)  Control Logic  Registers. & Technology 40 . etc… Memory Input / Output interfaces MYcsvtu Notes Rungta College of Engg.

& Technology 41 .Microprocessor based system  Interconnections between these units:    Address Bus Data Bus Control Bus MYcsvtu Notes Rungta College of Engg.

& Technology 42 .Basic definitions Bus: A shared group of wires used for communicating signals among devices  address bus: the device and the location within the device that is being accessed  data bus: the data value being communicated  control bus: describes the action on the address and data buses MYcsvtu Notes Rungta College of Engg.

& Technology 43 .Basic definitions Memory: Where instructions (programs) and data are stored Organized in arrays of locations (addresses). each storing one byte (8 bits) in general  A read operation to a particular location always returns the last value stored in that location MYcsvtu Notes Rungta College of Engg.

Basic definitions MYcsvtu Notes Rungta College of Engg. & Technology 44 .

 With respect to the data storage mechanism NVM are divided into the following groups: MYcsvtu Notes Rungta College of Engg.Basic definitions  Semiconductor Memories are classified according to the type of data storage and the type of data access mechanism into the following two main groups:  Non-volatile Memory (NVM) also known as Read-Only Memory (ROM) which retains information when the power supply voltage is off. & Technology 45 .

 Programmable ROM (PROM). & Technology 46 . MYcsvtu Notes Rungta College of Engg. The required contents of the memory is programmed during fabrication. It is a one-off procedure.Basic definitions  Mask programmed ROM. The required contents is written in a permanent way by burning out internal interconnections (fuses).

& Technology 47 . MYcsvtu Notes Rungta College of Engg. The contents can be re-programmed by applying a suitable voltages to the EEPROM pins. It is also based on the concept of the floating gate. Data is stored as a charge on an isolated gate capacitor (“floating gate”).  Electrically Erasable PROM (EEPROM) also known as Flash Memory. Data is removed by exposing the PROM to the ultraviolet light.Basic definitions  Erasable PROM (EPROM).

MYcsvtu Notes Rungta College of Engg. also known as Random Access Memory (RAM). & Technology 48 . where data is retained as long as there is  Dynamic RAM. From the point of view of the data storage mechanism RAM are divided into two main groups: power supply on. where data is stored on capacitors and requires a periodic refreshment.Basic definitions  Read/Write (R/W) memory.  Static RAM.

MYcsvtu Notes Rungta College of Engg. & Technology 49 .Basic definitions I/O devices:  Enable system to interact with the world.  Interface between the computer and other peripherals or human.

Basic definitions Can be classified by:  Type of data stream: Serial or parallel  Type of interaction with the processor: Programmed I/O. or DMA  Type of connection to the processor: Memory-mapped I/O or I/O-mapped I/O  MYcsvtu Notes Rungta College of Engg. Interrupt Driven. & Technology 50 .

Basic microprocessor architecture  A microprocessor consists of:  ALU – performs arithmetic and logic calculation  Registers – temporarily store data  Control Unit – Synchronizes the operations of all components MYcsvtu Notes Rungta College of Engg. & Technology 51 .

MYcsvtu Notes Rungta College of Engg.  Eight bi-directional data lines provide access to a system data bus.536 bytes of 8 bits each.8085 Microprocessor-Features  The Intel 8085 microprocessor is an NMOS 8-bit device.  Sixteen address bits provide access to 65. & Technology 52 .

& Technology 53 .  It requires only a 5 volt supply.8085 Microprocessor-Features  Control is provided by a variety of lines which support memory and I/O interfacing. the 8085 is available in two clock speeds. MYcsvtu Notes Rungta College of Engg. In addition. and a flexible interrupt system.  The 8085 provides an upward mobility in design from the 8080 by supporting all of the 8080‟s instruction set and interrupt capabilities.

MYcsvtu Notes Rungta College of Engg. (single phase square wave. the 8085A and the 8085A-2. & Technology 54 . )  8085A-2 .  8085A -clock frequency of 3 MHz (single phase square wave. requiring only a crystal externally.8085 Microprocessor-Features  The 8085 comes in two models. )  This single clock is generated within the 8085 itself.clock frequency of 5 MHz.

) MYcsvtu Notes Rungta College of Engg. & Technology 55 .  Has additional four more interrupts(3 masked and use vector areas between the existing ones of the 8080.  Includes the RST instruction and the eight vectors.8085 Microprocessor-Features  The 8085 supports the interrupt structure of the 8080.

Hence 8085 is useful as a complete control device for remote control applications.)  The 8085 supports the entire 8080 instruction set. In addition.RIM and SIM. two new instructions are added. & Technology 56 .8085 Microprocessor-Features  The 8085 has two pins dedicated to the generation or reception of serial data. (allow the MP to send and receive serial bits with a large software program. MYcsvtu Notes Rungta College of Engg.

 The 8085 has many new support devices to ease design work. 8085 makes use of multiplexing of the lower 8 bits of the address with the data bits on the same 8 pins.8085 Microprocessor-Features  Unlike the 8080 . MYcsvtu Notes Rungta College of Engg.  These include the 8259 Programmable Interrupt controller. several new I/O devices with various amounts of RAM. ROM. & Technology 57 . parallel I/O and timer-counters. the 8202 Dynamic RAM controller.

which has been decoded. & Technology 58 .8085 Microprocessor Architecture  Internal architecture description  Control Unit  Generates signals within microprocessor to carry out the instruction. MYcsvtu Notes Rungta College of Engg.

Internal architecture description  Arithmetic Logic Unit  The ALU performs the actual numerical and logic operation such as „add‟. & Technology 59 .  Uses data from memory and from Accumulator to perform arithmetic. etc.' AND‟. „subtract'.  Always stores result of operation in Accumulator MYcsvtu Notes Rungta College of Engg. „OR‟.

one accumulator.  In addition. & Technology 60 . and one flag register.Internal architecture description  Registers  The 8085/8080A-programming model includes six registers. MYcsvtu Notes Rungta College of Engg. it has two 16-bit registers: the stack pointer and the program counter.

E. MYcsvtu Notes Rungta College of Engg.BC. They can be combined as register pairs .  The programmer can use these registers to store or copy data into the registers by using data copy instructions. these are identified as B.to perform some 16-bit operations. and HL .D.Internal architecture description  The 8085/8080A has six general-purpose registers to store 8-bit data. and L. & Technology 61 .H.C. DE.

The accumulator is also identified as register A. & Technology 62 .  This register is used to store 8-bit data and to perform arithmetic and logical operations.  The result of an operation is stored in the accumulator.Internal architecture description  Accumulator  The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). MYcsvtu Notes Rungta College of Engg.

(P).Internal architecture description  Flags  The ALU includes five flip-flops. and Auxiliary Carry (AC) flags. & Technology 63 . Carry (CY).  They are called Zero (Z). Parity MYcsvtu Notes Rungta College of Engg. Sign (S). which are set or reset after an operation according to data conditions of the result in the accumulator and other registers.

MYcsvtu Notes Rungta College of Engg.  For example. if the sum in the accumulator is larger than eight bits. & Technology 64 . the flipflop called the Zero (Z) flag is set to one. after an addition of two numbers.  When an arithmetic operation results in zero. Carry.Internal architecture description  The most commonly used flags are Zero. called the Carry flag (CY) is set to one. The microprocessor uses these flags to test data conditions. and Sign.

 However.Internal architecture description  The 8-bit register. called the flag register is adjacent to the accumulator. it is not used as a register. five bit positions out of eight are used to store the outputs of the five flipflops. & Technology 65 . MYcsvtu Notes Rungta College of Engg.

& Technology 66 .Internal architecture description  The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction MYcsvtu Notes Rungta College of Engg.

the instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY flag is set.Internal architecture description  These flags have critical importance in the decision- making process of the microprocessor. Rungta College of Engg. & Technology 67 MYcsvtu Notes .  The conditions (set or reset) of the flags are tested through the software instructions.  For example.

 The microprocessor uses this register to sequence the execution of the instructions. Memory locations have 16-bit addresses. & Technology MYcsvtu Notes 68 .  This register is a memory pointer. Rungta College of Engg.Internal architecture description  Program Counter (PC)  This 16-bit register deals with sequencing the execution of instructions. and that is why this is a16-bit register.

& Technology 69 MYcsvtu Notes .  When a byte (machine code) is being fetched.Internal architecture description  Program Counter (PC)  The function of the program counter is to point to the memory address from which the next byte is to be fetched. the program counter is incremented by one to point to the next memory location Rungta College of Engg.

& Technology 70 . MYcsvtu Notes Rungta College of Engg.Internal architecture description  Stack Pointer (SP)  The stack pointer is also a 16-bit register used as a memory pointer. called the stack.  It points to a memory location in R/W memory.  The beginning of the stack is defined by loading 16-bit address in the stack pointer.

Decoder then takes instruction and „decodes‟ or interprets the instruction.Internal architecture description  Instruction register & Decoder  An Instruction Register and decoder system interpret the programmer‟s instructions and implement them via nano code. & Technology 71 .  Decoded instruction then passed to next stage.  Temporary store for the current instruction of a program. MYcsvtu Notes Rungta College of Engg. Latest instruction sent here from memory prior to execution.

Programming model of 8085 MYcsvtu Notes Rungta College of Engg. & Technology 72 .

& Technology 73 .8085 System Bus  A typical microprocessor communicates with memory and other devices (input and output) using three busses:  Address Bus  Data Bus and  Control Bus. MYcsvtu Notes Rungta College of Engg.

 Its "width" is 16 bits. therefore 16 bits = 16 wires.  Address Bus consists of 16 wires. & Technology 74 . MYcsvtu Notes Rungta College of Engg. therefore 16 bits.8085 System Bus  Address Bus:  One wire for each bit.

 Because memory consists of boxes. ie 0000000000000000 up to 1111111111111111. each with a unique address. which can be used.8085 System Bus.Address Bus  A 16 bit binary number allows 216 different numbers. or 32000 different numbers. MYcsvtu Notes Rungta College of Engg. the size of the address bus determines the size of memory. & Technology 75 .

writing data.  The memory the selects box number 3 for reading or  Address bus is unidirectional. not other way.Address Bus  To communicate with memory the microprocessor sends an address on the address bus. to the memory. MYcsvtu Notes Rungta College of Engg. ie numbers only sent from microprocessor to memory. & Technology 76 . eg 0000000000000011 (3 in decimal).8085 System Bus.

& Technology 77 .Address Bus  Question?: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits). in order to be able to specify an address in this memory? MYcsvtu Notes Rungta College of Engg.8085 System Bus. how many wires does the address bus need.

8085 System Bus  Data Bus:  Data Bus: carries „data‟. such as memory. in binary form. MYcsvtu Notes Rungta College of Engg. between microprocessor and other external units.  Typical size is 8 or 16 bits. & Technology 78 .

8085 System Bus -Data Bus
 The Data Bus typically consists of 8 wires. Therefore,

28 combinations of binary digits.
 Data bus used to transmit "data“ , ie information, results

of arithmetic, etc, between memory and the microprocessor.

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8085 System Bus -Data Bus
 Bus is bi-directional.  Size of the data bus determines what arithmetic can be

done.  If only 8 bits wide then largest number is 11111111 (255 in decimal).  Therefore, larger number have to be broken down into chunks of 255.  This slows microprocessor.

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8085 System Bus -Data Bus
 Data Bus also carries instructions from memory to the

microprocessor.
 Size of the bus therefore limits the number of possible

instructions to 256, each specified by a separate number.

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8085 System Bus
 Control Bus:  Control Bus are various lines which have specific

functions for coordinating and controlling microprocessor operations.

 Eg: Read/Not Write line, single binary digit.

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8085 System Bus
 Control whether memory is being „written to‟ (data

stored in memory) or „read from‟ (data taken out of memory) 1 = Read, 0 = Write.

 May also include clock line (s) for timing/synchronizing,

„interrupts‟, „reset‟ etc.

 Cannot function correctly without these vital control

signals.

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8085 System Bus- Control Bus
 The Control Bus carries control signals partly

unidirectional, partly bi-directional.
 Control signals are things like "read or write". This tells

memory that we are either reading from a location, specified on the address bus, or writing to a location specified.

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8085 System Bus- Control Bus
 In the microprocessor the three busses are external to

the chip (except for the internal data bus).  In case of external busses, the chip connects to the busses via buffers, which are simply an electronic connection between external bus and the internal data bus.

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Example: Memory Read Operation

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Example: Instruction Fetch Operation
 

Instructions (program steps) are stored in memory. To run a program, the individual instructions must be read from the memory in sequence, and executed. Program counter puts the 16-bit memory address of the instruction on the address bus.

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Instruction Fetch Operation

Control unit sends the Memory Read Enable signal to access the memory. The 8-bit instruction stored in memory is placed on the data bus and transferred to the instruction decoder.

Instruction is decoded and executed.

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Example: Instruction Fetch Operation

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Example: Instruction Fetch Operation

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& Technology 91 . it becomes obvious that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. the low order bits remain for only one clock period and they would be lost if they are not saved externally.  The high order bits of the address remain on the bus for three clock periods. Also.De multiplexing Address & Data Lines From the above description. notice that the low order bits of the address disappear when they are needed most.  MYcsvtu Notes Rungta College of Engg. However.

Then when ALE goes low. we will be able to latch the address. the address is saved and the AD7– AD0 lines can be used for their purpose as the bidirectional data lines. & Technology 92 . we will use an external latch to save the value of AD7– AD0 when it is carrying the address bits.  Given that ALE operates as a pulse during T1. We use the ALE signal to enable this latch.  MYcsvtu Notes Rungta College of Engg.De multiplexing Address & Data Lines To make sure we have the entire address for the full three clock cycles.

Demultiplexing Address & Data Lines MYcsvtu Notes Rungta College of Engg. & Technology 93 .

the signal needs to be used with both memory and I/O. it must be combined with the IO/M signal to generate different control signals for the memory and I/O. However.Generating Control Signals  The 8085 generates a single RD signal. & Technology 94 .  Keeping in mind the operation of the IO/M signal we can use the following circuitry to generate the right set of signals: MYcsvtu Notes Rungta College of Engg. So.

& Technology 95 .Generating Control Signals MYcsvtu Notes Rungta College of Engg.

& Technology 96 .8085 Functional Block Diagram MYcsvtu Notes Rungta College of Engg.

8085 Pin description MYcsvtu Notes Rungta College of Engg. & Technology 97 .

or the 8-bit address of an I/O device.536 locations.A15:  These tri state lines are outbound only.  They provide the upper 8 bits of the 16-bit-wide address which identifies one unique 8-bit byte within the MP‟s address space. MYcsvtu Notes Rungta College of Engg.8085 Pin description  Pin Description  ADDRESS LINES A8 . & Technology 98 .  Sixteen address lines provide an address space of 65.

& Technology 99 .AD7:  These tri state lines may by either inbound or outbound. MYcsvtu Notes Rungta College of Engg.  They provide a multiplexing between the lower 8 bits of the 16-bit-wide address early in a machine cycle and 8 data bits later in the cycle.8085 Pin description  ADDRESS-DATA LINES AD0 .

they may be either inbound or outbound.AD7:  When containing addresses. MYcsvtu Notes Rungta College of Engg. these lines are outbound only.8085 Pin description  ADDRESS-DATA LINES AD0 . & Technology 100 . when containing data.  They also will contain the 8 bits of an I/O device address during an I/O operation. depending upon the nature of the machine cycle.

 The falling edge of ALE is set to guarantee setup and  ALE can also be used to strobe the status information.8085 Pin description  ALE Address Latch Enable:  It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. hold times for the address information. MYcsvtu Notes Rungta College of Engg. & Technology 101 .

& Technology 102 .  This signal appears outbound early in a machine cycle to advise the external circuitry that the AD0 .8085 Pin description  ALE Address Latch Enable:  ALE is never 3stated . MYcsvtu Notes Rungta College of Engg.AD7 lines contain the lower 8 bits of a memory address.

S1. as well as the S0. & Technology 103 .8085 Pin description  ALE Address Latch Enable:  It should be used to clock a catch-and-hold circuit such as a 74LS245 or 74LS373. and I-O/M lines will be stable and may be taken by the external circuitry.  The falling edge of ALE is the point at which the signals on the AD lines. MYcsvtu Notes Rungta College of Engg. so that the full address will be available to the system for the rest of the machine cycle.

& Technology 104 . MYcsvtu Notes Rungta College of Engg. S1.8085 Pin description  STATUS LINES S0. such as very slow RAM or other specialized devices.  The S0 and S1 lines are made available for circuits which need advanced warning of the ensuing operation. & I-O/M:  These three status lines serve to indicate the general status of the processor with respect to what function the MP will perform during the machine cycle.

or toward I/O (line is high). The I-O/M line approximates in one line what the S0 and S1 lines do in two.8085 Pin description  STATUS LINES S0. S1. & I-O/M:  The system may not normally need to monitor these lines.  It indicates whether the operation will be directed toward memory (line is low). & Technology 105 . MYcsvtu Notes Rungta College of Engg.

& Technology 106 . Encoded status of the bus cycle:  S1 S0 Operation 0 0 HALT 0 1 WRITE 1 0 READ 1 1 FETCH  S1 can be used as an advanced R/W status. MYcsvtu Notes Rungta College of Engg.8085 Pin description  Data Bus Status.

as well as identify its direction. & Technology 107 . MYcsvtu Notes Rungta College of Engg.8085 Pin description  READ & WRITE (/RD & /WR):  These lines indicate which direction the MP expects to pass data between itself and the external data bus.  These lines also serve to time the event.

8085 Pin description  READ & WRITE (/RD & /WR):  RD -READ. 3stated during Hold and Halt modes.  WR-WRITE. Data is set up at the trailing edge of WR. & Technology 108 . MYcsvtu Notes Rungta College of Engg. indicates the data on the Data Bus is to be written into the selected memory or I/O location. indicates the selected memory or 1/0 device is to be read and that the Data Bus is available for the data transfer.

it indicates that the memory or peripheral is ready to send or receive data. the CPU will wait for Ready to go high before completing the read or write cycle. MYcsvtu Notes Rungta College of Engg.8085 Pin description  READY :  If Ready is high during a read or write cycle.  If Ready is low. & Technology 109 .

& Technology 110 .8085 Pin description  This is an input line which may be used as a signal from external RAM that a wait state is needed.  The negation of Ready. MYcsvtu Notes Rungta College of Engg. since the RAM is not able to provide the data or accept it in the time allowed by the MP. by being pulled low. will cause the 8085 to enter wait states.

 It indicates that another Master is requesting the use of the Address and Data Buses. & Technology 111 .  The CPU.8085 Pin description  HOLD :  These lines provide the 8085 with a DMA capability by allowing another processor on the same system buses to request control of the buses. will relinquish the use of buses as soon as the completion of the current machine cycle. MYcsvtu Notes Rungta College of Engg. upon receiving the Hold request.

MYcsvtu Notes Rungta College of Engg.8085 Pin description  HOLD :  Internal processing can continue. the „ 85 will tri state its address. & Technology 112 . and certain control lines.  The „85 will remain off the buses until HOLD is negated.  Upon receipt of HOLD. data.  This signals the other processor that it may proceed. then generate HLDA.

 The INTR is enabled and disabled by software.8085 Pin description  During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine.  When the Hold is acknowledged.  The processor can regain the buses only after the Hold is removed. Data. MYcsvtu Notes Rungta College of Engg. RD. WR. the Address. and IO/M lines are 3stated. & Technology 113 .

8085 Pin description  HLDA :  HOLD ACKNOWLEDGE. & Technology 114 .indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle.  The CPU takes the buses one half clock cycle after HLDA goes low. MYcsvtu Notes Rungta College of Engg.  HLDA goes low after the Hold request is removed.

the „85 will complete the instruction in process. MYcsvtu Notes Rungta College of Engg.  Upon receipt of INTR.8085 Pin description  INTR :  INTERRUPT REQUEST:  This line provides a vectored interrupt capability to the 8085. then generate INTA as it enters the next machine cycle. & Technology 115 .

MYcsvtu Notes Rungta College of Engg. is used as a general purpose interrupt. & Technology 116 .  It is sampled only during the next to the last clock cycle of the instruction. which the „85 uses to locate an interrupt vector in low RAM.8085 Pin description  INTR :  The interrupting device will jam a Restart (RST) instruction onto the data bus.

MYcsvtu Notes Rungta College of Engg.8085 Pin description  INTR :  If it is active.  It is disabled by Reset and immediately after an interrupt is accepted. & Technology 117 . the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued.

8085 Pin description  INTA :  INTERRUPT ACKNOWLEDGE.is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted.  It can be used to activate the 8259 Interrupt chip or some other interrupt port. & Technology 118 . MYcsvtu Notes Rungta College of Engg.

5. MYcsvtu Notes Rungta College of Engg. 6.5. & Technology 119 .8085 Pin description  RST 5.5:  These three lines are additional interrupt lines which generate an automatic Restart. without jamming. 7. to vectors in low RAM which are between those used by the normal INTR instruction.

MYcsvtu Notes Rungta College of Engg. and each other.8085 Pin description  RST 5.5:  The 5. will cause an automatic restart to a 4-byte vector located between 5 and 6 of the normal vectors used by INTR.5 line.5.  These lines have priority over the INTR line. & Technology 120 . 7.5. for example. 6.

5. & Technology 121 . MYcsvtu Notes Rungta College of Engg.5:  They also have certain electrical characteristics for assertion.5. and may be masked off or on by software. 7.8085 Pin description  RST 5.  These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted. 6.

Lowest Priority  The priority of these interrupts is ordered as shown above.Highest Priority  RST 6.5 .5 .  These interrupts have a higher priority than the INTR MYcsvtu Notes Rungta College of Engg.8085 Pin description  RST 7.5  RST 5. & Technology 122 .

 It is unaffected by any mask or Interrupt Enable. & Technology 123 . It has the highest priority of any interrupt MYcsvtu Notes Rungta College of Engg.8085 Pin description  TRAP:  This is an un maskable interrupt with a fixed vector in low RAM.  It is recognized at the same time as INTR.  Trap interrupt is a non maskable restart interrupt.

& Technology 124 . used with the 8080. has been brought inside the MP.  The reset circuitry in the 8224.  The RESET IN line is generated asynchronously by some sort of external circuit. such as an RC network or Reset switch. MYcsvtu Notes Rungta College of Engg.8085 Pin description  RESET IN :  These lines provide for both MP and system reset.

the „85 will internally synchronize the Reset with the clock of the processor. MYcsvtu Notes Rungta College of Engg.8085 Pin description  RESET IN :  Upon receipt of this signal. & Technology 125 .  Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip flops. then generate RESET OUT for other devices in the system.

& Technology 126 .8085 Pin description  RESET IN :  None of the other flags or registers (except the instruction register) are affected. MYcsvtu Notes Rungta College of Engg.  The CPU is held in the reset condition as long as Reset is applied.

 Can be used as a system RESET. & Technology 127 . MYcsvtu Notes Rungta College of Engg.8085 Pin description  RESET OUT:  Indicates CPU is being reset.  The signal is synchronized to the processor clock.

MYcsvtu Notes Rungta College of Engg.  The input frequency is divided by 2 to give the internal operating frequency.8085 Pin description  X1. & Technology 128 .  These two pins provide connection for an external frequency determining circuit to feed the 8085‟s clock. X2 :  Crystal or R/C network connections to set the internal clock generator.

X2 :  This is normally a crystal. MYcsvtu Notes Rungta College of Engg. X1 alone may be used as a single input from an external oscillator.8085 Pin description  X1. although other resonant circuits may be used.  The internal oscillator of the „85 will divide the frequency by two for the system clock. & Technology 129 .

MYcsvtu Notes Rungta College of Engg. & Technology 130 .8085 Pin description  CLK :  Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU.  This line provides a system clock signal to external circuits which need to be in synchronization with the MP. X2 input period.  The period of CLK is twice the X1.

8085 Pin description  IO/M :  IO/M indicates whether the Read/Write is to memory or l/O. & Technology 131 .  Tri stated during Hold and Halt modes MYcsvtu Notes Rungta College of Engg.

8085 Pin description  SID:  Serial input data line . & Technology 132 .  The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. MYcsvtu Notes Rungta College of Engg.

 The output SOD is set or reset as specified by the SIM instruction.8085 Pin description  SOD :  Serial output data line. & Technology 133 . MYcsvtu Notes Rungta College of Engg.

and may be tested or set by the Read Interrupt Mask (RIM) or Set Interrupt Mask (SIM) instructions. MYcsvtu Notes Rungta College of Engg. & Technology 134 .8085 Pin description  SID and SOD:  These two lines provide for a single serial input or output line to/from the 8085.  These lines are brought into the device as D7.

6.5.  The SID and SOD lines are simple single bit I/O lines.5. and 7.8085 Pin description  SID and SOD:  These two instructions also have control over the mask which controls the RST 5. MYcsvtu Notes Rungta College of Engg. and TRAP. interrupts. any timing required to provide external communication via them must be provided by the software.5. & Technology 135 .

 Vss: Ground Reference.8085 Pin description  Vcc: +5 volt supply. MYcsvtu Notes Rungta College of Engg. & Technology 136 .

& Technology 137 .  Its basic clock speed is 3 MHz thus improving on the present 8080's performance with higher system speed.8085 Functional Description  The 8085A is a complete 8 bit parallel central processor. MYcsvtu Notes Rungta College of Engg.  It requires a single +5 volt supply.

and a ROM or PROM/IO chip  The 8085A uses a multiplexed Data Bus.  The address is split between the higher 8bit Address Bus and the lower 8bit Address/Data Bus.8085 Functional Description  Also it is designed to fit into a minimum system of three IC's: The CPU. MYcsvtu Notes Rungta College of Engg. a RAM/ IO. & Technology 138 .

MYcsvtu Notes Rungta College of Engg.  The lower 8bits are latched into the peripherals by the Address Latch Enable (ALE).8085 Functional Description  During the first cycle the address is sent out. & Technology 139 .

Hold.8085 Functional Description  During the rest of the machine cycle the Data Bus is used for memory or I/O data. & Technology MYcsvtu Notes 140 . Ready. and all Interrupts are synchronized. and IO/Memory signals for bus control.  The 8085A provides RD. WR.  An Interrupt Acknowledge signal (INTA) is also provided. Rungta College of Engg.

& Technology 141 .8085 Functional Description  The 8085A also provides serial input data (SID) and serial output data (SOD) lines for simple serial interface. MYcsvtu Notes Rungta College of Engg. restart interrupts and one non-maskable trap interrupt. the 8085A has three maskable. The 8085A provides RD. WR and IO/M signals for Bus control.  In addition to these features.

8085 Functional Description  Status Information:  Status information is directly available from the 8085A. and provides the user with advanced timing of the type of bus transfer being done.  The status is partially encoded.  ALE serves as a status strobe. MYcsvtu Notes Rungta College of Engg. & Technology 142 .

FETCH MYcsvtu Notes Rungta College of Engg. READ. S1 Carries the following status information:  HALT.8085 Functional Description  Status Information  IO/M cycle status signal is provided directly also. WRITE.  Decoded So. & Technology 143 .

MYcsvtu Notes Rungta College of Engg. In the 8085A the 8 LSB of address are multiplexed with the data instead of status.  This also frees extra pins for expanded interrupt capability.  The ALE line is used as a strobe to enter the lower half of the address into the memory or peripheral address latch. & Technology 144 .8085 Functional Description  Status Information  S1 can be interpreted as R/W in all bus transfers.

7. 5. RST 7.  INTR is identical in function to the 8080 INT.5. 6.5. & Technology 145 .5.  Each of the three RESTART inputs. RST6. and TRAP.8085 Functional Description  Interrupt and Serial l/O  The 8085A has5 interrupt inputs: INTR.5. MYcsvtu Notes Rungta College of Engg.5.5 has a programmable mask. RST5.  TRAP is also a RESTART interrupt except it is non maskable.

& Technology 146 .  The non-maskable TRAP causes the internal execution MYcsvtu Notes Rungta College of Engg.8085 Functional Description  Interrupt and Serial l/O  The three RESTART interrupts cause the internal execution of RST (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. of a RST independent of the state of the interrupt enable or masks.

MYcsvtu Notes Rungta College of Engg.5. RST 5.RST 6. RST 7.8085 Functional Description  The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows: lowest priority. & Technology 147 .5.5.  TRAP highest priority. INTR  This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt.

MYcsvtu Notes Rungta College of Engg.5 can interrupt a RST 7.  The TRAP input is both edge and level sensitive.  It is not affected by any flag or mask.5 routine.  TRAP:  The TRAP interrupt is useful for catastrophic errors such as power failure or bus error.  The TRAP input is recognized just as any other interrupt but has the highest priority.5 routine if the interrupts were re-enabled before the end of the RST 7. & Technology 148 .8085 Functional Description  RST 5.

with the result that the more complicated instructions take longer to execute. & Technology 149 .8085 Timings  Instruction Cycle –  The time required by the 8085 to fetch and execute one machine language instruction is defined as an Instruction Cycle. the instructions may be of different complexities. MYcsvtu Notes Rungta College of Engg.  As in the 8080.

MYcsvtu Notes Rungta College of Engg. & Technology 150 . however.8085 Timings  Instruction Cycle –  The 8085‟s method of instruction execution inside the MP is more organized. and so the time required to execute any instruction is more predictable and more regular.

by the instruction being executed. in which the instruction itself is obtained from RAM. & Technology 151 .  The shortest instruction would require just one machine cycle. MYcsvtu Notes Rungta College of Engg.  Each machine cycle is essentially the result of the need. to access the RAM.8085 Timings  Machine Cycle –  Each instruction is divided into one to five Machine Cycles.

and the remaining four to be divided into fetching and saving other bytes. the first to obtain the instruction byte itself. MYcsvtu Notes Rungta College of Engg.8085 Timings  The longest. while numbers 4 & 5 may be needed to save a 2-byte address somewhere else in RAM. & Technology 152 . would consist of five RAM accesses.  For example. cycles numbers 2 & 3 may be needed to fetch two more bytes of an address. of five machine cycles.

 These six lines can define seven different machine cycle types as follows.8085 Timings  The type of machine cycle being executed is specified by the status lines I-O/M. & Technology 153 . /WR. and the control lines /RD. S0. and S1. MYcsvtu Notes Rungta College of Engg. and /INTA.

 It is defined with S0 and S1 asserted high. MYcsvtu Notes Rungta College of Engg.Types of machine cycle  OPCODE FETCH:  This is the first machine cycle of any instruction. & Technology 154 . and I-O/M and /RD low.  It is a read cycle from RAM to obtain an instruction byte.

1 respectively. MYcsvtu Notes Rungta College of Engg.  It is a read cycle from RAM to obtain a data or address byte.  It is defined with S0 and S1 set to 0. & Technology 155 . and I-O/M and /RD low.Types of machine cycle  MEMORY READ:  This is a normal read cycle of any byte except the OP code.

Types of machine cycle  MEMORY WRITE:  This is a normal write cycle to memory.  It is defined with S0 and S1 set to 1. and I-O/M and /WR low.  It is a write cycle to RAM to store one byte in the specified address MYcsvtu Notes Rungta College of Engg. 0 respectively. & Technology 156 .

MYcsvtu Notes Rungta College of Engg. 1 respectively. and with I-O/M high and /RD low.  It is a read cycle which will bring one byte into the MP from the input device specified.  It is defined with S0 and S1 set to 0.Types of machine cycle  I/O READ:  This is a normal read cycle from an I/O device. & Technology 157 .

 It is a write cycle which will send one byte outbound from the MP to the specified output device.  It is defined with S0 and S1 set to 1. and with I-O/M high and /WR low. 0 respectively. & Technology 158 .Types of machine cycle  I/O WRITE:  This is a normal write cycle to an I/O device. MYcsvtu Notes Rungta College of Engg.

Types of machine cycle  INTERRUPT ACKNOWLEDGE:  This is a response to an interrupt request applied to the MP via the INTR line. MYcsvtu Notes Rungta College of Engg. IO/M set high. 1 respectively. & Technology 159 .  It is defined with S0 and S1 set to 1. and both /RD and /WR also high.

MYcsvtu Notes Rungta College of Engg. & Technology 160 . although the interrupting device will jam an interrupt vector onto the D0-D7 lines on the next machine cycle.  It is neither a read nor write cycle.Types of machine cycle  The Interrupt Acknowledge pin is also held to a low asserted level.

& Technology 161 .  It occurs under three differently defined conditions: MYcsvtu Notes Rungta College of Engg.Types of machine cycle  BUS IDLE:  This is an idle cycle in which no specific bus activity is defined.

IO/M set low. and neither /RD nor /WR asserted (both high).8085 Timings-Special instructions  Double Add Instruction (DAD):  This instruction requires enough execution time to merit its own Idle cycle. 1 respectively.  Since neither a read nor a write are specified.  It is defined with S0 and S1 set to 0. no bus action takes place. & Technology 162 . MYcsvtu Notes Rungta College of Engg.

MYcsvtu Notes Rungta College of Engg. All bits are held high.8085 Timings-Special instructions  Acknowledge of Restart or Trap:  This idle cycle allows time for the „85 to cope with a RST or Trap interrupt request. & Technology 163 .

& Technology 164 . /RD.  The Hold line is really the proper one to use for DMA or multiple processors. MYcsvtu Notes Rungta College of Engg. and /WR lines are all tri stated. which would allow them to be controlled by other devices.  INTA is held inactive. but not tri stated.  The I-O/M.8085 Timings-Special instructions  Halt:  This idle cycle indicates that the MP has executed a Halt instruction.

is further divided into Tstates. will be either 4 or 6 T-states in length.  Each T-state. during which the OP code is being fetched.  The first machine cycle. & Technology 165 . during which an access of a RAM address or an I/O device is made (except the idle cycles).8085 Timings-T-states T-states Each of the machine cycles defined above. will be about 333 nanoseconds in length. MYcsvtu Notes Rungta College of Engg. for an „85 with a 3 MHz clock.

6 states are required.  If multiple accesses are needed.8085 Timings-T-states T-states-  Whether 4 or 6 T-states are used depends upon whether the instruction needs further information from RAM. & Technology 166 . MYcsvtu Notes Rungta College of Engg. if the execution can run to completion. the cycle will be 4 states long. or whether it can be executed to completion straight away .

A8-A15. Rungta College of Engg.8085 Timings-T-states The actions of the major signals of the „85 during each of the 10 possible types of T-states. and AD0-AD7 contains whatever would be appropriate for the type of instruction being executed. It may be summarized as follows:  T1 STATE:  This state is the first of any machine cycle. & Technology MYcsvtu Notes 167 .  S0-S1 lines. I-O/M.

at this early point in the machine cycle. to be dealt with. whether the MP is attempting to address a RAM location or an I/O device. MYcsvtu Notes Rungta College of Engg.8085 Timings-T-states T1 STATE:  The S0-S1 and I-O/M lines will define.  The address lines will identify the location or I/O device . & Technology 168 .

8085 Timings-T-states T1 STATE:  The Address Latch Enable (ALE) line will allow some sort of external circuitry to catch and hold the contents of the AD0-AD7 lines to be used as the low byte of the address.  The /RD. and /INTA lines are all negated at this time. MYcsvtu Notes Rungta College of Engg. & Technology 169 . /WR.

8085 Timings-T-states T1 STATE:  Since the AD0-AD7 lines are being used to present an address byte. MYcsvtu Notes Rungta College of Engg. besides. is asserted. since this is the time that the AD0-AD7 contents will contain the lower address byte. ALE. & Technology 170 . however. it‟s too early to do so. it would be inappropriate to move data on the data bus. which must be caught and held outside the „85 for use by the following Tstates.  It‟s also too early for /INTA.

 The AD0-AD7 lines will now prepare to either accept or present a data byte (they are in a state of transition during T2).  The address lines retain the bit pattern selecting one byte from RAM or an I/O device. MYcsvtu Notes Rungta College of Engg. & Technology 171 .8085 Timings-T-states T2 STATE:  All lines except ALE (which will be inactive for the rest of the machine cycle) will assume the proper level for the type of instruction in progress.

to indicate the nature of the data transaction. & Technology 172 .  Either /RD or /WR will assert during T2. S1 lines are still displaying the original settings of T1.  INTA will assert at T2 if an interrupt cycle has started. MYcsvtu Notes Rungta College of Engg.8085 Timings-T-states T2 STATE:  I-O/M and the S0.

All signals set up during T2 will remain constant during Tw.  A specific point in T2 is defined. a Tw is inserted to allow the external circuitry more time to prepare for data transmission. & Technology 173 .  This corresponds to the same actions in the 8080 device. after which a late negation of Ready will not cause the Tw to be inserted.8085 Timings-T-states WAIT STATE:  If the Ready line was negated during T2. MYcsvtu Notes Rungta College of Engg.

 This will cause the data byte standing on AD0-AD7 to disappear MYcsvtu Notes Rungta College of Engg.  At the end of T3.8085 Timings-T-states T3 STATE:  All lines set up during T2 will remain the same in T3. which will be conducting data either into or out of the 8085. the /RD or /WR line will negate to indicate the end of the active function. except the AD0-AD7 lines. & Technology 174 .

8085 Timings-T-states T4 . & Technology 175 . while I-O/M is negated.  The S0 & S1 lines are both asserted. which specifies that the „85 is involved in an Opcode fetch.  No bus actions are required. MYcsvtu Notes Rungta College of Engg.T6 STATES:  These states are required for time to permit the 8085 to continue processing internally.

/WR.  The AD0-AD7 lines are tri stated. and INTA lines are all negated. MYcsvtu Notes Rungta College of Engg. & Technology 176 . the A8-A15 retain their original setting. the /RD.8085 Timings-T-states T4 . this corresponds correctly with the Machine Cycle chart.T6 STATES:  Since T4 through T6 will exist only on the first machine cycle of an instruction.

and the „85 is alive inside.8085 Timings-Special conditions  Special conditions:  In addition to the T-states described above.  It must be kept in mind that during any of these. the MP clocks are still running. Halts. it has simply shut itself off the buses to allow external events to occur. there are also various conditions during states involved in Resets. & Technology 177 . MYcsvtu Notes Rungta College of Engg. and Holds.

& Technology 178 .8085 Timings-Special conditions  Special conditions:  These states tri state the address. /RD. whether it is a Reset. which do indicate what type of machine cycle the system is in. I-O/M. or Halt MYcsvtu Notes Rungta College of Engg. Hold.  The other lines are held at inactive levels except the S0 & S1 lines. and /WR lines to allow external devices to control them.. AD.e. i.

& Technology 179 .  During this time. the „85 is simply waiting for something to occur.8085 Timings-Special conditions  HOLD AND HALT STATES :  The 8085 has provisions for the execution of a Halt instruction. a Hold Request. which causes the system to go into T-halt states. MYcsvtu Notes Rungta College of Engg.  There are three ways out of a Halt: A Reset. and an enabled interrupt.

MYcsvtu Notes Rungta College of Engg.  It will return to the halt condition when Hold negates.8085 Timings-Special conditions  HOLD AND HALT STATES :  If a Hold Request occurs during a Halt.  If an interrupt occurs during a halt. the „85 will honor it by going into T-hold cycles as long as the Hold line remains asserted. the MP will go into an interrupt cycle if the interrupt was enabled. & Technology 180 .

8085 Timings-Special conditions  HOLD AND HALT STATES :  It will be ignored if it was not enabled. MYcsvtu Notes Rungta College of Engg. & Technology 181 .  An enabled interrupt during a hold state will have to wait until the hold clears before being given control of the system.

Example  The instruction code 0100 1111 (4FH – MOV C. & Technology 182 .8085 Timings.  Illustrate the steps and the timing of data flow when it is being fetched MYcsvtu Notes Rungta College of Engg. A) is stored in memory location 2005H.

Example Mp Communication MYcsvtu Notes Rungta College of Engg. & Technology 183 .

& Technology 184 .Timing Diagram MYcsvtu Notes Rungta College of Engg.

Some Terminologies:  After observing timing diagram we can say. & Technology 185 .    4FH is a one – byte instruction One external operation – fetching 4F from 2005H Entire operation needs 4 clock periods MYcsvtu Notes Rungta College of Engg.

& Technology 186 .II INSTRUCTION SET & PROGRAMMING WITH 8085 MYcsvtu Notes Rungta College of Engg.UNIT.

Instruction
 An instruction is a binary pattern designed inside a

microprocessor to perform a specific function.

 The entire group of instructions, called the instruction

set, determines what functions the microprocessor can perform.

 The 8085‟s instructions are made up of bytes.

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Instruction
 In microprocessor parlance, a byte is described as 8

contiguous binary bits treated as a unit.

 The least significant bit is on the right, and is labeled Bit

0.

 The most significant bit is on the left, and is Bit 7. Thus,

the machine coding is "origin zero", unless noted otherwise.
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Instruction
 Note also that there is no parity bit, or provision for it, as

would be found in larger systems.  The 8085‟s instructions are either one, two, or three bytes long.  In all cases, the first byte contains the essential information, such as the OP code.  The second and third bytes, if included, provide operand information that won‟t fit in the first byte.

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Instruction Set Classification
 These instructions can be classified into the following

five functional categories:

    

data transfer (copy) operations arithmetic operations, logical operations, branching operations, and machine-control operations.

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Data Transfer (Copy) Operations
 Data Transfer (Copy) Operations  This group of instructions copy data from a location

called a source to another location called a destination, without modifying the contents of the source.  In technical manuals, the term data transfer is used for this copying function.  The various types of data transfer (copy) are listed below together with examples of each type:

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Data Transfer (Copy) Operations
 Copy from source to destination

 MOV Rd, Rs
 This instruction copies the contents of the source M, Rs

register into the destination register; the contents of Rd, M the source register are not altered.  If one of the operands is a memory location, its location is specified by the contents of the HL registers.  Example: MOV B, C or MOV B, M

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Data Transfer (Copy) Operations
 Move immediate 8-bit

 MVI Rd, data
 The 8-bit data is stored in the destination register or M,

data memory.  If the operand is a memory location, its location is specified by the contents of the HL registers.  Example: MVI B, 57H or MVI M, 57H

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Data Transfer (Copy) Operations
 Load accumulator

 LDA 16-bit address
 The contents of a memory location, specified by a16-bit

address in the operand, are copied to the accumulator.  The contents of the source are not altered.  Example: LDA 2034H

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Data Transfer (Copy) Operations
 Load accumulator indirect

 LDAX B/D Reg. pair
 The contents of the designated register pair point to a

memory location. This instruction copies the contents of that memory location into the accumulator.  The contents of either the register pair or the memory location are not altered.  Example: LDAX B

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Data Transfer (Copy) Operations
 Load register pair immediate

 LXI Reg. pair, 16-bit data
 The instruction loads 16-bit data in the register pair

designated in the operand.  Example: LXI H, 2034H or LXI H, XYZ

MYcsvtu Notes

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Data Transfer (Copy) Operations
 Load H and L registers direct

 LHLD 16-bit address
 The instruction copies the contents of the memory

location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H.  The contents of source memory locations are not altered.  Example: LHLD 2040H
MYcsvtu Notes Rungta College of Engg. & Technology 197

Data Transfer (Copy) Operations
 Store accumulator direct  STA 16-bit address  The contents of the accumulator are copied into the

memory location specified by the operand.  This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address.  Example: STA 4350H

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The contents of the accumulator are not altered.Data Transfer (Copy) Operations  Store accumulator indirect  STAX Reg. & Technology 199 .  Example: STAX B MYcsvtu Notes Rungta College of Engg. pair  The contents of the accumulator are copied into the memory location specified by the contents of the operand (register pair).

 Example: SHLD 2470H MYcsvtu Notes Rungta College of Engg.  This is a 3-byte instruction.Data Transfer (Copy) Operations  Store H and L registers direct  SHLD 16-bit address  The contents of register L are stored into the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. the second byte specifies the low-order address and the third byte specifies the high-order address. & Technology 200 .

& Technology 201 . and the contents of register L are exchanged with the contents of register E.Data Transfer (Copy) Operations  Exchange H and L with D and E  XCHG none  The contents of register H are exchanged with the contents of register D.  Example: XCHG MYcsvtu Notes Rungta College of Engg.

& Technology 202 .  Example: SPHL MYcsvtu Notes Rungta College of Engg.Data Transfer (Copy) Operations  Copy H and L registers to the stack pointer  SPHL none  The instruction loads the contents of the H and L registers into the stack pointer register.  The contents of the H and L registers are not altered. the contents of the H register provide the high-order address and the contents of the L register provide the low-order address.

& Technology 203 . the contents of the stack pointer register are not altered.  The contents of the H register are exchanged with the next stack location (SP+1). however.Data Transfer (Copy) Operations  Exchange H and L with top of stack  XTHL none  The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register.  Example: XTHL MYcsvtu Notes Rungta College of Engg.

Data Transfer (Copy) Operations  Output data from accumulator to a port with 8-bit address  OUT 8-bit port address  The contents of the accumulator are copied into the I/O port specified by the operand. & Technology 204 .  Example: OUT F8H MYcsvtu Notes Rungta College of Engg.

 Example: IN 8CH MYcsvtu Notes Rungta College of Engg. & Technology 205 .Data Transfer (Copy) Operations  Input data to accumulator from a port with 8-bit address  IN 8-bit port address  The contents of the input port designated in the operand are read and loaded into the accumulator.

its location is specified by the contents of the HL registers.Arithmetic instructions  Add register or memory to accumulator  ADD R –  The contents of the operand (register or memory) are M added to the contents of the accumulator and the result is stored in the accumulator.  All flags are modified to reflect the result of the addition.  If the operand is a memory location. & Technology 206 .  Example: ADD B or ADD M MYcsvtu Notes Rungta College of Engg.

 If the operand is a memory location.Arithmetic instructions  Add register to accumulator with carry  ADC R  The contents of the operand (register or memory) and M the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator.  All flags are modified to reflect the result of the addition. & Technology 207 .  Example: ADC B or ADC M MYcsvtu Notes Rungta College of Engg. its location is specified by the contents of the HL registers.

Arithmetic instructions  Add immediate to accumulator  ADI 8-bit data  The 8-bit data (operand) is added to the contents of the accumulator and the result is stored in the accumulator. & Technology 208 .  Example: ADI 45H MYcsvtu Notes Rungta College of Engg.  All flags are modified to reflect the result of the addition.

 Example: ACI 45H MYcsvtu Notes Rungta College of Engg. & Technology 209 .Arithmetic instructions  Add immediate to accumulator with carry  ACI 8-bit data  The 8-bit data (operand) and the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator.  All flags are modified to reflect the result of the addition.

 Example: DAD H MYcsvtu Notes Rungta College of Engg. pair  The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is stored in the HL register.Arithmetic instructions  Add register pair to H and L registers  DAD Reg.  The contents of the source register pair are not altered.  No other flags are affected. the CY flag is set.  If the result is larger than 16 bits. & Technology 210 .

Example: SUB B or SUB M MYcsvtu Notes Rungta College of Engg.Arithmetic instructions  Subtract register or memory from accumulator  SUB R  The contents of the operand (register or memory ) are M subtracted from the contents of the accumulator. its location is specified by the contents of the HL registers.  All flags are modified to reflect the result of the subtraction. & Technology 211 . and the result is stored in the accumulator.  If the operand is a memory location.

& Technology 212 . its location is specified by the contents of the HL registers.  If the operand is a memory location.  All flags are modified to reflect the result of the subtraction.Arithmetic instructions  Subtract source and borrow from accumulator  SBB R  The contents of the operand (register or memory ) and M the Borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. Example: SBB B or SBB M MYcsvtu Notes Rungta College of Engg.

 All flags are modified to reflect the result of the subtraction. & Technology 213 .Arithmetic instructions  Subtract immediate from accumulator  SUI 8-bit data  The 8-bit data (operand) is subtracted from the contents of the accumulator and the result is stored in the accumulator.  Example: SUI 45H MYcsvtu Notes Rungta College of Engg.

Arithmetic instructions  Subtract immediate from accumulator with borrow  SBI 8-bit data  The 8-bit data (operand) and the Borrow flag are subtracted from the contents of the accumulator and the result is stored in the accumulator.  Example: SBI 45H MYcsvtu Notes Rungta College of Engg. & Technology 214 . All flags are modified to reflect the result of the subtraction.

 Example: INR B or INR M MYcsvtu Notes Rungta College of Engg. & Technology 215 . its location is specified by the contents of the HL registers.Arithmetic instructions  Increment register or memory by 1  INR R The contents of the designated register or memory) are M incremented by 1 and the result is stored in the same place.  If the operand is a memory location.

 Example: INX H MYcsvtu Notes Rungta College of Engg. & Technology 216 .Arithmetic instructions  Increment register pair by 1  INX R  The contents of the designated register pair are incremented by 1 and the result is stored in the same place.

& Technology 217 . its location is specified by the contents of the HL registers.  If the operand is a memory location.  Example: DCR B or DCR M MYcsvtu Notes Rungta College of Engg.Arithmetic instructions  Decrement register or memory by 1  DCR R  The contents of the designated register or memory are M decremented by 1 and the result is stored in the same place.

& Technology 218 .Arithmetic instructions  Decrement register pair by 1  DCX R  The contents of the designated register pair are decremented by 1 and the result is stored in the same place.  Example: DCX H MYcsvtu Notes Rungta College of Engg.

P.Arithmetic instructions  Decimal adjust accumulator  DAA none The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD) digits. CY flags are altered to reflect the results of the operation. Z. S. AC. and the conversion procedure is described below. & Technology 219 . MYcsvtu Notes Rungta College of Engg.  This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion.

& Technology 220 .  If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set. the instruction adds 6 to the high-order four bits.Arithmetic instructions  Decimal adjust accumulator  If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set. the instruction adds 6 to the low-order four bits.  Example: DAA MYcsvtu Notes Rungta College of Engg.

 Example: JMP 2034H or JMP XYZ MYcsvtu Notes Rungta College of Engg.Branching operations  Jump unconditionally  JMP 16-bit address The program sequence is transferred to the memory location specified by the 16bit address given in the operand. & Technology 221 .

& Technology 222 .Branching operations  Jump conditionally  Operand: 16-bit address  The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below.  Example: JZ 2034H or JZ XYZ MYcsvtu Notes Rungta College of Engg.

Branching operations  JC Jump on Carry CY = 1  JNC Jump on no Carry CY = 0  JP Jump on positive S = 0  JM Jump on minus S = 1  JZ Jump on zero Z = 1  JNZ Jump on no zero Z = 0  JPE Jump on parity even P = 1  JPO Jump on parity odd P = 0 MYcsvtu Notes Rungta College of Engg. & Technology 223 .

 Example: CALL 2034H or CALL XYZ MYcsvtu Notes Rungta College of Engg.  Before the transfer.Subroutine  Unconditional subroutine call  CALL 16-bit address  The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. & Technology 224 . the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack.

 Example: CZ 2034H or CZ XYZ MYcsvtu Notes Rungta College of Engg. & Technology 225 .  Before the transfer.Subroutine  Call conditionally  Operand: 16-bit address  The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. the address of the next instruction after the call (the contents of the program counter) is pushed onto the stack.

Subroutine  CC Call on Carry CY = 1  CNC Call on no Carry CY = 0  CP Call on positive S = 0  CM Call on minus S = 1  CZ Call on zero Z = 1  CNZ Call on no zero Z = 0  CPE Call on parity even P = 1  CPO Call on parity odd P = 0 MYcsvtu Notes Rungta College of Engg. & Technology 226 .

and program execution begins at the new address.  The two bytes from the top of the stack are copied into the program counter. & Technology 227 .  Example: RET MYcsvtu Notes Rungta College of Engg.Subroutine  Return from subroutine unconditionally  RET none  The program sequence is transferred from the subroutine to the calling program.

Subroutine  Return from subroutine conditionally  Operand: none  The program sequence is transferred from the subroutine to the calling program based on the specified flag of the PSW as described below.  Example: RZ MYcsvtu Notes Rungta College of Engg. & Technology 228 . and program execution begins at the new address.  The two bytes from the top of the stack are copied into the program counter.

& Technology 229 .Subroutine  RC Return on Carry CY = 1  RNC Return on no Carry CY = 0  RP Return on positive S = 0  RM Return on minus S = 1  RZ Return on zero Z = 1  RNZ Return on no zero Z = 0  RPE Return on parity even P = 1  RPO Return on parity odd P = 0 MYcsvtu Notes Rungta College of Engg.

Other instructions  Load program counter with HL contents  PCHL none  The contents of registers H and L are copied into the program counter. & Technology 230 .  Example: PCHL MYcsvtu Notes Rungta College of Engg.  The contents of H are placed as the high-order byte and the contents of L as the low-order byte.

Other instructions  Restart  RST 0-7 The RST instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending upon the number.  The instructions are generally used in conjunction with interrupts and inserted using external hardware. & Technology 231 .  The addresses are: MYcsvtu Notes Rungta College of Engg.  However these can be used as software instructions in a program to  transfer program execution to one of the eight locations.

Restart          Instruction Restart Address RST 0 0000H RST 1 0008H RST 2 0010H RST 3 0018H RST 4 0020H RST 5 0028H RST 6 0030H RST 7 0038H MYcsvtu Notes Rungta College of Engg. & Technology 232 .

5 0034H  RST 7.5 003CH MYcsvtu Notes Rungta College of Engg.Restart  The 8085 has four additional interrupts and these interrupts generate RST instructions internally and thus do not require any external hardware.5 002CH  RST 6. & Technology 233 .  These instructions and their Restart addresses are:  Interrupt Restart Address  TRAP 0024H  RST 5.

Logical instructions Compare register or memory with accumulator  CMP R  The contents of the operand (register or memory) are M compared with the contents of the accumulator. MYcsvtu Notes Rungta College of Engg.  Both contents are preserved . & Technology 234 .

& Technology 235 .Logical instructions  The result of the comparison is shown by setting the flags of the PSW as follows:  if (A) < (reg/mem): carry flag is set  if (A) = (reg/mem): zero flag is set  if (A) > (reg/mem): carry and zero flags are reset  Example: CMP B or CMP M MYcsvtu Notes Rungta College of Engg.

MYcsvtu Notes Rungta College of Engg. & Technology 236 .  The values being compared remain unchanged.Logical instructions  Compare immediate with accumulator  CPI 8-bit data  The second byte (8-bit data) is compared with the contents of the accumulator.

& Technology 237 .Logical instructions  The result of the comparison is shown by setting the flags of the PSW as follows:  if (A) < data: carry flag is set  if (A) = data: zero flag is set  if (A) > data: carry and zero flags are reset  Example: CPI 89H MYcsvtu Notes Rungta College of Engg.

Z. S.  CY is reset. its address is specified by the contents of HL registers.  If the operand is a memory location. and the result is placed in the accumulator. & Technology 238 .  Example: ANA B or ANA M MYcsvtu Notes Rungta College of Engg. P are modified to reflect the result of the operation.AC is set.Logical instructions  Logical AND register or memory with accumulator  ANA R  The contents of the accumulator are logically ANDed with M the contents of the operand (register or memory).

 CY is reset.  S. & Technology 239 .Logical instructions  Logical AND immediate with accumulator  ANI 8-bit data  The contents of the accumulator are logically ANDed with the 8-bit data (operand) and the result is placed in the accumulator. P are modified to reflect the result of the operation.  AC is set.  Example: ANI 86H MYcsvtu Notes Rungta College of Engg. Z.

 S. its address is specified by the contents of HL registers.  Example: XRA B or XRA M MYcsvtu Notes Rungta College of Engg.Logical instructions  Exclusive OR register or memory with accumulator  XRA R  The contents of the accumulator are Exclusive ORed with M the contents of the operand (register or memory). & Technology 240 .  If the operand is a memory location. Z. P are modified to reflect the result of the operation. and the result is placed in the accumulator.  CY and AC are reset.

 S.  Example: XRI 86H MYcsvtu Notes Rungta College of Engg. & Technology 241 .  CY and AC are reset. P are modified to reflect the result of the operation. Z.Logical instructions  Exclusive OR immediate with accumulator  XRI 8-bit data  The contents of the accumulator are Exclusive ORed with the 8-bit data (operand) and the result is placed in the accumulator.

 S.Logical instructions  Logical OR register or memory with accumulator  ORA R  The contents of the accumulator are logically ORed with M the contents of the operand (register or memory). and the result is placed in the accumulator.  CY and AC are reset. Z. its address is specified by the contents of HL registers. P are modified to reflect the result of the operation.  If the operand is a memory location. & Technology 242 .  Example: ORA B or ORA M MYcsvtu Notes Rungta College of Engg.

Z. & Technology 243 . P are modified to reflect the result of the operation.  Example: ORI 86H MYcsvtu Notes Rungta College of Engg.Logical instructions  Logical OR immediate with accumulator  ORI 8-bit data  The contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is placed in the accumulator.  S.  CY and AC are reset.

Logical instructions  Rotate accumulator left  RLC none  Each binary bit of the accumulator is rotated left by one position. P.  Example: RLC MYcsvtu Notes Rungta College of Engg. Z.  CY is modified according to bit D7. & Technology 244 .AC are not affected.  S.  Bit D7 is placed in the position of D0 as well as in the Carry flag.

AC are not affected.  S.  CY is modified according to bit D0. Z.  Bit D0 is placed in the position of D7 as well as in the Carry flag.Logical instructions  Rotate accumulator right  RRC none  Each binary bit of the accumulator is rotated right by one position. & Technology 245 . P.  Example: RRC MYcsvtu Notes Rungta College of Engg.

 CY is modified according to bit D7.  Example: RAL MYcsvtu Notes Rungta College of Engg. Z.  Bit D7 is placed in the Carry flag.  S. AC are not affected.Logical instructions  Rotate accumulator left through carry  RAL none  Each binary bit of the accumulator is rotated left by one position through the Carry flag. and the Carry flag is placed in the least significant position D0. P. & Technology 246 .

Logical instructions  Rotate accumulator right through carry  RAR none  Each binary bit of the accumulator is rotated right by one position through the Carry flag. and the Carry flag is placed in the most significant position D7. AC are not affected.  S.  Bit D0 is placed in the Carry flag.  Example: RAR MYcsvtu Notes Rungta College of Engg.  CY is modified according to bit D0. P. & Technology 247 . Z.

& Technology 248 . No flags are affected. Example: CMA MYcsvtu Notes Rungta College of Engg.Logical instructions      Complement accumulator CMA none The contents of the accumulator are complemented.

Logical instructions  Complement carry  CMC none  The Carry flag is complemented.  No other flags are affected. & Technology 249 .  Example: CMC MYcsvtu Notes Rungta College of Engg.

No other flags are affected.  Example: STC MYcsvtu Notes Rungta College of Engg. & Technology 250 .Logical instructions  Set Carry  STC none The Carry flag is set to 1.

Example: NOP MYcsvtu Notes Rungta College of Engg. & Technology 251 . However no operation is executed. The instruction is fetched and decoded.Machine control instructions       No operation NOP none No operation is performed.

 Example: HLT MYcsvtu Notes Rungta College of Engg. & Technology 252 .Machine control instructions  Halt and enter wait state  HLT none  The CPU finishes executing the current instruction and halts any further execution.  An interrupt or reset is necessary to exit from the halt state.

 No flags are affected. & Technology 253 .Machine control instructions  Disable interrupts  DI none  The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled.  Example: DI MYcsvtu Notes Rungta College of Engg.

thus disabling the interrupts.  This instruction is necessary to enable the interrupts (except TRAP). No flags are affected.Machine control instructions  Enable interrupts  EI none  The interrupt enable flip-flop is set and all interrupts are enabled. the interrupt enable flip flop is reset. Example: EI MYcsvtu Notes Rungta College of Engg. & Technology 254 .  After a system reset or the acknowledgement of an interrupt.

& Technology 255 .  Example: RIM MYcsvtu Notes Rungta College of Engg.5.5. 6.5 and read serial data input bit. 5.  The instruction loads eight bits in the accumulator with the following interpretations.Machine control instructions  Read interrupt mask  RIM none  This is a multipurpose instruction used to read the status of interrupts 7.

Machine control instructions  Set interrupt mask  SIM none  This is a multipurpose instruction and used to implement the 8085 interrupts 7.5. and serial data output.  Example: SIM MYcsvtu Notes Rungta College of Engg.5. & Technology 256 .5. 6. 5.  The instruction interprets the accumulator contents as follows.

Stack  The Stack Pointer  The stack on an 8080/8085 can be located anywhere in RAM memory. & Technology 257 . pointed to by the stack pointer SP.  Every time something is pushed on to the stack. the SP pointer is decremented. so the stack is growing down in memory. MYcsvtu Notes Rungta College of Engg.

D or H. & Technology 258 . which in fact is the LSB register of the AF pair MYcsvtu Notes Rungta College of Engg.Stack  Stack operations are always performed with registers pairs.  A register pair is referenced by the name of the MSB register: B.  The only exception is PSW.

whether it comes from the PUSH instruction. & Technology 259 MYcsvtu Notes . a subroutine call.Stack  A push on the stack. or interrupt has the following sequence:      Decrement SP by 1 Save most significant byte of register pair Decrement SP by 1 Save least significant byte of register pair Naturally a pop from the stack has just the opposite effect: Rungta College of Engg.

& Technology 260 .Stack  Load least significant byte of register pair  Increment SP by 1  Load most significant byte of register pair  Increment SP by 1 MYcsvtu Notes Rungta College of Engg.

pair  The contents of the register pair designated in the operand are copied onto the stack in the following sequence.  The stack pointer register is decremented and the contents of the high order register (B.Stack  Push register pair onto stack  PUSH Reg. E. & Technology 261 . D.  Example: PUSH B or PUSH A MYcsvtu Notes Rungta College of Engg. A) are copied into that location. flags) are copied to that location. H.  The stack pointer register is decremented again and the contents of the low-order register (C. L.

E. D.  The stack pointer register is again incremented by 1. pair  The contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C. status flags) of the operand.  Example: POP H or POP A MYcsvtu Notes Rungta College of Engg. & Technology 262 . H. A) of the operand.Stack  Pop off stack to register pair  POP Reg.  The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B. L.

A or MVI A. a destination can be a register or an output port.  The sources and destination are operands.  In these instructions the source can be a register. & Technology 263 . 82H are to copy data from a source into a destination. MYcsvtu Notes Rungta College of Engg.The 8085 Addressing Modes  The instructions MOV B. an input port.  The various formats for specifying operands are called the ADDRESSING MODES. or an 8-bit number (00H to FFH).  Similarly.

 Indirect addressing.  Direct addressing.  Register addressing.  Implicit addressing MYcsvtu Notes Rungta College of Engg. they are:  Immediate addressing.The 8085 Addressing Modes  For 8085. & Technology 264 .

 Example: MVI R. Load the immediate data to the destination provided. & Technology 265 .  Example: MOV Rd. data  Register addressing  Data is provided through the registers.The 8085 Addressing Modes  Immediate addressing  Data is present in the instruction. Rs MYcsvtu Notes Rungta College of Engg.

The 8085 Addressing Modes  Direct addressing  Used to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device.  Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port 01H.  Example: IN 00H or OUT 01H MYcsvtu Notes Rungta College of Engg. & Technology 266 .

 The second address is where the data is stored. & Technology 267 .The 8085 Addressing Modes  Indirect Addressing  This means that the Effective Address is calculated by the processor and the contents of the address (and the one following) is used to form a second address. MYcsvtu Notes Rungta College of Engg.  Note that this requires several memory accesses. two accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded into the register.

 Either hex or decimal numbers are acceptable.  They are not translated into machine code or assigned any memory locations in the object file.  ORG (origin)  org 20  The next block of instructions or data should be stored in memory locations starting at 2010. MYcsvtu Notes Rungta College of Engg.8085 Assembler Directives  Assembler directives are instructions to the assembler concerning the program being assembled. & Technology 268 .

 A HLT instruction may suggest the end of a program. but does not necessarily mean it is the end of assembly.  "start" is the label at the beginning of the program*. & Technology 269 . MYcsvtu Notes Rungta College of Engg.8085 Assembler Directives  END  end  start end of assembly.

& Technology 270 . lookup. MYcsvtu Notes Rungta College of Engg.  lookup's value may be referred by name in the program.  Similar to a constant statement. is equal to 2.8085 Assembler Directives  EQU  (equate)  lookup equ 2  The value of the term.

MYcsvtu Notes Rungta College of Engg.  This may be the memory location used as an input buffer. & Technology 271 .8085 Assembler Directives  inbuf equ 2099  The value of the term. inbuf. is 2099.

8085 Assembler Directives  DB  (define byte)  data: db 34 or data: db 34  db A2. MYcsvtu Notes Rungta College of Engg.  Assembled bytes of data are stored in successive memory locations until all values are stored.db 93  Initializes an area byte by byte.  The label is optional and may be used as the memory location of the beginning of the data. & Technology 272 .

In this example. & Technology 273 .  DS (define storage)  table: ds 10  Reserves a specified number of memory locations.10 memory locations are reserved for "table".  The label may be used as the memory location of the beginning of the block of memory.8085 Assembler Directives  DW (define word)  long: dw 2050 Initializes an area two bytes at a time. MYcsvtu Notes Rungta College of Engg.

a memory location. ways. an internal register. or 8-bit (or 16-bit) address.Instruction Format  An instruction is a command to the microprocessor to perform a given task on a specified data. called the operation code (opcode).  Each instruction has two parts: one is task to be performed.It may include 8-bit (or 16-bit ) data. called the operand. & Technology 274  The operand (or data) can be specified in various MYcsvtu Notes . Rungta College of Engg. and the second is the data to be operated on.

& Technology 275 .Instruction Format  In some instructions. the operand is implicit.  Instruction word size  The 8085 instruction set is classified into the following three groups according to word size:  One-word or 1-byte instructions  Two-word or 2-byte instructions  Three-word or 3-byte instructions MYcsvtu Notes Rungta College of Engg.

Instruction Format  One-Byte Instructions  A 1-byte instruction includes the op code and operand in the same byte.  Operand (s) are internal register and are coded into the instruction.  For example:  Copy the contents of the accumulator in the register C.A 0100 1111 4FH MYcsvtu Notes Rungta College of Engg. & Technology 276 .  MOV C.

 CMA 0010 1111 2FH MYcsvtu Notes Rungta College of Engg. & Technology 277 .Instruction Format  Add the contents of register B to the contents of the accumulator.  ADD B 1000 0000 80H  Invert (compliment) each bit in the accumulator.

& Technology 278 .Instruction Format  MOV rd. MYcsvtu Notes Rungta College of Engg.  Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is the destination of the data. rs  rd <-.rs copies contents of rs into rd. sss is the code of the source register.

 For example:  Load an 8-bit data byte in the accumulator.  MVI A. & Technology 279 .  Source operand is a data byte immediately following the op code. the first byte specifies the operation code and the second byte specifies the operand. Data 3E MYcsvtu Notes Rungta College of Engg.Instruction Format  Two-Byte Instructions  In a two-byte instruction.

& Technology 280 . The assembly language instruction is written as  Mnemonics Hex code  MVI A.Instruction Format  Assume that the data byte is 32H.data  Example: MVI A. 32H . MYcsvtu Notes Rungta College of Engg.30H coded as 3EH 30H as two contiguous bytes.3E 32H  The instruction would require two memory locations to store in memory.  MVI r. data  r <-.

Instruction Format  ADI data  A <-.A + data  OUT port where port is an 8-bit device address. MYcsvtu Notes Rungta College of Engg.  Since the byte is not the data but points directly to where it is located this is called direct addressing.A.  (Port) <-. & Technology 281 .

the first byte specifies the op code.  JMP 2085H MYcsvtu Notes Rungta College of Engg.Instruction Format  Three-Byte Instructions  In a three-byte instruction.  Op code + data byte + data byte  For example:  Transfer the program sequence to the memory location 2085H. & Technology 282 . and the following two bytes specify the 16-bit address.  Note that the second byte is the low-order address and the third byte is the high-order address.

Instruction Format  C3 85 20  First byte Second Byte Third Byte  This instruction would require three memory locations to store in memory.  rp <-. & Technology 283 . DE.opcode + data byte + data byte  LXI rp.  Three byte instructions . HL used as 16-bit registers. data16  rp is one of the pairs of registers BC.data16 MYcsvtu Notes Rungta College of Engg.  The two data bytes are 16-bit data in L H order of significance.

MYcsvtu Notes Rungta College of Engg.  This is also immediate addressing.0520H coded as 21H 20H 50H in three bytes.  This is also an example of direct addressing.  Example: LDA 2134H coded as 3AH 34H 21H.(addr) Addr is a 16-bit address in L H order.Instruction Format  Example:  LXI H. & Technology 284 .  LDA addr  A <-.

MYcsvtu Notes Rungta College of Engg.Delay generation  Delay are generated using subroutine  Delays are generated for different purpose  Example.Traffic signal. counters (timer circuits) etc  They may also be generated using NOP instruction. & Technology 285 .

& Technology 286 .Delay generation  Ways to generate delay-  Delay depends on the total number of T states present in the subroutine  To start with a “counter” is set up  For small delays an 8 bit register is set up  For large delays a 16 bit register is used as counter  Nested lops are also used in which two registers are used MYcsvtu Notes Rungta College of Engg.

Delay generation  Small delay generation  8 bit register is used as counter  SUBROUTINE Set an 8 bit register as a counter MVI B. & Technology . FFH  DELAY DCR B  JNZ DELAY  RET  MYcsvtu Notes -7T -4T -10T/7T -10T 287 Rungta College of Engg.

 For the last jump the condition becomes untrue and it comes out the loop. & Technology 288 .  Total T states in the above program  =7T+(COUNT-1)(4T+10T)+(4T+7T)+10T  =7T+254*14T+11T+10T  =3584 T states MYcsvtu Notes Rungta College of Engg.Delay generation  The loop is executed count-1 times.

5 micro secs  Td= 3584*.792 mili secs MYcsvtu Notes Rungta College of Engg.5  =1792 microseconds  =1.Delay generation  Now if clock period=. & Technology 289 .

E-4T  ORA D-4T  JNZ DELAY-10T/7T  RET-10T MYcsvtu Notes Rungta College of Engg.FFFF H-10T  DELAY DCX D-6T  MOV A.Delay generation  Long delay generation  16 bit register is used as counter  LXI D. & Technology 290 .

5 micro secs  Td=1572857*. & Technology 291 .Delay generation  Total number of T states=  10t+(6t+4t+4t+10t)*count-1+(6t+4t+4t+7t)+10t  = 10t+(6t+4t+4t+10t)*65534+(6t+4t+4t+7t)+10t  =1572857 t states  If 1t=.43ms MYcsvtu Notes Rungta College of Engg.5=  =786.

& Technology 292 .3333 micro secs clock cycle)  Write a subroutine for 8085 to generate a delay of 100microsecs(assume 320 ns clock cycle) MYcsvtu Notes Rungta College of Engg.Delay generation  Write a subroutine for 8085 to generate a delay of 10ms(assume .

C  ORA B  JNZ UP  FREQUENCY=2 MHz MYcsvtu Notes Rungta College of Engg. & Technology 293 .Calculate the delay generated by the following set of instructions  LXI B.3480 H  UP DCX B  MOV A.Delay generation  If the clock frequency of a 8085 system is 2MHz.

6T MOV A.10T DELAY DCX D.count H.Delay programs            Sol1For .3333)*10 = 30030.E4T ORA D4T JNZ DELAY10T/7T RET10T Rungta College of Engg.03 secs = 30030 t states It‟s a large value hence reg pair is used as counter Program LXI D. & Technology 294 MYcsvtu Notes .3333 micro secs clock cycle 10 ms=(1/.

Delay programs  30030*T = 10T+(6+4+4+10)* count-1 Count +(6+4+4+7)T+10T = 1250. & Technology 295 .5 = (1250)d MYcsvtu Notes Rungta College of Engg.

count H  DELAY DCR B  JNZ DELAY  RET -7T -4T -10T/7T -10T MYcsvtu Notes Rungta College of Engg.Delay programs  Sol 2  Program  MVI B. & Technology 296 .

5 * T = 7T+(4T+10T) count-1 +(4T+7T)+ 10T Count = 21.Delay programs  100 micro secs = (100/320 ns) = 312. & Technology 297 .32 =(21)d = 15H MYcsvtu Notes Rungta College of Engg.5 t states 312.

5 micro secs  Td= 10T+(6T+4T+4T+10T)* count-1 +(6+4+4+7)T+10T Hence substituting the values of 1 T & count we have Td = 161288. & Technology 298 .5 micro secs = 161.16 s MYcsvtu Notes Rungta College of Engg.Delay programs  Sol 3  Given frequency = 2 MHz  Count = (3480)H = (13440)d  T = (1/2*10^6) = .28 ms = .

A MYcsvtu Notes Rungta College of Engg.M  MOV B. & Technology 299 . STACK  LXI H.Programs for code conversion  Binary to ASCII code conversion  LXI SP. 4050 H  LXI D. 4060 H  MOV A.

& Technology 300 .B MYcsvtu Notes Rungta College of Engg.Binary to ASCII code conversion  RRC  RRC  RRC  RRC  CALL ASCII  STAX D  INX D  MOV A.

SUBROUTINE ANI 0F H CPI 0A H JC CODE ADI 30 H CODE ADI 30 H RET Rungta College of Engg.Binary to ASCII code conversion           CALL ASCII STAX D HLT ASCII. & Technology 301 MYcsvtu Notes .

ASCII TO BINARY  SUBROUTINE  SUI 30 H  CPI 0A H  RC  SUI 07 H  RET MYcsvtu Notes Rungta College of Engg. & Technology 302 .

BCD TO BINARY CONVERSION  BCD TO BINARY CONVERSION  LXI SP. 4060 H  MOV A. STACK  LXI H. & Technology 303 . 4050 H  LXI B.M  CALL BCD TO BINARY  STAX B  HLT MYcsvtu Notes Rungta College of Engg.

BCD TO BINARY CONVERSION  SUBROUTINE BCD TO BINARY       PUSH B PUSH D MOV C.A MOV A.C MYcsvtu Notes Rungta College of Engg.A ANI OF H MOV B. & Technology 304 .

0A H MOV D.BCD TO BINARY CONVERSION         ANI F0 H RRC RRC RRC RRC MVI E. & Technology 305 .A XRA A MYcsvtu Notes Rungta College of Engg.

& Technology 306 .BCD TO BINARY CONVERSION  SUM ADD E  DCR D  JNZ SUM  ADD B  POP D  POP B  RET MYcsvtu Notes Rungta College of Engg.

64H MYcsvtu Notes Rungta College of Engg.M CALL SUB1 HLT SUB1 LXI H. 4FFF H LXI H.4060 H MVI B.BINARY TO BCD CONVERSION        LXI SP. & Technology 307 . 4050 H MOV A.

& Technology 308 .BINARY TO BCD CONVERSION             MYcsvtu Notes CALL CONVERSION MVI B.A CONVERSION MVI M.0A H CALL CONVERSION MOV M. FF H LOOP INR M SUB B JNC LOOP ADD B INX H RET Rungta College of Engg.

4060 H MYcsvtu Notes Rungta College of Engg. 03 H CALL UNPACK HLT UNPACK LXI B. 4050 H MVI D.BCD TO 7 SEGMENT LED CODE CONVERSION       LXI SP. & Technology 309 . 4FFF H LXI H.

& Technology 310 .M ANI F0 H RRC RRC RRC CALL LED CONVERSION INX B MOV A.M MYcsvtu Notes Rungta College of Engg.BCD TO 7 SEGMENT LED CODE CONVERSION         AHEAD MOV A.

& Technology 311 .BCD TO 7 SEGMENT LED CODE CONVERSION  ANI 0F H  CALL LED CONVERSION  INX B  INX H  DCR D  JNZ AHEAD  RET MYcsvtu Notes Rungta College of Engg.

& Technology 312 MYcsvtu Notes .M STAX B POP H RET Rungta College of Engg. CODE ADD L MOV L.BCD TO 7 SEGMENT LED CODE CONVERSION          LED CONVERSION PUSH H LXI H.A MOV A.

8BH  MVI C. C  ADD D  OUT PORT1  HLT MYcsvtu Notes Rungta College of Engg.Sample Programs  Write an assembly program to add two numbers  Program  MVI D. 6FH  MOV A. & Technology 313 .

Sample Programs  Write an assembly program to multiply a number by 8  Program  MVI A. & Technology 314 . 30H  RRC  RRC  RRC  OUT PORT1  HLT MYcsvtu Notes Rungta College of Engg.

30H  MVI C.Sample Programs  Write an assembly program to find greatest between two numbers  Program  MVI B. 40H  MOV A. B  CMP C  JZ EQU  JC GRT  OUT PORT1  HLT MYcsvtu Notes Rungta College of Engg. & Technology 315 .

C  OUT PORT1  HLT MYcsvtu Notes Rungta College of Engg. 01H  OUT PORT1  HLT  GRT: MOV A.Sample Programs  EQU: MVI A. & Technology 316 .

& Technology 317 .Sample Programs  Write a 8085 machine code program: Read two different memory locations  Add the contents  Send the result to output port 02 (display) if there is no overflow  Display “FF” if there is an overflow  Stop  MYcsvtu Notes Rungta College of Engg.

A LDA 2051 ADD B JNC 2013 3A 50 20 47 3A 51 20 80 D2 MYcsvtu Notes Rungta College of Engg.Sample Programs 2000 2001 2002 2003 2004 2005 2006 2007 2008 LDA 2050 MOV B. & Technology 318 .

2009 2010 2011 2012 2013 2014 2015 MVI A.FF OUT 02 HLT 13 20 3E FF D3 02 76 MYcsvtu Notes Rungta College of Engg. & Technology 319 .

MYcsvtu Notes Rungta College of Engg.Sample Programs  Multiply eight bit numbers using successive addition method numbers are loaded in reg. & Technology 320 . Result is stored in HL pair. D and C.

& Technology 321 . 0000  DAD B  DCR D  JNZ C008  HLT MYcsvtu Notes Rungta College of Engg.Sample Programs  MVI D. 05  LXI B. 0015  LXI H.

Assume the array starts from C200. & Technology 322 . MYcsvtu Notes Rungta College of Engg. Store the result at C300.Sample Programs  Write a program to find the positive numbers in an array of 10 elements.

09 LDA C001 LXI H. & Technology 323 MYcsvtu Notes .Sample Programs          MVI C . C002 ADD M INX H DCR C JNZ D008 STA C100 HLT Rungta College of Engg.

UNIT. & Technology 324 .III DATA TRANSFER & DEVICE SELECTION MYcsvtu Notes Rungta College of Engg.

Interface modules are used to match CPU and main memory characteristics to those of the peripheral devices MYcsvtu Notes Rungta College of Engg.  Peripheral devices are slower than CPUs and require special . & Technology 325 .Data transfer & device selection  Input-Output (I/O) describes the transference of information between main memory and the various peripheral devices attached to a computer.

a keyboard is a character–based input device. & Technology 326 . Keyboard input is very slow. MYcsvtu Notes Rungta College of Engg.Data transfer & device selection  I/O device characteristics  The speed of data transfer and the quantity of data that is transferred are two critical factors of I/O devices. and each character of a keyboard is inputted into a PC as an ASCII code.  For example.

 There is an expected input by an application program in response to a „read statement‟ of some kind that requests input of data for the program.Data transfer & device selection  Task  Why is character input slow?  There are different types of character input from a keyboard. think about dataentry into an expert system. MYcsvtu Notes Rungta College of Engg. & Technology 327 .

since the program that is undergoing execution is not expecting such inputs or interrupts. under the „Unix‟ operating system typing Control-c will stop a program that is running. Alt.Data transfer & device selection  On other occasions. MYcsvtu Notes Rungta College of Engg. & Technology 328 .  For example. the user may wish to interrupt what the computer is doing.  In terms of computation these are examples of unexpected inputs. in contrast under a „Windows type‟ operating system typing Control-c is an editing command to copy data and typing Control. Delete will restart a PC.

 The computer must be able to respond quickly to each keyboard.  The computer must have the capability to distinguish between the different keyboards.Data transfer & device selection  On a multi user system. many keyboards might be connected to a single computer. MYcsvtu Notes Rungta College of Engg. & Technology 329 .  The computer must not lose input data even if several keyboards transmit a character input simultaneously. and the physical distances of the keyboards to the computer may be long.

 VDUs and most printers are output devices. MYcsvtu Notes Rungta College of Engg. & Technology 330 .Data transfer & device selection  Task  How do you think a mouse action can act as an interrupt?  Disks. screens and other I/O devices operate under the CPU program control. and the output that is produced is determined by the program undergoing execution. printers.

it is always the program undergoing execution in the CPU that initiates I/O data transfer. MYcsvtu Notes Rungta College of Engg. & Technology 331 . but as we have previously discussed there can be a „blur‟ to this concept and disks can be considered to be both I/O devices as well as storage devices.Data transfer & device selection  Disks are storage devices.  Furthermore. the CPU will continue processing other tasks while waiting for a particular I/O operation to complete.  In these cases. where the input and the output are determined by the program undergoing execution.

& Technology 332 .  In such cases. or it may be stalled due to a miss feed of paper. MYcsvtu Notes Rungta College of Engg.  For example. in order that appropriate action can be taken. a printer may already have a print job.  There might not be a floppy disk in a floppy disk drive or a hard disk might be servicing a different request.Data transfer & device selection  There are occasions when an I/O device being addressed is busy or not ready. it is beneficial for the I/O device to be able to provide status information to the CPU.

 c) Programmed I/O is suitable for slow devices and word transfers. MYcsvtu Notes Rungta College of Engg.Data transfer & device selection  Requirements for sufficient and effective handling of I/O  a) There must be a means for individually addressing different I/O devices. & Technology 333 .  e) There must be mechanisms to handle devices with extremely different control requirements.  d) Faster I/O devices must have mechanisms to transfer blocks of data.  b) There must be mechanisms by which I/O devices can communicate with the CPU.

32 or even 64. the formats required by different devices are different. Some devices require a single portion of data. others a block of data. others 16. MYcsvtu Notes Rungta College of Engg. Some devices expect 8 bits of data.  For example. & Technology 334 .Data transfer & device selection  Consequently. it is impractical to connect I/O devices directly to a CPU without some form of interface unit that is unique to each device.

a computer system requires substantially different interface hardware and software for each I/O device. Rungta College of Engg.  Therefore.Data transfer & device selection  Data may be transmitted serially or in parallel. & Technology 335 MYcsvtu Notes .  Incompatibilities in speed between the various I/O devices and the CPU render synchronization a major problem.

 Such control requirements would consume a vast amount of CPU time.  Additionally. there is a necessity for the provision of addressing. status control and external control capabilities. MYcsvtu Notes Rungta College of Engg. each I/O device requires its own unique interface module to serve between itself and the CPU. synchronization.  I/O devices therefore have different requirements. & Technology 336 .  Consequently.Data transfer & device selection  Magnetic disks have electromechanical control requirements that must be met.

Interface modules  Interface modules  Interface modules can be very simple and control a single I/O device. Alternatively. controlling many I/O devices and may have substantial built in intelligence MYcsvtu Notes Rungta College of Engg. interface modules can be complex. & Technology 337 .

MYcsvtu Notes Rungta College of Engg.Interface modules Serial & parallel data transfer  There are many types of interface modules. & Technology 338 . but they all have one important characteristic. which distinguishes whether they support parallel data transfer or serial data transfer.  A parallel interface transfers multiple bits of data simultaneously using a separate data line for each bit.

& Technology 339 .Interface modules Serial & parallel data transfer  Parallel data transfer MYcsvtu Notes Rungta College of Engg.

Interface modules Serial & parallel data transfer  In contrast.  Serial data transfer MYcsvtu Notes Rungta College of Engg. & Technology 340 . a serial interface transfers single bits of data consecutively over a single data line.

 However.Interface modules  It is possible to transfer data a word[1] at a time. & Technology 341 . blocks of data are transferred. MYcsvtu Notes Rungta College of Engg. the amount of data that is transferred between devices such as disks and tapes renders word transfer far too slow for modern high-speed computers. which is adequate for slow operating I/O devices.  A further problem is that a computer has many I/O devices.  Consequently. and many may attempt to transfer data simultaneously.

 Different devices operate at different speeds to each other and the CPU. For example. whereas a disk might transfer data at millions of bytes/sec. a dot-matrix printer may output 40 characters/sec. & Technology 342 . there is a requirement to distinguish and separate I/O from these different devices. MYcsvtu Notes Rungta College of Engg.Interface modules  Therefore.  To prevent data loss such I/O operations must be synchronized.

 The unit is composed of three registers: a data register.Interface modules  A simple parallel I/O interface. a control register and a status register. which can be accessed by the CPU over the system bus. MYcsvtu Notes Rungta College of Engg. & Technology 343 .

& Technology 344 . MYcsvtu Notes Rungta College of Engg.Interface modules  The external data bus is a collection of parallel data lines that can be configured to be either input or output by writing a suitable bit pattern into the control register.

serves as a buffer between the system bus and the external data bus.  The status register is used to flag whether a device is ready and data is available. MYcsvtu Notes Rungta College of Engg. therefore.Interface modules  Once configured. data is transferred to or from the external data bus by reading or writing from or to the data register or port.  This data port.  The CPU by using the control bus can inspect the status register to determine whether data can be sent or received. & Technology 345 .

MYcsvtu Notes Rungta College of Engg.Interface modules-Handshake concept  The data bus must be able to support data transfer with a wide range of peripheral devices. & Technology 346 .  The speeds of the different peripheral devices are usually known. therefore control or handshake signals are provided to synchronize the bus activities of the interface device and the I/O device. see Figure .

 A handshake protocol is used that uses two control lines: data available and data accepted. & Technology 347 . which puts data on the data bus and asserts the data available control line. MYcsvtu Notes Rungta College of Engg.Interface modules-Handshake concept  The example typically represents how data is transferred from an output port to a peripheral device such as a printer.  The handshake is initiated by the interface module.

& Technology 348 .  After the printer has completed processing.  When the interface module receives this acknowledgement. it reads the data from the bus and broadcasts an acknowledgement by asserting the data accepted control line.Interface modules-Handshake concept  When the peripheral device (in this case a printer) detects this signal. MYcsvtu Notes Rungta College of Engg. it negates the data available control line. it negates the data accepted control line and the handshake is completed.

 Even if a block of data is transferred between a disk and the CPU in a single instruction. & Technology 349 . MYcsvtu Notes Rungta College of Engg.  For example.  It is advantageous to enable the CPU to process other tasks while a slow I/O transfer is taking place. a CPU could execute many instructions in that time that a single character is printed.Interface modules-Handshake concept  I/O operations consume large amounts of processing time. a large amount of time is wasted waiting for the task to complete.

& Technology 350 .I/O DATA TRANSFER SCHEME  I/O DATA TRANSFER SCHEME  Its divided into two data transfer  Programmed data transfer 1) synchronous data transfer 2) asynchronous data transfer  DMA data transfer MYcsvtu Notes Rungta College of Engg.

& Technology 351 .Programmed I/O data transfer  Modes of I/O Transfer: Programmed I/O  There are three ways by which the transfer of data between an I/O device and memory can be managed or scheduled:  programmed I/O  Interrupt-controlled I/O and  Direct Memory Access (DMA). MYcsvtu Notes Rungta College of Engg.

such as the one shown in Figure.Programmed I/O data transfer  Many I/O modules permit control lines to be programmed to suit the needs of a particular peripheral device.  Each data transfer is carried out by executing a polling loop.  With programmed I/O the CPU has control over all aspects of the data transfer. MYcsvtu Notes Rungta College of Engg. & Technology 352 .

Programmed I/O data transferPolling loop MYcsvtu Notes Rungta College of Engg. & Technology 353 .

 In the case that the I/O device is not ready because the examine flag is negated. data is transferred and the processor loops back.  In the case that the I/O device is ready because the examine flag is asserted. the processor schedules data transfer to a peripheral device by first reading the port status register to see if the peripheral device is ready to transmit or receive data.Programmed I/O data transfer  In this example. the processor loops back. MYcsvtu Notes Rungta College of Engg. & Technology 354 .

can waste large amounts of CPU time.Programmed I/O data transfer  The major disadvantage of programmed I/O is the polling loop. or busy waiting. and it is therefore inefficient in terms of CPU usage. keyboards and monitors. & Technology 355 . MYcsvtu Notes Rungta College of Engg.  Programmed I/O is slow and is suitable for character transmission I/O devices such as printers.

& Technology 356 .  For example. MYcsvtu Notes Rungta College of Engg.  Interrupt driven I/O is more efficient than programmed I/O. Alt. because an I/O device signals the CPU when it requires a service. Delete on a PC interrupts the program that is running and restarts the PC.Interrupt driven I/O  Modes of I/O Transfer: Interrupt driven I/O  With interrupt driven I/O the normal flow of a program is interrupted to react to a special event. typing Control.

where IRQ represents Interrupt Request.  It is common for a PC to have between 8 and 15 interrupt lines. MYcsvtu Notes Rungta College of Engg. which are labeled IRQ1. interrupt driven I/O frees the CPU to continue executing other tasks. & Technology 357 .  Most computers have interrupt lines to detect and record the arrival of an interrupt request.Interrupt driven I/O  Consequently. IRQ2 and so on.

the PC and status register are saved by pushing them onto a Return Address Stack (RAS).  Before control is passes to the interrupt handler.Interrupt driven I/O  In the case that an IRQ is asserted the computer suspends the program that is undergoing execution. the CPU passes program control to an interrupt handler or service routine.  When an interrupt is accepted. MYcsvtu Notes Rungta College of Engg. & Technology 358 .

and control is passed back to the interrupted program. & Technology 359 .  Multiple interrupts can occur together. MYcsvtu Notes Rungta College of Engg. in which case a priority mechanism must decide the order in which the interrupts are handled.  Once the interrupt has been completed the PC and status register is popped from the RAS.Interrupt driven I/O  The interrupt handling program is now executed until a Return from Exception (RTE) instruction is encountered at the end of the interrupt.

 Second.Interrupt driven I/O  There are two major disadvantages of interrupt driven I/O. since the PC and Status Register are pushed onto the RAS before control is passed to the interrupt handler and they are popped from the RAS when an RTE is encountered. then a significant overhead is involved which can impact on processor performance MYcsvtu Notes Rungta College of Engg. & Technology 360 .  First. all data transfers involve moving data to and from the CPU registers.

MYcsvtu Notes Rungta College of Engg. see storage device handout. particularly those used for block devices such as magnetic disks use DMA.DMA I/O  Modes of I/O Transfer: DMA I/O  An alternative mechanism that avoids the use of the CPU is called Direct Memory Access (DMA).  Many device controllers. & Technology 361 .

& Technology 362 .  Once the data has been transferred the Interface module notifies the CPU.DMA I/O  Data is directly transferred between a peripheral device from main memory and the CPU is bypassed. so that the CPU is aware that the data transfer has completed and main memory access can then resume. MYcsvtu Notes Rungta College of Engg.

then DMA is particularly useful in a multitasking system.  There are several advantages of DMA. MYcsvtu Notes Rungta College of Engg. & Technology 363 . First DMA is particularly good at fast data transfers.  Second.DMA I/O  Data transfer is initiated using programmed I/O by the program that is undergoing execution in the CPU. and multi user systems. since the CPU can be used for other tasks.  The CPU is then bypassed for the remainder of the interrupt.

 For example. & Technology 364 .DMA I/O  DMA is not restricted to I/O device – Memory transfers. it can be used with other high-speed devices. MYcsvtu Notes Rungta College of Engg. DMA is an effective means of transferring video data from memory to a video I/O device for rapid display.

MYcsvtu Notes Rungta College of Engg.g. & Technology 365 .: A "0100 0001" would become "1 0100 0001 0".Asynchronous and synchronous data transmission  Asynchronous and synchronous data transmission  Asynchronous transmission uses start and stop bits to signify the beginning bit ASCII character would actually be transmitted using 10 bits  e.  The extra one (or zero depending on parity bit) at the start and end of the transmission tells the receiver first that a character is coming and secondly that the character has ended.

MYcsvtu Notes Rungta College of Engg.  This allows the receiver to recognize when the second packet of information is being sent. & Technology 366 .  The start and stop bits must be of opposite polarity.  In the previous example the start and stop bits are in bold.Asynchronous and synchronous data transmission  This method of transmission is used when data are sent intermittently as opposed to in a solid stream.

Asynchronous and synchronous data transmission  Synchronous transmission uses no start and stop bits but instead synchronizes transmission speeds at both the receiving and sending end of the transmission using clock signals built into each component. nodes. & Technology 367 .  A continual stream of data is then sent between the two MYcsvtu Notes Rungta College of Engg.

& Technology 368  Ways to get around this problem include re- MYcsvtu Notes . so some bytes could become corrupted (by losing bits). as the clocks will eventually get out of sync.Asynchronous and synchronous data transmission  Due to there being no start and stop bits the data transfer rate is quicker although more errors will occur. Rungta College of Engg. and the receiving device would have the wrong time that had been agreed in protocol (computing) for sending/receiving data. synchronization of the clocks and use of check digits to ensure the byte is correctly interpreted and received.

data is sent via a bitstream. MYcsvtu Notes Rungta College of Engg.Asynchronous and synchronous data transmission  Synchronous and Asynchronous data transfer are two methods of sending data over a phone line. & Technology 369 .  In order to do this. where they are prepared to be sent as such a stream.  In synchronous data transmission. modems gather groups of characters into a buffer. which sends a group of characters in a single stream.

called synchronization.  They accomplish this by sending special characters.Asynchronous and synchronous data transmission  In order for the stream to be sent. or syn. synchronous modems must be in perfect synchronization with each other. & Technology 370 . MYcsvtu Notes Rungta College of Engg. characters.

including a start bit and a stop bit. data is coded into a series of pulses. & Technology 371 . the data stream is sent.Asynchronous and synchronous data transmission  When the clocks of each modem are in synchronization.  In asynchronous transmission. followed by a stop bit designating that the transfer of that bit is complete MYcsvtu Notes Rungta College of Engg.  A start bit is sent by the sending modem to inform the receiving modem that a character is to be sent.  The character is then sent.

Memory-Mapped I/O  I/O devices are treated like memory locations  Processor uses memory-access instructions and addressing modes to access I/O devices  I/O devices and memory locations cannot have the same address  Address is 16 bits wide  Memory of 64K is shared with I/O devices MYcsvtu Notes Rungta College of Engg. & Technology 372 .

I/O-mapped I/O  Processor controls I/O by a group of dedicated control signals  Processor uses special instructions to access these I/O  Each I/O (or port) is identified by a unique port number  IN and OUT instructions are used. MYcsvtu Notes Rungta College of Engg.  256 combinations or 256 I/O devices can be assembled  Same 8 bit address is copied to A0-A7 and A8 – A15. & Technology 373 .  64 k memory and 256 I/O devices are available.

& Technology 374 .  However. the ROM does not have a WR signal.Memory structure & its requirements RAM Data Lines ROM WR Input Buffer Address Lines CS Address Lines CS Output Buffer RD Output Buffer RD Data Lines Date Lines  The process of interfacing the above two chips is the same. MYcsvtu Notes Rungta College of Engg.

Memory structure & its requirements  8085 requires memory to-  Read op code  To read/write data  Hence both EPROM & RAM are interfaced with it  Multiple EPROM & RAM could be interfaced anywhere with in the address range of 8085 MYcsvtu Notes Rungta College of Engg. & Technology 375 .

Memory structure & its requirements  Memory chip consists of registers to store data  They are represented as  2k*8.  Each location stores 8 bit  2*1024 registers & each register could store only 8 bits MYcsvtu Notes Rungta College of Engg. & Technology 376 . 4k*8. 8k*8 etc  2k*8 means it has address range of 2*1024 bytes.

 8085 has 16 address lines  It can address 64 k memory  Interfacing means we have to place the available memory chip (2k. & Technology 377 .8k.16k EPROM/RAM) with in the 64 k byte address range) MYcsvtu Notes Rungta College of Engg.Steps for memory interfacing with 8085  Enable the memory chip  Identify the address at which the data had to be operated.4k.

& Technology 378 .Steps for memory interfacing with 8085  Placing in the address range is also referred as “Mapping”  Memory could be placed anywhere  Mapping decides address of the memory component  Its not necessary to use 64 KB of memory  It depends on the application  We can expand the memory in order to get the memory size we want. MYcsvtu Notes Rungta College of Engg.

 Some are used for decoding the address of the memory chip.  All these steps depend on the range of the memory chip to be connected to 8085 MYcsvtu Notes Rungta College of Engg.  This may require the use of the decoder IC 74LS138.  Reset address of 8085 if 0000 h.Steps for memory interfacing with 8085  We can have multiple EPROM and multiple RAM. So at least mapping of one EPROM is necessary at 0000 h  Some address lines of 8085 are used to connect directly to the memory chip. & Technology 379 .

& Technology 380 .Steps for memory interfacing with 8085  Accessing memory can be summarized into the following three steps:  Select the chip.  Identify the memory register. MYcsvtu Notes Rungta College of Engg.  Enable the appropriate buffer.

The MEMR signal can be used to enable the RD line on the memory chip.  MYcsvtu Notes Rungta College of Engg.  Part of the address bus will select the chip and the other part will go through the address decoder to select the register.  The signals IO/M and RD combined indicate that a memory read operation is in progress.Steps for memory interfacing with 8085 Translating this to microprocessor domain:  The microprocessor places a 16-bit address on the address bus. & Technology 381 .

 What concerns us is the other part that must be decoded externally to select the chip. MYcsvtu Notes Rungta College of Engg.  A large part of the address bus is usually connected directly to the address inputs of the memory chip.  This can be done either using logic gates or a decoder. & Technology 382 .Address decoding  The result of address decoding is the identification of a register for a given address.  This portion is decoded internally within the chip.

The Overall Picture  Putting all of the concepts together. we get: A15.A10 Chip Selection Circuit 8085 A15-A8 ALE CS AD7-AD0 Latch A9.A0 1K Byte Memory Chip WR RD IO/M D7.D0 RD WR MYcsvtu Notes Rungta College of Engg. & Technology 383 .A0 A7.

& Technology 384 .Examples of memory interfacing with 8085  Single EPROM & Single RAM.case1 0000 H 4K EPROM 0FFF H 1000 H 4K RAM 1FFF H MYcsvtu Notes Rungta College of Engg.

Examples of memory interfacing with 8085  Single EPROM & Single RAM-Case 2 0000 H 4K EPROM 0FFF H 2000 H 4K RAM 2FFF H FFFF H MYcsvtu Notes Rungta College of Engg. & Technology 385 .

& Technology 386 .Examples of memory interfacing with 8085  Two EP ROMs and Single RAM 0000 H 4K EPROM 0FFF H 0FFF H RAM C000 H COOO H 4K EPROM CFFF H FFFF H MYcsvtu Notes Rungta College of Engg.

Examples of memory interfacing with 8085  Interface 2KB of memory to 8085 with starting address 8000 H  Sol Placing the starting address of the chip on the address lines of 8085 we have  A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MYcsvtu Notes Rungta College of Engg. & Technology 387 .

& Technology 388 .Examples of memory interfacing with 8085  2 KB = 2*2^10 = 2 ^ 11  Hence 11 address lines (A0-A10) are connected directly to the memory chip and A15 to A11 are used for selecting the chip  MYcsvtu Notes Rungta College of Engg.

& Technology 389 .  The chip is selected by providing a low signal at its chip select pin.  Their logic is so adjusted so that the output of NAND gate is low. MYcsvtu Notes Rungta College of Engg.  A15 to A11 are used to select the chip using the NAND gate.Examples of memory interfacing with 8085  The final address of the chip is obtained as follows A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1  Hence the range of the chip is from 8000 H to 87FF H.  The A15 to A11 address lines are used as inputs to the NAND gate.

& Technology 390 .Shadow memory/Folded memory/Linear decoding  Its also known as partial or linear decoding  In this type of decoding its not necessary to use all address lines  Address lines which are not really required for selection of chip could be used for finding different address range of a single memory chip MYcsvtu Notes Rungta College of Engg.

MYcsvtu Notes Rungta College of Engg.Shadow memory/Folded memory/Linear decoding  Example-  Interface 1K*8 EPROM to 8085 using linear decoding  Sol  Lets assume the starting address as 0000 H. & Technology 391 .  The address range of the given chip is obtained as follows A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1  ie the range is 0000 H to 03FF H.

Shadow memory/Folded memory/Linear decoding  Now if the logic of A15 and A14 lines are changed as follows A15 A14 0 0 0 1 1 0 1 1  we have the different address range of the same chip as followsMYcsvtu Notes Rungta College of Engg. & Technology 392 .

MYcsvtu Notes Rungta College of Engg. & Technology 393 .Shadow memory/Folded memory/Linear decoding  0000 H 03FF H  4000 H 43FF H  8000 H 83FF H  C000 H C3FF H  This results in wastage of address space.

Shadow memory/Folded memory/Linear decoding 0000 H Actual Address 03FF H 4000 H 43FF H 8000 H Folded Address83FF H C000 H C3FF H FFFF H MYcsvtu Notes Rungta College of Engg. & Technology 394 .

Absolute decoding  In absolute decoding no address space is wasted  Its used when number of peripherals is more  More hardware is required MYcsvtu Notes Rungta College of Engg. & Technology 395 .

UNIT.IV INTERRUPTS MYcsvtu Notes Rungta College of Engg. & Technology 396 .

MYcsvtu Notes Rungta College of Engg.  The process starts from the I/O device  The process is asynchronous. & Technology 397 .Interrupts  Interrupt is a process where an external device can get the attention of the microprocessor.

Interrupts  Classification of Interrupts  Interrupts can be classified into two types:  Maskable Interrupts (Can be delayed or Rejected)  Non-Maskable Interrupts (Can not be delayed or Rejected) MYcsvtu Notes Rungta College of Engg. & Technology 398 .

The Microprocessor may respond to it as soon as possible. Rungta College of Engg. & Technology 399 MYcsvtu Notes .Interrupts  Interrupts can also be classified into:  Vectored (the address of the service routine is hard- wired)  Non-vectored (the address of the service routine needs to be supplied externally by the device)  An interrupt is considered to be an emergency signal that may be serviced.

Interrupts  What happens when MP is interrupted ?  When the Microprocessor receives an interrupt signal.  Each interrupt will most probably have its own ISR. & Technology 400 . MYcsvtu Notes Rungta College of Engg. it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt.

MYcsvtu Notes Rungta College of Engg.Responding to Interrupts  Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not. & Technology 401 .

& Technology 402 .  Vectored: The address of the subroutine is already known to the Microprocessor  Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor MYcsvtu Notes Rungta College of Engg.Responding to Interrupts  There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored.

it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine.  The „DI‟ instruction is a one byte instruction and is used to Disable the non-maskable interrupts. MYcsvtu Notes Rungta College of Engg. This subroutine is called ISR (Interrupt Service Routine)  The „EI‟ instruction is a one byte instruction and is used to Enable the non-maskable interrupts. & Technology 403 .The 8085 Interrupts  When a device interrupts.

MYcsvtu Notes Rungta College of Engg. & Technology 404 .The 8085 Interrupts  The 8085 has a single Non-Maskable interrupt.  The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop.

& Technology 405 .Interrupts in 8085 Interrupt Save program counter Send out interupt acknowledge Disable interrupts INTA Main routine Go back Go to service routine Get original program counter EI RET Service routine MYcsvtu Notes Rungta College of Engg.

& Technology 406 .Saving the PC in Stack MYcsvtu Notes Rungta College of Engg.

5.  The INTR input is the only non-vectored interrupt. RST 6.  INTR is maskable using the EI/DI instruction pair. RST 6.5 are all automatically vectored. & Technology 407 . RST 7.  RST 5.  RST 5. The INTR input.5 are all maskable.Hardware Interrupts  The 8085 has 5 interrupt inputs.5.5.5. and RST 7.  TRAP is the only non-maskable interrupt in the 8085  TRAP is also automatically vectored  MYcsvtu Notes Rungta College of Engg.

5 RST 7.5 TRAP Maskable Yes Yes Yes Yes No Vectored No Yes Yes Yes Yes MYcsvtu Notes Rungta College of Engg. & Technology 408 .5 RST 6.Interrupts Interrupt name INTR RST 5.

8085 Interrupts TRAP RST7.5 INTR INTA 8085 MYcsvtu Notes Rungta College of Engg. & Technology 409 .5 RST 5.5 RST6.

 The IVT is usually located in memory page 00 (0000H .00FFH).  All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT).  The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives. & Technology 410 . MYcsvtu Notes Rungta College of Engg.Interrupt Vectors and the Vector Table  An interrupt vector is a pointer to where the ISR is stored in memory.

jump to the ISR location MYcsvtu Notes Rungta College of Engg.  Because the RST 7. Microprocessor knows .  Microprocessor goes to 003C location and will get a JMP instruction to the actual ISR address. RST7. a device interrupts the Microprocessor using the RST 7. & Technology 411 .Interrupt Vectors and the Vector Table  Example: Let .5 is knows as Call 003Ch to Microprocessor. in which memory location it has to go using a call instruction to get the ISR address.  The Microprocessor will then.5 interrupt line.5 interrupt is vectored.

& Technology 412 . disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted MYcsvtu Notes Rungta College of Engg. MP completes current instruction. If INTR is high. The 8085 checks for an interrupt during the execution of every instruction.The 8085 Non-Vectored Interrupt Process • • • The interrupt process should be enabled using the EI instruction.

MP saves the memory location of the next instruction on the stack and the program is transferred to „call‟ location (ISR Call) specified by the RST instruction MYcsvtu Notes Rungta College of Engg. & Technology 413 .The 8085 Non-Vectored Interrupt Process • INTA allows the I/O device to send a RST instruction through data bus. • Upon receiving the INTA signal.

& Technology 414 . RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted MYcsvtu Notes Rungta College of Engg.The 8085 Non-Vectored Interrupt Process • • • Microprocessor Performs the ISR. ISR must include the „EI‟ instruction to enable the further interrupt within the program.

The 8085 Non-Vectored Interrupt Process  The 8085 recognizes 8 RESTART instructions:  RST0 . & Technology 415 .  Each of these would send the execution to a predetermined hard-wired memory location: MYcsvtu Notes Rungta College of Engg.RST7.

Hard-wired memory location of Restart Restart Instruction RST0 RST1 RST2 RST3 RST4 RST5 RST6 RST7 MYcsvtu Notes Equivalent to CALL 0000H CALL 0008H CALL 0010H CALL 0018H CALL 0020H CALL 0028H CALL 0030H CALL 0038H 416 Rungta College of Engg. & Technology .

MYcsvtu Notes Rungta College of Engg. from the interrupting device.  While INTA is active the microprocessor reads the data lines expecting to receive. & Technology 417 .Restart Sequence  The restart sequence is made up of three machine cycles  In the 1st machine cycle:  The microprocessor sends the INTA signal. the opcode for the specific RST instruction.

 Then the microprocessor jumps to the address associated with the specified RST instruction. & Technology 418 . MYcsvtu Notes Rungta College of Engg.Restart Sequence  In the 2nd and 3rd machine cycles:  the 16-bit address of the next instruction is saved on the stack.

Timing Diagram of Restart Sequence MYcsvtu Notes Rungta College of Engg. & Technology 419 .

 So. & Technology 420 .Hardware Generation of RST Op code  How does the external device produce the op code for the appropriate RST instruction?  The op code is simply a collection of bits. the device needs to set the bits of the data bus to the appropriate value in response to an INTA signal. MYcsvtu Notes Rungta College of Engg.

Hardware Generation of RST Op code MYcsvtu Notes Rungta College of Engg. & Technology 421 .

sending the Microprocessor the RST 5 instruction. (the 1st machine cycle of the RST operation):  The Microprocessor activates the INTA signal.Hardware Generation of RST Op code  During the interrupt acknowledge machine cycle.  This signal will enable the Tri-state buffers. & Technology 422 .  The RST 5 instruction is exactly equivalent to CALL 0028H MYcsvtu Notes Rungta College of Engg. which will place the value EFH on the data bus.  Therefore.

Issues in Implementing INTR Interrupts  How long must INTR remain high? The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction.  MYcsvtu Notes Rungta College of Engg.  The longest instruction for the 8085 is the conditional CALL instruction which requires 18 T-states. & Technology 423 .  The INTR must remain active long enough to allow for the longest instruction.

& Technology 424 .5 T- states.5 ≈ 5.Issues in Implementing INTR Interrupts  Therefore. MYcsvtu Notes Rungta College of Engg.  If f= 3MHZ then T=1/f and so.8 micro seconds]. the INTR must remain active for 17. INTR must remain active for [ (1/3MHZ) * 17.

& Technology 425 .  MYcsvtu Notes Rungta College of Engg. Otherwise.Issues in Implementing INTR Interrupts  How long can the INTR remain high? The INTR line must be deactivated before the EI is executed.  Once the microprocessor starts to respond to an INTR interrupt. Therefore. the microprocessor will be interrupted again. INTR should be turned off as soon as the INTA signal is received. INTA becomes active (=0).

MYcsvtu Notes Rungta College of Engg.  Therefore.  We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority.Multiple Interrupts & Priorities  How do we allow multiple devices to interrupt using the INTR line?  The microprocessor can only respond to one signal on INTR at a time. & Technology 426 . we must allow the signal from only one of the devices to reach the microprocessor.

 The inputs are assigned increasing priorities according to the increasing index of the input.Multiple Interrupts & Priorities using Priority Encoder  The solution is to use a circuit called the priority encoder (74LS148). & Technology 427 .  This circuit has 8 inputs and 3 outputs. MYcsvtu Notes Rungta College of Engg.  The 3 outputs carry the index of the highest priority active input.  Input 7 has highest priority and input 0 has the lowest.

D4 and D3 of the op codes change in a binary sequence from RST 7 down to RST 0.  The other bits are always 1.  Bit D5. & Technology 428 . MYcsvtu Notes Rungta College of Engg.Multiple Interrupts & Priorities using Priority Encoder  Note that the op codes for the different RST instructions follow a set pattern.  The one draw back to this scheme is that the only way to change the priority of the devices connected to the 74366 is to reconnect the hardware.  This allows the code generated by the 74366 to be used directly to choose the appropriate RST instruction.

& Technology 429 .Multiple Interrupts & Priorities using Priority Encoder MYcsvtu Notes Rungta College of Engg.

5.The 8085 Maskable/Vectored Interrupts  The 8085 has 4 Masked/Vectored interrupt inputs.5 003CH Rungta College of Engg. RST 7.  They are automatically vectored according to the following table:  Interrupt Vector RST 5.5  They are all maskable. & Technology 430 MYcsvtu Notes . RST 6.5 0034H RST 7.5 002CH RST 6.5.  RST 5.

MYcsvtu Notes Rungta College of Engg.The 8085 Maskable/Vectored Interrupts  The vectors for these interrupt fall in between the vectors for the RST instructions.  That‟s why they have names like RST 5.5 (RST 5 and a half). & Technology 431 .

5. & Technology 432 .  Through individual mask flip flops that control the availability of the individual interrupts.5  These three interrupts are masked at two levels: Through the Interrupt Enable flip flop and the EI/DI instructions.5 and RST 7. RST 6.  The Interrupt Enable flip flop controls the whole maskable interrupt process.  These flip flops control the interrupts individually.Masking RST 5.  MYcsvtu Notes Rungta College of Engg.

& Technology 433 .Interrupt Structure MYcsvtu Notes Rungta College of Engg.

and reset the interrupt flip flop. & Technology 434 . If there is an interrupt.The 8085 Maskable/Vectored Interrupt Process • • • The interrupt process should be enabled using the EI instruction. the microprocessor will complete the executing instruction. The 8085 checks for an interrupt during the execution of every instruction. MYcsvtu Notes Rungta College of Engg. and if the interrupt is enabled using the interrupt mask.

The microprocessor jumps to the specific service routine.The 8085 Maskable/Vectored Interrupt Process • • • • The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table. & Technology 435 MYcsvtu Notes . The service routine must include the instruction EI to re-enable the interrupt process. Rungta College of Engg. it saves the address of the next instruction on the stack. When the microprocessor executes the call instruction.

MYcsvtu Notes Rungta College of Engg. the RET instruction returns the execution to where the program was interrupted. & Technology 436 .Manipulating the Masks  At the end of the service routine.  The Interrupt Enable flip flop is manipulated using the EI/DI instructions.

 This instruction takes the bit pattern in the Accumulator and applies it to the interrupt mask enabling and disabling the specific interrupts. MYcsvtu Notes Rungta College of Engg. RST 6.5.5 are manipulated using the SIM instruction.5 and RST 7.Manipulating the Masks  The individual masks for RST 5. & Technology 437 .

5 Serial Data Out Enable Serial Data 0 .5 M5. & Technology 438 .Available RST6.5 Mask 1 .5 MSE M7.Set the masks according to bits 0-2 } Not Used Force RST7.5 Mask Mask Set Enable 0 .5 Mask 0 .Masked RST7.5 Flip Flop to reset MYcsvtu Notes Rungta College of Engg.Ignore bits 0-2 1 .Ignore bit 7 1 .5 M6.Send bit 7 to SOD pin RST5.How SIM Interprets the Accumulator 7 6 5 4 3 2 1 0 SDO SDE XXX R7.

5.5  Bit 2 is the mask for RST 7. the interrupt is masked. If the mask bit is 0.  MYcsvtu Notes Rungta College of Engg.SIM and the Interrupt Mask  Bit 0 is the mask for RST 5.5  Bit 1 is the mask for RST 6. the interrupt is available.  If the mask bit is 1. & Technology 439 .

The SIM instruction is used for multiple purposes and not only for setting interrupt masks. & Technology 440 . bit 3 is necessary to tell the microprocessor whether or not the interrupt masks should be modified MYcsvtu Notes Rungta College of Engg.  It is also used to control functionality such as Serial Data Transmission.  If it is set to 1.SIM and the Interrupt Mask  Bit 3 (Mask Set Enable . the new setting are applied.MSE) is an enable for setting the mask.  Therefore.  If it is set to 0 the mask is ignored and the old settings remain.

5 is unmasked.  If a signal on RST7. & Technology 441 . a flip flop will remember the signal.SIM and the Interrupt Mask  The RST 7. the microprocessor will be interrupted even if the device has removed the interrupt signal.5 interrupt is the only 8085 interrupt that has memory.  This flip flop will be automatically reset when the microprocessor responds to an RST 7.  When RST7. MYcsvtu Notes Rungta College of Engg.5 arrives while it is masked.5 interrupt.

 Bit 5 is not used by the SIM instruction MYcsvtu Notes Rungta College of Engg.5 memory even if the microprocessor did not respond to it. & Technology 442 .SIM and the Interrupt Mask  Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.

and RST7.5 is enabled. & Technology 443 . RST6.5 is enabled.Using the SIM Instruction to Modify the Interrupt Masks  Example: Set the interrupt masks so that RST5.5 is masked. MYcsvtu Notes Rungta College of Engg.

Disable 6.Enable 5. & Technology 444 .Enable 7.Don‟t use serial data bit 6 = 0  .5 bit 0 = 0  .Allow setting the masks bit 3 = 1  .5 bit 1 = 1  .5 bit 2 = 0  .Using the SIM Instruction to Modify the Interrupt Masks First.Serial data is ignored bit 7 = 0 MYcsvtu Notes Rungta College of Engg. determine the contents of the accumulator  .Bit 5 is not used bit 5 = 0  .Don‟t reset the flip flop bit 4 = 0  .

5  SIM . Prepare the mask to enable RST 7. Apply the settings RST masks MYcsvtu Notes Rungta College of Engg. 0A .5. & Technology 445 .Using the SIM Instruction to Modify the Interrupt Masks Contents of accumulator are: 0AH  EI . Enable interrupts including INTR  MVI A. and 5. disable 6.5.

a logic 1 is stored in the flip-flop as a “pending” interrupt.5 is positive edge sensitive. & Technology 446 . the line does not have to be high when the microprocessor checks for the interrupt to be recognized.  MYcsvtu Notes Rungta College of Engg.  Since the value has been stored in the flip flop.  The line must go to zero and back to one before a new interrupt is recognized.5 line. When a positive edge appears on the RST7.Triggering Levels  RST 7.

5 and RST 5. MYcsvtu Notes Rungta College of Engg.  The interrupting signal must remain present until the microprocessor checks for interrupts. & Technology 447 .Triggering Levels  RST 6.5 are level sensitive.

5 M5.5 Memory RST 7.5 M 7. RST7.5 RST 6. & Technology Interrupt Enable Flip Flop 448 .5 P5.5 M6.5 P6.5 IE M7.Determining the Current Mask Settings  RIM instruction: Read Interrupt Mask  Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and mask.5 M 6.5 7 6 5 4 3 2 1 0 SDI P7.5 MYcsvtu Notes Rungta College of Engg.5 M 5.5 RST 5.

5 Mask Serial Data In RST7.5 RST5.5 M5.5 Interrupt Pending RST5.5 IE M7.Available 1 .5 Mask RST6.5 P6. & Technology 449 .5 P5.Masked Interrupt Enable Value of the Interrupt Enable Flip Flop MYcsvtu Notes Rungta College of Engg.5 Mask RST7.5 M6.How RIM sets the Accumulator’s different bits 7 6 5 4 3 2 1 0 SDI P7.5 Interrupt Pending RST6.5 Interrupt Pending } 0 .

5 and RST 5.5.  They can be used by a program to read the mask settings in order to modify only the right mask.5  They return the contents of the three mask flip flops. & Technology 450 .The RIM Instruction and the Masks  Bits 0-2 show the current setting of the mask for each of RST 7. RST 6. MYcsvtu Notes Rungta College of Engg.

 It can be used by a program to determine whether or not interrupts are enabled. & Technology 451 .The RIM Instruction and the Masks  Bit 3 shows whether the maskable interrupt process is enabled or not. MYcsvtu Notes Rungta College of Engg.  It returns the contents of the Interrupt Enable Flip Flop.

& Technology 452 .5 and RST6.5.The RIM Instruction and the Masks  Bits 4-6 show whether or not there are pending interrupts on RST 7.5.5 pins. and RST 5.5 memory flip flop.  Bit 6 returns the current value of the RST7.5  Bits 4 and 5 return the current value of the RST5. RST 6. MYcsvtu Notes Rungta College of Engg.

 The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit. & Technology 453 .The RIM Instruction and the Masks  Bit 7 is used for Serial Data Input. MYcsvtu Notes Rungta College of Engg.

 Using the RIM instruction. & Technology 454 . it is possible to can read the status of the interrupt lines and find if there are any pending interrupts. interrupts may occur during an ISR and remain pending. MYcsvtu Notes Rungta College of Engg.Pending Interrupts  Since the 8085 has five interrupt lines.

TRAP  TRAP is the only non-maskable interrupt. & Technology 455 . It does not need to be enabled because it cannot be disabled.  It is edge and level sensitive.  MYcsvtu Notes Rungta College of Engg.  It has the highest priority amongst interrupts.

TRAP It needs to be high and stay high to be recognized. then high again. & Technology 456 .  Once it is recognized. MYcsvtu Notes Rungta College of Engg.   TRAP is usually used for power failure and emergency shutoff. it won‟t be recognized again until it goes low.

The 8085 Interrupts Interrupt Name INTR RST 5.5 Maskable Masking Method DI / EI DI / EI SIM DI / EI SIM Vectored Memory Triggering Method Level Sensitive Level Sensitive Edge Sensitive Level & Edge Sensitive 457 Yes No No Yes Yes No Yes Yes Yes TRAP MYcsvtu Notes No None Yes No Rungta College of Engg.5 RST 7.5 / RST 6. & Technology .

The SIM format will be 7 6 5 4 3 2 1 0 0 0 0 0 MYcsvtu Notes Rungta College of Engg.Interrupt Programs  Enable all interrupts of 8085  Sol. & Technology 0 0 1 0 458 .

08 H  SIM MYcsvtu Notes Rungta College of Engg. & Technology 459 .Interrupt Programs  Program  EI  MVI A.

Interrupt Programs  Assume microprocessor is completing an RST 7.5 interrupt request. If it is pending enable RST 6. otherwise return to main program MYcsvtu Notes Rungta College of Engg.5 is pending . & Technology 460 . check to see if RST 6.5 without affecting any other interrupts.

A ANI 20H JNZ NEXT EI RET NEXT MOV A.B ANI 0D H ORI 08 H SIM RET Rungta College of Engg. & Technology 461 MYcsvtu Notes .Interrupt Programs             Program RIM MOV B.

V ARCHITECTURE OF PERIPHERAL INTERFACING DEVICES MYcsvtu Notes Rungta College of Engg.UNIT. & Technology 462 .

MYcsvtu Notes Rungta College of Engg.  A few are listed here.Support devices for the 8085  At the time of introduction of the 8085. several additional support devices were introduced to enable the „85 to be adapted to a great variety of system organizations. & Technology 463 .

Support devices for the 8085  8155-RAM+ 3 I/O Ports+Timer  8251-Communication Controller  8253-Programmable Interval Timer  8254-Programmable Interval Timer  8255-Programmable Peripheral Interface  8257-DMA Controller  8259-Programmable Interrupt Controller  8279-KeyBoard/Display Controller  8755-EPROM+2 I/O Ports MYcsvtu Notes Rungta College of Engg. & Technology 464 .

8355/8755 Multifunction Device (memory +IO)  Features  2kbytes ROM(8355) / EPROM(8755)  Two bidirectional 8 bit I/O ports  Each port line individually programmable for I or O  Internal AD demux using ALE  Generates ready signal  Separate control lines for I/O section MYcsvtu Notes Rungta College of Engg. & Technology 465 .

8355/8755  Vdd=25V for programming EPROM  Vcc=5V. & Technology 466 . Vss=0V MYcsvtu Notes Rungta College of Engg.Block diagram.

 ROM8755UV EPROM 8355 mask ROM. MYcsvtu Notes Rungta College of Engg.8355/8755  8085ROMI/OLSI 8355 for the 8085 circuit has been designed around ROM and parallel I / O ports are integrated in the LSI. 80858088  Address and data bus interfaces directly by the state because they can more 8085 to 8088 can also be applied. 8755 is a builtin UV EPROM. & Technology 467 .

8355/8755  Port and DDR addresses A1 A0 Port/DD R 0 0 1 1 MYcsvtu Notes 0 1 0 1 Port A Port B DDR A DDR B Rungta College of Engg. & Technology 468 .

8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)  The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication.  This device also receives serial data from the outside and transmits parallel data to the CPU after conversion. the 8251 receives parallel data from the CPU and transmits serial data after conversion. MYcsvtu Notes Rungta College of Engg.  As a peripheral device of a microcomputer system. & Technology 469 .

& Technology 470 .Block diagram of the 8251 USART MYcsvtu Notes Rungta College of Engg.

8251 USART  The 8251 functional configuration is programmed by software. & Technology 471 .  Operation between the 8251 and a CPU is executed by program control. MYcsvtu Notes Rungta College of Engg.  Table shows the operation between a CPU and the device.

& Technology 472 . Command (setting of operation) MYcsvtu Notes Rungta College of Engg. Mode instruction (setting of function)  2.8251 USART  Control Words  There are two types of control word.  1.

8251 USART
 Mode Instruction

 Mode instruction is used for setting the function of the

8251. Mode instruction will be in "wait for write" at either internal reset or external reset. That is, the writing of a control word after resetting will be recognized as a "mode instruction."  Items set by mode instruction are as follows:  • Synchronous/asynchronous mode  • Stop bit length (asynchronous mode)  • Character length
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473

8251 USART
 Parity bit

 Baud rate factor (asynchronous mode)
 Internal/external synchronization (synchronous mode)  Number of synchronous characters (Synchronous

mode)

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8251 USART
 The bit configuration of mode instruction is shown in

Figures.  In the case of synchronous mode, it is necessary to write one-or two byte sync characters.  If sync characters were written, a function will be set because the writing of sync characters constitutes part of mode instruction.

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8251 USART-Bit configuration of mode instruction (Asynchronous)

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8251 USART-Bit configuration of mode instruction (Synchronous)

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8251 USART
 Command  Command is used for setting the operation of the 8251.

It is possible to write a command whenever necessary after writing a mode instruction and sync characters.

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8251 USART
       

Items to be set by command are as follows: Transmit Enable/Disable Receive Enable/Disable DTR, RTS Output of data. Resetting of error flag. Sending to break characters Internal resetting Hunt mode (synchronous mode)

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8251 USART-Bit configuration of command word

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8251 USART
 Status Word  It is possible to see the internal status of the 8251 by

reading a status word.  The bit configuration of status word is shown in Fig

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8251 USART-Bit configuration of status word

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8251 USART Pin Description
 D 0 to D 7 (l/O terminal)  This is bidirectional data bus which receive control

words and transmits data from the CPU and sends status words and received data to CPU.

 RESET (Input terminal)  A "High" on this input forces the 8251 into "reset

status."  The device waits for the writing of "mode instruction."  The min. reset width is six clock inputs during the operating status of CLK.
MYcsvtu Notes Rungta College of Engg. & Technology 483

8251 USART Pin Description
 CLK (Input terminal)  CLK signal is used to generate internal device timing.

CLK signal is independent of RXC or TXC.  However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode.

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& Technology MYcsvtu Notes 485 .8251 USART Pin Description  WR (Input terminal)  This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251.  RD (Input terminal)  This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251. Rungta College of Engg.

If C/D = high.8251 USART Pin Description  C/D (Input terminal)  This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU. data will be accessed. command word or status word will be accessed. MYcsvtu Notes Rungta College of Engg. If C/D = low. & Technology 486 .

& Technology 487 . only setting CS = High.8251 USART Pin Description  CS (Input terminal)  This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. MYcsvtu Notes Rungta College of Engg.  Note: The device won‟t be in "standby status".

 It is also possible to set the device in "break status" (low level) by a command. & Technology 488 . MYcsvtu Notes Rungta College of Engg.  The device is in "mark status" (high level) after resetting or during a status when transmit is disabled.8251 USART Pin Description  TXD (output terminal)  This is an output terminal for transmitting data from which serial-converted data is sent out.

& Technology 489 .  If the CPU writes a data character.  Note: TXRDY status word indicates that transmit data character is receivable. MYcsvtu Notes Rungta College of Engg. TXRDY will be reset by the leading edge or WR signal. regardless of CTS or command.8251 USART Pin Description  TXRDY (output terminal)  This is an output terminal which indicates that the 8251is ready to accept a transmitted data character.  But the terminal is always at low level if CTS = high or the device was set in "TX disable status" by a command.

 In "synchronous mode. MYcsvtu Notes Rungta College of Engg. if transmit data characters are no longer remaining and sync characters are automatically transmitted." the terminal is at high level. & Technology 490 .  If the CPU writes a data character. TXEMPTY will be reset by the leading edge of WR signal.8251 USART Pin Description  TXEMPTY (Output terminal)  This is an output terminal which indicates that the 8251 has transmitted all the characters and had no data character.

 Then TXD and TXEMPTY will be "High". data written before disable will be sent out.8251 USART Pin Description  Note : As the transmitter is disabled by setting CTS "High" or command. that data is not sent out and TXE will be "High". Even if a data is written after disable.  After the transmitter is enabled. it sent out. MYcsvtu Notes Rungta College of Engg. & Technology 491 .

 In "synchronous mode. 1/16 or 1/64 the TXC.8251 USART Pin Description  TXC (Input terminal)  This is a clock input signal which determines the transfer speed of transmitted data. MYcsvtu Notes Rungta College of Engg." the baud rate will be the same as the frequency of TXC.  In "asynchronous mode".  It can be 1.  The falling edge of TXC sifts the serial data out of the 8251. & Technology 492 . it is possible to select the baud rate factor by mode instruction.

MYcsvtu Notes Rungta College of Engg.  In such a case. an overrun error flag status word will be set. RXRDY will be reset by the leading edge of RD signal.  Unless the CPU reads a data character before the next one is received completely.  If the CPU reads a data character. the preceding data will be lost. & Technology 493 .8251 USART Pin Description  RXRDY (Output terminal)  This is a terminal which indicates that the 8251 contains a character that is ready to READ.

& Technology 494 .  In "synchronous mode.  In "asynchronous mode.8251 USART Pin Description  RXD (input terminal)  This is a terminal which receives serial data. 1/16. MYcsvtu Notes Rungta College of Engg. 1/64 the RXC.  RXC (Input terminal)  This is a clock input signal which determines the transfer speed of received data. It can be 1." it is possible to select the baud rate factor by mode instruction." the baud rate is the same as the frequency of RXC.

8251 USART Pin Description  SYNDET/BD (Input or output terminal)  This is a terminal whose function changes according to mode. the terminal will be reset. MYcsvtu Notes Rungta College of Engg. & Technology 495 . if sync characters are received and synchronized." this terminal is at high level.  In "external synchronous mode. "this is an input terminal.  In "internal synchronous mode.  If a status word is read.

8251 USART Pin Description  A "High" on this input forces the 8251 to start receiving data characters. & Technology 496 . if RXD is at high level. After Reset is active. the terminal will be output at low level.  The terminal will be reset.  In "asynchronous mode. MYcsvtu Notes Rungta College of Engg." this is an output terminal which generates "high level“ output upon the detection of a "break" character if receiver data contains a "lowlevel" space between the stop bits of two continuous characters.

 DTR (Output terminal)  This is an output port for MODEM interface.  The input status of the terminal can be recognized by the CPU reading status words. & Technology 497 .8251 USART Pin Description  DSR (Input terminal)  This is an input port for MODEM interface. MYcsvtu Notes Rungta College of Engg.  It is possible to set the status of DTR by a command.

8251 USART Pin Description  CTS (Input terminal)  This is an input terminal for MODEM interface which is used for controlling a transmit circuit.  RTS (Output terminal)  This is an output port for MODEM interface.  The terminal controls data transmission if the device is set in "TX Enable" status by a command.  Data is transmittable if the terminal is at low level.  It is possible to set the status RTS by a command. MYcsvtu Notes Rungta College of Engg. & Technology 498 .

8255 Programmable Peripheral Interface  The Intel 8255 (or i8255) Programmable Peripheral Interface chip is a peripheral chip originally developed for the Intel 8085 microprocessor.  It was later made (cloned) by many other manufacturers.  This chip was later also used with the Intel 8086 and its descendants. known as the MCS-85 Family. & Technology 499 . and as such is a member of a large array of such chips. MYcsvtu Notes Rungta College of Engg.

 Other such chips are the 2655 Programmable MYcsvtu Notes Rungta College of Engg.8255 Programmable Peripheral Interface  Are in DIP 40 and PLCC 44 pins encapsulated versions. and is similar to other such chips like the Motorola 6520 PIA (Peripheral Interface Adapter) the MOS Technology 6522 (Versatile Interface adapter) and the MOS Technology CIA (Complex interface Adapter) all developed for the 6502 family. & Technology 500 .  This chip is used to give the CPU access to programmable parallel I/O.

and many others. the Western Design Center WDC 65C21. the 6820 PIO  (Peripheral Input/Output) from the Motorola 6800 family.8255 Programmable Peripheral Interface  Peripheral Interface from the Signetics 2650 family of microprocessors. & Technology  The 8255 are used in home computers as SV-328 and MYcsvtu Notes 501 . but is perhaps most well known for its use in the original IBM-PC's parallel printer port (now largely defunct and replaced by the USB standard. all MSX. an enhanced 6520. and considered a legacy port). Rungta College of Engg.

MYcsvtu Notes Rungta College of Engg.8255 Programmable Peripheral Interface  However. and is sometimes used together with a micro controller to expand its I/O capabilities. most often the functionality the 8255 offered is now not implemented with the 8255 chip itself anymore. but is embedded in a larger VLSI chip as a sub function.  The 8255 chip itself is still made. & Technology 502 .

8255 PPI. & Technology 503 .Pin diagram MYcsvtu Notes Rungta College of Engg.

each can be set independently for I or O.8255 PPI  Features:  3 8-bit IO ports PA. PB.  Each PC bit can be set/reset individually in BSR mode.1 and PC for mode 0 and for BSR. PB for 0. PC  PA can be set for Modes 0. 2. & Technology 504 .  Modes 1 and 2 are interrupt driven. MYcsvtu Notes Rungta College of Engg. 1.  PC has 2 4-bit parts: PC upper (PCU) and PC lower (PCL).

& Technology 505 .  TTL compatible.  Improved dc driving capability MYcsvtu Notes Rungta College of Engg.8255 PPI  PA and PCU are Group A (GA) and PB and PCL are Group B (GB)  Address/data bus must be externally demux'd.

8255 PPI  Block diagram  MYcsvtu Notes Rungta College of Engg. & Technology 506 .

& Technology 507 . MYcsvtu Notes Rungta College of Engg.8255 PPI  The 8255A is a programmable peripheral interface (PPI) device designed for use in Intel microcomputer systems.  The functional configuration of the 8255A is programmed by the systems software so that normally no external logic is necessary to interface peripheral devices or structures.  Its function is that of a general purposes I/O component to Interface peripheral equipment to the microcomputer system bush.

& Technology 508 .8255 PPI  Data Bus Buffer  This 3-stable bi-directional 8-bit buffer is used to interface the 8255A to the systems data bus. MYcsvtu Notes Rungta College of Engg.  Control words and status information are also transferred through the data bus buffer.  Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU.

issues commands to both of the Control Groups.8255 PPI  Read/Write and Control Logic  The function of this block is to manage all of the Internal and External transfers of both Data and Control or Status words. MYcsvtu Notes Rungta College of Engg.  It accepts inputs from the CPU Address and Control business and in turn. & Technology 509 .

and the CPU.  A “low” on this Input pin enables the 8255A to send the data or status information to the CPU on the data bus. it allows the CPU to “read from the 8255A. & Technology 510 .8255 PPI  (CS) Chip Select  A “low‟ on this input pin enables the communication between the 8255A.  (RD) Read.  In essence. MYcsvtu Notes Rungta College of Engg.

MYcsvtu Notes Rungta College of Engg.  They are normally connected to the least significant bits of the address bus (A0 and A1).  (A0 and A1)  Port Select 0 and Port Select 1.8255 PPI  (WR) Write.  The Input signals.  A “ low” on the input pin enables the CPU to write data or control words into the 8255A. & Technology 511 . in conjunction with the RD and WR Inputs. controls the selection of one of the three ports or the control word registers.

B. & Technology 512 . C) are set to the Input mode MYcsvtu Notes Rungta College of Engg.8255 PPI  (RESET)  Reset  A “high” on this Input clears the control register and all ports (A.

 The control word contains information such as “mode”. bit set”. bit reset”. that Initializes the functional configuration of the 8255A. etc. MYcsvtu Notes Rungta College of Engg. & Technology 513 . the CPU “output” a control word to the 8255A.8255 PPI  Group A and Group B Controls  The functional configuration of each port is programmed by the systems software.  In essence.

receives control words from the internal data bus and issues the proper commands to its associated ports. MYcsvtu Notes Rungta College of Engg.8255 PPI  Each of the Control blocks (Group A and Group B) accepts commands from the Read/Write Control Logic. & Technology 514 .

MYcsvtu Notes Rungta College of Engg. & Technology 515 .  No Read operation of the Control Word Register is allowed.8255 PPI  Control Group A –  Port A and Port C upper (C7 C4)  Control Group B – Port B and Port C lower (C3 C0)  The Control Word Register can only be written into.

8255 PPI  Ports A. MYcsvtu Notes Rungta College of Engg. and C).  All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personally to further enhance the power and flexibility of the 8255A. B. B. and C  The 8255A contains three 8-bit ports (A . & Technology 516 .

 This port can be divided into two 4-bit ports under the mode control.  Port B . MYcsvtu Notes Rungta College of Engg.8255 PPI  Port A. & Technology 517 .  Each 4-bit port contains a 4-bit latch and it can be used for the controls signal outputs and status signal inputs in conjunction with ports A and B.  Port C-One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input).One 8-bit data output latch/buffer and one 8-bit data input buffer.One 8 bit data output latch/buffer and one 8-bit data input latch.

8255A OPERATIONAL DESCRIPTION
 Mode Selection  There are three basic modes of operation that can be

selected by the systems software:  Mode 0 – Basic Input/Output  Mode 1 – Strobed Input/Output  Mode 2 – Bi-Directional Bus

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8255A OPERATIONAL DESCRIPTION
 When the reset Input goes “high” all ports will be set to

the Input mode (i.e., all 24 lines will be in the high Impedance state).  After the reset is removed the 8255A can remain in the input mode with no additional Initialization required.  During the execution of the systems program any of the other modes may be selected using a single output Instruction.  This allows a single 8255A to service a variety of peripheral devices with a simple software maintenance routine.
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8255A OPERATIONAL DESCRIPTION
 The modes for Ports A and Port B can be separately

defined, while Port C is divided into two portions as required by the Port A and Port B definitions.  All of the output registers, including the status flip-flops, will be reset whenever the mode is changed.  Modes may be combined so that their functional definition can be “tailored” to almost any I/O stricture.  For instance; Group B can be programmed in Mode 0 to monitor simple switch closing or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interruptdriven basis.
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8255A OPERATIONAL DESCRIPTION

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8255A OPERATIONAL DESCRIPTION

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8255A OPERATIONAL DESCRIPTION
 The Mode definitions and possible mode combinations

may seem confusing at first but after a cursory review of the complete device operation a simple , logical I/O approach will surface.  The design of the 8255A has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no use of the available pints.
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8255A OPERATIONAL DESCRIPTION
 Single Bit Set/Reset Feature

 Any of the eight bits of Port C can be Set or Reset using

a single OUT put Instruction.  This feature reduces software requirements in Controlbased applications.  When Port C is being used as status/control for Port A or B.These Bits can be set or reset by using the Bit set/reset operation just as if they were data output port.

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8255A OPERATIONAL DESCRIPTION

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8255A OPERATIONAL DESCRIPTION
 Interrupt Control Functions  When the 8255A is programmed to operate in mode 1

or mode 2, control signals are provided that can used as interrupt request input to the CPU.  The interrupt request signal generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C.  This function allows the Programmer to disallow or allow a specific I/O device to interrupt the CPU without affecting any other device in the interrupt structure.
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8255A OPERATIONAL DESCRIPTION
 INTE flip-flop definition

 (BIT-SET) – INTE is SET – Interrupt enable
 (BIT-RESET) – INTE is RESET – Interrupt disable  Note: All Mask flip-flops are automatically reset during

mode selection and device reset.

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8255A Operating Modes
 Operating Modes  Mode 0 (Basic Input/Output).  This functional configuration provides simple input

operations for each of the three ports.  No “handshaking” is required data is simply written to or read from a specified port.

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8255A Operating Modes
 Basic Functional Definitions:

 Two 8-bit ports and two 4-bit port
 Any port can be input or output.  Outputs are not latched.  Inputs are not latched.  16 different Input/output configurations are not possible

in this Mode.

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 This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “handshaking” signals. & Technology 530 .8255A Operating Modes  MODE 1 (Strobed Input/Output). In mode 1. MYcsvtu Notes Rungta College of Engg. port A and Port B use the lines on port C to generate or accept these “handshaking” signals.

8255A Operating Modes  Basic Functional Definitions:  Two groups (Group A and Group B)  Each group contains one 8-bit data port and one 4-bit control/data port  The 8-bit data port can be either Inputs or output Both inputs and outputs are latched. & Technology 531 . MYcsvtu Notes Rungta College of Engg.  The 4-bit port is used for control and status of the 8-bit data port.

 IBF (Input Buffer Full F/F)  A “high” on this output indicates that the data has been loaded into the input latch. MYcsvtu Notes Rungta College of Engg.  IBF is set by STB input being low and is reset by the rising edge of the RD input.8255A Operating Modes  Input Control Signal Definition  STB (Strobe Input).  A “ low “ on the input loads data into the input latch.  In essence. & Technology 532 . an acknowledgement.

& Technology 533 . INTR is set by the STB is a “one”.  INTE A Controlled by bit set/reset of PC4  INTE B Controlled by set/reset PC2 MYcsvtu Notes Rungta College of Engg. IBF is a “one “ and INTE is “one “.  It is reset by the falling edge of RD.8255A Operating Modes  INTR (Interrupt Request)  A “high” on this output can be used to interrupt the CPU when an input device is requesting service.  This procedure allows an input device to request service from the CPU by simply strobing its data into port.

8255A Operating Modes MYcsvtu Notes Rungta College of Engg. & Technology 534 .

 The OBF output will go “low” to indicate that the CPU has written data out to the specified port. & Technology 535 . ACK (Acknowledge Input).  A “low” on this input informs the 8255A that the data from port A or port B has been accepted. MYcsvtu Notes Rungta College of Engg.8255A Operating Modes  Output Control Signal Definition  OBF (Output Buffer Full F/F).  The OBF F/F will be set by rising edge of the WR input being low.

INTR (Interrupt Request). MYcsvtu Notes Rungta College of Engg.  INTE A .Controlled by bit set/reset of PC6. & Technology 536 .  It is reset by the falling edge of WR.8255A Operating Modes  In essence.Controlled by bit set/reset of PC2.  INTE B . INTR is set when ACK is a “one”. a response from the peripheral device indicating that it has received the data output by CPU.  A “high” on the output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. and INTE is a “one”. OBF is a “one”.

& Technology 537 .8255A Operating Modes MYcsvtu Notes Rungta College of Engg.

& Technology 538 .8255A Operating Modes  Combination of MODE 1 Port A and B can be Individually defined as Input or output in Mode 1 to support a wide variety of strobed I/O application. MYcsvtu Notes Rungta College of Engg.

& Technology 539 . MYcsvtu Notes Rungta College of Engg.  Interrupt generation and enable/disable functions are also available.  “Handshaking” signals are provided to maintain proper bus flow discipline in a similar manner to MODE.1.  This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bi-directional bus I/O).8255A Operating Modes  Mode 2 (Strobed Bidirectional Bus I/O).

bi-directional bus port (Port A). & Technology 540 .  The 5-bit control port (Port C) is used for control and status for the 8-bit.8255A Operating Modes  Basic Functional Definitions:  Used in Group A only.  Both Inputs and Outputs are latched.  One 8-bit. MYcsvtu Notes Rungta College of Engg. bi-directional bus Port (Port A) and a 5-bit control Port (Port C).

& Technology 541 .  A high on this output can be used to interrupt the CPU for both input or output operations. MYcsvtu Notes Rungta College of Engg.8255A Operating Modes  Bi-directional Bus I/O Control Signal Definition  INTR (Interrupt Request).

 Controlled by bit set/reset of PC6 MYcsvtu Notes Rungta College of Engg.8255A Operating Modes  Output Operations  OBF (Output Buffer Full). INTE 1 (The INTE Flip-Flop Associated with OBF). ACK (Acknowledge). the output buffer will be in the high impedance state.  The OBF output will go “low” to indicate that the CPU has written data out to port A. & Technology 542 .  A “low” on this input enables the tri-state output buffer of port A to send out the data.  Otherwise.

 INTE 2 (The INTE Flip-Flop Associated with IBF).8255A Operating Modes Input Operations STB (Strobe Interrupt) STB (Strobed Input). IBF (Input Buffer Full F/F).      MYcsvtu Notes Rungta College of Engg. A “low” on this input loads data into the input latch. & Technology 543 .  Controlled by bit set/reset of PC4. A “high” on this output indicates that data has been loaded into the input latch.

8255A Operating Modes A1 0 0 1 A0 0 1 0 Select PA PB PC 1 MYcsvtu Notes 1 CONTROL REGISTER Rungta College of Engg. & Technology 544 .

R=0) 545 0(0=B X SR) MYcsvtu Notes Rungta College of Engg. One bit is S/R at a time.8255A Operating Modes  BSR mode  Bit set/reset. applicable to PC only.  Control word: D7 D6 D5 X D4 X D3 B2 D2 B1 D1 B0 D0 S/R( S=1. & Technology .

8255A Operating Modes  I/O mode D7 1 (1=I/O) D6 D5 D4 PA D3 PCU D2 GB mode select D1 PB D0 PCL GA mode select MYcsvtu Notes Rungta College of Engg. & Technology 546 .

D0(PCL): 1=input  0=output 1=mode1 0=output MYcsvtu Notes Rungta College of Engg. D5: GA mode select: 00 = mode0  01 = mode1  1X = mode2  D4(PA). D3(PCU): 1=input  D2: GB mode select: 0=mode0  D1(PB).8255A Operating Modes  D6. & Technology 547 .

PB. Plain I/O.  Two 4 bit ports PCU and PCL. Outputs latched. inputs buffered.  Two 8 bit ports PA.  Mode 1  (Input and output data are latched) MYcsvtu Notes Rungta College of Engg.8255A Operating Modes  Mode 0: No interrupts. & Technology 548 .

& Technology 549 .8255A Operating Modes  PC bits in input mode: D7 PC7 D6 PC6 D5 IBF-A D4 INTE-A / STB-Abar D3 INTR-A D2 INTE-B / STB-Bbar D1 IBF-B D0 INTR-B PC BITS IN OUTPUT MODE OBF-Abar INTE-A / ACK-Abar PC5 PC4 INTR-A INTE-B / ACK-Bbar OBF-Bbar INTR-B MYcsvtu Notes Rungta College of Engg.

PC2. STB-bar is external connection.  INTE is internal connection. PC4 pin to external strobe). MYcsvtu Notes Rungta College of Engg. & Technology 550 .8255A Operating Modes  Input mode:  D4. D2: Set/Reset INTE using BSR. STB-bar input is connected to external peripheral's strobe output (i.e.

PC2.8255A Operating Modes  Output mode:  D6.  INTE is internal connection. & Technology 551 . ACK-bar is external connection. D2: Set/Reset INTE using BSR.e. PC6 pin to external ack). MYcsvtu Notes Rungta College of Engg. ACK-bar input is connected to external peripheral's acknowledge output (i.

8255A Operating Modes  Mode 2  Only for PA  Status: D7 D6 D5 D4 D3 D2 D1 D0 OBF. & Technology X X 552 .INTE IBF-A INTE INTR X A-bar 1(O/P 2(I/P) -A )/ / ACKSTBAA-Bar BAR MYcsvtu Notes Rungta College of Engg.

Programmable Keyboard/Display Interface 8279  A programmable keyboard and display interfacing chip.   Keyboard has a built-in FIFO 8 character buffer.  The display is controlled from an internal 16x8 RAM that stores the coded display information. MYcsvtu Notes Rungta College of Engg.  Controls up to a 16-digit numerical display. Scans and encodes up to a 64-key keyboard. & Technology 553 .

PIN DIAGRAM OF 8279 MYcsvtu Notes Rungta College of Engg. & Technology 554 .

reading the keyboard. MYcsvtu Notes Rungta College of Engg.  BD: Output that blanks the displays.  CS: Chip select that enables programming.  CN/ST: Control/strobe.  CLK: Used internally for timing. etc.  DB7-DB0: Consists of bidirectional pins that connect to data bus on micro.Pin out Definition of 8279  A0: Selects data (0) or control/status (1) for reads and writes between micro and 8279. connected to the control key on the keyboard. Max is 3 MHz. & Technology 555 .

MYcsvtu Notes Rungta College of Engg.Pin out Definition of 8279  IRQ: Interrupt request. & Technology 556 . becomes 1 when a key is pressed. reads data/status registers.  OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant nibble of display.  RESET: Connects to system RESET. data is available.  RD(WR): Connects to micro's IORC or RD signal.

MYcsvtu Notes Rungta College of Engg.  SL3-SL0: Scan line outputs scan both the keyboard and displays. & Technology 557 .  Shift: Shift connects to Shift key on keyboard.Pin out Definition of 8279  RL7-RL0: Return lines are inputs used to sense key depression in the keyboard matrix.

& Technology 558 .Keyboard Interface of 8279 MYcsvtu Notes Rungta College of Engg.

no need for external resistor pull-ups.  The 74LS138 drives 0's on one line at a time.Keyboard Interface of 8279  The keyboard matrix can be any size from 2x2 to 8x8. & Technology 559 .  Pins SL2-SL0 sequentially scan each column through a counting operation.  RL pins incorporate internal pull-ups.  The 8279 scans RL pins synchronously with the scan. MYcsvtu Notes Rungta College of Engg.

sets scan and debounce times. 560  001 Clock  010 Read MYcsvtu Notes Rungta College of Engg. & Technology . type of key scan Programs internal clk.Keyboard Interface of 8279  D7 D6 D5  000 Function Mode set Purpose Selects the number of display positions. FIFO Selects type of FIFO read and address of the read.

write inhibit Allows halfbytes to be blanked. Clears the display or FIFO Clears the IRQ signal to microprocessor 561 MYcsvtu Notes Rungta College of Engg.Keyboard Interface of 8279  D7 D6 D5  011   100  101  110  111 Function Read Display Write Display Display Clear End interrupt Purpose Selects type of display read and address of the read. Selects type of write and address of the write. & Technology .

& Technology 562 .Keyboard Interface of 8279  First three bits given below select one of 8 control registers (opcode).  DD field selects either:  8.  000DDMMM  Mode set: Opcode 000.  MMM sets keyboard mode.or 16-digit display  Whether new data are entered to the rightmost or leftmost display position MYcsvtu Notes Rungta College of Engg.  DD sets displays mode.

& Technology 563 .Keyboard Interface of 8279  DD  00  01  10  11 Function 8-digit display with left entry 16-digit display with left entry 8-digit display with right entry 16-digit display with right entry MYcsvtu Notes Rungta College of Engg.

encoded display scan Strobed keyboard. & Technology 564 .Keyboard Interface of 8279 MMM field:  DD Function   000  001  010  011  100  110  111 MYcsvtu Notes Encoded keyboard with 2-key lockout Decoded keyboard with 2-key lockout Encoded keyboard with N-key rollover Decoded keyboard with N-key rollover Encoded sensor matrix101Decoded sensor matrix Strobed keyboard. decoded display scan Rungta College of Engg.

 Strobed: An active high pulse on the CN/ST input pin strobes data from the RL pins into an internal FIFO for reading by micro later. 1101.Keyboard Interface of 8279 Encoded: Sl outputs are active-high. follow binary bit pattern 0-7 or 0-15. 1011.  Pattern output: 1110.   MYcsvtu Notes Rungta College of Engg.  Decoded: SL outputs are active-low (only one low at any time). 0111. & Technology 565 .

Keyboard Interface of 8279  2-key lockout/N-key rollover: Prevents 2 keys from being recognized if pressed simultaneously/Accepts all keys pressed from 1st to last. & Technology 566 . MYcsvtu Notes Rungta College of Engg.

Keyboard Interface of 8279  001PPPPP The clock command word programs the internal clock driver.  MYcsvtu Notes Rungta College of Engg.  The code PPPPP divides the clock input pin (CLK) to achieve the desired operating frequency.  Z selects auto-increment for the address. e.   010Z0AAA The read FIFO control word selects the address (AAA) of a keystroke from the FIFO buffer (000 to 111).g. 100KHz requires 01010 for a 1 MHz CLK input. & Technology 567 .

 100ZAAAA  Selects write address -.Z selects auto-increment so subsequent writes go to subsequent display positions.Keyboard Interface of 8279  011ZAAAA  The display read control word selects the read address of one of the display RAM positions for reading through the data port. & Technology 568 MYcsvtu Notes . Rungta College of Engg.

 MYcsvtu Notes Rungta College of Engg.Keyboard Interface of 8279  1010WWBB The display write inhibit control word inhibits writing to either the leftmost 4 bits of the display (left W) or rightmost 4 bits.  BB works similarly except that they blank (turn off) half of the output pins. & Technology 569 .

Keyboard Interface of 8279  1100CCFA The clear control word clears the display. & Technology 570 . FIFO or both.  If CC is 10. all display RAM locations become 00000000. --> 00100000. and sets address pointer to 000.  If CC are 00 or 01.  1110E000 -End of Interrupt control word is issued to clear IRQ pin in sensor matrix mode.  MYcsvtu Notes Rungta College of Engg. if CC is 11.  Bit F clears FIFO and the display RAM status. --> 11111111.

MYcsvtu Notes Rungta College of Engg. PPPPP is programmed to 30 or 11110.0 MHz drives CLK input. If 3.  Program the FIFO. external decoder used to drive matrix.  Keyboard type is programmed next. & Technology 571 .Keyboard Interface of 8279  Clock must be programmed first.  The previous example illustrates an encoded keyboard.

 To determine if a character has been typed.Keyboard Interface of 8279  Once done. the contents of the FIFO status word is copied into register AL: MYcsvtu Notes Rungta College of Engg. a procedure is needed to read data from the keyboard. the FIFO status register is checked. & Technology 572 .  When this control port is addressed by the IN instruction.

Keyboard Interface of 8279 MYcsvtu Notes Rungta College of Engg. & Technology 573 .

Keyboard Interface of 8279  Code given in text for reading keyboard.  Data returned from 8279 contains raw data that need to be translated to ASCII: MYcsvtu Notes Rungta College of Engg. & Technology 574 .

 The CT and SH indicate whether the control or shift keys were pressed. & Technology 575 .Keyboard Interface of 8279 Row and column number are given the rightmost 6 bits (scan/return).  MYcsvtu Notes Rungta College of Engg.  This can be converted to ASCII using the XLAT instruction with an ASCII code lookup table.  The Strobed Keyboard code is just the state of the RLx bits at the time a 1 was `strobed' on the strobe input pin.

Six Digit Display Interface of 8279 MYcsvtu Notes Rungta College of Engg. & Technology 576 .

& Technology 577 .  Used for controlling real-time events such as real-time clock.  Each capable in of counting in binary or BCD with a maximum frequency of 10MHz. and motor speed and direction control.Programmable Interval Timer: 8254/8253  Three independent 16-bit programmable counters (timers). MYcsvtu Notes Rungta College of Engg. events counter.

 Programmed with 15us on the PC/XT.  Interrupts the micro at interrupt vector 8 for a clock tick.Programmable Interval Timer: 8254/8253  Usually decoded at port address 40H-43H and has following functions:  Generates a basic timer interrupt that occurs at approximately 18.  Provides a timing source to the internal speaker and other devices MYcsvtu Notes Rungta College of Engg. & Technology 578 .2Hz.  Causes DRAM memory system to be refreshed.

& Technology 579 .8253/54 Functional Description MYcsvtu Notes Rungta College of Engg.

& Technology 580 . A0:  The address inputs select one of the four internal registers with the 8254 as follows: MYcsvtu Notes Rungta College of Engg.8253/54 Pin Definitions  A1.

 It is often connected to the PCLK signal from the bus controller.8253/54 Pin Definitions  CLK: The clock input is the timing source for each of the internal counters.  G: The gate input controls the operation of the counter in some modes.  CS: Chip Select enables the 8254 for programming. MYcsvtu Notes Rungta College of Engg. & Technology 581 . and reading and writing.

8253/54 Pin Definitions  OUT: A counter output is where the wave-form generated by the timer is available. & Technology 582 .  RD/WR: Read/Write causes data to be read/written from the 8254 and often connects to the IORC/IOWC. MYcsvtu Notes Rungta College of Engg.

8253/54 Programming  Each counter is individually programmed by writing a control word. followed by the initial count. binary or BCD count and type of operation (read/write MYcsvtu Notes Rungta College of Engg. & Technology 583 .  The control word allows the programmer to select the counter. model of operation.

& Technology 584 .8253/54 Programming MYcsvtu Notes Rungta College of Engg.

 Minimum count is 1 all modes except 2 and 3 with minimum count of 2. then the first byte (LSB) stops the count. and the second byte (MSB) starts the counter with the new count. MYcsvtu Notes Rungta College of Engg.  If two bytes are programmed. & Technology 585 .  Each counter has a program control word used to select the way the counter operates.8253/54 Programming  Each counter may be programmed with a count of 1 to FFFFH.

& Technology 586 .8253/54 Modes  There are 6 modes of operation for each counter:  Mode 0: An events counter enabled with G. MYcsvtu Notes Rungta College of Engg.  The output becomes a logic 0 when the control word is written and remains there until N plus the number of programmed counts.

& Technology 587 . The G input triggers the counter to output a 0 pulse for `count' clocks.  MYcsvtu Notes Rungta College of Engg.  Counter reloaded if G is pulsed again.8253/54 Modes  Mode 1: One-shot mode.

& Technology 588 . MYcsvtu Notes Rungta College of Engg.  The separation between pulses is determined by the count.8253/54 Modes  Mode 2: Counter generates a series of pulses 1 clock pulse wide.  The cycle is repeated until reprogrammed or G pin set to 0.

MYcsvtu Notes Rungta College of Engg. & Technology 589 . 50% duty cycle otherwise OUT is high 1 cycle longer.8253/54 Modes  Mode 3: Generates a continuous square-wave with G set to 1.  If count is even.

& Technology 590 .8253/54 Modes  Mode 4: Software triggered one-shot (G must be 1). MYcsvtu Notes Rungta College of Engg.

 G controls similar to Mode 1. MYcsvtu Notes Rungta College of Engg. & Technology 591 .8253/54 Modes  Mode 5:  Hardware triggered one-shot.

8253/54 Program  Explain the 8253 control word format and set up the 8253 as a square wave generator with 1 ms period if the input frequency to the 8253 is 1 MHz MYcsvtu Notes Rungta College of Engg. & Technology 592 .

MYcsvtu Notes Rungta College of Engg.The input frequency is 1 MHz.8253/54 Program  Sol-  Assume counter 0 is used to generate the square wave and the addresses of counter 0 = 10 H and the control register is 13 H  The output period required is 1 ms. so input period = 1 micro secs. & Technology 593 .

BCD counting and square wave generator mode will be as follows  MYcsvtu Notes Rungta College of Engg. & Technology 594 . 16 bit counter.8253/54 Program  Count value = Required period/Input period = 1 ms/ 1 micro secs= (1000)d  The control word format to initialize counter 0.

8253/54 Program 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 1 Select counter 0 BCD counting Mode 3 square wave generator Select counter 0 load lsb first then msb Read load lsb first then msb MYcsvtu Notes Rungta College of Engg. & Technology 595 .

 OUT  MVI A.8253/54 Program  The 8253 initialization program will be as follows-  MVI A. & Technology 596 .  OUT 37H 13 H 00H 10 H 10H 10 H MYcsvtu Notes Rungta College of Engg.  OUT  MVI A.

8155 RAM  256* 8 BIT WORDS  Single +5 volt power supply  Complete static operation  Internal address latch  2 programmable 8 bit I/O ports  1 programmable 6 bit I/O ports  Programmable 14 bit binary counter  Multiplexed address and data bus MYcsvtu Notes Rungta College of Engg. & Technology 597 .

 The I/O portion consists of three general purpose I/O ports.General Description of 8155  8155 are RAM chips to be used with 8085  The RAM portion is designed with 2K bit static cell organized as 256 *8  They have a maximum access time 400 ns to permit use with no wait states in 8085 CPU.  8155 has maximum access time of 300ns for use with the 8085. & Technology 598 . MYcsvtu Notes Rungta College of Engg.

MYcsvtu Notes Rungta College of Engg. & Technology 599 . thus allowing the other two ports to operate in handshake mode.  A 14 bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse for the CPU system depending on timer mode.General Description of 8155  One of the three ports can be programmed to be status pins.

& Technology 600 .Block Diagram of 8155 MYcsvtu Notes Rungta College of Engg.

& Technology 601 .Pin Diagram of 8155 MYcsvtu Notes Rungta College of Engg.

 Input high on this line resets the chip and initializes the three I/O ports to input mode. MYcsvtu Notes Rungta College of Engg. & Technology 602 .  The width of reset pin should typically be 600ns.Pin Description of 8155  Reset (I)  The reset signal is a pulse provided by 8085 to initialize the system.

 The address can be either for the memory section or the I/O section depending on the polarity of IO/M(bar) signal MYcsvtu Notes Rungta College of Engg. & Technology 603 .  The 8 bit address is latched into the address latch on the falling edge of the ALE.Pin Description of 8155  AD0-AD7(I/O)  These are three address or data lines that interface with the CPU lower 8 bit data/address bus.

& Technology 604 .Pin Description of 8155  The 8 bit data is either written into the chip or read from the chip depending on the status of write and read input signals  CE(bar) (I)  Chip enable  This pin is active low MYcsvtu Notes Rungta College of Engg.

Pin Description of 8155  RD(I)  Input low on this line with the chip enable active enables the AD0-7 buffers. MYcsvtu Notes Rungta College of Engg. & Technology 605 .  Otherwise the content of the selected I/O port will be read to the AD bus.  If IO/M(bar) is low the RAM content will be read out to the AD bus.

& Technology 606 .Pin Description of 8155  WR(I)-  Input low on this line with the chip enable active causes the data on the AD lines to be written to the Ram or I/O ports depending on the polarity of IO/M(bar) MYcsvtu Notes Rungta College of Engg.

& Technology 607 .Pin Description of 8155  ALE(I)  Address latch enable  This control signal latches the address on the AD0-7 lines and the state of the chip enable and IO/M(bar) into the chip at the falling edge of ALE. MYcsvtu Notes Rungta College of Engg.

& Technology 608 .Pin Description of 8155  IO/M (bar) (I)  IO/ memory select  This line selects the memory if low and selects the IO if high  PA0-PA7(I/O)  These 8 lines are general purpose IO lines. MYcsvtu Notes Rungta College of Engg.

 The in out direction is selected by programming the command and status register MYcsvtu Notes Rungta College of Engg.Pin Description of 8155  The in out direction is selected by programming the command and status register  PB0-PB7  These 8 lines are general purpose IO lines. & Technology 609 .

Pin Description of 8155  PC0-PC5(I/O)  These 6 pins can function as either input port . output port or as control signal for Pa and PB. & Technology 610 .  Programming is done through the C/S register  When they are used as control signals they will provide the following MYcsvtu Notes Rungta College of Engg.

& Technology 611 .Pin Description of 8155  PC0-  PC1 PC2 PC3 PC4 PC5- intr (port a interrupt) bf (port a buffer full) strobe (bar)-(port a strobe) intr (port b interrupt) bf (port b buffer full) strobe (bar)-(port b strobe) MYcsvtu Notes Rungta College of Engg.

& Technology 612 .Pin Description of 8155  Timer in (I)  This is the timer input to the control timer  Timer out (O)  this pin is the timer output  this output can be either a square wave or a pulse depending on the timer mode MYcsvtu Notes Rungta College of Engg.

Pin Description of 8155  VCC(I)  +5 volt power supply  VSS  Ground reference MYcsvtu Notes Rungta College of Engg. & Technology 613 .

Programming information  The command register  It consists of 8 latches. one for each bit  Four bits(0-3) define the mode of the ports.  The last two bits are for timer.  The C/S register contents can be altered at any time by using the I/O address xxxxx000 during a write operation MYcsvtu Notes Rungta College of Engg.  Two bits(4-5) enable or disable the interrupts from port C when it acts as control port. & Technology 614 .

 One (6) for the status of the timer.  The status of the timer and IO section can be polled by reading the C/S register. MYcsvtu Notes Rungta College of Engg.Programming information  Status register  It consists of seven latches.  6 bits(0-5) for the status of the port. & Technology 615 . one for each bit.

Timer section  The timer is 14bit counter that counts the timer input pulses. & Technology 616 .  The timer has the IO address xxxxx100 for the lower order byte of the register and the IO address xxxxx101 for the higher order byte of the register MYcsvtu Notes Rungta College of Engg.  It provides a square wave or a pulse when terminal count (TC) is reached.

Timer section  Tp program the timer the count length register is loaded first one byte at a time by selecting the timer addresses.  Bits 0-13 will specify the length of the next count and bits 14-15 will specify the timer output mode. & Technology 617 .  The valve loaded into the count length register can have any value from 2h through 3FFF h in bits 0-13 MYcsvtu Notes Rungta College of Engg.

& Technology 618 .Timer section  There are four modes to choose from-  0.puts out low during the second half of the count  1-square wave  2-single pulse upon TC being reached  3-repetitive single pulse every time TC is readied and automatic reload of counter upon TC being reached un till instructed to stop by a new command loaded into C/S MYcsvtu Notes Rungta College of Engg.

Timer section  Bits 6-7 of the C/S register are used to start and stop the counter  C/S7 C/S6 0 00 11 01 1- Function NOP STOP STOP AFTER TC START MYcsvtu Notes Rungta College of Engg. & Technology 619 .

Timer section  Timer format MYcsvtu Notes Rungta College of Engg. & Technology 620 .

Timer section  M2 and M1 define the timer mode as follows M2 M1 Function  0 0 Puts out low during  0 1  1  1 0 1 second half of the count. Square wave ie the period of the square equals the count length programmed with automatic reload at terminal count Single pulse upon TC being reached Automatic reload ie single pulse every time TC being reached 621 MYcsvtu Notes Rungta College of Engg. & Technology .

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