IMPLEMENTATION OF MAC UNIT USING FPGA

AIM: To implement MAC unit using FPGA. SOFTWARE REQUIRED: Xilinx TOOLS REQUIRED: FPGA kit ALGORITHM: Step 1: Start the program. Step 2: Declare the input variables. Step 3: When x1=1 arithmetic operation. Step 4: When x1=0 logical operation. Step 5: Example:When x1=1,s1=1,s2=1 and s3=1 it gives invalidOutput using conditional operator.Step 6: Example:When x1=0,s1=1,s2=1 and s3=0 it gives 2’sCompliment Output using conditional operator.Similarly for Everyother input values. Step 7: Stop the program. THEORY: In the majority of digital signal processing (DSP) applications thecritical operations usually involve many multiplications and/or accumulations. For real-time signal processing, a high speed and highthroughput Multiplier Accumulator (MAC) is always a key to achieve a high performance digital signal processing system. Inthe last few years, the main consideration of MAC design is to enhance

its speed. This is because; speedand throughput rate is always the concern of digital signal processingsystem. But for the epoch of personal communication, low power designalso becomes another main design consideration. This is because; batteryenergy available for these portable products limits the power consumption of the system. Therefore, the main motivation of this work is to investigatevarious VLSI Design and Implementation ofLow Power MAC Unit withBlock Enabling Technique. PROGRAM: module MAC(clk,rst,a,b,z); input clk,rst; input[2:0] a,b; output z; wire[5:0] w; multiplier U1(.a(a),.b(b),.p(w)); pipo U2(.RIN(w),.clk(clk),.rst(rst),.ROUT(z)); endmodule module multiplier(a,b,p); input[2:0] a,b; output[5:0] p;

output sum.output[5:0] ROUT. and(u[1].b[0]).i[5].cout.l(i[1]).cin(u[6]). or(i[7].l(su[0]).. endmodule module hadd(sum.sum(p[1]).rst.a[2].b[0]).a[2].a[0].sum(su[0]).a[2]. output s.d(i[7]). and(u[5]. wire[1:0] su... hadd h5(.sum(p[2]).sum(i[5]).clk. and(u[7]..m(u[1]).m(u[5]).. and(u[0].m(u[2]).cry(i[6])).ROUT).. and(u[2].e(u[4]).. input clk.s(p[4]).m.m(i[2]).b[2]).sum(su[1]). end end endmodule module fadd(s.l(u[0]). hadd h3(..e..m)..a[0].cry(i[1])). and(u[3]. wire[8:0]i.a[1]. end else begin ROUT<=RIN.cin).cry.a[0].cry(i[2]))..cin.b[1]).a[1]. and(p[0].b[1])..a[1]. fadd f3(.b[0]). hadd h2(. always @(posedge clk or negedge rst) begin if(!rst) begin ROUT<=6'b000000.d.i[4])..s(p[3]).. input d.b[2]).m(su[1]).rst.cry(i[0])). hadd h4(. assign s=(d^e^cin).l(u[3]). and(u[6].d(i[8])..l.cout.l(i[0]). endmodule module pipo(RIN.. hadd h1(. input l. and(u[4]...b[2]).wire[7:0] u.cout(i[8])).. fadd f4(.e(i[6]).cin(u[7]). ...cry. input[5:0] RIN.cry(i[6]))..e. reg[5:0]ROUT.cout(p[5])). assign cout=((d&e)|(e&cin)|(d&cin))..b[1]).

endmodule RESULT: Thus the MAC unit was implemented using FPGA .cry.wire sum. assign cry=(l&m). assign sum=(l^m).

use IEEE. use IEEE. s.ALL. Modelsim. entity ha is Port ( a. Step 7: End the process. . Step 2: Declare the input ports a.STD_LOGIC_UNSIGNED. Step 4:Begin the process using behavioral architecture. end ha.ALL. Step 6: Assign c=a.b: in STD_LOGIC. cin.b. architecture Behavioral of ha is begin s<=a XOR b. Step 3: Declare output ports s. TOOLS REQUIRED:  FPGA kit. use IEEE.DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING FPGA AIM: To implement a combinational circuits using FPGA. b. c<=a AND b. FULL ADDER: Step 1: Start the program. Step 5: assign s and cy value. SOFTWARES REQUIRED:   Xilinx. Step 3: Declare the output ports s. cy.STD_LOGIC_ARITH. c. Step 6: end the process. Step 4: Begin the process using behavioral architecture. b. PROGRAM: HALF ADDER: Library IEEE.Assign s=ab.ALL. Step 5:. Step 2: Declare the input ports a.  ALGORITHM: HALF ADDER: Step 1: Start the program. end Behavioral.STD_LOGIC_1164.c: out STD_LOGIC).

cy<=(a and b)or(b and cin)or(cin and a). .b. use IEEE.STD_LOGIC_ARITH. architecture Behavioral of full is begin s<=a xor b xor cin.cy : out STD_LOGIC). end full. use IEEE.STD_LOGIC_1164. end Behavioral.STD_LOGIC_UNSIGNED. RESULT: Thus the combinational circuit was designed and implementedusing FPGA and its truth table was verified. use IEEE.ALL.ALL.ALL. entity full is Port ( a.FULL ADDER: library IEEE.cin : in STD_LOGIC. s.

comp2. output out.sl1.x1. Step 6: Example:When x1=0. assign arith =s1?(s2?(s3? invalid:comp 2):(s3? comp1:squ)): .invalid. PROGRAM: module a1(a.out).b.DESIGN AND IMPLEMENTATION OF ALU USING FPGA AIM To implement ALU using FPGA. assign sl 1=a>>2.diff. assign sr 1=a<<2. assign or 1=a | b.. wire [3:0] and1. assign out=x1?arith:log.not1. assign not 1=~a.wire [7:0] prod. Step 7: Stopthe program. Step 2: Declare the input variables. wire [4:0] sum. Step 5: Example:When x1=1. wire [3:0] sr1. wire [7:0] out.s3. assign invalid=8’b00000000. wire [7:0] arith.s2=1 and s3=1 it gives invalidOutput using conditional operator. assign sum=a+b.s3. assign and 1=a&b. SOFTWAREREQUIRED:   ALGORITHM: Step 1: Start the program.or1.squ.s1=1.b. assign prod=a*b.s1. Similarly for Everyother input values. assign diff=a-b.s1=1. Step 3: When x1=1 arithmetic operation. wire [3:0] comp1. Xilinx.s2. input s1. input[3:0]a. Step 4: When x1=0 logicaloperation. Modelsim.s2=1 and s3=0 it gives 2’sCompliment Output using conditional operator.x1.s2.log. assign squ=a^b. assign comp 2=~a+8’b00000001. assign comp 1=~a.

. assign log=s1?(s2? invalid:invalid):(s3? invalid:sl1)): (s2? invalid:sl1)):(s2?(s3? sr1:not)(s3? or1:and 1)).(s2?(s3? invalid:prod)(s3? diff:sum)). end module RESULT: Thus the ALU was designed and implemented using FPGA and its output was verified.

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