SEMATECH Symposium June 23, 2011 Tokyo Accelerating the next technology revolution

CMOS Scaling Beyond FinFETs: Nanowires and TFETs

Chris Hobbs, Wei-Yip Loh, Kerem Akarvardar, Paul Kirsch, and Raj Jammy June 22, 2010
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Outline
• • • • Advanced CMOS Scaling Overview Nanowires TFETs Summary

14 June 2011

2

Device scaling options

Id,sat

Vg
14 June 2011 3

Device scaling options Id.sat Vg 14 June 2011 4 .

Ge.sat Vg 14 June 2011 5 .Device scaling options 1 • Very high mobility/high injection velocity • SiGe. InGaAs • Graphene [e ~15000 cm2/V-s at RT] Id.

sat Vg 14 June 2011 6 .Device scaling options 2 1 • Very high mobility/high injection velocity • SiGe. InGaAs • Graphene [e ~15000 cm2/V-s at RT] • Better electrostatic control • Multiple gates + more channel area • FinFETs. nanowire FET Id. Ge.

so drain leaks to source Well Source and drain are much closer… Gate looses control of channel region • Thin Silicon Channel Thin silicon channel with gate on both sides helps maintain channel control.Why are Multi-Gates beneficial? Single Gate Device Gate Source Extension Halo Channel Conventional MOSFET Scaling to improve performance Drain Source Lg Drain Gate can’t control down here. FinFET n ai r Double Gate Device Fin Gate D 4-Gate Device Nanowire Gate D n ai r Source Drain Gates on both sides ur So Si Wafer Surface ce c ur So e 14 June 2011 7 .

Performance and power tradeoff Typical Ion-Ioff for CMOSFETs • Same transistor with specifications tuned for performance or power @ cost. 14 June 2011 8 .

14 June 2011 9 .Al m l Fa at c er e i a Tr ls/ an ar si ch st ite or c t Sc ur a es lin /n g I ov s s el ue pr s o c (n es ee se d s) ne w Performance and power tradeoff Typical Ion-Ioff for CMOSFETs • Same transistor with specifications tuned for performance or power @ cost.

IEDM 2010 2007 2009 • • 2009 2011 2013 2015 Past: Performance improved by scaling device dimensions.MOSFET scaling trends Planar High-K 32nm New materials 22nm? 16nm? Si-Ge Device III-V Device 12nm+ 45nm SEMATECH.9 SEMATECH. Planar CMOS and Beyond: A continuous spectrum of devices. VLSI 2009 (Production) Intel IEDM 2007 (Production) Intel IEDM 2009 IBM. Now: Performance improved by Novel Materials and Architectures. VLSI 2007 SEMATECH. Doris IEDM 2002 Intel. VLSI 2006 NXP FINFET. IEDM 2009 6nm Length B. IEDM 2009 Nano-wire (LETI IEDM’08) 10 . 14 June 2011 Non planar • Intel Tri-Gate. IEDM 2007.

Non-planar devices Motivation: – Gate wrap-around helps control short channel effects in scaled devices – High mobility channels enables higher drive currents Scaling Pathways w and w/o 3rd gate ? OR High  Heterogeneous High  Bulk vs SOI OR SiN HM Si BOX 14 June 2011 HfO2 TiN Homgeneous 11 .

doping and silicide Gate etch NW Scaling and smoothness Si SiGe Si SiGe Si Spacer etch and process schemes Processing and integration Group IV channel material SiGe SiGe BOX Si Spacer etch and process schemes Processing and integration Group IV channel material FinFET/Trigate Nanowire • Most nanowire module issues are similar to FinFET module issues with added degree of integration complexity.Critical FinFET/Trigate/Nanowire Modules Source/Drain SEG. 14 June 2011 12 . doping and silicide Gate etch Fin Scaling and smoothness Source/Drain SEG.

Silicon Nanowires Wmask = 50 nm suspended wires 45 source MG 0n m Si HiK drain 10 nm Single Si Nanowire Silicide Data |VD| = 1 V |VD| = 50 mV 450 ID (A/um) Wmask = 50 nm nm PFET NFET Gate length = 40 nm NW width = 50 nm NW height = 20 nm VGS (V) 14 June 2011 13 .

– Vdd scaling limited by SS.Gate wraparound improves rolloff Swing (V/dec) • Omega Gate FinFET Nanowire device has smaller rolloff compared to FinFET. – Multiple GAA nanowires to meet ITRS targets. – In contrast. 14 Lmask (nm) 14 June 2011 . – Wrapping gate around channel improves short channel control. total current in FinFET can be increased with taller fins.  TFET! DIBL (V/V) SiN HM PFET Si BOX HfO2 TiN • Gate-All-Around (GAA) Device: – Total current in nanowire limited by crossectional area. VDS = -50 mV • PFET Long channel SS is similar for Omega-Gate and FinFET. – Different device structure needed to reduce Vdd.

14 June 2011 15 .Stacked Si nanowire formation using SiGe SiGe/Si Superlattice Fin etch Selective SiGe etch Si Si Si SiGe SiGe BOX Si Si Si SiGe SiGe Si SiGe Si Si SiGe BOX Suspended NWs Pt SiN Si SiGe Si SiGe Si BOX Si SiGe Si SiGe Si 200 nm Si BOX • Stacking nanowires helps increase total drive current to meet ITRS targets.

2nm) Universal (100) 13 1x10 2x10 3 13 NINV (#/cm ) Extracted by Split CV Method • SiGe PFETs have higher mobility than Si fins.5nm) Si {100}<100> 2 Si fin (Tinv = 1.8nm) Si {110}<110> SiGe {110}<110> eff (cm /V-s) 250 200 150 100 50 0 0 (100) shell/core fin (100) universal (Tinv=1.High mobility SiGe FinFETs/nanowires 350 300 (110) SiGe fin SiGe {100}<100> (Tinv= 1. • Potential for performance > strained Si in non-planar devices 14 June 2011 16 .

Outline • • • • Advanced CMOS Scaling Overview Nanowires TFETs Summary 14 June 2011 17 .

nanowire FET • Improve on-off ratio • Tunnel FET • Very steep ∆SS << 60 mV/dec • Low bias voltages (<< 1V) • Nano Electro Mechanical switch (NEMS) • Hybrid: Ion by CMOS + Ioff by NEMS • Zero Leakage Power Id.sat Vg 14 June 2011 18 . Ge.Device scaling options 2 1 • Very high mobility/high injection velocity • SiGe. InGaAs • Graphene [e ~15000 cm2/V-s at RT] • Better electrostatic control • Multiple gates + more channel area • FinFETs.

Ge. nanowire FET • Improve on-off ratio • Tunnel FET • Very steep ∆SS << 60 mV/dec • Low bias voltages (<< 1V) • Nano Electro Mechanical switch (NEMS) • Hybrid: Ion by CMOS + Ioff by NEMS • Zero Leakage Power Id.Device scaling options 2 1 • Very high mobility/high injection velocity • SiGe. InGaAs • Graphene [e ~15000 cm2/V-s at RT] • Better electrostatic control • Multiple gates + more channel area • FinFETs.sat 3 Vg 14 June 2011 19 .

Packan (Intel). . 2004) (P..01 0. Semico Conf. Meyerson et al. • VCC scaling limited by VT and subthreshold slope (which is kT/q limited)  need “green” devices not governed by kT/q ~ 60mV/dec limit. 2007 IEDM Short Course) • Passive power has shown continuous increase due to VDD scaling limit.VCC scaling for “green” electronics 1E+03 Power Density (W/cm2) Active Power Density 1E+02 1E+01 1E+00 1E-01 1E-02 1E-03 1E-04 Passive Power Density 1E-05 0.. 14 June 2011 20 .1 1 Gate Length (μm) (B. IBM.

SS < 60mV/dec 14 June 2011 21 .0 20 30 Electrons go over thermionic energy barrier • Boltzmann distribution of carriers causes leakage.0 Cox q I DS  exp( VGS ) Cox  Cdep kT 1. TFET: • Carriers go through the energy barrier.Working mechanism of TFET MOSFET Low ION Log ID COX VG φS High IOFF Operation Range Ec Ev CDEP MOSFET: • For Narrow On/Off Voltage Range: – Low Ioff  Low Ion – High Ion  High Ioff 0.0 -1.6 0.2 0.5 ON Log ID OFF EC EV 40 50 X [nm] 60 70 0.5 0.0 -0. Band-to-Band Tunneling.0 0.8 1.4 0.2 0.0 0.5 -1.8 1.6 0.4 0.0 -2.0 Energy [eV] • TFET 0.5 1.

5 0. 22 . SEMATECH-UCB DARPA STEEP Project 14 June 2011 Very Low SS.0 -0.5V 1x10 -6 46mV/dec -1.0V -6 -6 ID [A/um] -6 VG=-1. Metal Schottky PIN and Si-pocket PIN have been demonstrated.0 -1.5 0. need more Ion.0 -0.Si PIN tunneling FETs 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 10 -5 5x10 4x10 3x10 2x10 -6 VG=-2.0 0 -2.5 VG=-1.5 VD [V] -1.0V -2.0 VG [V] -1.0 Several types TFETs with Si PIN. Ultra-low subthreshold of < 50 mV/dec has been achieved over 103 order of drive current.

Dig.75 1. p. 947. ED. 2004. p. 2008.5 • Highest Ion (~ 109 A/m) at Vcc = 1.2 0. VBT 23 14 June 2011 .6 Vds (V) Vds (V) 0. Krishnamohan [2] F. Vgate-VBT (V) -0. Y.0 0.0V for Si TFET using optimized flash anneal for Nd activation.00 1. Overlap 10nm Sim.0 -1. 163. Choi [5] This work [6] 1 Channel SS (mV/dec) Material @ RT InGaAs 150~290 Ge 50 ~ 60 Si 460 Ge >400 Si Si Si Si 42 ~ 200 285 52. [5] IEEE EDL. K.70 1.4 0. 2008. p162 10 5 >10 4 >10 Ion is taken at overdrive of Vg-VBT = 2.0 -0.949. 2007. Overlap 0nm 10 10 10 10 -6 -7 Lg ~ 46 nm Vg = 0V Lg = 56nm Metal gate SiN spacer High-K ID (A/m) 10 10 10 10 -8 I ITunnel Thermonic -9 NiSi n+ 80nm Si p+ NiSi 10 10 -10 10 Temp = 213K~313K in step of 20K -11 -2. 743.00 0. [6] 40th ESSDERC 2010. Dig. p.00 0.5 0. [3] IEDM Tech.00 References S. Ioff taken at onset of BT-BT.. Dig. Mayer [3] K. [2] IEDM Tech.0 0.1 12* 84 109 1 Ion/Ioff > 10 6 10 2 > 10 2 > 10 10 10 5 4 4 3 1 • [1] IEDM Tech. [4] IEEE Trans. 2009.ND activation for high Ion Si TFET SEMATECH-UCB ESSDERC 2010 10 10 -3 -4 -5 -6 -7 -8 -9 Idrain (A/m) Experimental Sim.80 0. vol 51(2).5 -1. Krishnamohan [2] T. Good Ion.04 0. Overlap 5nm Sim. poor SS. p. Bhuwalka [4] W. 28(8). vol.80 1. Mayer [3] F.50 1.2 0. 279.8 120 ~ 250 Ion (A/m) 20 10 -4 10 4 0. Mookerjea [1] T.0V except for *. p.

g.Eg engineering : H-TFET • Effective Eg can be engineered by using heterostructure (e. Ge on Si) • Ge % from 25 ~ 50%  Bandgap engineering to enhance tunneling • Abrupt doping gradient by in-situ Bdoped SiGe and post annealing n+ Si (Drain) Gate p+Ge (Source) i-Si Heterostructure TFET Ec offset and bandgap narrowing for high tunneling g g g g SEMATECH-UCB DARPA Joint Project Much lighter Hole mass 14 June 2011 24 .

Preliminary InGaAs TFETs results indicates further optimization is needed to improve the poor SS.g.8 1.53GaAs Diodes -1 1st lot 2nd lot (Si) Eg=1.2 0.2V 1E03 Drain Current (A/µm) 10 13 High Dit In0.1eV. III-V has smaller bandgap and heterostructures (e.5 [C.5 -1.5 0.0 • • • Tunneling is a strong function of bandgap.69eV.5V 2 10 10 10 10 10 1 n+i-p+ In0. Vd=0. high Ioff.0 -0.0 0.III-V tunnel FETs (InAs) Eg=0. InAs/AlxGa1-xSb) have staggered or even zero bandgap  direct tunneling.14-15.6 0. 2008] Vgate (V) Vdiode (V) 0.0 0.0 -1. high Dit and poor Rco. 25 14 June 2011 . pp.53GaAs CB edge 10 Junction Leakage 3 Dit (#/cm /eV 2 1E06 - VB edge 12 Idiode (A/cm ) (Ge) Eg=0. Vd=0. Hu et al.4 0. VLSI-TSA.5 1.0 0. Vd=1V 10 -3 1E09 0.5 -1.36eV.0 -0.0 -5 p-Type n-Type Gate Voltage (V) 10 11 -7 -2.

VLSI-TSA. April. Hu et al. 2008 ] • Large field. good capacitive coupling btw gate & pocket • Abrupt turn-on due to overlap of valence/conduction bands • Tunable turn-on voltage 14 June 2011 26 .Novel design: pocket structure TFET P+ Pocket N+ S ource PBuried Oxide P+ Drain [ C.

2 0.8 0.0 14 June 2011 27 .3 0.6 0.5 0.4 0. w/ pocket Sim.7 0.0 Schottky-Source P-I-N TFET Silicon Gate BOX 100nm 10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 10 -4 NiSi BOX N+ Si Gate NiSi Si Probability ID [A/m] BOX N+ < Pocket > Gate NiSi Si 20 60 100 140 180 220 Subthreshold Swing [mV/dec] Measured Sim.0 V G [V] -0. 2010 NiSi • Achieved sub-60 mV/dec (46mV/dec) with 30% dies showing sub60mV/dec Si TFET with high-K/MG 0.1 0.5 0.Dopant-segregated Si-pocket TFET SEMATECH-UCB VLSI Symp. no pocket BOX N+ < No Pocket > -1.9 0.5 -1.

5 2 .5 1 .5 0.5 13 P++ P+ i N+ Tunneling Front P++ P+ N+ 10 10 4 -10 -11 TFET with pocket Control TFET -1.5 V L g = 100 nm -0.0 -0.0 1 .0 p-Type 10 11 n-Type V g a te (V ) -2.0 0.1 V 0.5 Vgate (V) 14 June 2011 .0 -1.S-MLD pocket InGaAs pocket TFETs 10 10 -4 -5 -6 -7 -8 -9 Pocket AlOx Idrain (A/m 10 10 10 10 n+ AlOx i Control V g-V BT = 0.5 -1.2 V to 1. 28 300K pocket 2 Dit (#/cm /eV 3 PVCR 2 10 12 C o n tro l 1 0 .0 V drain (V) 1.0 Control Pocket VB edge CB edge 10 • N+/p. • Improved gate coupling and Dit observed.0 0.5 in step of 0. • Enhanced drive current obtained due to enhanced vertical field at gated pocket n-p+ junction.pocket structure achieved on InGaAs TFET.

Luisier et al. Luisier et al. [8] S..4 0.0 0. 104. 2009. [7] M. 2008. 2008.2 Vgate (V) 0.0 10 -11 0. Nayfeh et al.4 0. Hu et al. Solid-State Elect. 2008. [4] Q. Mookerjea et al. EDL. Verhulst et al. EDL.36 [1] GaSb-InAs UTB [7] GaSb-InAs NW [7] InSb UTB [7] InGaAs [8] Eg = 0.0 0.72 eV InAs NW [6] Eg = 0..2 Vgate (V) 0. VLSI-TSA 2008 [3] A. 949. 1013. Zhang et al.... 2009. [5] V. (invited). 913. 30. TED.M. 29 ..S.Simulation of TFETs IV TFETs (Simulation) 10 -3 IIIV TFETs (Simulation) 10 -3 Ge/Si pocket [1] s-Ge/s-Si [2] Ge pocket [1] -5 Si pocket [1] Ge UTB [4] Idrain (A/m Idrain (A/m 10 10 10 Ge-source Si NW [3] 10 10 10 -5 SG Pocket Eg =0. [6] M. 602. IEDM. APL.6 0.6 0.17 eV -9 Si PNPN [5] Intel 32nm LP IEDM 2009 [9] Si TFET Ge TFET Si MOSFET -9 Intel 32nm LP IEDM 2009 [9] 10 -11 0. Nagavarapu et al. 2009. 14 June 2011 [2] O.8 1.. 1074.0 [1] C. IEDM.37 eV 60 mV/dec -7 Ge NW [3] Si NW [3] -7 InSb NW [7] 60 mV/decEg = 0. 064514.8 1. 2009.

2 Vgate (V) 0.53GaAs -9 In0.0 -0.8 1.4 0.4 -0.Current TFET performance P-TFET (experimental) 10 -3 N-TFET (experimental) 10 -3 Idrain (A/m 32nm pFET [9] (LP) p-channel n-channel Si TFET[12] Lg = 70nm PNPN Si TFET [5] Lg = 1m 10 10 10 -5 60 mV/dec DSS Si TFET [17] Lg = 20 m SOI TFET [14] Lg = 100 nm Si TFET [16] Lg = 56 nm Idrain (A/m 60 mV/dec 32nm nFET GeOI TFET [14] Lg = 0.2 Vgate (V) 0. No physical demonstration of TFET with both high Ion > 100 A/m and SS < 60 mV/dec has been demonstrated so far.2 10 -11 Ge-source TFET [15] Lg = 5m TFET [13] TFET [8] L = 100nm g Lg = 100nm 0.8 -0.4 m 10 10 10 -5 -7 -7 In0.0 • • Experiments show higher sub-threshold slope than simulations.0 0. 30 14 June 2011 .6 -0.0 0.6 0.7GaAs -9 10 -11 -1.

Summary • Power Constrained CMOS Scaling requires new materials and device structures to enable continued scaling. • Nanowires: – Better short channel control than FinFETs with added degree of integration complexity • TFETs: – Band to band tunneling transport mechanism allows for sub60mV subthreshold slope  Vcc reduction  lower power consumption – TFETs simulations show promise for Vcc reduction and additional process improvements are needed to improve device performance. 14 June 2011 31 .

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