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April 1988 Revised September 2000
74F182 Carry Lookahead Generator
The 74F182 is a high-speed carry lookahead generator. It is generally used with the 74F181 or 74F381 4-bit arithmetic logic units to provide high-speed lookahead over word lengths of more than four bits.
s Provides lookahead carries across a group of four ALUs s Multi-level lookahead high-speed arithmetic operation over long word lengths
Order Number 74F182SJ 74F182PC Package Number M16D N16E Package Description 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
L.0 1.0/8.4 mA 20 µA/−9. G2 G1 G3 P0 . Carries are rippled between lookahead blocks. There are several possible arrangements for the carry interconnects.0 1.3 Input IIH/IIL Output IOH/IOL 20 µA/−1.0/4.4 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA Functional Description The 74F182 carry lookahead generator accepts up to four pairs of Active LOW Carry Propagate (P0–P3) and Carry Generate (G0–G3) signals and an Active HIGH Carry input (Cn) and provides anticipated Active HIGH carries (Cn + x. Cn+z) across four groups of binary adders.6 mA 20 µA/−2.0/2.8 mA 20 µA/−3.0 1.74F182 Unit Loading/Fan Out Pin Names Cn G0. the 74F182 can be used with binary ALUs in an active LOW or active HIGH input operand mode.0/14.3 50/33.0/8. P1 P2 P3 Cn+x − Cn+z G P Carry Input Carry Generate Inputs (Active LOW) Carry Generate Input (Active LOW) Carry Generate Input (Active LOW) Carry Propagate Inputs (Active LOW) Carry Propagate Input (Active LOW) Carry Propagate Input (Active LOW) Carry Outputs Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Description U.0/16. 32-Bit ALU with Rippled Carry between 16-Bit Lookahead ALUs www. The connections (Figure 1) to and from the ALU to the carry lookahead generator are identical in both cases. A 28-bit ALU is formed by dropping the last 74F181 or 74F381.0 50/33.0 1. The 74F182 also has Active LOW Carry Propagate (P) and Carry Generate (G) outputs which may be used for further levels of lookahead. The logic equations provided at the outputs are: Cn+x = G0 + P0 Cn Cn+y = G1 + P1 G0 + P1 P0 Cn Cn+z = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 Cn G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 P = P2 P2 P1 P0 Also.com 2 .0/6. Cn+y.8 mA 20 µA/−4.fairchildsemi.3 50/33.2 mA 20 µA/−8. *ALUs may be either 74F181 or 74F381 FIGURE 1.0 1.0 1. The critical speed path follows the circled numbers. but all achieve about the same speed. HIGH/LOW 1.6 mA 20 µA/−4.
fairchildsemi.74F182 Truth Table Inputs Cn X L X H X X L X X H X X X L X X X H G0 H H L X X H H X L X X X H H X X L X X X X H X X X L H X X X L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Outputs G2 P2 G3 P3 Cn+x Cn+y Cn+z L L H H G P P0 H X X L X H X X X L X X H X X X X L G1 P1 H H H L X X X H H H X L X X X X H H X X L X H X X X L L X H X X X X L L X X H X X X X L X H X X L H H H H L X X X X H H H X L X X H X X X X L L L X H X X X X L L X X H X L H H H H L X X X H X X X X L L L X X X H L L L L H H H L L L L H H H H H H H H L L L L H H H H L 3 www.com .
www.74F182 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.fairchildsemi.com 4 .
0 0.0 mA mA mA Max Max Max 10% VCC 5% VCC 10% VCC 2.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired.5V to +7.2 Typ Max Units V V V V V µA µA µA V µA mA Min Min Min Max Max Max 0.6 IOS ICCH ICCL Output Short-Circuit Current Power Supply Current Power Supply Current −60 18.0 Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IOL = 20 mA VIN = 2.75 3.5V to +5.5 5.5V (G3.8 −1.0V VOUT = VCC IID = 1.0V −0.0 0.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0. P1) VIN = 0.com .7V VIN = 7.4 −9. P0.fairchildsemi. Note 2: Either voltage limit or current limit is sufficient to protect inputs.0V −30 mA to +5. G2) VIN = 0.8 −8. Functional operation under these conditions is not implied.0 50 Min 2.5 −150 28.74F182 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.0 7.4 23.5V to VCC −0.5V (G1) VOUT = 0V VO = HIGH VO = LOW 5 www.5V to +5.2 −2.5 2.5V −0.7 0.5V (P3) VIN = 0.4 −3.5V (P2) VIN = 0.5V (G0.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.75 −1.0 36.5V (Cn) VIN = 0.5V to +7.6 −4. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current 4.
0 10.0 2.5 10.0 2.9 6.0 TA = −55°C to +125°C VCC = +5.0 3.5 5.0 7.0 7.5 3. P1.0 11.8 6. Cn+y.0 3.0 3.1 10.6 6.0 3. or G2 to Cn+x.3 5.0 9.fairchildsemi.5 6.5 6.0 3. or P3 to G Propagation Delay Gn to G Propagation Delay Pn to P 3.0V CL = 50 pF Typ 6.0 9.7 4. Cn+y.0 3.5 ns ns ns 2.0V CL = 50 pF Min 3.5 5.9 8. G1. or Cn+z Propagation Delay P1. Cn+y.0 2.0 2.5 3.0 3.5 1.5 VCC = +5.5 12.0 2.0 3.5 8.5 Max 9.5 1.5 1.5 1.0 10.0 11.5 1.5 3.0 8.0 ns 3. Cn+z Propagation Delay P0.5 9.5 9.0 3.0V CL = 50 pF Min 3. P2.74F182 AC Electrical Characteristics TA = +25°C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Cn to Cn+x.2 3.0 3.0 8.com 6 .0 5.0 3.0 2.5 2.0 Max 12.5 6.0 2.0 8.0 6.0 TA = 0°C to +70°C VCC = +5.5 8.0 ns ns Units www.5 1.5 7.5 11.0 2.0 8.0 3.0 12.7 Max 8.0 10. or P2 to Cn+x.5 7.5 7. or Cn+z Propagation Delay G0.7 5.0 11.5 2.0 11.0 10.2 2.
fairchildsemi.com .74F182 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Package (SOP). 5.3mm Wide Package Number M16D 7 www. EIAJ TYPE II.
www.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described. Life support devices or systems are devices or systems which.fairchildsemi.74F182 Carry Lookahead Generator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP).com 8 2. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system. As used herein: 1.com . and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling. www. can be reasonably expected to result in a significant injury to the user. or to affect its safety or effectiveness.fairchildsemi. JEDEC MS-001. or (b) support or sustain life. (a) are intended for surgical implant into the body. 0.