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Control Store

Next State control

IB SB BC DB

Instruction decoders

OP

TY

NA

Branch Control Unit

Control word decoders

IRE IRF

Execution Unit
BITS Pilani, Pilani Campus

An instruction is fetched and placed in IRE
Translation of part of IRE provides the control store address Each flow chart state address correspond to a control word Control word specifies EU operations Control word contains the next control word address

BITS Pilani, Pilani Campus

OP

TY

NA

OP : Control Fields fields of bits decoded to drive control lines in execution unit.

TY: Control store address Select Next address type select
BC : Branch conditionally NA modified by condition code from EU

DB: Direct Branch
Next control store address is NA IB: Instruction branch- next control store address is from the control word decoders using IRE (for next instruction) SB: Sequence Branch : Next control store address is from control word decoders using IRE (for next sequence) NA : Next state address
BITS Pilani, Pilani Campus

The state ID becomes the location of the control word in a control store BITS Pilani. Pilani Campus .To personalize the control word -The tasks become bits in the control fields (OP) -The next state becomes the control store address select (TY) and next address (NA) .

Pilani Campus .Execution Unit Instruction Decoders Control word format Control word decoders Controller block diagram BITS Pilani.

Instruction Decoders -MIN Processor uses two instruction decoders -One decoder points to the first control word in address mode sequence -Other points to the first control word in execution sequence -The last state in any execution sequence shows IB in next state block BITS Pilani. Pilani Campus .

Instruction Decoders -IB instruction decoder points to the first control word sequence in the next instruction sequence -The last state in any address mode sequence shows SB in the next state block -SB instruction decoder points to the first control word in execution sequence -Instruction with no address mode sequence IB points to first control word in execution sequence BITS Pilani. Pilani Campus .

Pilani Campus brzz2 ADD RX (RY+d)@ abdm1 abdm2 abdm3 abdm4 oprm1 oprm2 brzz3 brzz2 abdm1 oprm1 oprm1 oprm1 oprm1 oprm1 .Example instruction execution Instruction Control word sequence Next control word address IB Instruction Decoder SB Instruction Decoder POP popr1 popr2 brzz3 popr2 brzz3 brzz2 abdm2 abdm3 abdm4 oprm2 brzz3 brzz2 oprr1 BITS Pilani.

Instruction Control word sequence Next control word address oprr2 brzz2 - IB Instruction Decoder SB Instruction Decoder SUB RX. RY oprr1 oprr2 brzz2 adrm1 test1 ldrm2 adrm1 adrm1 test1 test1 TEST RY @ ldrm2 push1 PUSH BITS Pilani. Pilani Campus .

Pilani Campus . S. SR. NR POP PUSH Instructions or Address mode L ST A.IB Decoder Address Abdm1 Adrm1 Brzz1 Ldrr1 Strr1 Oprr1 Popr1 Push1 SB Decoder Address Ldrm1 Strm1 Oprm1 Test1 Instructions or Address mode (RY +d)@ RY@ BZ LR STR AR. N T execution sequences address mode sequence execution sequences BITS Pilani.

Pilani Campus .Control word format OP field contains fields for the execution unit TY and NA fields for the next state address AO PC T2 REGS T1 ALU K DI DO IRE IRF BITS Pilani.

Pilani Campus .PC control Different uses off PC pc  a a  pc b  pc none pc  a alu pc  a rx BITS Pilani.

A-Bus PC 0 0 1 none b  pc 1 pc  a B-Bus x BITS Pilani. Pilani Campus .

T2 control Different uses off T2 t2  a t2  b a  t2 b  t2 none BITS Pilani. Pilani Campus .

t2a’ t2a. Pilani Campus .A-Bus t2a.t2b’ T2 t2b.t2b 0 o 1 none b  t2 1 t2 a t2 b B-Bus BITS Pilani.

ry  b b  ry b  rx. Pilani Campus . b  ry rx  a. a  ry rx  a.REG CONTROL ry  a b  rx ry  b. b  ry none BITS Pilani. b  rx rx  a rx  b.

Pilani Campus .ar3/(b r3)’ r3 MPX R3 r3a r3b BITS Pilani.

Pilani Campus .OP RX MODE RY AO PC T2 REGS T1 … MPX Control word reg Control field decoder n.2 n decoder r a  r / (b  r )’ ra rb BITS Pilani.

OP AO PC T2 REGS T1 … RX MODE RY Control word reg RY Control field decoder n.2 n decoder . Pilani Campus n.2 n decoder  ry a  ry / (b  ry )’ ry  a ry b Control word reg Control field decoder BITS Pilani.

r3 a = (rx  a ). Pilani Campus .y3 r3 b = (rx  b ).x3 + (ry a).y3 to A to B BITS Pilani.x3 + (ry b).

Pilani Campus . b  ry rx  b. b  rx rx  a Control lines ry  a b  rx. rx .Control word states ry  a b  rx ry  b. ry . rx b  rx. ry  b rx  a rx  b.b  ry BITS Pilani.

a  ry. b  ry. none BITS Pilani. ry . ry  b b  ry. ry rx  a. b  ry none rx  a. ry  b b  ry b rx.Control word states Control lines rx  a. ry b  rx. a  ry rx  a. Pilani Campus . rx .

Pilani Campus .Control lines for execution unit rx  a ry  a rx  b ry  b ry rx a  ry b  ry b  rx BITS Pilani.

Pilani Campus .00 00 none 01 b  rx 11 10 rx  a rx  a b  ry ry  a rx  b b  ry b  ry  ry a  ry 01 11 b  ry b  rx a  ry b  rx ry  b b  rx  rx 10 rx  a ry  b rx  a BITS Pilani.

Pilani Campus .Control word states none b  rx ry  a rx  a b  ry Control field bit assignments 0000 0001 0010 0011 0100 BITS Pilani.

b  ry rx  a. b  rx rx  a. Pilani Campus .Control word states rx  b. ry  b b  rx. a  ry Control field bit assignments 0110 0111 1001 1011 1101 BITS Pilani. b  ry ry  b.

Control Lines rx  a ry  a rx  b Decoder patterns xx11 0010 0110 ry  b 10xx BITS Pilani. Pilani Campus .

Control Lines  rx  ry a  ry b  rx Decoder patterns xx01 x1xx 11xx xx01 b  ry 01xx BITS Pilani. Pilani Campus .

ry  a  alu 0010 ry  a  do t1  b  a0. ry 0111 BITS Pilani. Pilani Campus .

Input bit pattern Active control lines 0111 rx  a xx11  ry b  ry x1xx 01xx BITS Pilani. Pilani Campus .

rx b  ry. t2 from strr1 Input bit pattern Active control lines rx  b 0110 0110  ry b  ry x1xx 01xx BITS Pilani. Pilani Campus .

Pilani Campus .BITS Pilani.