OOPS Concepts System Verilog

What is SystemVerilog?
qSystemVerilog is a hardware description and Verification language(HDVL) qSystemVerilog is an extensive set of enhancements to IEEE 1364 Verilog2001 standards qIt has features inherited from Verilog HDL,VHDL,C,C++ qAdds extended features to verilog

Verilog Shortcomings

Verilog
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Static components Deals at low lever of abstraction Declaring a transaction Passing transaction from one component to another Ex: USB Frame

Scenario Generation
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Result Checking

Summary of Verilog Shortcoming
Module can not take care of Complex frame declaration Being static in nature, difficult to declared dynamic scenario Module can not be declared in array Module can not be passed as argument Module can not be take care of encapsulation, inheritance for future revisions

Shortcoming Cont. ● BFM does not support module DPI Functional Coverage Connecting Components Event scheduling Polymorphism ● ● ● ● ● ..

Polymorphism ● Class – ● Random Constraints Inter Process Synchronization ● . Dynamic Array Encapsulation. Assoc. Inheritance. Array.SystemVerilog Features ● Literal Values : Logic Arrays : Dynamic in Nature – ● Ex: Queue.

SystemVerilog Features Contd ● Scheduling Scemantics Clocking Blocks Program Block Assertions Interface Functional Coverage DPI ● ● ● ● ● ● .

Introduction ● Objects are the building blocks of OOP technology The key fetures to understand OOPs is that object basically have two aspects – – ● State Behavior .

OOPS concepts ● Class Object Properties Method Inheritance Encapsulation Polymorphism ● ● ● ● ● ● .

endfunction function read_data.Class ● Central point of OOP Defines the properties and behavior of objects made of that class class packet. function write_data. bit [31:0] data. endfunction endclass ● .

Object ● Class is the central point of OOPS Object is the basic unit of object orientation with behavior. p2 = new(). ● ● ● ● ● . identity and state An object is expresed by the variables and methods of that class packet p1. p2. p1 = new().

Variables & Methods ● Attributes are defined by variables and behaviors are represented by methods Methods define the abilities of an object. ● .

Inheritance ● Inheritance is a mechanism of reusing and extending existing classes without modifying them. Subclass inherits all members of parents The objects are distinguished from each other by some attributes but share some/most of the common attributes – – ● ● Better data analysis Reduces development time .

data [255:0]. function set_data. function get_data. endclass ● Class packet_A extends packet. set_data are members of class packet_A get_data is the additioonal member that packet_A has ● ● . endclass data.Example Class packet.set_data are members of class packet Data.

we have three types data hding mechanism – – – ● ● Private members Protected members Public members .Encapsulation ● Seprating objects state from its behavior This helps in hiding an object's data describing its state from any further modification by external component In system verilog.

Polymorphism ● Polymorphism means many shapes Functions can be implemented with the same name but behaviour is different and correct execution takes place at run time ● .

System Verilog .

Introduction ● System verilog is built on top of verilog Improves the readability. productivity. reusability of verilog based code Help to create more concise HW description Extensive support for directed and constrained random testbench . assertion based erification ● ● ● . coverage driven verification.

typedef. dynamic queues. enum bounded queues. 1). Z) and bit (0.New constructs ● Extensions to data types for better encapsulation and compactness of code and for tighter specification – – C data types: int. associative arrays including automatic memory management freeing users from de-allocation issues dynamic casting and bit-stream casting Automatic/static variables – – – . struct. logic (0. union. tagged unions for safety Dynamic data types: string. 1. dynamic arrays. X. classes.

// pack stream = {stream. p. q}.randomize()).len. p. end – ● set membership . q = {<< byte{p.crc}}. Packet p = new. p.header.void’(p.Extended operators for concise description ● Wild equality and inequality built-in methods operator overloading streaming operators – – – ● ● ● byte q[$].payload.

Extended procedural statements ● pattern matching on selection statements for use with tagged unions enhanced loop statements plus the foreach statement C like jump statements: return. break. continue final blocks that executes at the end of simulation (inverse of initial) extended event control and sequence events ● ● ● ● .

Enhanced process control ● Extensions to always blocks to include synthesis consistent simulation semantics Extensions to fork…join to model pipelines and for enhanced process control Fine-grain process control ● ● .

Enhanced tasks and functions ● C like void functions pass by reference default arguments pass by name optional arguments import/export functions for DPI (Direct Programming Interface) ● ● ● ● ● .

and event sequencing . event variables. encapsulation.● Classes: Object-Oriented mechanism that provides abstraction. and safe pointer capabilities Automated testbench support with random constraints Interprocess communication synchronization – – – ● ● semaphores mailboxes event extensions.

and promote reusability: – – – ● cycle-based signal drives and samples synchronous samples race-free program context .● Clarification and extension of the scheduling semantics Cycle-Based Functionality: Clocking blocks and cycle-based attributes that help reduce development. ease maintainability.

● Assertions Extended hierarchy support Interfaces to encapsulate communication Functional coverage ● ● ● .

Reactive .Scheduling semantics ● A time slot is divided into a set of ordered regions: – – – – – – – – Preponed Pre-active Active Inactive Pre-NBA NBA Post-NBA Observed .Postponed .

● The purpose of dividing a time slot into these ordered regions is to provide predictable interactions between the design and testbench code. This allows properties and checkers to sample data when the design under test is in a stable state ● .

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Data Type .

user-defined vector size logic: 4-state SystemVerilog data type. user-defined vector size integer: 4-state Verilog-2001 data type. 8 bit signed integer or ASCII character bit :2-state SystemVerilog data type. 16 bit signed integer Int : 2-state SystemVerilog data type. user-defined vector size reg :4-state Verilog-2001 data type. 32 bit signed integer time :4-state Verilog-2001 data type. 64 bit signed integer byte :2-state SystemVerilog data type. 32 bit signed integer Longint : 2-state SystemVerilog data type. 64-bit unsigned integer ● ● ● ● ● ● ● ● .Integer data type ● Shortint : 2-state SystemVerilog data type.

rest two will return TRUE ● ● ● ● ● ● . unsi_h ='hff .Signed and unsigned data types ● Bit signed [7:0] si_h. si_h='hff. Byte by_h. Bit unsigned [7:0] unsi_h. by_h='hff (*_h=='hff) all will return TRUE (*_h==-1) unsi_h will return FALSE.

but shall be at least large enough to hold a pointer on the machine in which the tool is running.● Void data type: – – Non existant data Can be assigned as a return type of function The chandle data type represents storage for pointers passed using the DPI Direct Programming Interface The size of this type is platform dependent. ● chandle data type – – ● class .

atooct().compare atoi(). atohex(). atobin() . Toupper.getc. putc.String data type ● Variable size Dynamically allocated array of bytes Provides special method to work on strings – – – ● ● Len. tolower.

Event Data Type ● SystemVerilog events provide a handle to a synchronization object an event variable can be assigned another event variable or the special value null When assigned another event variable. the association between the synchronization object and the event variable is broken ● ● ● ● . both event variables refer to the same synchronization object. When assigned null.

// declare a new event called done event done_too = done.● event done. // event variable with no synchronization object ● ● . // declare done_too as alias to done event empty = null.

}IR. typedef struct { bit [7:0] opcode.Structures and unions ● struct { bit [7:0] opcode. bit [23:0] addr. // named structure type instruction IR. bit [23:0] addr. // define variable ● ● ● ● ● ● . } instruction.

Arrays ● An array is a collection of variables. all of the same type. and accessed using the same name plus one or more indices ● .

Unpacked array: bit c [7:0].bit c [8] ● ● ● .Packed and unpacked arrays ● Packed array: represented as continuous set of bits Unpacked array:may or may not be represented as coontinuous set of bits Packed array:bit [7:0] c.

Multidiomensional array ● Reg [7:0][9:0] a [8]. ● ● ● Then a [i] [j] [k] .

The space for a dynamic array doesn’t exist until the array is explicitly created at runtime. data_type array_name []..Dynamic arays ● A dynamic array is one dimension of an unpacked array whose size can be set or changed at runtime. Functions – ● ● new().delete().size() .

When the size of the collection is unknown or the data space is sparse. ● ● ● . but can be of any type.Associative arrays ● Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically. Associative arrays do not have any storage allocated until it is used the index expression is not restricted to integral expressions. an associative array is a better option.

Associative array methods ● num(). exists(string) first(index).prev(index) ● . last(index).delete(index).next(index).

pop_front() ● ● ● ● . but there are methods to insert and delete entries with index Size().QUEUE ● int q[$] Queue ie generally first in first out.push_front() pop_back(). insert().delete() push_back().

.Dynamic Arrays.Assignment ● Make the asynchronous tb using QUEUEs.

Classes offer inheritance and abstract type modeling ● ● ● . assigned. deleted.CLASS ● SystemVerilog introduces an object-oriented class data abstraction Classes allow objects to be dynamically created. and accessed via object handles Object handles provide a safe pointer-like mechanism to the language.

master_id = 5’bx. endfunction task clean(). bit [40:0] address. command = 0. // initialization function new(). endtask . command = IDLE.//data or class properties bit [3:0] command. address = 0.class Packet . integer time_requested. integer status. bit [4:0] master_id. address = 41’b0. master_id = 5’bx. integer time_issued.

current_status(). // declare a variable of class Packet p = new.Objects (class instance) ● Packet p. . // initialize variable to a new allocated object of the class Packet Calling tasks – ● ● p.

. data = $urandom. addr = pa. logic [3:0] addr. function void print(). addr = pa.print(). // explicit constructor // explicit constructor function new(input logic [3:0] function new(input logic [3:0] pa).pt(3)).addr. one. endfunction endfunction endclass endclass –Class –Full declaration Properties/Methods access to all members –Object variable (handle) defined of a specific class type –Class instance created with constructor Explicit or implicit method new basicframe one = basicframe one = new(.Simple Class class basicframe.addr = 4. $display("%h %h". data = $urandom.data). // 4 75 one. pa).. one. endfunction endfunction function void print(). . logic [7:0] data. // 4 75 .addr.. logic [7:0] data. two = new(. $display("%h %h". .pt(address)).data).pt(address)).print(). initial begin initial begin two = new(..pt(3)).addr = 4. basicframe two. class basicframe. new(. one. basicframe two. logic [3:0] addr.

one. logic [3:0] avec. abit. one. . function void print(). one. int avec. $display("%0d %b %h". child one = new(). $display("%d %d". abit. function void print().avec = 0. function void print().. . abit). $display("%0d %b %h". byte abyte. avec.print(). $display("%d %d". one. avec. one. logic [3:0] avec.avec = 0. logic abit.. function void print(). class parent. // 0 1 ff one. abyte).print(). Inheritance –Subclass inherits all members of parent. Can over-ride parent's members –Parent members are accessed as if they were members of the subclass. endfunction endfunction endclass endclass –A class declaration can extend an existing class.. avec.abyte = 8'hff. abit).abyte = 8'hff. endfunction endfunction endclass endclass class child extends parent. initial begin initial begin one.abit = 1'b1. abyte). avec. // 0 1 ff . int avec. class child extends parent. child one = new(). byte abyte.abit = 1'b1. one. logic abit.Inheritance class parent..

a2).. super. c1 = a2. endfunction endfunction endclass endclass –Parent constructor is implicitly called as first line of subclass constructor. logic p1. // 1 0 one. function new(input logic a1. endfunction endfunction function void print().. // 1 0 . c1). –Parent constructor must be explicitly called to pass arguments. function new(input logic a1. logic c1. c1). p1. function void print(). Must be the first line of subclass constructor –Prefix super allows a subclass to access parent members . Otherwise hidden by subclass members child one = new(1'b0. $display("%b %b". logic c1. function new(input logic a1). one. logic p1. c1 = a2. p1 = a1.new(a1).print(). class parent. p1 = a1. function new(input logic a1). 1'b0). class child extends parent.Inheritance and Constructors class parent. a2). p1.print(). 1'b0). child one = new(1'b0. super. initial begin initial begin one.b1 = 1'b1. endfunction endfunction endclass endclass class child extends parent. .b1 = 1'b1..new(a1).. one. . $display("%b %b".

Assignment. copying ● Packet p1. p1 = new. P1 P1 . renaming. P1 ● ● ● Packet p2. P2 p2 = p1.

Packet p2.● Shallow copy Packet p1. Packet p2 = new. p2. ● Deep copy Packet p1 = new. p2 = new p1. p1 = new. ● ● ● ● ● ● ● ● ● ● ● .copy(p1).

the method needs to be declared virtual . endfunction endclass ● ● class LinkedPacket extends Packet.Overridden members ● class Packet. endfunction endclass ● ● ● ● ● ● ● ● ● ● To call the overridden method via a parent class object (p in the ● example). function integer get(). function integer get(). get = -i. integer i = 1. get = i. integer i = 2.

Virtual Method ● virtual class BasePacket. function integer send(bit[31:0] data). // body of the function endfunction endclass ● ● ● ● ● ● ● . virtual function integer send(bit[31:0] data). endfunction endclass ● ● class EtherPacket extends BasePacket.

● Virtual class can not be instantiated All the methods of abstract class should be overriden Useful subclasses can be derived Virtual methods can be overdriven ● ● ● .

packets[1] = tp.// extends BasePacket GPSSPacket gp = new. EtherPacket ep = new.● polymorphism allows the use of a variable in the superclass to hold subclass objects. It allows reference the methods of those subclasses directly from the superclass variable – – – – – – Polymophism:DynamicMethodLookup ● BasePacket packets[100].// extends BasePacket TokenPacket tp = new.// extends BasePacket packets[0] = ep. .

send().● packets[1]. It shall invoke the send method associated with the TokenPacket class ● .

input bit clk). logic start.Interface ● interface simple_bus. always @(posedge clk) a. endmodule ● ● ● ● ● ● ● ● ● . logic req. logic avail.req & avail. data. logic [1:0] mode. endinterface: simple_bus ● ● module memMod(simple_b us a. logic [7:0] addr. rdy. gnt.gnt <= a.

● module top. .. simple_bus sb_intf(). . input bit clk). memMod mem (sb_intf.b(sb_intf). endmodule ● ● module cpuMod(simple_bu s b. endmodule ● ● ● ● ● ● ● ● .clk(clk)). logic clk = 0.. cpuMod cpu (. clk).

endinterface ● ● ● ● ● . d. d). d).● interface i2. wire a. input c. b. b. b. c. modport slave (output a. output c. modport master (input a.

– – .Program Block ● The program block serves three basic purposes: – It provides an entry point to the execution of testbenches. It provides a syntactic context that specifies scheduling in the Reactive region. It creates a scope that encapsulates programwide data.

program p1.) int shared.. endprogram endmodule ● ● ● ● ● ● ● ...● module test(.. .. endprogram program p2.. ...

● A program block can contain one or more initial blocks. Type and data declarations within the program are local to the program scope and have static lifetime. ● ● ● ● . or other programs.interfaces. modules. It cannot contain always blocks. Program variables can only be assigned using blocking assignments. Non-program variables can only be assigned using nonblocking assignments. References to program variables from outside any pro-gram block shall be an error. UDPs.

Eliminating race conditions ● Program block helps to avoid DUT/TB race conditions as they are supposed to execute in reactive region .

sorting and insertion methods .Queue… qData storage array [$] •Variable size array with automatic sizing •Searching.

Mailbox q Fifo with flow control •passes data between two processes •put() – stimgen calls put() to pass data to bfm •get() – bfm calls get() to retrieve data from stimgen stimgen bfm put() mailbox get() .

// Put data object into mailbox mbx.num(). // Non-blocking version success = mbx. // data will be updated with data from FIFO success = mbx. // Number of elements in mailbox count = mbx. // Non-blocking version mbx. // Number of elements in mailbox . mbx = new().num().peek(data).put(data).get(data).get(data). mailbox mbx.peek(data).put(data). mbx = new(). // allocate mailbox // allocate mailbox mbx. // Put data object into mailbox mbx. // Look but don’t remove mbx.try_get(ref data).try_get(ref data). // Look but don’t remove count = mbx.Mailbox mailbox mbx. // data will be updated with data from FIFO mbx.

#5 Fork #5 a = 0. Join Clk= 1.Fork/join Fork/join Initial Begin fork Clk =0. #10 b = 0. end Clk becomes 1 at t=15 join .

Fork/join Fork/join_any Initial Begin fork Clk =0. Join_any Clk= 1. #5 Fork #5 a = 0. end Clk becomes 1 at t=10 Join_any . #10 b = 0.

end . #10 b = 0. #5 Fork #5 a = 0. Join_none Clk becomes 1 at t=5 Join_none Clk= 1.Fork/join Fork/join_none Initial Begin fork Clk =0.

Semaphore qUsed for Synchronization •Variable number of keys can be put and removed •controlled access to a shared object •think of two people wanting to drive the same car – the key is a semaphore .

// constraint expression src[1:0] == 2’b00. rand logic [7:0] src. Constraint my_constraints { Constraint my_constraints { src[1:0] == 2’b00. // constraint expression …………… // always set src[1:0] to 0 …………… // always set src[1:0] to 0 } } endclass:packet endclass:packet . rand logic [7:0] src. rand logic [7:0] dest.Constraint qControl randomization •Values for random variable can be controlled through constraint expressions •These are declared within constraint block Class packet . rand logic [7:0] dest. Class packet .

global. check chk = new().valid ).Covergroup qCaptures results from a random simulation •bins qEncapsulates the coverage •transitions specification Covergroup Covergroup coverpoint coverpoint check @(posedge top. global. endgroup:check endgroup:check ……………… ……………… check chk = new().valid ).test.test. check @(posedge top. . coverpoint top. coverpoint top.

Program Block q Benefits: • Encapsulates the testbench • Separates the testbench from the DUT • Provides an entry point for execution • Creates a scope to encapsulate program-wide data q Functionality: • Can be instantiated in any hierarchical location ü Typically at the top level • Ports can be connected in the same manner as any other module .

drives just after clock clock Design Testbench Sampl e inputs Drive output s .Program Block q The testbench (program) runs separately from design (module) • Triggered by clock • Samples just before clock edge.

Interface qbundling of port signals •provide an abstract encapsulation of communication between blocks •Directional information (modports) •Timing (clocking blocks) •Functionality (routines.assertions) device1 interface device2 .

bit valid .Interface Interface:An example Interface bus_a (input clock). Interface bus_a (input clock). bit rd_wr . logic [7:0] address. logic [7:0] address. logic [31:0] data . bit valid . Endinterface: bus_a Endinterface: bus_a . bit rd_wr . logic [31:0] data .

Clocking Block qSpecify synchronization characteristics of the design qOffer a clean way to drive and sample signals qFeatures •Clock specification •Input skew.output skew •Cycle delay (##) .

module or program .Clocking Block qCan be declared inside interface.

input ck. initial begin initial begin sab = sd. input #2ns ein. reg [7:0] sab . input [31:0] din . endclocking:sd endclocking:sd reg [7:0] sab . din.din[7:0].Clocking Block Module M1(ck.enin. dout. enin. din. sab = sd. end end endmodule:M1 endmodule:M1 Signals will be driven 3ns after posedge ck Signals will be sampled 2ns before posedge ck . dout). dout. . enout. output #3ns enout. Module M1(ck. enin. input #2ns ein. output #3ns enout.enin. output enout .din[7:0]. enout. dout).din . output [31:0] dout output [31:0] dout . clocking sd @(posedge ck).din . input ck. input [31:0] din . output enout . clocking sd @(posedge ck).

Modports qAn interface can have multiple •Master/Slave, viewpointsTransmitter/Receiver qThese can be specified using modports
Interface bus_b (input clock); Interface bus_b (input clock); logic [7:0] addr,data; logic [7:0] addr,data; logic [1:0] mode logic [1:0] mode bit ready bit ready modport master (input modport master (input ; ; ; ;
All signal names in a modport must be declared in the interface

ready,output addr,data,mode) ; ready,output addr,data,mode) ; modport slave (input addr,data,mode,output ready) ; modport slave (input addr,data,mode,output ready) ; endinterface: bus_b endinterface: bus_b

Conclusio n
q Some of SystemVerilog Testbench constructs were discussed
qBut still a long way to go……..

Thank you

References
Websources:

1.

www.systemverilog.org

2. www.asic-world.com/systemverilog/index.html 3. http://svug.org/
Books :

1. Writing Testbenches using SystemVerilog - Janick Bergeron 2. Verification Methodology Manual - Janick Bergeron 3. SystemVerilog For Verification - Chris Spear

Test Cases Test Bench ENV SCOREBOARD SEQUENCER DRIVER MONITOR Interface MEMORY DUT Assertions .

Assignment ● Designing TB using Program Block .

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