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A Novel Single-Phase Five-Level Inverter With Coupled Inductors


Zixin Li, Member, IEEE, Ping Wang, Yaohua Li, and Fanqiang Gao, Member, IEEE
AbstractIn this paper, a novel single-phase ve-level inverter is proposed using coupled inductors. This inverter can output velevel voltage with only one dc source. No split of the dc voltage capacitor is needed, totally avoiding the voltage balancing problem in conventional multilevel inverters. The level of the output voltage is only half of the dc-link voltage in all conditions, leading to much reduced dv/dt. This inverter is based on the widely used three-arm power module and the voltage stresses on all the power switches are the same, making it very easy to construct. Operation mechanism of this inverter is analyzed and the possible switching patterns are investigated. Based on these analyses, a novel optimized modulation scheme is presented. With this modulation method, no dc components exist in the inductor currents, which is very helpful for minimization of the inductors. Simulation and experimental results show the validity of the proposed inverter together with the optimized modulation scheme. Index TermsMultilevel converters, power converters, pulse width modulation, single-phase.
Fig. 1. Proposed single-phase ve-level inverter.

I. INTRODUCTION INCE their introduction, multilevel inverters have been receiving much attention and as a result many different topologies have been proposed. The academic papers and theses focusing on multilevel inverter topologies are almost innumerable. These topologies can be classied according to many criteria. This paper will focus on single-phase multilevel inverters. For single-phase multilevel inverters, the most common topologies are the cascaded, diode-clamped, and capacitorclamped types [1][3]. There exist many other topologies [4][26]. In general, multilevel inverter topologies can be classied into two types: Type I and Type II. Type I uses multiple dc voltage sources and Type II uses multiple (split or clamping) dc voltage capacitors. Type I includes the traditional cascaded topologies [1][3], those presented in [4][8] and so forth. Type II includes the conventional diode-clamped, capacitor-clamped inverters, the topologies proposed in [9][26]. In terms of singlephase multilevel inverters, the disadvantages of the two types are apparent. Type I suffers from the availability of the multiple dc voltage sources. In practice, bulky transformers either of low

Manuscript received August 9, 2011; revised October 1, 2011; accepted November 13, 2011. Date of current version March 16, 2012. Recommended for publication by Associate Editor B. Wu. The authors are with the Institute of Electrical Engineering, Chinese Academy of Sciences, 100190 Beijing, China (e-mail: lzx@mail.iee.ac.cn; wangping@mail.iee.ac.cn; yhli@mail.iee.ac.cn; yhli@mail.iee.ac.cn). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2011.2176753

or medium frequency are usually necessary if a Type I inverter is adopted. This is a great challenge to when it comes to volume, weight, and cost minimization. The problem with Type II is mainly the balancing of the dc capacitor voltages, though some topologies can achieve self-balancing with certain control algorithms. A multilevel inverter with only one dc source and no split capacitors may be the most desirable topology but unfortunately this type of inverter has yet to be discovered. Recently, multilevel inverters with coupled inductors have drawn some researchers interest and a half-bridge three-level inverter has been proposed using two power switches, two diodes, and two coupled inductors [27][30]. Whereas, as for single-phase ve-level cases, two such half-bridges, i.e., six power devices (four power switches, two diodes) and four (two pairs of) coupled inductors will be needed [28], [29]. What is more, dc component exists in the inductor current in these of inverters, which is harmful to the full use of the magnetic cores. More recently, [31] presented a single-phase inverter called a ve-level-active-neutral-pointclamped with coupled inductor (5L-ANPC-CI). The 5L-ANPLCI inverter uses eight power switches, and split of the dc-link capacitor is needed. Thus, the risk of unbalanced capacitor voltage exists if the inverter is not properly modulated. This paper presents a novel single-phase ve-level inverter using coupled inductors and the common three-arm power module (see Fig. 1). With the proposed inverter, only one dc voltage source is needed and split of the dc voltage capacitor is also avoided, which eliminates the problem of dc capacitor voltage balancing with the conventional topologies. Meanwhile, six power switches with the same voltage stress and only one set of coupled inductors are adopted. Also, less inductor is needed in the inverter proposed in this paper compared with the topology

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in [28] and [29]. In addition, an optimized modulation scheme of this inverter is also presented. With this modulation method, no dc component exists in the inductor currents under all load conditions, which will benet the full use of the magnetic cores and minimization of the inductors. Theoretical analyses, numerical simulation, and experimental results are presented to show the validity of the proposed inverter with the optimized modulation method. II. PROPOSED SINGLE-PHASE FIVE-LEVEL INVERTER Fig. 1 shows the circuit of the proposed single-phase velevel inverter. In Fig. 1, 2E is the dc-link voltage and L1 and L2 are the two coupled inductors. The mutual inductance of the two inductors is M and the output terminals of this inverter are 1 (the same point as the output of arm a) and 2. Obviously, this topology is very simple and can be constructed simply by adding two coupled inductors to a conventional three-arm inverter bridge. A. Role of the Coupled Inductors It is, in fact, the adoption of the coupled inductors that makes it possible to output ve-level voltage with only one dc voltage source. So the role of the coupled inductors will be analyzed rst. Suppose that the two coupled inductors are with the same number of turns or obtained by a center-tapped inductor. The leakage inductances of the two inductors are L 1 and L 2 , respectively. Assuming that L 1 = L 2 = L , the voltage equations of the coupled inductors can be expressed as follows: (M + L )dib /dt M dic = ubn u2n dt (M + L )dic /dt M dib = ucn u2n . dt (1) (2)

TABLE I SWITCHING STATES AND OUTPUT VOLTAGE OF THE PROPOSED INVERTER

B. Switching States for Five-Level Output Voltage From Fig. 1 and (5), the output voltage of the proposed inverter can be expressed as u12 = u1n u2n = u1n (ubn + ucn ) . 2 (6)

Meanwhile, according to Kirchhoffs current law, one can obtain ib + ic + iL = 0. From (1) to (3), the following equation can be derived: u2n = (ubn + ucn + L diL /dt) . 2 (4) (3)

In the following discussion, the power switches in one arm are assumed to switch complementarily. For instance, S2 must be turned OFF if S1 is turned ON and vice versa. So the following discussion will only focus on the switching states of S1 , S3 , and S5 . For convenience of analysis, the number 1 will be used to denote the ON state of one switch and 0 will be used to denote the OFF state. In fact, u1n , ubn , and ucn all can generate two-level voltage (+E and E). According to (6), the voltage levels of u12 can be summarized in Table I. Obviously, the proposed inverter can generate ve voltage levels at its output terminals. From Table I, it should be pointed out that the switching state of S1 must be 1 if u12 0 and the switching state of S1 must be 0 if u12 0. This means S1 and S2 will switch at the fundamental frequency of the reference signal. So, the switching losses of S1 and S2 will be very low in the proposed inverter. III. PROPOSED MODULATION METHOD Although the proposed inverter can output ve-level voltage, the modulation method must be analyzed in detail for safe operation. This section will focus on the pulse-width modulation (PWM) method for this inverter. From the above analysis, the switching state of S1 is decided by the sign of u12ref (the reference of u12 ): S1 is 1 if u12ref 0 and S1 is 0 if u12ref 0, which is very easy to implement. However, the switching states of S3 and S5 cannot be selected without careful study. To decide the switching states of (S3 , S5 ), the following four cases will be discussed: Case I (+E < u12ref < + 2E): In this case, the voltage of u12 should alternate between +2E and +E. According to Table I, the switching states of (S3 , S5 ) within every switching period Ts can be (0, 0)(0, 1) (dened as SS1 , the note xy means alternating between x and y) or (0, 0)(1, 0) (dened as SS2 ).

Generally, the leakage inductance can be designed to be very small and its inuence can be ignored in most cases. Therefore, (4) can be rewritten as u2n = (ubn + ucn ) . 2 (5)

This result is interesting and shows that the coupled inductors will perform as an adder of the two input voltage at the non-common-connected terminals with the common-connected terminal as the output. Actually, without the help of the coupled inductors, the proposed inverter will not be able to output ve-level voltage.

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TABLE II SWITCHING STATES SUITABLE FOR (S 3 , S 5 )

Fig. 2.

Generation of the dwelling time dened in (7).

Case II (0 u12ref < +E): In this occasion, the voltage of u12 should alternate between +E and 0. Based on Table I, the switching states of (S3 , S5 ) within every Ts can be (0, 1)(1, 1) (dened as SS3 ) or (1, 0)(1, 1) (dened as SS4 ). Case III (E < u12ref 0): In this case, the voltage of u12 should alternate between +0 and E. According to Table I, the switching states of (S3 , S5 ) within every Ts can be (0, 0)(0, 1) (which is already dened as SS1 in Case I) or (0, 0)(1, 0) (which is already dened as SS2 in Case I). Case IV (2E < u12ref < E): In this occasion, the voltage of u12 should alternate between E and 2E. Based on Table I, the switching states of (S3 , S5 ) within every Ts can be (0, 1)(1, 1) (which is already dened as SS3 in Case II) or (1, 0)(1, 1) (which is already dened as SS4 in Case I). From the above analysis, one can conclude that only four types of switching states within every switching period Ts can be selected for (S3 , S5 ), i.e., SS1 , SS2 , SS3 , and SS4 , which are listed in Table II. Meanwhile, if the reference voltage u12ref is given within certain Ts , there are always two possible choices, i.e., SS1 or SS2 for Case I and Case III and SS3 or SS4 for Case II and Case IV. For further discussion, the dwelling time for the switch that switches within every Ts is dened as (|u12ref | K E) Ts E where the integer K is calculated by Tdwell = K = oor |u12ref | E . (7)

(8)

The function oor(x) rounds x to the nearest integer less than x. Obviously, the dwelling time in (7) can be generated using the conventional triangle wave which is shown in Fig. 2. For convenience of understanding, the green parts in Fig. 3 illustrate the dwelling time within every Ts . Actually, the proposed inverter can be modulated in such a way that only one of S3 and S5 carries out the dwelling time while the other one is always ON or OFF within one Ts . Taking Case I as an example, if SS1 is selected, S5 will switch and carry out the dwelling time while S3 is always OFF within one Ts ; if SS2 is selected, S3 will switch and carry out the dwelling time while S5 is always OFF within one Ts . As there are always two choices for selecting the switching states of (S3 , S5 ), a great many switching patterns can be found

within one fundamental period. Fig. 3 just shows six of the possible switching patterns for (S3 , S5 ), i.e., SP1SP6. All of these switching patterns can generate the ve-level output voltage u12 as shown in Fig. 3. However, as the coupled inductors are connected between arms b and c, the voltage ubc may contain dc or fundamental components in case of improper modulation. If dc component exists in ubc , the currents in the coupled inductors may increase to quite a large value, which is very dangerous to the normal operation of the inverter. In order to operate the inverter safely and minimize the size and weight of the coupled inductors, the following rules for modulation should be satised. 1) The voltage ubc should not contain any dc component. Otherwise, the inverter may have the risk of overcurrent. 2) The currents in the coupled inductors should not contain any fundamental or loworder harmonic component under no-load condition. Otherwise, the magnetization current to the core of the inductors together with the inverter losses will be increased, leading to decreased efciency of the inverter and increased ux density of the inductor core. Considering the above rules, not all of the possible switching patterns for (S3 , S5 ) can be selected. Indeed, the two possible choices (SS1 or SS2 for Case I and Case III and SS3 or SS4 for Case II and Case IV) for (S3 , S5 ) within one Ts have the same role on the output voltage, but the voltage ubc they generate differs a lot. For example, it is seen from Table II that both SS1 and SS2 can generate an output voltage alternating between +2E and +E (0 and E) if the switching state of S1 is 1 (0). Namely, SS1 and SS2 have the same role on the output voltage of this inverter. Whereas, if SS1 is adopted, the voltage on the coupled inductors ubc will be 0 or 2E while ubc will be 0 or +2E if SS2 is adopted. If SS1 makes the current in the coupled inductors increase, SS2 will make that current decrease and vice versa. This is also true for SS3 and SS4 . Therefore, SS1 SS4 cannot be selected in consecutive switching periods without change. Otherwise, fundamental or low-order harmonics will appear in the inductor currents under no load and it will also increase the inductor currents when the inverter is loaded. Based on these analyses, the proper modulation or switching strategy for the proposed inverter can be obtained. As SS1 and SS3 generate 0 and 2E while SS2 and SS4 generate 0 and +2E to ubc , the four switching states must be selected in such a manner that ubc will change its sign in every Ts . In this way, only ripple component other than dc or fundamental component

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Fig. 3.

Dwelling time (green part) within every T s and the some of the possible switching patterns for S 3 and S 5 (SP1SP6). TABLE III RULES FOR SELECTING SWITCHING STATES OF (S 3 , S 5 )

the leakage inductance, one can obtain 2M dib dic = ubc . dt 2M dt (9)

Solving (3) and (9), the currents in the coupled inductors can be expressed as follows: ib = 1 (iL + iripple ) 2 (10) i = 1 (i i c L ripple ) 2 where 1 (11) ubc dt. iripple = 2M Suppose the ripple current in the coupled inductors is limited to I, the inductance M can be determined. Considering the most serious condition, i.e., |ubc | is always equal to 2E within one Ts , the largest ripple current in the coupled inductors can be calculated as follows: iripple(m ax) = I = 1 2M
Ts

will appear in the inductor currents under no load, and it will not introduce extra magnetization currents to the inductor core. To summarize, the rules for selecting the optimum switching states that can minimize the inductor currents are listed in Table III. For instance, if E < u12ref 0 or the Case III in the (k1)th Ts and the switching state of (S3 , S5 ) is SS1 in the (k1)th Ts , the switching state of (S3 , S5 ) will be SS2 , SS4 , SS2 , or SS4 in the kth Ts if it is Case I, Case II, Case III, or Case IV in the kth Ts , respectively. According to the rules listed in Table III, the six switching patterns shown in Fig. 3 are not all suitable. For example, SP1SP4 do not meet the rules listed in Table III while SP5 and SP6 are suitable. IV. DESIGN OF THE COUPLED INDUCTORS In order to design the coupled inductors, the relationship between the currents of the coupled inductors ib , ic and the load current iL should be analyzed. Using (1) and (2) and neglecting

2Edt =
0

Ts E . M

(12)

Hence, the inductance M should satisfy Ts E . (13) I Meanwhile, from (10) one can see that the coupled inductors also carry half the load current besides the ripple current. Therefore, the load current should also be taken into account in designing the inductor core. It is clear from (10) that one inductor and thus the switch S3 /S4 or S5 /S5 carries about half the load current if the ripple component is low. Interestingly, the high-switching frequency devices S3 S6 take only half the load current while the low-switching frequency devices S1 S2 carry the whole load M>

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Fig. 4.

Steady-state results when u 1 2 re f = 40 cos(100t) V. (a) u 1 2 and u 1 2 re f . (b) ib , ic , and iL .

TABLE IV PARAMETERS OF THE INVERTER FOR SIMULATION AND EXPERIMENT

current. Thereby, the switching and conduction losses of S3 S6 will not be very high because they only carry half of the load current. On the other hand, S1 and S2 switch at the fundamental frequency which will lead to very small switching losses. This characteristic of the proposed inverter makes it very suitable for high-current applications. V. SIMULATION RESULTS In order to verify the validity of the topology with the optimized modulation scheme in this paper, the proposed inverter is tested with series-connected RL load. The load resistor is RL and the load inductor is LL . The parameters of this inverter are listed in Table IV. Also, the ve-level inverter can also output three-level voltage if the modulation index is low. To verify the validity of the presented modulation method both in low and high modulation

index cases, the reference voltage u12ref is set as 40 cos(100t)V (modulation index = 0.4) when t < 0.11 s and u12ref is set as 80 cos(100t)V (modulation index = 0.8) when t 0.11 s. Fig. 4(a) and (b) shows the simulation results of the proposed inverter in steady state when the modulation index is 0.4. One can see that the output voltage of the inverter has three levels. In meantime, the ripple components in ib and ic are almost complementary to each other. Therefore, the ripple component in the load current is substantially reduced compared with that in ib or ic . It is also clear from Fig. 4(b) that the currents of the two coupled inductors have the same fundamental component and no dc component exist in them. Fig. 5(a) and (b) shows the steady-state performance of the inverter in this paper when the modulation index is 0.8. One can see that the output voltage of the inverter increases from three to ve levels. Still, the ripple components in ib and ic are almost complementary to each other and the fundamental components are almost the same. Besides, no dc components exist in ib and ic . From Figs. 4 and 5, the fundamental component of ib or ic is about half the load current which can be explained by (10). To test the dynamic performance of the proposed inverter, u12ref is changed from 40 cos(100t) V to 80 cos(100t) V at the instant of t = 0.11 s and the simulation results are displayed in Fig. 6. It is seen from Fig. 6(a) that the level number of the output voltage increases to ve at t = 0.11 s. The currents in the two coupled inductors are well balanced even in dynamic state which is proved by Fig. 6(b). In fact, a little difference is generated

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Fig. 5.

Steady-state results when u 1 2 re f = 80 cos(100t) V. (a) u 1 2 and u 1 2 re f . (b) ib , ic , and iL .

Fig. 6.

Dynamic state results when u 1 2 re f changes from 40 cos(100t) V to 80 cos(100t) V at t = 0.11 s. (a) u 1 2 and u 1 2 re f . (b) ib , ic , and iL .

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Fig. 7.

Photo of the coupled inductors.

Fig. 8. u 1 2 (upper yellow line: 100 V/div). ib and ic (lower pink and purple lines: 5 A/div) under no load when the modulation index is 0.4.

between ib and ic at t = 0.11 s. Anyway, the fundamental components of the two currents become balanced naturally although the high-frequency components caused by the switching are still complementary to each other. What is more, in all these simulations, the height of the staircase in the output voltage is 50 V or half of the dc-link voltage either in three-level or in ve-level

Fig. 9. Experimental results of the proposed inverter under RL load when the modulation index is 0.4. (a) u 1 2 (upper yellow line: 100 V/div), ib and ic (lower pink and purple lines: 5 A/div). (b) u 1 2 (upper yellow line: 100 V/div) and iL (lower pink line: 5 A/div). (c) Spectrum of ib /ic . (d) Spectrum of iL .

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Fig. 10. u 1 2 (upper yellow line: 100 V/div), ib and ic (lower pink and purple lines: 5 A/div) under no load when the modulation index is 0.8.

condition. Compared with the H-bridge inverter, this is a substantial reduction of the dv/dt in the inverter output voltage. VI. EXPERIMENTAL RESULTS The proposed inverter together with the optimized modulation scheme has also been experimentally tested. In the experiments, six 1200 V insulated gate bipolar transistors are taken as the power switches S1 S6 . The modulation algorithms are implemented in a TMS320F28335 DSP (TI product). The other parameters of this inverter are the same as those listed in Table IV and the photo of the coupled (center-tapped) inductors is shown in Fig. 7. Figs. 812 show the experimental results of the proposed inverter under no load and RL load conditions with the modulation index of 0.4 and 0.8. It is clear that the output voltage is of three-level when the modulation index is 0.4 while it is of ve-level when the modulation index is 0.8. Whether the modulation index is low or high, the currents in the two coupled inductors have no dc or fundamental component under no load condition, which are shown in Figs. 8 and 10. When the inverter is loaded, S3 S6 take only half of the load current and still no dc component exist in the coupled inductor currents, which can be seen from Figs. 9 and 11. Meanwhile, the ripple components of the currents in the coupled inductors are almost complementary to each other. Therefore, the load current has little ripple components. It is clear from Figs. 9(c) and (d) and 11(c) and (d) that the total harmonic distortion (THD) of ib and ic are high, but the THD of the load current iL is much lower compared with that of ib and ic . This result cannot be achieved without the optimized modulation scheme. Meanwhile, one can see that the high-order harmonics in ib and ic are around 2 kHz or half of the carrier frequency of S3 S6 , but not the carrier frequency. This is because the ripple component of the currents in ib and ic are determined by the difference of S3 and S5 . Taking the Case I region of SP5 or SP6 in Fig. 3 as an example, the switching

Fig. 11. Experimental results of the proposed inverter under RL load when the modulation index is 0.8. (a) u 1 2 (upper yellow line: 100 V/div), ib and ic (lower pink and purple lines: 5 A/div). (b) u 1 2 (upper yellow line: 100 V/div) and iL (lower pink line: 5 A/div). (c) Spectrum of ib /ic . (d) Spectrum of iL .

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fore, the presented topology is very suitable for low to medium power applications, especially for high-current cases. REFERENCES
[1] J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multilevel inverters: A Survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724738, Aug. 2002. [2] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, A survey on cascaded multilevel inverters, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 21972206, Jul. 2010. [3] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, A survey on neutral-point-clamped inverters, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 22192230, Jul. 2010. [4] Y.-S. Lai and F.-S. Shyu, Topology for hybrid multilevel inverter, IEE Proc. Electron. Power Appl., vol. 149, no. 6, pp. 449458, Nov. 2002. [5] Y. Hinago and H. Koizumi, A single-phase multilevel inverter using switched series/parallel DC voltage sources, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 26432650, Aug. 2010. [6] H. Akagi and R. Kitada, Control and design of a modular multilevel cascade BTB system using bidirectional isolated DC/DC converters, IEEE Trans. Power Electron., vol. 26, no. 9, pp. 24572464, Sep. 2011. [7] Y.-H. Liao and C.-M. Lai, Newly-constructed simplied single-phase multistring multilevel inverter topology for distributed energy resources, IEEE Trans. Power Electron., vol. 26, no. 9, pp. 23862392, Sep. 2011. [8] J. Shi, W. Gou, H. Yuan, T. Zhao, and A. Q. Huang, Research on voltage and power balance control for cascaded modular solid-state transformer, IEEE Trans. Power Electron., vol. 26, no. 4, pp. 11541166, Apr. 2011. [9] F. Z. Peng, A generalized multilevel inverter topology with self voltage balancing, IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 611618, Jul. 2001. [10] Y. Ounejjar and K. Al-Haddad, A novel high energetic efciency multilevel topology with reduced impact on supply network,, in Proc. IEEE 34th Ann. Conf. Ind. Electron. (IECON), 2008, pp. 489494. [11] S.-J. Park, F.-S. Kang, M. H. Lee, and C.-U. Kim, A new single-phase ve-level PWM inverter employing a deadbeat control scheme, IEEE Trans. Power Electron., vol. 18, no. 3, pp. 831843, May 2003. [12] G. Ceglia, V. Guzman, C. Sanchez, F. Ibanez, J. Walter, and M. I. Gimenez, A new simplied multilevel inverter topology for DCAC conversion, IEEE Trans. Power Electron., vol. 21, no. 5, pp. 13111319, Sep. 2006. [13] L. Chen, L. Hu, L. Chen, Y. Deng, and X. He, A multilevel converter topology with fault-tolerant ability, IEEE Trans. Power Electron., vol. 20, no. 2, pp. 405415, Mar. 2005. [14] A. Chen and X. He, Research on hybrid-clamped multilevel-inverter topologies, IEEE Trans. Ind. Electron., vol. 53, no. 6, pp. 18981907, Dec. 2006. [15] G.-J. Su, Multilevel dc-link inverter, IEEE Trans. Ind. Appl., vol. 41, no. 3, pp. 848854, May 2005. [16] F.-P. Zeng, G.-H. Tan, J.-Z. Wang, and Y.-C. Ji, Novel single-phase velevel voltage-source inverter for the shunt active power lter, IET Power Electron., vol. 3, pp. 480489, 2010. [17] Z. Du, L. M. Tolbert, J. N. Chiasson, and B. Ozpineci, A cascade multilevel inverter using a single DC source, in Proc. IEEE Appl. Power Electron. Conf. (APEC), 2006, pp. 426430. [18] Z. Du, B. Ozpineci, L. M. Tolbert, and J. N. Chiasson, DCAC cascaded H-bridge multilevel boost inverter with no inductors for electric/hybrid electric vehicle applications, IEEE Trans. Ind. Appl., vol. 45, no. 3, pp. 963970, May/Jun. 2009. [19] M. Glinka, Prototype of multiphase modular-multilevel-converter with 2 MW power rating and 17-level-output-voltage, in Proc. IEEE Power Electron. Spec. Conf. (PESC), 2004, pp. 25722576. [20] M. Glinka and R. Marquardt, A new AC/AC multilevel converter family, IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 662669, Jun. 2005. [21] M. Hagiwara and H. Akagi, Control and experiment of pulsewidthmodulated modular multilevel converters, IEEE Trans. Power Electron., vol. 24, no. 7, pp. 17371746, Jul. 2009. [22] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, Modulation, losses, and semiconductor requirements of modular multilevel converters, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 26332642, Aug. 2010. [23] A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, A hybrid cascade converter topology with series-connected symmetrical and asymmetrical diodeclamped h-bridge cells, IEEE Trans. Power Electron., vol. 26, no. 1, pp. 5165, Jan. 2011. [24] J. Li, S. Bhattacharya, and A. Q. Huang, A new nine-level active NPC (ANPC) converter for grid connection of large wind turbines for distributed

Fig. 12. Experimental results of the proposed inverter under RL load when u 1 2 re f changes from 40 cos(100t) V to 80 cos(100t) V: u 1 2 (upper yellow line: 100 V/div), ib / ic (middle pink and purple lines: 5 A/div) and iL (lower green line: 5 A/div).

pattern for (S3 , S5 ) is selected as SS1 SS2 SS1 L. Within one Ts , the difference between S3 and S5 or (S3 S5 ) is 1/0 if SS1 is selected while it is 1/0 if SS2 is selected. The voltage on the coupled inductors ubc will change its sign at half of the carrier frequency. Therefore, the high-order harmonics in ib and ic are around half of the carrier frequency. The dynamic performance of the inverter is also tested by experiment and the results are shown in Fig. 12. The test condition is the same as the simulation. Clearly, the level number of the output voltage increases from three to ve when the modulation index changes from 0.4 to 0.8. A little difference is generated between ib and ic at the transient state. However, the fundamental components of the two currents also become balanced later while the ripple components are complementary to each other. All these experimental results t the simulation results well and show the validity of the proposed topology with the optimized modulation scheme. VII. CONCLUSION This paper proposed a novel single-phase ve-level inverter based on coupled inductors. This inverter can output ve-level voltage with only one dc source and no split of the dc voltage capacitor, totally avoiding the voltage balancing problem. The height of the staircase in the output voltage is only half of the dc-link voltage under any modulation index. Meanwhile, the voltage stresses on all the power switches are the same and only four switches are operated at high frequency. Operation mechanism of this inverter was analyzed and the optimized switching patterns were also presented to minimize the passive component. Verication results show validity of the proposed topology together with the modulation method. The coupled inductors may be the aw of this converter. However, the switches taking the high current have low-switching frequency while the switches taking the low current have high-switching frequency. There-

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[25]

[26]

[27] [28] [29] [30] [31]

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Ping Wang was born in Shanghai, China, in 1955. He received the B.S. degree from Lanzhou University, Lanzhou, China, in 1980. Since 1980, he has been with the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China, where he become an Assistant Engineer in 1985, a Senior Engineer in 1993, and a Professor of Power Electronics and Drives in 2008. From 1995 to 1996, he was a Visiting Researcher with the Fraunhofer Institute for Production Systems and Design Technology, Berlin, Germany. His research interests include power electronics, static power converters, active lter, and ac drives. Prof. Wang is a member of the China Electrotechnical Society.

Zixin Li (S08M10) was born in Hebei Province, China, in 1981. He received the B.Eng. degree in industry automation from North China University of Technology, Beijing, China, in 2001 and the Ph.D. degree (Honor) in power electronics and power drives from the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, in 2010. He joined the Institute of Electrical Engineering, Chinese Academy of Sciences, in 2010, where he is currently a Associate Professor. His research interests include circuit topology, control and analysis of power converters, especially multilevel converters in high-power elds. Dr. Li has received many honors and awards, including the scholarship awarded to excellent Ph.D. candidates at the Graduate University of Chinese Academy of Sciences offered by the Australia company BHP-Billiton in 2009 and the student scholarship at the IEEE ISIE in 2009.

Yaohua Li was born in Henan, China, in 1966. He received the Ph.D. degree in 1994 from Tsinghua University, Beijing, China. From 1995 to 1997, he was a Postdoctoral Research Fellow in the Institute of Electrical Machine, Technical University of Berlin, Berlin, Germany. He joined the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China, in 1997, where he is currently a Professor and Director of the Laboratory of Power Electronics and Electrical Drives. His research interests include analysis and control of electrical machines, and power electronics.

Fanqiang Gao (S10M11) was born in Hubei, China, in 1984. He received the B.Eng. degree in control science and engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2006, and the Ph.D. degree in power electronics and power drives from the Institute of Electrical Engineering, Chinese Academy of Sciences, Beijing, China, in 2011. His research interests include design, digital control, and analysis of power converters.