You are on page 1of 52

ECE 755

TUTORIAL 2

USING IC STATION

TUTORIAL 2
PART 1: Design and layout using standard cells ............................................................ 3 A) Design Entry .............................................................................................................. 3 B) Standard cell layout using IC station ......................................................................... 4 i) Creating a cell.......................................................................................................... 4 ii) Automatic layout .................................................................................................... 5 PART 2: Design and layout using standard cells ............................................................ 8 A) Layout........................................................................................................................ 8 i) Creating a cell.......................................................................................................... 8 ii) Viewing the design................................................................................................. 9 iii) Placing components in your design..................................................................... 10 iv)Adding well contacts ............................................................................................ 11 v) Routing your cell .................................................................................................. 12 vi)Placing contacts and vias...................................................................................... 13 vii)Placing ports ........................................................................................................ 14 B) Layout Verification DRC and LVS ...................................................................... 15 i) Design Rule Check (DRC) .................................................................................... 15 ii)Layout Vs Schematic (LVS) ................................................................................. 16 iii)Correcting LVS errors.......................................................................................... 17 PART 3: Hierarchical design......................................................................................... 19 PART 4: Diffusion sharing and transistor folding......................................................... 23 A) Diffusion sharing ..................................................................................................... 23 B) Transistor folding..................................................................................................... 26 PART 5: Placing IO pads............................................................................................... 31 i) Design Architect.................................................................................................... 31 ii) IC station .............................................................................................................. 33 PART 6: Post layout simulations using net list extracted from layout.......................... 38 PART 7: Simulating designs using Accusim................................................................. 42 PART 8: Using strokes in IC station ............................................................................. 48

PART 1: Design and layout using standard cells


A) Design Entry
This tutorial will take you through the steps involved in the creation and layout of designs using standard cell components. This tutorial has three parts. In the first we shall create a simple logic circuit in DA-IC using standard cells. Digital simulation of this circuit can be carried out using quicksim II as described in the quicksim tutorial. In the second part we will make an auto-layout of the design in IC -station. Finally we will perform post layout simulations using quicksim. 1) Invoke DA-IC by typing in adk_daic at command prompt and open a new sheet. 2) Figure 1 shows the schematic of the logic circuit to be used in this tutorial. All gates in this circuit are standard cell components. We can find the standard cell components in Schematic_edit palette Library Standard Cells Basic Logic Gates

Figure 1 3) Perform check sheet on the design. You might get some warning messages as shown in Figure 2. Ignore them. File Check Schematic

Figure 2 5) Create viewpoints as described in DA-IC part1 tutorial.

Reminder: Schematic_edit palette View point is tsmc035a

TSMC035 OK End Sim

B) Standard cell layout using IC station


i) Creating a cell
1) Invoke IC station by typing adk_ic on command line. Select create from the IC Session palette menu to open a new IC- sheet. 2) In the create dialog box choose With connectivity and In the box named EDDM schematic viewpoint select the layout viewpoint of the schematic. The layout viewpoint will be in your schematic directory. Click on logic loading options and select flat (do not forget this, or your tool might crash!). 3) Choose Ninety for the angle mode. 4) Now select the following as shown in Figure 3. Attach library: $ADK/technology/ic/tsmc035 Process : $ADK/technology/ic/tsmc035 Rules File : $ADK/technology/ic/tsmc035.rules

Figure 3

ii) Automatic layout


5) Now select Place & route option from the IC palettes menu. 6) Now click the autofp option from the place & route menu on the right. Click Ok in the dialog box that appears. Your screen will look like the one in Figure 4. The box enclosed by solid bars along each edge shows how the cells are going to be organized. Note: The options in the autofp window can be changed to get different floor plans.

Figure 4 7) Now choose stdcel from the place & route palette menu under "Autoplc". This will place the standard cells as shown in Figure 5. You will now see the standard cells placed in the floorplan box. Cell locations are determined by their interconnectivity.

Figure 5

8) Now select Ports from the Place & Route palette under "Autoplc". You will see lightly shaded areas along the port bars at the edge of the layout. By clicking on these shaded areas you get a message with the name of that particular port. Alternatively, after you first place the ports automatically, you can select some of them and place them individually at the location that you prefer. 9) Now select Autorou All from the Place & Route palette and press OK in the small window that pops up at the bottom of the screen. This should route all the connections in the design. 10) The layout that is generated is not compact enough. To eliminate un-necessary space we can use the layout compactor tool. Choose Compact. Compact the layout in both the horizontal and vertical directions. So select the down option and then run the compactor with the left option. Note: Do not compact more than once in a given direction. 11) Select setup IC Peek on view Refresh the screen by either zooming in or zooming out (Other way to refresh View should be a good representative of what is present on your screen.

Redraw). Figure 6

Figure 6 11) Now perform the design rules check. To do this select ICrules check from the IC palettes menu.

11.1) The DRC tool of IC station checks if your layout conforms to the design rules. DRC can be run on the entire layout of even a part of it. In this course we are using the design rules for the tsmc035. 11.2) If there are no design rule violations the status bar will be similar to the one shown in Figure 7. If there are errors the Total results field of the status bar will not be zero.

Figure 7 11.3) To see where and what the errors are select DRC->First. This shows the first error. For other errors keep selecting DRC->Next. 11.4) Once you are done with a check you can delete the results by selecting DRC->Delete All. This will remove the error markings from the layout. 12) Perform a LVS check on the layout. The Layout Vs Schematic tool of IC station checks if the layout matches the schematic in various aspects, Nets, Ports and number of nmos and pmos transistors. 12.1) To run LVS first close the logic window and then select Verifdp LVS in the IC pallettes menu on the right. In the dialog box that appears choose the sdl viewpoint of the schematic (like the way you had done while creating the layout) in the Source Name text box. 12.2) Once the LVS check is made the status bar will read "Mark results database loaded". You can view the results of the check by selecting Report LVS in the ICtrace(M) menu. A smiley face in the reports means your layout has passed the check.

Figure 8: LVS passed

PART 2: Design and layout using standard cells


A) Layout
Start IC station by typing adk_ic at the command prompt. This is an enhanced version of IC Station.

i) Creating a cell
We will create a schematic driven layout of a single inverter (that has two transistors). Select CREATE from the menu on the right hand side of the screen. A form titled CREATE CELL will appear. Enter the following, and then click OK: Cell Name: $PROJ_PARTS_<login_name>/<cell_name> Process: $ADK/technology/ic/tsmc035 Rules File: $ADK/technology/ic/tsmc035.rules Angle Mode: 90 Connectivity? With connectivity EDDM Schematic Viewpoint: <design_name>/sdl Logic Loading: Flat (Click on logic loading options) It is very important to change the logic loading to flat. Since you are not using a standard cell library for your design, you should leave the library line blank. If you wish to use the default technology of AMI05, you can leave the process and rules lines blank, also. They are loaded by default. Figure 1 shows a snapshot of the create cell. It is important that you specify the SDL viewpoint.

Figure 1: Create cell

ii) Viewing the design


Select DLA layout->Logic->open. Your schematic will open in another window. Once the empty cell has been opened, you should go to the DLA Layout menu via the palette menu. This will bring up the following palette (Figure 2) which has the most often needed functions for doing your SDL design. This palette has the most frequently needed items for performing SDL work. The top of the menu has two options for moving to other palettes: Device and Edit. Device takes you back to the DLA Device palette and Top takes you back to the top IC palette where you came from. 1) Logic section of the Pallet This section of the palette has functions for setting the viewpoint of the logic source, closing the schematic view and updating the EDDM database if changes are made while the viewpoint is open. The Open menu item will open the selected logic source window. 2) Place section This section has functions for selecting instances and ports. The Inst item lets you place your instances from your schematic into your layout. The AutoInst item will automatically place all unplaced or selected instances into your layout. Port will place ports from your schematic into your layout. 3) DEdit section The DEdit section provides functions for editing your placed devices. Such options are to move your MOSFET pins within your device; you can also split, join and fold your devices to make your layout more efficient. The Clean function will do a cleanup of your design should another function fail and leave your items selected or seemingly frozen. 4) Route section This section has many functions for routing, making ports, adding and removing items from a net and so on. 5) Edit item This provides a set of functions to change your device, and a few commonly used editing functions from the standard edit palette menu. You can place shapes, move, copy, flip, rotate, measure, etc. By using these, you don't have to change palettes for the most common operations. Figure 2:DLA layout palette 6) Drc section

Figure 3: Logic displayed with layout window on the left

iii) Placing components in your design


Auto Place instances You can quickly place all of your instances in your schematic into your cell by clicking on AutoInst in the ADK edit menu. The positions of the devices will resemble the placement of the schematic instances. That is, if a transistor is above another one in your schematic, it will be in your layout, also. Once the devices are placed, you can move them to fine-tune the placement. You will see overflows (yellow lines) between the pins of the devices that will help you to see the connectivity in your design. Use these as guides when moving your devices around. However, on account of some bugs in the software, there are times when even after making the connection, there are still overflows!!!! Therefore always confirm the connectivity in the layout with your design. If you only want to place some of the components, select them in the schematic and then click on AutoInst to instantiate only the selected item(s). Alternate approach: Manually placing instances If you prefer more control over initial placement of your devices, you can place them, manually. To do this, select the instance(s) that you wish to place in your schematic. Then click on Inst in the palette menu. A ghost image of each component, one at a time, will appear in your layout window. Click where you want to place this instance and then the next one will appear and you continue this procedure until all selected instances are placed. Again, you will see overflows to help you locate the best placement. In addition, you will see the current instance highlighted in your schematic. Once placed, the devices can be moved around your cell as any object.

10

Figure 4: Transistor layout with overflows Inorder to see the inside of the layout, you might sometime have to use the peek option. This is possible by Setup(top menu) IC PEEK ON VIEW, followed by refreshing (This setting holds for the entire session). Alternatively, you can use can just type peek 60 (the number is just an example) followed by refreshing the display. In Figure 4 you can see an nwell and a pwell. You need to separate both wells by 18 lambda(as stated in the tsmc035 rules file). You can use a ruler to this. Type add ruler or add ru and drag the ruler. To delete the ruler place del ruler or del ru. There is another way to measure distance. When you zoom in you can see pixels of minimum resolution (mouse pointer cannot be placed between these). The distance between two such pixels is 0.5 lambda. Finally to move Fets or any other objects you can use the Edit->move menu on the top.

iv)Adding well contacts


You will almost certainly want to add well (or bulk) contacts to your cells as well. These will tie your wells or bulk to metal so you can properly bias it as necessary. Again, there are two macros that make this a little easier. nwc will place an n-well contact into your cell where you click pwc will place a p-well contact into your cell where you click Both macros place a cell that has been predefined with proper rules to pass DRC. The bottom of the n-well contact is designed to abut to your n-well and the top of the p-well contact is designed to abut to your pwell. Keep this in mind if you decide to rotate or flip your contacts. You can always peek down into the contacts to see the full layout to better align your cells.

11

Figure 5: Layout with substrate contacts

v) Routing your cell


Once you have placed your components (or at least as many as you want to) you can route the overflows. There are many ways to route your design. All are manual or semi-automatic. There is no fully-automatic autorouting for SDL designs. Manual routing: Considering the inverter example, you will have to place some polysilicon wires. First, show the layer palette to make things easier. To do this operation, type sho la p (this stands for "show layer palette" but is easier to type). Now, while holding down the control key, click on the layers POLY and METAL1. If you need to scroll down the window, release the control key before scrolling, then hold it down again when clicking on the layers. Routing by using paths One way to manually route is to use paths. Paths are of a set width and you simply click at each point at which the path should touch. You can set the path to be defined from a center point or the left or right edge of the path. To add a path, click on Path in the ADK Edit menu (Object->Add->Path). The path prompt bar will appear and you will be able to specify the layer and width of the path via the Options button. You can also specify other options for how the path should be drawn. Once you have these options set, simply click at each point where you want the path to go. You will see the path being drawn as you go. Doubleclick at the end and the path will be complete. You can then go on and repeat this process for other paths you wish to place. Routing by placing shapes Optionally, you can have complete control over the size, shape and placement of the routes by placing geometric shapes, explicitly. You do this with the Shape command on the ADK Edit menu. When you click on Shape you are prompted for points that will define the corners of a polygon. You can use the Options button to select the layer on which the shape should be drawn. Coming back to the inverter layout, select Metal1 from the layer palette and then select the shape from DLA Layout palette. Draw power and ground rails next to pdiff and ndiff regions. When you are done your layout will be similar to the one shown in Figure

12

Figure 6: Layout with metal 1 routing Wire up the gate inputs with poly using paths. When you have made a complete connection, the overflow line will disappear. Be sure to follow the design rules! Two micron minimum width, three micron separation, etc. If you need to use metal, then you can simply click on the metal layer in the layer palette. Hence, placing paths to wire your circuit becomes fairly easy. Also remember to change the width as needed. Be sure to wire all the overflows. Also be sure to wire the correct pins to the power and ground rails.

Note: Use metal connections in one direction. Normally Metal 1 is used for horizontal connections and M2 for vertical ones(define it for your layout and try to stick to it). Following this reduces a lot of trouble in complex layout and also keeps the layout neat. Of course there can be exceptions as in this inverter example(small connections).

vi)Placing contacts and vias


Sooner or later you will need to place contacts from metal to poly or vias between metal layers. If you are using the routing tool then vias within your routes are places automatically. Contacts to poly and other methods of routing will require manual contact/via placement, however. There are some handy macros that have been defined in the ADK that will make placing contacts and vias easier. 1) pc (or poly contact) macro will place a poly contact to metal1 centered at the current cursor position. 2) pp (or place port) macro will let you place a port contact (a via from metal1 to metal2 and some blockage layers) where ever you click once the ghost image appears. Keep in mind that unless you change the port layer, all ports will be on metal2. You will need to place a port contact (or via) to get to metal1 to connect your port to metal1. Don't forget to do this!

13

Figure 7: Layout with contacts & vias

vii)Placing ports
Final step in the layout is adding ports. Ports are placed on metal connections. Ports should be of the same metal as that of the connection on which they are placed. To place ports choose Object->Add->shape and draw a 4 lambda x 4 lambda square (Can vary in size) and then choose Object->make->port. A small dialog box will appear at the bottom of the window. Enter the values in this box as per Table 1. Port purpose VDD GND Input Output Table 1 Direction In In In Out Type Power Power Signal Signal

14

NOTE: You might not be able to see the name of the ports. In that case Setup->IC->Port/Pin name display to ON. The final layout will look like the one in Figure 8.

Figure 8: Completed layout with ports.

B) Layout Verification DRC and LVS


i) Design Rule Check (DRC)
The DRC tool of IC station checks if your layout conforms to the design rules. DRC can be run on the entire layout of even a part of it. In this course we are using the design rules for the tsmc03( remember when setting up the SDL, we had selected the tsmc035 rules file !!!) 1) To run DRC select DLA layout DRC->check in the menu on the right. This check can be performed on the entire layout at the end or on a specific part of the design (by selecting the region) (Recommended while doing the connectionscheck DRC at regular intervals.) The design rules can also be checked from the ICpalettes. ICrules sections has a number of options for the same. You can perform the check on whole or a part of the layout using correct option under Setup scan. Also if there are design rule violations, you can view the errors by choosing the appropriate option.(first next etc in the set Scan to) and can view the DRC report by clicking on report in the palette. 2) If there are no design rule violations the status bar will be similar to the one shown in Figure 9. If there are errors the Total results field of the status bar will not be zero.

15

Figure 9: DRC message 3) To see where and what the errors are select DRC->First. This shows the first error. For other errors keep selecting DRC->Next. The error will be highlighted in the layout as shown in Figure 10. The type of error is displayed on the status bar. 4) Once you are done with a check you can delete the results by selecting DRC->Delete All. This will remove the error marking from the layout.

Figure10: DRC error

ii)Layout Vs Schematic (LVS)


The Layout Vs Schematic tool of IC station checks if the layout matches the schematic in various aspects, Nets, Ports and number of nmos and pmos transistors. 1) To run LVS first close the logic window and then select Verifdp->LVS in the IC pallettes menu on the right. In the dialog box that appears choose the sdl viewpoint of the schematic (like the way you had done while creating the layout) in the Source Name text box. 2) Once the LVS check is made the status bar will read "Mark results database loaded". You can view the results of the check by selecting Report->LVS in the ICtrace(M) menu. A smiley face in the reports means your layout has passed the check.

16

Figure 11: LVS passed

iii)Correcting LVS errors


Now let us see how to use the LVS report to correct the errors in our layout. Figure 11 shows a layout with no connection between the drains of the nmos and pmos.

Figure 12: LVS error This will be indicated in the LVS report obtained using report LVS.In the report scroll down to the table named "NUMBER OF OBJECTS AFTER TRANSFORMATION" as shown in Figure 12. The table shows the inconsistencies in the number of Nets, Instances and Ports. Here instances mean transistors. In the component type column mn and mp refers to nmos and pmos transistors.

17

Figure 13: LVS report The table shows that there are two extra net in the layout than in the source. Explanation for this is that in the schematic there is a VDD, GND, a connection between gates, and a connection between the drains of the pmos and nmos, whereas in the layout each drain is now a separate net and the there is also a dangling port connection. When you scroll down further, you will see a detailed description of the errors as shown in Figure 13. This table shows that there is connection between I$1:D and OUT, which is absent in the layout. Here 'I' means instance, '1' refers to the instance number and 'D' refers to the drain. To identify the FET refered by I$x select a FET in the logic window and then select Report->Object->Short. This will give you the I$ reference of the selected device. This can be done for nets also. The report also shows that there are two drain nets in the layout which are absent in the schematic. This table also gives the coordinates of the discrepancies, which can be tracked in the layout window. Once the errors are taken care of, run the LVS again and hopefully the next time you will be able to see a smiley face !!

Figure 14: LVS report with error details

18

PART 3: Hierarchical design


This tutorial guides you through the process of creating hierarchical designs. In this tutorial we will make the layout of two inverters in series. In order to proceed with this tutorial you should have laid out a inverter in IC station. Also, you should have created a schematic with both your inverters in Design architect and should have run the adk_dve on the schematic. 1) Create a sheet in IC station as you did for the basic inverter cell (Steps 1 - 5 in first tutorial)Be sure to select logic loading options->Flat in the Create Cell dialog box. 2) Select Objects->Add->Cell. Enter the full path to the cell in the dialog box that appears and then place the cell. Your sheet will look similar to the one shown in Figure 1.

Figure 1 3) In order to view the cell, select peek on view in the Setup->IC dialog box. 4) Following step 2 add another cell as shown in Figure 2.

19

Figure 2 1) As per the schematic we have substrates of both the nfets at the same potential (GND) and that of the pfets at the same potential (VDD). Hence we can "abut" the cells as shown in Figure 3. We can do this even in the basic cells. You should not do this between a nmos and a pmos.

Figure 3

20

6) Next step would be to make the necessary connections between the two cells. A point to note in Figure 3 is that there is no need to make explicit connections between the OUT of the first inverter and IN of the second inverter or between the power lines of the two cells. This is because the layout of the basic cell and the hierarchy has been planned such that the lines to be connected touch or overlap when the cells are abutted. This will avoid additional routing. 7) Ports at this level need to be placed. In this case we need the following ports: IN, OUT, VDD, GND. After placing the ports the final layout will look like the one in Figure 4. You can place ports on the ports belonging to lower level cells as in case of IN port in the figure (you cannot distinguish between the two by just looking at them).

Figure 4

21

8) To distinguish between ports of the current hierarchy and the lower ones, select the port. If the port you selected belongs to this hierarchy, you will get a message on the status bar similar to the one in Figure 5. This message was displayed when the OUT port of the current context was selected. If you select a port of a lower level cell you will get a message similar to the one in Figure 6. This message was displayed on selecting IN port of one of the inverter instances.

Figure 5

Figure 6 9) All this while your current working context was the topmost level. You can set your contexts to cells at lower levels. In our case we can edit the basic inverter cell by choosing Context->hierarchy->Set context and either click on the desired cell or enter the full path to the cell in the dialog box that appears. NOTE: Any change made to the cells in the lower context will change permenantly change that cell when saved. Hence the change made will reflect in every instance of that cell at all hierarchies in the current layout and even in other layouts. 10) To move higher in the hierarchy, choose Context->hierarchy->set context up and enter the number of levels. 11) While saving the layout you can specify whether to save the current context or the entire hierarchy by using File->Cell->Save cell menu.

22

PART 4: Diffusion sharing and transistor folding


This tutorial will take you through the process of sharing diffusion regions of transistors and folding large transistors

A) Diffusion sharing
When the source or drain 2 transistors of the same type form a net as in Figure 1, their diffusion regions can be shared. In Figure 1 the 2 nmos devices of the AND gate have their drain and source connected.

Figure 1 On sharing the diffusion regions the layout of both the transistors will look similar to the one in Figure 2. Since we are in the connectivity mode we can identify the transistors and their terminals by selecting them in the layout.

23

Figure 2 How to share diffusion regions? Create the ICstation sheet in normal fashion. The parameters for sheet creation are repeated below. Connectivity EDDM schematic viewpoint Logic loading options Angle mode : : : : With connectivity SDL viewpoint the of the schematic Flat Ninety

Method 1 1) The easiest way to share the diffusion regions is to autoinstantiate the schematic and let IC station figure out the transistors and the regions to be shared. 2) When the schematic of the AND gate in Figure 1 is auto-instantiated (AutoInst in the DLAlayout menu on the right) we get the layout similar to the one in Figure 3.

24

Figure 3 3) In Figure 3, we can see that the drains of the pmos are also diffusion shared as they have their drains connected to OUT. We can also note that a active contact is placed in case of pmos alone as their is a connection (OUT) to be made to the shared region. Method 2 4) The second method is to manually choose the transistors for diffusion sharing and instantiate them. This will instantiate the transistors after sharing the diffusion regions. The regions are correctly picked by ICstation. To do this click on the 2 transistors in the schematic window and select the Inst option from the DLAlayout menu on the right. If you chose the nmos, the layout will be similar to the one in Figure 2. Method 3 5) The third method is to manually pick the transistors and the regions to be shared. To do this the devices should be placed seperately. Now select the regions to be shared in the layout. In this example we choose the pmos and the their sources. 6) Now select DLAlayout->device->edit->join and click on OK in the box that appears at the bottom. The layout will similar to the one shown in Figure 4.

Figure 4 7) We can also split shared devices. Just select the shared region and click on DLAlayout->device->edit>split and then click on OK in the box that appears.

25

B) Transistor folding
In some circuits due to the required sizing of devices, we end up with a very odd aspect ratio for the layout. An example of such a circuit is shown in Figure 5. It is basically an inverter with W/L (nmos) = 1024/8 and W/L(pmos) = 64/8. If this schematic is auto-instantiated, it will look like the one in Figure 6. The wide p-device can be laid as 'n' parallel fets so that a better aspect ratio can be achieved. This technique is called folding.

Figure 5

26

Figure 6

How does folding work? Large transistors can be split into smaller ones and then shorting the corresponding terminals making up the required W/L. In such an arrangement we can share the diffusion drain and source of adjacent transistors and then we can short the terminals as shown in Figure 7. This also reduces the diffusion capacitance. Anyway, we need not be concerned about the whole process of splitting the transistor and sharing the diffusion regions. ICstation will do that for us. All we need to do is the shorting of corresponding terminals.

27

Figure 7 1) Select the gate of the transistor to be folded in the layout and then select DLAlayout->device->edit>fold. 2) A dialog box will appear at the bottom. Number of legs as required by the box is the number of parallel transistors into which you would like to split the large device. In this case we enter '8'. The layout will now look like the one in Figure 8.

28

Figure 8 3) In Figure 8 we can see 8 gates and alternating source and drain (you are in connectivity mode, so you can figure this out). Now we need to short the source, drain and gates of the devices. Let us take the case of shorting the drains. For this you might need to place poly contacts as in Figure 9 for all gates. You can use relative copy (rel copy) for this. 4) Select the block you need to replicate in this case the poly and the poly contact as in Figure 9. now select DLAlayout->rel copy. In the box that appears enter the number of copies and the distance between each. The layout will now look like the one in Figure 10.

Figure 9

Figure 10

29

5) In the same way short the drains and sources. The final layout will look like the one in Figure 11.

Figure 11

30

PART 5: Placing IO pads


After completing the layout (LVS and DRC) for the entire chip, the final step is to place the pads for the inputs and outputs. This has to be done in both the schematic as well as the layout. This tutorial will walk you through the placement of pads for a sample circuit.

i) Design Architect
1) Create a symbol for your final schematic. Open a new sheet in DA-IC and place the symbol. 2) There are three types of pads you will using here. They are signal pads, Vdd pads and ground pads. All signal inputs and outputs are connected to the pad named PadARef. Vdd and ground lines are connected to a pads named PadVdd and PadGnd. 3) All pads are found in $ADK/lib/pads/tsmc035. For placing a pad in design architect click on add>instance from the schematic_edit palette. In the navigation box enter the above path. For example to get a signal pad enter $ADK/lib/pads/tsmc035/PadARef. Figure 1 shows a signal pad connected one of the inputs.

Figure 1

31

4) The Vdd and Gnd pads are placed in similar fashion. These pads need to be connected to Vdd and Gnd respectively as shown in Figure 1. 5) As we can see in Figure 1 the pads have a default name 'PINxx'. Similar to naming ports, each pad should be given a name. To do this just select the name by placing the cursor on it and pressing F1 key. Then right click and choose the change values option to change the name. 6) The final schematic will look similar to the one in Figure 2.

Figure 2

32

ii) IC station
1) Create a new schematic in usual manner and place the cell (the complete layout). 2) To place a pad, choose the Objects->add->cell option from the menu on the top. In the box that appears are the bottom of the screen entire the following $ADK/technology/ic/pads/tsmc035/pads/<pad name>. Pad name is PadARef for signal pad, PadVdd for Vdd and PadGnd for Gnd. 3) An important point to note is that all signal pads should get power, hence need to be connected to the Vdd and Gnd pads. 4) Pads are shown in Figure 3. They are signal, vdd and gnd pads in top-down order. Adjacent pads are abutted. For correct abutting the green borders of the pads must align as shown in Figure 4.

Figure 3

33

Figure 4a

Figure 4b

5) Figure 5 shows 20 pads being placed around the cell. The vertically placed pads on the right side are connected to the Vdd and gnd, as they are abutted. Others need to be connected.

Figure 5

34

6) These connections can be made with the help of a connection pad called PadlessCorner. This pad can be found in the same location as the other pads. Place the PadlessCorner pads as shown in Figure 6.

Figure 6 7) Connections between the pads will be made with Metal2. The red lines in Figure 7a show the number of metal lines required their placements. Figure 7b shows the completed connection. Do not run the metal lines deep into the pads, it will cause DRC error.

Figure 7a Figure 7b

35

8) After connecting all the pads in corners to PadlessCorner pads, the inputs, outputs, vdd and ground need to be connected. All signals and power lines will be connected as shown in Figure 8 which shows the connection for GND.

Figure 8

9) After completing all the connections. The final layout will look like the one in Figure 9

Figure 9

36

10) On running DRC on the final layout you will get few errors. The number of errors you get should be equal to the number of pads you have. And the error will like the one shown in Figure 10. Ignore these errors.

Figure 10

37

PART 6: Post layout simulations using net list extracted from layout
The most accurate way to do post simulations is by extracting the net list from the layout. This tool is useful for those who claim their layout conforms with the schematic and blame the tool for LVS errors. Getting correct simulation results using this technique will prove that your layout is correct (as long as your test vectors are adequate). 1) To get started you need to create a directory 'eldo' in your ~/mgc directory. 2) Create your layouts in IC-station as usual. Run DRC and LVS checks. 3) Type 'spc' in IC-station this will create a <layout name>.sp file in the ~/mgc/eldo directory, where layout name is the name of the layout given in the create dialog box. Note: In order to do this the ports should be named correctly as per the schematic. 'spc' would run even otherwise but your etracted netlist will not simulate correctly. 4) A sample.sp file of the inverter we will be simulating is shown below. * File: /home/mamidi/example.sp. Creation time: Oct 20 23:44:25 2002 .subckt c2v Cx GND phs1 phs1_bar phs2 phs2_bar Rref VB1 VB2 VB4 VB5 VDD Vin Vout + VR VRDIV2 * devices: m0 5 VB5 1 1 p l=3u w=27u ad=44.55p as=44.55p m1 VDD VB1 VB1 VDD p l=6u w=4.5u ad=7.425p as=7.425p m2 VB2 VB2 VB1 VB1 p l=6u w=4.5u ad=7.425p as=7.425p m3 9 15 17 17 p l=3u w=25.05u ad=45.09p as=40.545p m4 25 VB1 VDD VDD p l=6u w=4.5u ad=7.425p as=7.425p m5 17 15 9 17 p l=3u w=25.05u ad=45.09p as=45.09p m6 9 15 17 17 p l=3u w=25.05u ad=45.09p as=45.09p m7 26 VB2 25 25 p l=6u w=4.5u ad=7.425p as=7.425p m8 17 15 9 17 p l=3u w=25.05u ad=45.09p as=45.09p m9 9 15 17 17 p l=3u w=25.05u ad=45.09p as=45.09p m10 VDD 5 1 VDD p l=16.5u w=4.5u ad=7.425p as=7.425p m11 17 15 9 17 p l=3u w=25.05u ad=45.09p as=45.09p m12 VB5 VB5 VDD VDD p l=16.5u w=4.5u ad=7.425p as=7.425p m13 27 VB4 9 9 p l=1.5u w=13.5u ad=22.275p as=22.275p cp41 16 14 0.352f cp42 17 GND 159.773f cp43 17 9 0.352f cp44 17 VB5 1.5724f cp45 17 14 0.88f cp46 17 15 5.4384f cp47 VRDIV2 GND 108.727f cp48 VRDIV2 GND 0.176f cp49 VRDIV2 14 4.1438f cp50 VRDIV2 15 0.176f cp51 VRDIV2 17 7.8958f cp52 phs2_bar GND 12.3087f cp53 phs2_bar GND 0.176f cp54 phs2_bar 15 0.1188f cp55 phs2_bar VRDIV2 0.2948f .ends c2v The first line in this file is a comment (comments start with a '*'). The line starting with .subckt defines the interface of the layout cell. The name of the subcircuit c2v is the same as the name of the layout cell. The

38

list of the cell ports follows (including VDD and GND). Following this is the description of all the devices in the layout. The devices are described as follows: * Letter 'm' specifies a mos device. * The following four numbers specifies the connections of the four terminals of the device. * Letter 'n' or 'p' specifies a n-mos or a p-mos. * This is followed by the length and width of the device in microns. * 'ad' and 'as' are the area of drain and source respectively. This is used to calculate the diffusion capacitances Following the description of the devices is the list of parasitics. Capacitances between various interconnects and GND as well as between interconnects (coupling capacitances) are listed. The statement .ends <layout name> appears at the end of the .sp file. 5) As the next step you will be writing a command file (.cmd). The command file describes all the input voltage sources similar to the include file in eldo. As an example let us take a .sp file for an inverter shown in Figure 1.

Figure 1

* File: /pong/usr5/p/mamidi/mgc/eldo/tmpinv.sp. Creation time: Sat Nov 16 19:37: 47 2002 .subckt tmpinv GND IN OUT VDD * devices: m0 OUT IN VDD VDD p l=0.4u w=1u ad=1.1p as=1.1p m1 OUT IN GND GND n l=0.4u w=1u ad=1.1p as=1.1p * lumped capacitances: cp1 OUT GND 1.2528f cp2 IN GND 1.4122f cp3 VDD GND 1.0576f .ends tmpinv A sample command file for this .sp file is as shown below: vdd VDD GND dc 5V Vgnd GND 0 dc 0

39

Vin IN GND pulse(0 5 0u 1n 1n 500u 1m) x1 GND IN OUT VDD tmpinvtmp .tran 100n 5m 0u 10u .probe tran v(IN) v(OUT) .end The first three lines describe the voltage sources. Their description is similar to those in the eldo include file. Following this is the sub-circuit declaration. 'x' is used to specify a sub-circuit declaration. '1' is the number or name assigned to the sub-circuit. This is like instantiating a sub-circuit. The .tran statement specifies a transient analysis. The .probe statement specifies the outputs you want to view. 6) Next step would be to concatenate the .sp file, model file and the command in the same order in a .cir file. Use the following commands to do that: cat filename.sp > filename.cir cat $ADK/technology/accusim/tsmc035.mod >> filename.cir cat filename.cmd >> filename.cir 7) You need to make one change in the .cir file. Delete the line that reads .ENDL 8) Now you are all set to run eldo in the command mode on the .cir file that you created. To do this type eldo filename.cir 9) This will show some warnings related to .LIB NOM etc. Ignore those warnings. Errors related to the .cmd file need to be debugged for the simulation to run. 10) On running the simulation successfully you will find a .cou file with the same name as the .cir file. This file contains the waveform database which can be viewed using a view called xelga. 11) type 'xelga' at the prompt. The xelga control panel shown in Figure 2 will appear with all the .cou files found in the current working directory listed. Double click the .cou file of interest.

Figure 2

40

12) The page composition dialog box shown in Figure 3 will appear. To chart each signal click on 'new' under graph commands and then select the signal and click on apply. If you don't create a new graph for each signal, the charts will be overlapped. The IN and OUT for this inverter is shown as in Figure

Figure 3

Figure 4

41

PART 7: Simulating designs using Accusim


This tutorial provides a step-wise explanation on using the Mentor Graphics electrical simulator. It provides a graphical user environment for simulating your designs in various modes, DC, Frequency and time. In this tutorial we will use the dc sweep and transient mode. An inverter shown in Figure 1 will be used a an example throughout the tutorial.

Figure 1 1) After creating the schematic and the viewpoints in DesignArchitect-IC run the adk_dve script as follows to create the accusim viewpoint. adk_dve -technology tsmc035 <schematic name> This script should be executed from the directory in which your schematic resides. 2) Start accusim by typing accusim <schematic name>/accusim . This will invoke the accusim window with the schematic. 3) Accusim uses a model file which specifies all technology dependent device parameters. This model file should be included into accusim by selecting File->auxillary files->load model library and then navigating to $ADK/technology/accusim/tsmc035.mod

DC analysis:
In DC analysis we sweep the input voltage of the inverter from 0 to 5V to obtain the characteristics of the inverter. 4) Choose DC from the mode palette (on the right hand side). 5) Now select the input to be swept by selecting the corresponding port. Choose setup analysis from the mode palette. This will pop-up the setup analysis dialogbox. 6) In this dialog box select dc sweep and also enter the starting and ending values for the sweep in the from and to text boxes respectively. For now leave the increment value box empty. For this experiment we sweep the input of the inverter from 0 to 5V as shown in Figure 2

42

Figure 2 7) Now select run to run the simulation. In the Add keeps dialog box that pops up select ALL (to view all signals in the circuit). 8) Once the simulation completes, select the signals you want to view and click on chart in the mode or the result palette. This will plot the input and the output waveforms as shown in Figure 3

43

Figure 3 9) A cursor can be added to the window by typing add cursor. Transient analysis: 10) Select time and setup analysis from the mode dialog box. 11) Enter the stop time for simulation. In this experiment we simulate a time interval of 5m. Note: Enter 'm' for milli and 'u' for micro 12) Now we need to force the input to the inverter. Select the input and choose add force from the mode dialog box. This pops-up the force dialog box. 13) We can specify a DC input by choosing DC and entering the magnitude. In the time mode we can choose between the various input waveforms as mentioned in the dialog box. In this experiment we select a pulse input as in Figure 4. Enter the following parameters: Initial value - 0V Pulsed value - 5V Frequency - 1KHz ('k' for kilo, 'm' for mega) duty cycle - 50%

44

Figure 4

14) Now run the simulation and chart the input and output as shown in Figure 5.

45

Figure 5 15) Another input waveform worth mentioning is PWL (piece-wise linear). Here we can specify timevalue pairs which specify the initial and final voltage and time of the ramp input. 16) Consider a sample input for PWL as shown in Figure 6. The input and output waveforms are charted in Figure 7.

Figure 6

46

Figure 7 17) To delete the forces, select the input force by clicking on the circle near the input port and press the delete key. Forces can also be deleted by choosing delete->forces from the menu and then choosing the required signals from the delete forces dialog box. 18) When you exit from accusim, Exit SimView dialog box is poped. choose without saving in this dialog box.

47

PART 8: Using strokes in IC station


Strokes provide a shortcut for performing various functions in mentor tools viz, copying, moving objects etc. Strokes are drawn using the middle mouse key. In IC station it is drawn on the layout sheet. IC-station interprets a stroke with reference to a 3x3 grid as shown in the figure below. -----------| 1 | 2 | 3 | -----------| 4 | 5 | 6 | -----------| 7 | 8 | 9 | -----------Hence every stroke traverses some elements of the grid one or more times. A number representing the grid elements traversed in the order of traversal is associated with each stroke. For example the figure below shows a stroke and its associated number.

Stroke# 4753

Some strokes in IC station

1) Invoke DRC: Stroke# 4753

48

2) Slicing a wire: Stroke# 7896321

3) Stretching a wire: Stroke# 321456987

4) Add Metal1 path 4 lambda wide: Stroke# 456

5) Add Metal2 path 4 lambda wide: Stroke# 258

6) Add p-well contact: Stroke# 147852365

49

7) Add n-well contact: Stroke# 147852369

8) Measure distance: Stroke# 3698789 Draw the stroke and then left click on the starting point and move the mouse in the direction you want to measure the distance. Left click again to come out of this mode.

9) Delete an object: Stroke# 741236987

10) To peek: Stroke# 15963

11) Unselect all : Stroke# 1478963

12) Add a via1: Stroke# 852

50

13) Add a poly contact: Stroke# 654

14) Add a poly path 2 lambda wide: Stroke# 74123654

15) Add a ruler: Stroke# 74123489

16) Set basepoint: Stroke# 1478987 Select the object and then set the basepoint.

17) Moving an object: Stroke# 74159

51

18) Copying an object: Stroke# 3214789

52