Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, and A. Paccagnella
Abstract—SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets (SEUs) that, by changing the FPGA’s configuration memory, may affect dramatically the functions implemented by the device. In this paper we describe a new approach for predicting SEU effects in circuits mapped on SRAM-based FPGAs that combines radiation testing with simulation. The former is used to characterize (in terms of device cross section) the technology on which the FPGA device is based, no matter which circuit it implements. The latter is used to predict the probability for a SEU to alter the expect behavior of a given circuit. By combining the two figures, we then compute the cross section of the circuit mapped on the pre-characterized device. Experimental results are presented that compare the approach we developed with a traditional one based on radiation testing only, to measure the cross section of a circuit mapped on an FPGA. The figures here reported confirm the accuracy of our approach.



ODERN SRAM-based field programmable gate arrays (FPGAs) offer high densities and in-system reprogrammability features that are very attractive for many electronic designs. Unfortunately, SRAM-based FPGAs are particularly sensitive to single event effects (SEEs) induced by high-energy ions [1], [2] and therefore they cannot be straightforwardly adopted in safety- or mission-critical applications, such as space-borne ones. Some works [1]–[3] have already investigated the sensitivity of SRAM-based FPGA devices to heavy ions, showing the probability for a particle to provoke a single event upset (SEU). This valuable information should, however, be coupled with indications about the probability for the circuit implemented in the FPGA to produce an error, i.e., the probability for an SEU to alter the expected circuit’s behavior in such a way that the circuit produces wrong output results. Although radiation testing is usually employed to measure SEU sensitivities, it is very expensive, and thus, more affordable techniques are needed. Moreover, the possibility of performing the analysis of SEU effects in the initial design phase, when only a model of the circuit is available, is becoming an increasingly important and necessary resource.
Manuscript received July 20, 2004. M. Violante, L. Sterpone, P. Bernardi, M. Sonza Reorda are with the Politecnico di Torino, Dip. Automatica e Informatica, 10129 Torino, Italy (e-mail: massimo.violante@polito.it; luca.sterpone@polito.it; paolo.bernardi@polito.it; matteo.sonzareorda@polito.it). M. Ceschia, D. Bortolato, and A. Paccagnella are with the Dipartimento di Ingegneria dell’Informazione, Università di Padova, 35131 Padova, Italy, and also with the Istituto Nazionale di Fisica Nucleare—Sez. Padova, 35131, Padova, Italy (e-mail: ceschia@dei.unipd.it; damib@dei.unipd.it; alessandro.paccagnella@unipd.it). Digital Object Identifier 10.1109/TNS.2004.839516

For this reason, researchers have investigated the use of simulation-based approaches for predicting the effects of SEUs. The methods proposed so far [4]–[6], although effective and accurate, are intended for the analysis of applications implemented as ASICs only. When the technology of interest is the SRAM-based FPGA, two complementary aspects should be considered: 1) SEUs may alter the memory elements the design embeds. For example, an SEU may alter the content of a register in the data-path, or the content of the state register of a control unit. 2) SEUs may alter the content of the memory storing the device’s configuration information. For example, an SEU may alter the content of a look-up table (LUT) inside a logic resource of the FPGA, or the routing of signals. As far as the former aspect is concerned, the available approaches are adequate. Conversely, the latter aspect demands much more complex analysis capabilities. The effects of SEUs in the device’s configuration memory are indeed not limited to modifications in the design’s memory elements, but may produce modifications to the interconnections inside a logic resource and among different logic resources. We have developed a simulation-based approach to address the aforementioned problem: through suitably defined fault models and an ad hoc developed simulation tool, our procedure is able to predict the effects of SEUs in the device’s configuration memory. After describing our approach, we report and discuss experimental results that compare the predicted SEU cross section with those obtained from radiation testing. These comparisons show that our method is quite accurate and that it can be used to predict the result of radiation testing. The main contribution of this work lies in the simulationbased procedure we described, and in the experimental validation we performed using radiation testing. II. PREVIOUS WORK The effects induced by SEUs on SRAM-based FPGAs have recently been investigated through radiation experiments (for example those reported in [1], [2], and [8]). The common denominator of these approaches is the adoption of a hardware set-up to expose the FPGA to radiation in order to measure the single event functional interrupt (SEFI) cross section of the FPGAs under investigation. An SEFI is generally defined as the result of an SEU that causes the device to stop operating properly. The mentioned approaches do not emphasize the analysis of the observed SEFI, i.e., the modifications induced by radiation on the FPGA’s configuration; therefore, they are valuable for understanding to what extent the specific circuit mapped on an

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we can compute the predicted cross section of the whole system. a better understanding of SEU effects on the FPGA’s resources can be exploited to identify new and efficient hardening techniques that may overcome the significant overhead that bedevils currently available techniques. It thus combines the effects of SEUs in the application layer with those in the physical layer.. Architecture of the fault-injection approach we developed. The application layer is a VHDL model that codes the netlist implementing the desired circuit. The physical layer is analyzed using the test-bed we introduced in [9]. This figure is the probthe predicted error rate. or during download operations [13]. routing resources.: SIMULATION-BASED ANALYSIS OF SEU EFFECTS IN SRAM-BASED FPGAs 3355 FPGA is resilient to SEU effects.. The purpose of this analysis is to characterize the FPGA device’s manufacturing technology from the point of view of sensitivity to radiation. radiation-testing experiments are performed to measure the cross section. thus simplifying the needed hardware set-up. the physical layer corresponds to the FPGA device on which the circuit is implemented. and memory elements (flip-flop. by changing the bitstream that is downloaded in the FPGA at power up. . to perform a final validation of the developed system. The important aspect of this approach is that the computation of the cross section does not depend on the application layer: in fact it may be performed by configuring the FPGA device with test circuits that are different from the application layer. As soon as both analyses are completed.e.e. which gives the probability for a particle to produce an SEU. On the one hand. For this purpose. circuit-oriented estimation techniques can be used during the early design phases to obtain quick feedback on the effects of SEUs. On the other hand. . erroneous output results.VIOLANTE et al. it may be exploited for any application using that technology. i. the two layers are analyzed independently. This approach identified the configuration memory’s bits responsible for each SEFI. the FPGA-based system is viewed as composed of two independent layers: the application layer and the physical layer. As an alternative to radiation testing. Conversely. we exploit the tools provided by the . but they provide few hints on the possible causes of SEFIs. and reviewed in Section III-D. and it is independent of the application using it. Some of them exploit run-time reconfiguration [11]: the FPGA is initially programmed with a fault-free bitstream and allowed to operate for some number of clock cycles before the bitstream is changed to emulate the effects of SEUs affecting the device’s configuration memory. 1. Radiation testing can thus be postponed to the last development phase. of the adopted FPGA device. The computation of the predicted error rate is performed by resorting to fault-injection experiments. Other approaches modify the bitstream before downloading it in the device’s configuration memory [12]. THE DEVELOPED APPROACH In this section. etc. In our approach. 1. Its building blocks are the components available within the adopted FPGA: LUTs that store the truth table of the Boolean functions the circuit implements. Starting from an initial description of the circuit the system implements. but none of them puts much emphasis on analyzing SEU effects on the FPGA’s resources required by the mapped circuit. and classified the observed SEFIs according to the affected FPGA’s resource. which provides Fig. This approach opens new possibilities. The main purpose of these approaches is to replace radiation testing during the design phase so as to be able to predict SEU effects by simulation. The analysis of the physical layer is required each time a new technology is exploited: once has been computed. For example. In the meantime. All these approaches emulate the effects of SEUs in the FPGA’s configuration memory as bit-flips in the memory content. register. they are not able to identify the origins of the SEFIs. The application layer corresponds to the digital circuit that implements the functionalities the system is intended to carry out. In our approach. To gain a better understanding of the effects of SEUs on FPGAs in terms of modifications induced on the device’s resources. Simulation-Based Analysis of SEU Effects This section describes the simulation-based analysis tool we developed for analyzing the application layer of the FPGA-based system. The application layer is analyzed using a simulation-based analysis tool described in Sections III-A–III-C. and independent suppliers for simulation operations. A similar approach was proposed in [14] for analyzing processor-based systems. which are based on fault models that emulate accurately the effects of SEUs in the configuration memory of FPGAs. an analysis that combines the results of radiation testing with those obtained from analyzing the meaning of every bit in the FPGA’s configuration memory was reported in [9] and [10]. The core of the tool is the fault-injection environment outlined in Fig.). A. III. several fault-injection approaches were recently proposed. it offers a high-level view of the effects of SEUs on the circuit mapped on an FPGA. ability that an SEU modifies the circuit implemented by the application layer in such a way that it produces SEFIs. It combines both ad-hoc developed tools with commercial tools provided by the FPGA vendor for place and route operations. thus paving the way for the development of accurate circuit-oriented estimation techniques able to predict SEU effects in the circuit mapped on the FPGA only. . The cross section obtained by this method is associated with the FPGA device. we describe the approach we developed for analyzing SEU effects in FPGA-based systems. i. as follows: (1) This figure gives the sensitivity to radiation of the whole systems.

fault location) describing when the SEU appears. b) Bridge: the track A/B is replaced with a new track C/B. and those controlling the logic resources used by the mapped circuit ( bits).e. Fault Models and Fault List Generation Tool This section describes the fault models and the tool we developed while performing the analysis of the physical layer of the system. the application layer). and some controlling logic resources. Conversely. provided that tools for obtaining the VHDL model of a circuit mapped on an FPGA is available (i. we describe the fault simulation tool we developed while targeting Xilinx devices. DECEMBER 2004 FPGA vendor for performing place and route operations. and produces a configuration file where the content of the device’s configuration memory is stored. etc. we can observe the following modifications induced by SEUs to the FPGA resource’s configuration. fault location). During simulations the outputs produced by the faulty application layer are compared with those of the fault-free one. c) Sequential defect: the content of a user memory bit is modified. Fault Simulation Tool In the following. The tools we developed produce the following figures: the number of configuration memory bits that needs to be programmed on the physical layer to implement the application layer. c) Conflict: a new track C/B is created that overlaps with A/B. while the bility for an SEU to appear in the used portion of the physical layer. Starting from the information stored in the bitstream. and it can be applied to other devices from other manufacturers. By considering the typical architecture of SRAM-based FPGAs. Given an SRAM-based FPGA device. However. the fault is classified as Effectless. accordingly to the fault models described in Section III-B. This preliminary step is typical of any design flow based on FPGA devices. Similarly.) that are used and it generates the list of faults (Fault List) to be injected. i. signal routing. This information defines the application layer. its configuration memory may be considered as consisting of two types of bits: some controlling signal-routing resources. B. To allow . Signal-routing resources are all those resources concerned with the transmission of information within the physical layer. and thus resource B is no longer fed with the expected logic value coming from resource A. which are sequences of one or more wire segments [15]. Each fault is described by the couple (fault-injection time. and which resource it modifies. while fault location corresponds bits. In our analysis [9]. as well as those left unprogrammed since the resources they control are not used. the routing of a logic signal from resource A to resource B (track A/B) may be affected as follows: a) Open: the track A/B is broken. two ad hoc developed tools are exploited. we concentrated on the devices belonging to the Xilinx Virtex family. and it identifies the bits used to route the ( bits). Fault to all the possible SEUs in sampling is exploited to reduce the number of faults to be is the number of simulated by the Fault Simulation tool: if simulated faults. these resources include: wire segments. b) Routing defect: signal routing inside the logic resource is altered. It then generates all the possible couples (fault-injection time. Resource B is thus driven by an unknown logic value which depends on the values coming from resources A and C..e. In general. in case the simulation of the Input Stimuli set concludes. while will be injected in the CLB ones. The tool we developed for Fault List generation analyzes the device configuration file produced by the place and route tools. The Fault List Generation Tool identifies the FPGA’s resources in the application layer (for logic implementation. It includes the bits that need to be programmed for implementing the application layer. the bitstream. The aforementioned figures are combined by means of (2) to : estimate the predicted circuit error rate (2) The term is the percentage of faults provoking Wrong ratio estimates the probaAnswers. the following effects are possible: a) Combinational defect: the logic function implemented by the logic resource is modified. NO.3356 IEEE TRANSACTIONS ON NUCLEAR SCIENCE. and tracks. the total number of configuration memory bits for the physical layer. and no mismatch is found. where fault-injection time ranges from the time of application of the first input stimuli to the last one. For example the paths connecting input ports to the look-up-tables implementing combinational functions are modified. our approach is general. which are wires unbroken by programmable switches (each end of a wire segment typically has a switch attached). 2) Logic resources: as soon as any SEU hits the bits controlling a logic resource. VOL. logic resources are all those resources concerned with the implementation of combinational or sequential logic functions [15]. The Fault Simulation Tool simulates serially the faults in the Fault List. The tool can be adapted easily to other devices from different manufacturers. [10]. the simulation is stopped and the effect provoked by the injected fault is classified as Wrong Answer. which is instead left dangling. and thus resource B is no longer fed with the expected logic value coming from resource A. As soon as a mismatch is found. then faults will be injected in the routing resource.. 6. the percentage of injected faults whose effects are classified as Wrong Answers. C. Conversely. 51. 1) Signal routing resources: as soon as any SEU hits the bits controlling the programmable switches attached to wire segments. fault-injection time will be randomly selected between the first and the last input stimuli.

An additional input port. A Control Host. collecting output responses. described in Section IV-A. D. During this process the set of VHDL instructions that model the fault are . and then its configuration memory is periodically read back. consists in configuring the physical layer with the application layer. we have a Test CPU (a Power-PC MPC860) that communicates with the Control Host as well as with the device under test. The application layer was a circuit composed of four 16 16-bit binary multipliers. The tool we developed exploits the ModelSim VHDL simulator for evaluating the outputs that faulty application layer produces. for each fault in the Fault List a new model. The test-bed can be used for two purposes. By relating the number of observed SEFIs with the estimated number of particles hitting the device’s surface is then possible to compute the device cross section. By comparing the read information with the fault-free bitstream we can measure the number of observed SEUs. IV. the test is restarted from the beginning. and it is briefly described here for the sake of completeness. It is provided with an IP connection with the set-up inside the irradiation chamber through which it sends commands and receives information about the status of the experiments. the test is stopped and the configuration of the FPGA Under Test is read back and sent to the Control Host for data logging. A Control Hardware is also used for adapting the Test CPU to the FPGA Under Test. EXPERIMENTAL RESULTS In this section. Radiation testing experiments were carried out at the Tandem Van De Graaff Accelerator of INFN-LNL. the circuit behaves as and when the inject is equal to 1 faults are injected. inject. the physical layer was a Xilinx Virtex XCV300 device which we exposed to various ion species ranging from 84 MeV carbon to 210 MeV nickel featuring linear energy transfer (LET) values between 1. Similarly. while the outputs were connected to an XOR gate array. located outside the irradiation chamber. Inputs of the four multipliers were connected in parallel. The multiplier occupies 2524 out of 3072 slices of the adopted XCV300 device and operates at 10 MHz. the typical test session systems. Before fault simulation can start. Inside the irradiation chamber. we performed two types of experiments. as well as data to be logged for elaboration purposes. As soon as a mismatch between the expected output values and the read ones is observed. .6 and 30 MeV cm /mg. Following this operation. the FPGA is inition of the physical layer. is finally added to the to activate the mutation at the injection interface of time: when inject is equal to 0. is computed as a mutation of . we determine the accuracy of the approach we developed.VIOLANTE et al. and then in continuously stimulating the FPGA device with a given set of input stimuli. The output responses are continuously collected and compared with the expected ones. Its purpose is to perform the low-level operations needed for running an experiment: programming the device under test. In this case. As previously done. 2 shows an overview of the test-bed.. Fig. Overview of the test-bed we developed for performing radiation-testing experiments on FPGA devices. FPGA vendors usually provide this type of tool. aims at evaluating the accuracy of estimation of the predicted cross section of a circuit mapped on a device with respect to that measured by means of radiation testing. applying input stimuli.e. Let us refer to the fault-free application layer as . . tially programmed with an empty bitstream. obtaining the measured cross section of the whole . The second one. Legnaro (PD). Test-Bed for Radiation Testing Experiments In this section. It can be exploited for measuring the cross section of an FPGA-based system. For this purpose. The first one. The test-bed was introduced in [9]. we describe the test-bed we developed for performing radiation-testing experiments in FPGA devices. when an SEFI is detected. i.: SIMULATION-BASED ANALYSIS OF SEU EFFECTS IN SRAM-BASED FPGAs 3357 TABLE I SUMMARY OF THE MUTATIONS INSERTED IN THE VHDL MODEL OF THE CONSIDERED CIRCUIT TO MIMIC THE EFFECTS OF SEUs IN THE DEVICE CONFIGURATION MEMORY Fig. and reading back the configuration memory of the device under test. we use the mutations reported inserted in in Table I. For this purpose. For this purpose. 2. aims at evaluating the accuracy of our simulation-based approach while modeling the effects of SEUs in the device configuration memory. In particular. the test-bed can be used to measure the cross sec. is used to monitor the experiment execution. In our experiments. described in Section IV-B. including its main components. the application layer is first obtained by exploiting the ncd2vhdl tool provided by Xilinx. Italy. designers to evaluate the correctness of their designs after place and route. by relating this figure with the estimated number of particles hitting the device’s surface is then possible to compute the device cross section.

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