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Chapter11: SYMBOLIC SIGNAL FLOW GRAPH METHODS IN SWITCHED-CAPACITOR DESIGN

M. Helena Fino, STUDENT MEMBER IEEE
Universidade Nova de Lisboa Faculdade de Ciências e Tecnologia DEE Email: helena@ecsm4.ist.utl.pt

José E. Franca, SENIOR MEMBER IEEE
Instituto Superior Técnico Centro de Microsistemas Email: franca@ecsm4.ist.utl.pt

Adolfo Steiger Garção
Universidade Nova de Lisboa Faculdade de Ciências e Tecnologia DEE Email: asg@uninova.pt

11.1

Introduction
In previous chapters the use of symbolic methods has been largely dedicated

to the lower levels of analog circuit design encompassing circuit elements such as amplifiers and comparators [1, 2, 3]. In this chapter we shall describe symbolic signal flow graph (SFG) computational techniques for the analysis and synthesis of switched-capacitor (SC) circuits. This is based on a hierarchical approach in which signal processing building blocks are defined in terms of basic elements whose characterization resides in a knowledge-base. This knowledge-base can be developed both for analog and digital discrete-time building blocks using the common SFG representation of their operation but, for conciseness, we shall consider herein its specific implementation only for discrete-time SC signal processing building blocks. Besides the Introduction this chapter comprises six additional sections. Section 11.2 discusses the flow of information for circuit analysis and synthesis

11-1

of SC building blocks and establishes the hierarchical plans to be considered for the development of an automated design environment. Section 11.3 describes the SFGbased method for generating the symbolic transfer functions of SC networks. After giving a brief description of the SC elementary blocks and the corresponding SFG representation we shall introduce a simple rule-based approach for automatic identification. Then, Section 11.4 describes the symbolic analyzer where a pattern matching technique is used for generating the SFG representation of SC building blocks and yielding the corresponding symbolic z-domain transfer function. The use of such symbolic analyzer is discussed in Section 11.5 for carrying out highly flexible step-by-step synthesis of SC building blocks, and in Section 11.6 for automatic knowledge capturing of those SC building blocks. Finally, Section 11.7 summarizes and concludes the chapter.

11.2

Analysis and Synthesis in Circuit Design
Circuit design can be broadly characterized by the close interrelation of

synthesis and analysis procedures. Here, we define synthesis as the process through which the designer usually assembles simple, fully characterized circuit primitives to create more complex, unknown circuit topologies. These circuit topologies are then characterized and verified using analysis procedures, which throughout this chapter are based on symbolic computational techniques. This section provides a simple description of the basic flow of information for both Analysis and Synthesis, as well as the most relevant procedures required for automating both.

11.2.1

Flow of Information for Analysis

Fig. 11-1 illustrates the flow of information during the analysis of a simple

11-2

SC building block. Once the Description of a Building Block

is given an

Interpretation process identifies the constituting SC elementary blocks, and then characterizes each of them in order to determine the behavior of the overall SC building block. Such interpretation is carried out based on a set of primitives usually consubstantiated in a set of rules which define the structure of the elementary blocks and the corresponding characterization. From the interpretation process, the SFG representing the operation of the SC building block is obtained. An Equation Extractor is then applied to such SFG yielding the symbolic zdomain transfer function of the building block under analysis. Later, the transfer function symbols can be instantiated to numerical values so that in the Evaluation phase the frequency response of the circuit is obtained and relevant performance criteria are evaluated.

Building Block Description

x y

ay x

b y x y x

Interpretation

-a.z- 1/2

Primitives - (1 / b) 1 (1 - z -1 )
- 1/2

Equation Extractor

a.z H(z) = b (1 - z - 1 ) z num 2 (1 - z - 1 ) =
- 1/2

Numerical Instantiation

a=1, b=2 => H(z)

Evaluation

11-3

Fig. 11-1: Flow of information during the analysis of an SC building block.

11.2.2

Formulation Method for Building Block Interpretation

As mentioned before, the building block interpretation is based on a set of primitives that characterize the SC elementary blocks, and is usually accomplished in two phases. In the identification phase, the building block description is browsed so that by applying appropriate pattern matching techniques all the constituting elementary blocks are recognized. Then, in the Characterization phase, the characterization of each one of the constituting elementary blocks is computed and the overall characterization of the building block is thus obtained. In order to assist the interpretation process for the characterization of the building block the core of primitives should provide one set of rules concerned with the identification phase of the interpretation process, and another set of rules concerned with the evaluation of the characterization of the elementary blocks. Later, in Section 11.3, we shall discuss the relevant rules for the core of primitives for SC analysis and synthesis and which are based on representation techniques. discrete-time SFG

11.2.3

Flow of Information for Synthesis

The typical flow of information during the synthesis of an SC building block circuit is represented in Fig. 11-2. The first step consists of obtaining the numerical z-domain transfer function to meet the target specifications. This is accomplished using well known computer-based routines, e.g. [4], and therefore will not be considered here. The second step is the Building Block Topology Synthesis where the topological characterization of a building block is obtained and the

11-4

In the Dimensioning phase.1 ) 1 − 1/2 z.z.1 b (1 .1 ) b y .corresponding symbolic z-domain transfer function is evaluated.z .z = b (1 .z ) a.z.1 y Evaluation Fig.1 Dimensioning z 2 (1 . Since the resulting system of equations is usually not solvable by algebraic means it is necessary to place additional constraints on the symbolic expressions of the coefficients.(1 / b) (1 .z.1/2 y x Building Block Topology Synthesis y -a.1 ) − 1/2 Building Block Description x y y x 2 y y x z. These constraints are usually based on structural knowledge of 11-5 .1/2 and y x y H(z) = a.z. This step makes use of the same set of primitives previously mentioned for analysis and which characterize the relevant SC elementary blocks. the symbolic expressions of the coefficients of the z-domain transfer function are equated to the previously obtained numerical coefficients. 112: Typical flow of information for synthesis of an SC building block.1/2 Equation Extraction .1 ) 1 . Numerical Specifications x H(z) = a z 2 (1 .z .

e. variability of the frequency response against capacitance ratio errors. 6. are evaluated. The equations are based on structural information of the building block and may be automatically evaluated be applying a structural evaluator to the netlist description of the block. in the Evaluation phase. The particular case for SC networks will be described in detail in Section 11.3. 11.4 Equation Extractor for Dimensioning In the flow of information for analysis we have introduced an equation extractor responsible for producing the symbolic z-domain transfer function of the SC building block represented by the appropriate SFG. however. whose discrete-time operation is characterized with respect to the associated timing diagram.2. the frequency response of the building block is obtained and relevant performance criteria.3 Switched-Capacitor Primitives and Identification Techniques 11.1 SFG Representation of SC Elements SC networks consist of the interconnection of SC elementary blocks. In the above synthesis process.the building block topology. the Equation Extractor must also produce additional equations introducing constraints on the symbolic expressions of the coefficients in order to make possible to automatically dimension all the building block parameters. 7] we can derive 11-6 . Finally. 11. By using classical SC circuit analysis techniques [5. capacitors and operational amplifiers.g.6. comprising such elements as switches.

Parasitic Compensated Toggle Switched Capacitor (PCTSC). All SFGs shown in Fig. Toggle Switch Capacitor (TSC). Note that all SC elementary blocks represented here refer to the same timing diagram indicated at the bottom of the figure. 11-3 comprise three different transmission factors. the time delay (advance) of the input and output sampling instants of the SC elements with reference to the associated timing diagram.3.zb and K. as in summarized Fig. The sign associated with the transmission factor K indicates the phase of the input (output) variables with respect to the positive reference phases. In the case of the active SC elementary block also represented in Fig. that provide some physical insight into the operation of the corresponding SC elementary blocks. as is the case of all quasi-passive SC elementary blocks. When the SC element transforms a sampled input voltage signal into a sampled output packet of charge K represents the equivalent capacitance value. 11-3. and Inverting Parasitic Compensated Toggle Switched Capacitor (IPCTSC) [8]. Some icons are also indicated in order to simplify schematic representations. Positive voltages are defined from a node to ground while positive packets of charge are defined for a flow into an output node or for a flow from an input node. Toggle Switch Inverter (TSI). K represents the equivalent transimpedance value (here the inverse of a capacitance) describing the transformation of a sampled input packet of charge into a sampled output voltage signal. respectively. za. The transmission factors za and zb represent. 11-3. Open Floating Resistor (OFR).for various SC elementary blocks the corresponding SFG representation. The transmission factor K indicates the relationship between the sampled input and output variables. i.2 Rule-Based Identification 11-7 .e. 11.

11-8 . a pattern-matching technique is employed based on Structural Rules residing in the system knowledge-base.For the identification of the SC elementary blocks comprising a given SC network.

x . 2K.z ) (K = .K.K.C) ∆Q Open floating resistor (OFR) x y ∆Q x. y (K = -C) z +a ∆Q Feedback capacitor x ∆Q a) C y V z -a K (1 . c) SFG.K.b V ∆Q b) y x -a -b 0 c) d) Fig.a K (1 . 2K .z . 2K .C) -a-1 z+ a ∆Q z +b Toggle switched-inverter (TSI) C y x ∆Q C y x. y K (K = + C) z+ b ∆Q x v y 2C Inverting parasitic-compensated TSC (IPCTSC) -a-1 K z y x x ∆Q 2C V x . x .a x. 11-3: Elementary blocks for SC networks. 2K . Switch-timing.y V K (K = + C) ∆Q x y Parasitic-compensated TSC (PCTSC) -a y z 2C ∆Q V x . b) Icons. d) 11-9 .x za v x K (K = + C) z +a V ∆Q z+ b Toggle switched-capacitor (TSC) x v y C x v y 2C ∆Q z.1 ) (K = . a) Structure.y V z -a K (K = .x v x v y C x ∆Q Memory capacitor V z.1 / C) z.

The first switch. /* switch */ /* capacitor */ Rule 11-1: Structural rule for the identification of a Toggle Switch Inverter. capa(N.gnd. A third switch.Phasei). sw(N. 11. sw(N. Between the same node X and node Y is a capacitor with capacitance value C.Outp. Once an SC elementary block has been identified based on the structural rules discussed above the corresponding SFG can be evaluated based on two groups of Evaluation Rules. 11-4.Inp. which also operates with the same phase Phasei is connected between node Y and ground.C). Finally. Such TSI comprises four switches and a capacitor.4.Phaseo).Phasei. One group of evaluation rules is concerned with the calculation of the delay term as a function not only of the switching phases but 11-10 .Phaseo).Phasei). a switch operating in the same phase Phaseo as the one connected to the input node is connected between node Y and the output node.4 11.X. operating with phase Phasei is connected between the input node (Inp) of the element and node X.Y.Inp.Y.An example of the Prolog [9] structural rule defining a TSI is shown below.gnd. tsi(N.Y.C):sw(N.X. Connected between this node and ground is another switch operating with phase Phaseo. sw(N.Outp.Phaseo.1 SFG-Based Symbolic Analysis of SC Networks Formulation Method The SFG of an SC network is generated from its circuit description employing information residing in the knowledge-base. as schematically illustrated in Fig.X.

the predicate delays is invoked so that the delay Dels associated with the input voltage sampling instant is computed.TiPref. Pref.P2. the predicate calcdelay starts by obtaining the falling edge instants ToP1 and ToP2 of the phases P1 and P2 that control the operation of the SC elementary block. as well as the falling edge instant ToPref of the phase taken for reference.ToPref.ToP2].Delay):member([P1./* ToPref . 11-4: The SFG of an SC network is derived from its description based on the characterization of SC elementary blocks residing in the knowledge-base.ToP2.Deluni.Tframe).Tframe). /* Delay in input voltage sampling */ delayt(Period.Delay). /* ToP1. the clock period. Once the delay 11-11 . /* Delay =Deltotal/Deluni */ Rule 11-2: Rule for the evaluation of the delay term of an SC elementary block.also of the reference phase. calcdelay(Period. to be considered.TiP2. This is illustrated below in Rule 11-2 for the simple example of the TSI SC element previously considered.falling edge of phase P2*/ member([Pref. Period.ToP1.Pref. As we can see.ToPref.Delt). /* ToP2 . Then.P1.Dels).Tframe).ToP2.ToPref].Tframe. Building Block Description structural description elementary SFG SC elementary block characterization Identification SFG generator Interpretation Fig.ToP1.ToP1]. /* Delay in charge transfer*/ Deltotal is Dels + Delt. and the unit delay.phase */ delays(Period.falling edge of phase P1*/ member([P2.TiP1.falling edge of the ref. quo(Deltotal.Deluni. Deluni.

/* sampling phase is after the charge transfer phase */ To is ToP2 + Period.ToP2.ToP2. ToP1. In this case.!. the charge transfer process will only take place in the next clock cycle.Dels):ToP1 @>ToP2.. Deltotal. ToP1. is consubstantiated by Rules 11-5 and Rule 11-6 shown below. Rule 11-4: Rule for evaluating the delay associated to the input voltage sampling of an SC elementary block when the sampling instant. Dels is ToP1 . Deluni. delays(Period. ToP2.Dels):Dels is ToP1 .ToPref. Rule 11-5 is applied when the charge transfer instant. occurs after the charge transfer instant. Delt. Rule 11-4 is applied when the sampling instant occurs prior to the charge transfer instant. and Dels will be given by the difference between ToP1 and ToP2+Period.To. Rule 11-3: Rule for evaluating the delay associated to the input voltage sampling of an SC elementary block when the sampling instant. ToP2. The predicate for the evaluation of the delay associated to the charge transfer process.e. at ToP2+Period.Delt related to the charge transfer instant is calculated by the predicate delayt the total delay factor. of the capacitance pertaining 11-12 . delays(Period. ToP2. Finally the Delay term is obtained by normalizing the previously calculated total delay with respect to the unit delay. occurs prior to the charge transfer instant. ToP1 of the capacitance pertaining to the SC element occurs after the corresponding charge transfer instant. i. ToP2. Rule 11-3 is applied when the input voltage sampling instant.ToPref. The predicate delays is consubstantiated by Rule 11-3 and Rule 11-4 shown below. ToP1. ToP1.ToP2. is obtained by adding together Dels and Delt. and Dels is given by the difference between ToP1 and ToP2.

Delt):Tref2 is ToPref + Period. The simple case for a TSI element is illustrated in Rule 11-7. ToP1. given the capacitance value. Delt is ToP2 . occurs prior to the reference phase. C. is obtained by invoking predicated ratFormpf . ToPref. Rule 11-6 considers the case when the charge transfer instant occurs after the reference phase. ToPref + Period must be considered. In this case. Delt is given by the difference between ToP2 and ToPref. the transmission factor.ToPref. ToPref. Y. which returns in the third argument the symbolic representation of the ratio between the first two 11-13 . is firstly evaluated (here K=-C) and then the TSI SFG weight.ToP2. delayt(Period.ToPref. delayt(Period. Delay. Delt will be given by the difference between ToP2 and ToPref + Period. Rule 11-5: Rule for evaluating the delay associated to the charge transfer process of an SC elementary block when the charge transfer instant. The second group of rules for the SFG evaluation of SC elements concerns the symbolic characterization of the weight factor Y. K.Delt):ToP2 @<= ToPref. ToP2.ToPref. so that the reference phase of the next clock cycle. ToPref.6: Rule for evaluating the delay associated to the charge transfer process of an SC elementary block when the charge transfer instant.Tref2.to the SC element occurs prior to the reference instant. Rule 11.!. As we can see. ToP1. Delt is ToP2 . ToP2. of the capacitor pertaining to the SC element and the previously calculated delay. occurs after the reference phase.ToP2. Here.

/* ratFormpf( num.C. the remaining SC elementary blocks are identified using the rulebased techniques discussed before. e. the number of distinct phases. Once the symbols in the z-domain transfer function are instantiated to numerical values 11-14 . The SFG of each one of those SC elementary blocks is calculated by applying the rules residing in the knowledge-base and taking into account both the reference phase and the unit delay computed for the operational amplifier that is fed by the SC elementary block under consideration. In order to avoid conflicts in the identification phase the more complex SC elements. those which are parasitic compensated. num/den) */ */ Rule 11-7: Rule for evaluating the SFG weight factor of a TSI. In order to generate the overall symbolic SFG corresponding to a given SC network the automatic SFG generator first browses the associated netlist so that the operational amplifiers with a feedback capacitor are recognized and.g.Y).[1]. both the phase at which the output voltage of the amplifier is sampled (Phaseref) and the unit delay are determined. for each of them. ratFormpf(K*z^Delay. also in symbolic form. To conclude the overall SFG generation. Mason's rule [10] is applied for determining the overall z-domain transfer function.K). two distinct cases must be considered. then the unit delay is equal to the period of the clock signal controlling the operation of the circuit. Otherwise.Delay. nphases. den.Y):/* Y = -C * z^Delay /1 minus([C].arguments. After generating the symbolic SFG of a circuit. at which the input signal is sampled is determined and the unit delay is obtained by dividing the period of the clock by nphases. Should the circuit function with a sampled and held input signal. For determining the unit delay. ratpol(tsi. are identified firstly and their constituting capacitors marked as already pertaining to an identified element.

5 Step-by-Step SC Synthesis and Knowledge Capture The first step in the synthesis process consists in obtaining a network topology that may be submitted to the dimensioning process. are associated. 11. respectively. the operational amplifiers OP1 and OP2 are recognized and.4.2 Working Example An example considering an SC decimator using an active-delayed block architecture [11] is illustrated in Fig. unknown network topology In the process of creating new topologies based on a set of fully characterized 11-15 . phase 1 is considered as the reference phase.the frequency response of the network can be obtained.5a and with time frame represented in Fig. the reference phases 5 and 1. such as the variability of the frequency response against capacitance ratio errors. 11-5. 11. to each of them. Further performance criteria. 11-5c. the delay factor of the corresponding SFG is calculated considering phase 5 as their reference phase. the remaining SC elementary blocks of the circuit are identified: for those belonging to block1. Given the decimator netlist. 11-5b is graphically illustrated in Fig. Then. The SFG obtained for the SC decimator in Fig. fully characterized circuit primitives to create a more complex. For this the designer may opt for either using a previously defined and fully characterized building block topology or for exploring a new topology by assembling simple. 11. can also be easily obtained either by instantiating different capacitance values or by instantiating nominal capacitance values as well as their associated tolerances. for the elements pertaining to block2.

11-16 . so that the designer gains a qualitative insight into the key parameters responsible for the behavior of the circuit.circuit primitives a symbolic calculation is carried out for every step of the construction of the network.

2d 9.a .4.z-4 -c3.d 3.z -c9.inp 4.z -6 -c5.1 b 1 outp OP1 OP2 reference phase for block2 a) waveform 7 waveform 5 1.1 2. 11-5: SFG generation for an SC decimator with ADB architecture.6 2.d 1.6 1.1 1.z-8 -d7 .c .z-2 c 1.6 8 3.z-5 -d4 .6 2.2 3.3.z -1 c0 -1/b 1 outp z-1 Fig.z-5 -c4 .c 2 .z-3 -c2 . b) Time Frame c) Signal Flow Graph. 7 5.c 1.d 6.z -6 -d 5.c .d 4.1 2.d 0.7 block1 3. a) Circuit.z-7 -d 6.1 4.z-8 -c7.7 9 4. 11-17 .d 5.1 4.b .z-7 -c 6.1 3. e .d 2.2d8.2d9.6 1.z-3 -d2 .z-2 -d1 .1 waveform 6 waveform 4 waveform 3 waveform 2 waveform 1 inp b) d9 .z -1 c) -1/a e 9 -9 .z-4 -d3 .z-9 d8 .c 6.6 5.c 0.c 4.c 7.5 a block2 reference phase for block1 5.2d 8.c 3 .6 3.z-9 -c8 .1 3.6 5.c 5.

respectively. respectively. Then. 11-6b.1 we consider the case of adding two branches to the input of the first operational amplifier yielding the SFG and transfer function shown. 11-6d. respectively. In Fig. with the addition of a damping capacitor E. By using the symbolic analyzer the designer obtains the SFG and symbolic expression for the denominator D(z). Then.2 and in Fig. depicted in Fig. 116c. 11-6d.1.1 for the second operational amplifier and thus finally leading to a network topology whose SFG and symbolic transfer function are described. The same operation is repeated in Fig. As illustrated in Fig. 11-6b. the first step consists in generating a basic structure that implements the quadratic denominator of the transfer function. respectively.3. in Fig. In Fig. 11-6b.5. this yields the SFG and symbolic expression for the denominator D(z) represented. 11-6a.During such step-by-step synthesis process the knowledge created may be kept in the system knowledge-base so that it may be reused whenever it is needed to parameterize the same network to meet given target specifications.3.3. 12]. it is necessary to damp the loop. 11-18 . 11-6. in Fig.1 this is accomplished by connecting in a loop one negative SC integrator and one positive SC integrator. in order to realize the quadratic numerator function feedforward branches must be added from the input terminal to the output of the circuit.2 and Fig. as shown in Fig. 11-6a. 11-6d.3.2 and in Fig. 11-6a.1 Step-by-Step Synthesis For illustration purposes we consider the step-by-step synthesis of a classical SC biquadratic section [7.2 and in Fig. 11-6c. 11. 11-6c. in Fig.

.C.z-1 ) 2 b.A.e OP2 -1 D(1-z -1) -Az-1 OP1 e.3) 11-19 E B -1 E -Ez C D -1 B(1-z-1 ) e.A.1) a.AE/BD) z BD( 1. B e.o -1 -2 D (z) = 1 + (AC/BD + AE/BD .1) b.C.2) z + (1 . 11-6: Using the symbolic analyzer for the step-by-step synthesis of an SC biquadratic .2) a.z -1 ) 2 D C -1 B(1-z-1 ) 2 e.3) Fig.2) z z BD( 1.o OP2 -Az -1 -1 D(1-z-1 ) -1+ D (z) = 1 + (AC/BD .2) b.e OP1 a.

o 11-20 E B C e Ez -1 -E -Az I -1 e.o OP2 outp D B e -1 D(1-z -1) -Az -1 outp E C E -Ez -1 B(1-z-1) H (z) = AH z -2 -1 − AG z -1 OP1 (BD .H.G.o G inps -Hz-1 inps c.H.A.AE) z-2 + (2BD + AC + AE) z-1 + BD -1 G inps inps d.e e.A.2) Fig.2) e.e e.) d.C.e e.e e.2) .e e.I.J.G.o OP2 outp D OP1 -1 -1 D(1-z ) -Hz -1 -1 B(1-z-1) -Jz -1 outp H (z) = (AH .JD) z-2− (AG + ID + JD) z − ID (BD .1) d.1) c.o e.2) c.AE) z-2 + (2BD + AC + AE) z -1+ BD e.e.C. 11-6: (cont.

11. Building Block Topology Description Interpretation z-tansfer function generation Structural Evaluation Equation Extraction Topology Description z-transfer function Integrating Capacitors Coupling Capacitors SC Equivalences Voltage Capacitor Sets Normalizing Capacitor Sets Fig. a structural evaluation process is also applied to the building block topology to produce the relevant knowledge concerning the capacitance values. 11-7. 11-8a. 11-7: Symbolic characterization for SC filter design. After obtaining the symbolic z-domain transfer function. 11-21 . Firstly. The process of generating the symbolic characterization of an SC filter is depicted in Fig. it determines such capacitors whose capacitance value may be usually pre-set to some fixed value so that the extra degrees of freedom for design are eliminated. as illustrated in Fig. This is the case of the Integrating Capacitors which can be pre-set to unit such that the associated capacitance ratios are replaced by absolute capacitance values.5.2 Building Block Characterization The complete parameterization of a building block may only be attained if the system is able not only to generate its symbolic z-domain transfer function but also provide the additional structural knowledge needed to size the final capacitance values [13].

1) b. c) by using established equivalencies between SC branches. In Fig.1) a.e c.e e.e e.F.J.o e.o B b.2) e.e D e. b) by pre-setting coupling capacitors.1. In Fig.2) X Y 1 e.A.B X Y a.3) e.C.o B e.A.A.o b. 11-8b further constraints on the capacitance values may also be applied either by pre-setting the value of the Coupling Capacitor A to unit [12] or by pre-setting the Coupling Capacitors A and C to the same value A. 11-8: Reducing design variables: a) by replacing capacitance ratios with nominally equivalent absolute capacitance values.F.o e.e c.1) Fig. 11- 11-22 .J.2) J B e.e D e.e e.I.C.J.e D e.F.

8c a pair of switched-capacitors connected between the same nodes are pre-set to the same value.k i Fig. The determination of this value is usually calculated by numerical simulation of the circuit and may be used to trade-off the dynamic range of the circuit against capacitance spread and hence the total capacitor area. 11-10. the SC Structural Evaluator starts by grouping the circuit capacitors into non overlapping capacitor sets such that the capacitors in the capacitor set Si are those capacitors 11-23 . In order to perform such voltage scaling the required output voltage level V i of each operational amplifier is calculated and then all the capacitors connected or switched to the associated output terminal are multiplied by a factor ki = V i V where V represents the initial output voltage level. F2 D A V V/k i V/k i F2. 11-9: Voltage scaling of an operational amplifier output. 11-9. as well as the Normalizing Capacitor Sets upon which we can apply capacitance scaling and sizing the unit capacitance value for capacitance normalization. For the capacitance scaling operation.k i A. The SC Structural Evaluation process also determines the Voltage Capacitor Sets which can be affected by voltage scaling operations. illustrated in Fig. leading also to the elimination of one circuit variable. consist in scaling the output voltage level of each operational amplifier in the circuit to the required value.k i D. illustrated in Fig. Voltage scaling operations.

m C. In order to find a first set of unscaled capacitance values the system equates the numerical and the symbolic transfer functions of the selected building block topology.m H. each capacitor is multiplied by a factor Cµ mi = Ci. as well as the types of constraints considered is represented. C E F2 D G H G. is determined. In Fig.3 Dimensioning The last step in the synthesis process consists in the determination of the capacitance values of the building block by equating its symbolic and numerical transfer functions. 11-24 . If the system of equations possesses no extra degrees of freedom. for every capacitors set Si . 11-11. if a valid solution is found. a flow chart representing the unscaled dimensioning. Then. For the resulting system of equations the number of extra degrees of freedom. As mentioned before. The constraints criteria are based on structural information generated by the characterization process. further constraints must usually be considered on the capacitance values in order to sizing the final capacitance values. 11.which are connected or switched to the input terminal of operational amplifier i.5. 11-10: Capacitance scaling considering E as the minimum capacitance value. then the capacitance values are immediately calculated and.min is the smallest capacitor in the capacitor set Si .min where Cµ is the adopted unit capacitance value and Ci.m D. m Cµ F2 . Nextra.m xm (m = Cµ /E) Fig.

then a new network topology must be selected. building block symbolic characterization numerical H(z) computes Nextra Y evaluate capacitance values generate numerical netlist End evaluate capacitance values generate numerical netlist constraints=[(1. the values found are not valid.cinteg)] End Nextra=0 ? N cinteg=1 Nextra=Nextra-Ncinteg Nextra=0 ? N Y Cequal or Ccouple-based constraints [cn] evaluate capacitance values Valid valid ? Y generate numerical netlist constraints=[(1. Whenever extra degrees of freedom are found. on the other hand.[cn]] N End Fig.cinteg). 11-11: Unscaled dimensioning of a circuit for a target numerical transfer function. constraints are imposed to the network by pre-setting to unit the Integrating 11-25 .the numerical netlist of the circuit is produced. If.

then the capacitance values are immediately calculated leading to the generation of the numerical netlist of the network.1 Building Block Knowledge-Base In the previous section we have described the symbolic characterization that must be generated for each network topology so that its dimensioning may be 11-26 . This process usually leads to a set of design equations from which the capacitance values can be univocally determined. cequal. The program. the capacitance values pertaining to the list of coupling capacitors.6 Automatic Synthesis In this Section we shall present a program for the automatic symbolic synthesis of SC networks. including those which employ multirate techniques. The system keeps track of the capacitors that have been pre-set to unit. 11. 11. if no additional degrees of freedom are found. then the numerical netlist of the building block is automatically generated and a list of the constraints imposed during the unscaled dimensioning process is produced. once having set the corresponding capacitance to a common value yield the application of SC equivalencies. or to the list of those capacitors. If no satisfactory solution is found. this is based on such criteria as presetting to unit or to a common value. If. Usually. Again. which. on the contrary. extra degrees of freedom still need to be eliminated. was implemented in BIM Prolog. If a satisfactory solution is obtained. then a message is sent suggesting an alternative network topology should be considered. respectively. ccouple. then it is necessary to start an interactive process of exploring additional constraints to be applied. Switcake ( Switched capacitor knowledge-based environment).6.Capacitors.

thus immediately generating the 11-27 .accomplished in a fully automatic way. In this case. are defined. Considering the case of SC networks. i. by defining concepts characterized by its attributes. procedures which are activated without the explicit influence of the user. genstruct and gengraph. represented in Frame 11-1.e. 15] to enable keeping the knowledge in a structured way. besides those demons used for maintaining the knowledge-base consistency. While the former is activated once the netlist of a building block has been introduced. circdesc. we have defined the basic concept. framebased systems also account for the implementation of Demons. two additional demons. Frame: circdesc { netlist: /* supports netlist */ Demons: emptynet actgraph genstruct timeframe: /* supports timeframe */ Demons: emptygraph actztransf gengraph graph: /* supports SFG */ cfeedb: /*suports list of integrating capacitors */ ccouple: /* supports list of coupling capacitors */ cequal: /* supports list of capacitors for SC equivalences */ cinpamp: /* supports list of capacitors for capacitance scaling */ coutpamp: /* supports list of capacitors for voltage scaling */ supertype: symbcirc } Frame 11-1: Frame circdesc for supporting knowledge related to the symbolic characterization of SC networks Besides enabling the representation of knowledge in a structured way. For representing the knowledge automatically generated for the symbolic characterization of SC networks we have used a frame-based system [14.

corresponding structural knowledge. Frame: symbcirc { isa: circdesc outnode: Demons: genztransf ztransf: .6. By considering the output of the network at different nodes. 11. Hence.2nd order lowpass IIR SC decimator In this first example we consider the design of a 2nd order lowpass SC decimator. 52 7 (11-1) where the numerical numerator coefficients are given in Table 11-1. maximum passband ripple of 0. and thus generating the corresponding SFG. For a decimating factor M = 4 the resulting normalized z-domain transfer function is expressed by z −1.2 Working Example 1 . the latter is activated once the time frame has been edited.05 dB and cut-off frequency of 6 kHz.. we obtain distinct z-domain transfer functions.5 ∑ n i z − i i= 0 H(z) = −8 −4 z − 2. 40 z + 1. } /* inherits the attributes of circdesc */ /* supports the definition of the output node*/ /* generates H(z) */ /* supports H(z) */ Frame 11-2: Frame symbcirc for supporting z-domain transfer function of an SC network. as illustrated in Frame 11-2. 11-28 . we have considered an additional concept for supporting the network z-domain transfer function. which inherits all the attributes of the corresponding network characterization. with Chebyshev approximation.

e 0 . x 0. 11-13 we illustrate the knowledge generated during the several steps in editing the description of the basic topology represented in Fig.48675 The implementation of the above z-domain transfer function is accomplished using the optimum SC decimating architecture [16] represented in Fig.8761 18.o 3 4 3. i 0 1 2 3 4 5 6 7 ni*103 4.e 4. y 3. x2 . 11-12. x3 .o 4.0784 29.TABLE 11-1: NUMERATOR COEFFICIENTS FOR THE 2ND ORDER LOWPASS SC DECIMATOR. In this example.8368 3. the clocking scheme illustrated in Fig. Once the netlist of this basic structure is given the corresponding structural characterization is automatically generated yielding the frame iir2nd represented in the third column. 11-12: Basic topology for a 2nd order SC decimator with M = 4.f.83332 13.956 10.o 2. y2 .9711 22.e 1.a. e. 11-14 with the output voltage at phase e has been considered.o inp Fig.e d 1 2 b e. 11-12.2108 27. Once this information is given the SFG of the circuit is automatically generated. y .o 2.e e. 11-29 1. WITH M = 4. In Fig.e 3. The next step in the characterization process corresponds to the definition of the clocking scheme that controls the circuit as well as its output sampling phase. y1 .c. x1 .

[[([-y3] .[ampop. [0])].2]. 0 .[[([-y1] .[4. 0 .1.2.y2].[([0] .5 .[capacitor. -3 . 11-12. [(4.[([0] .y0. [(inp.c]] ccouple: [a. -4 .outp.3.1).1.3). [1])]]].[([0] . [(4.8].inp.0 .[([-b] .inp. [0])]. [(inp. [tsi. 0 .4.o.4.e.e.outp).[[([f] .e.x1.o. -1 . 0 . 0 .[1.[[([-x0] . [ampop. -2 .2.o.x3].1.[[([-x1] .[([0] .e.1. [(2. 0 .4).e.e]. 11-14: Representation of the clocking scheme considered for the SC decimating topology represented in Fig.o. [capacitor.1).3. [(inp. 0 .1.5]. [d])]]].[[([0] . -2 .[[([0] .[([0] .0 . [0])]. [0])]. o 3 2 1 e 4 0 1 2 3 4 5 z 6 -1 7 8 Fig.4.x2]. [-1])]. [e.5 .y2.2). [ofr. 0 . [a.[b.inp. [1])]]].3).e.[([0] . -1 .[ofr.6.4].[2.x0]. [0])].d. -4 .f] cequal: nil cfeedb: [b.3].[[([-a] . [(inp.1.f]] timeframe: [8.d] cinpamp: [[c.3).inp.3).inp.[([0] . [1])]]]] Fig.4. [0])].5.1). 0 .3.0 .3.d]. 11-12. 0 .x0.y3]] coutpamp: [[a.[([-d] . [1])]]].[tsi.[tsi. [tsi. [0])].[([0] . 0 .[switch. 0 . 0 .4.0 .[([0] .[[([-y0] . [(inp.2. [-1])]. [(3. 0 .d].a].[o.2. [(inp.f].c.3).[[([-y2] .o. [0])].3.y1.5 . [b])]]].o. [(4. [0])].1. [1])]. [0])]. -3 .inp.4].5 . [1])]]].x3].f. 0 . -4 .b].1). 11-30 .5 . [1])]]].3. -4 .gnd. [1])]]].gnd. 11-13: Representation of the knowledge generated during the editing process for the SC decimating topology represented in Fig.y3].[([0] .o.[([0] .[tsi.5 .1).b. -4 .4.inp. [0])].c. [1])]]].5 .3.[[([-x2] .x2. [(inp.0.1.[[([-x3] .5 .4.[[([c] .3. [(inp.3. [1])]]].[tsi.1.3.inp.[[([0] . [1])]]]. [1])]]].x1].e.[([0] .1].[3.Operations Demons Frame iir2nd Edit Netlist Save Netlist genstruct Edit Timeframe netlist: [[tsi.y1].y0].3).0 .1. 0 . [tsi. 0 . [tsi. [1])]]].7]] Save Timeframe gengraph graph: [[(1.2.

(f.a). [([(b.5e+00).d)] .d)] . 0)]] Frame iir2nd4 incall: iir2nd outnode: 4 ztransf: [[([(x3.5e+00).b)].a).(-y1.5e+00). [([(b. ([(-2.d)].(-y3.-3.c)].f).a).0e+00). 11-31 . ([(b.d)] .-6. we come to the analysis equations represented in (11-2). Operations Select output node.-7.(f.d)].f).(c.0e+00).d)].-8.5e+00).5e+00).d)] . ([(x1.] . -5. ([(x2.b). ([(x0. by either considering the output signal from node 2 or from node 4.a).-4.f).d)] .(x0. 11-12.5e+00)]. ([(-x0.50e+00). ([(-x1.(-y0.c)].(-f.5e+00).b).f). -8.d).d)] .([(-x2. ([(b.b)].50e+00).d).d)] . during the characterization process.-1.(-f. -8.5e+00).(x2.b.50e+00).5e+00). no Demons Frames Frame iir2nd2 incall: iir2nd outnode: 2 ztransf: [[([(-x3.5e+00). ([(x2.(-y0.b)]. 11-15. ([(y2.b). ([(y1.-3.-4. ([(x1. ([(-2.b.a).d).b).(-y1.b). ([(y0.a). 0)]] Save output node.0e+00).50e+00). -4.(-y2.-8.d)] .Then.0e+00). -5. no genztransf genztransf Fig.c)] .c)] .5e+00). -1. -4.(c.(x3.5e+00)]. ([(x0.(x1. ([(x3. By selecting iir2nd4 and equating the symbolic transfer function to the numerical transfer function corresponding to the target specifications.-6. -2.d). the symbolic characterization generated during the characterization process of the basic decimator topology given is illustrated in Fig.d)] . 11-15: Representation of the knowledge generated for the SC decimating topology represented in Fig.d)].d)]. -2.-7. ([(y3.(-y3.(-y2.

x2-d. a capacitance scaling process is applied 11-32 . In order to maximize the dynamic range at the output of the first operational amplifier.956e-3 d. Finally.b.8 dB is applied to the capacitors connected at the output of this first operational amplifier thus leading to the capacitance values in Fig.54561 x1-y1 = 18.83332e-3 f = 0. a scaling factor of 5.8368e-3 y3 = 29.9711e-3 c .f = 1. yielding the system of equations (11-3).y1 = 18.x0-y0 = 27.d = 1.48675e-3 a.0784e-3 (11-4) Solving the system of equations (4) leads to the capacitance values shown in Fig.c .136 x2-y2 = 10.8761e-3 y1 = 13. the coupling capacitor a is also preset to unit yielding the linear system of equations (11-4) with no extra degrees of freedom.y3 = 3.2108e-3 dy0 = 4.x2-y2 = 10.f = -2.x1-d.4136 b.54561 The existing extra degrees of freedom are automatically eliminated based on the structural information of the selected topology.x1-y1 = 18.x3-y3 = 3.9711e-3 a.956e-3 y2=22.y0 = 27.y3 = 29.0784e-3 b.d.83332e-3 a.c . the first step in the elimination of the extra degrees of freedom consists of pre-setting to unit the integrating capacitors.0784e-3 (11-3) Since this system of equations still possesses an extra degree of freedom.0 (11-2) -2. 11-17a.8368e-3 y3 = 29.54561 a.48675e-3 x0-y0 = 27.4136 a.f = -0.y2 = 22.2108e-3 y0 = 4.d + d.9711e-3 a.8368e-3 d.8761e-3 dy1 = 13. a.2108e-3 y0 = 4. For this purpose.y2 = 10.f = -0. x3-y3 = 3.48675e-3 a.a.d + a.x3-d.8761e-3 y1 = 13.956e-3 y2 = 22. 11-16a.x0-d.83332e-3 f = 0.

094 -10 1st operational amplifier -20 2nd operational amplifier -30 -40 0 4e+04 8e+04 1e+05 (a) (b) Fig.0688e2 d = 1.000 y0= 1.456094e-1 x0= 3.292703e-2 x2= 3. 11-17 a) Capacitance values after capacitance scaling.0066 x3= 1.833332e-3 y1= 1. 11-16.8dB a = b = d =1 c = 1.5679 y3= 6.0734e2 b = 2.397106e-2 y2= 2.00297 x1= 1.00702 x2= 1.291519e-2 x3= 3.921078e-2 -10 1st operational amplifier -20 -30 2nd operational amplifier -40 0 4e+04 8e+04 1e+05 (a) (b) Fig.000 y1= 2.037037 f = 1. b) Frequency response of the circuit obtained after the final sizing of the circuit of Fig. 11-17b.89058 y2= 4.320012e-1 f = 5.leading to the values in Fig. 11-33 .269754e-2 y0= 4.270948e-2 x1= 3. 0 a = 1.207841e-2 y3= 2. 11-12. 11-16: a) Unscaled capacitance values and b) frequency response obtained after a first-cut sizing of the circuit in Fig. 0 5.12885e2 x0= 1.587e1 c = 4.

6.99723. a pole Q-factor of Qp = 30 at fp = 1700 Hz and 0 dB DC gain.11.089093 − 1. z−2 H(z) = 1− 1. 9 e o C D inps E o 5 6 e o 1 3 e 4 F 7 B e 8 G o e A e 10 outp o o e 2 I H J Fig.z −1 + 0. 11-18: SC Biquad for realizing a lowpass-notch filtering function. The given specifications yield the z-domain transfer function 0.Lowpass-notch SC biquad This second example deals with the design of an SC biquad section with a notch frequency at fz = 1800 Hz. The second purpose is concerned with the dimensioning process and is related to the removal.z −2 (11-5) 11-34 .089093.z −1 + 0. of extra degrees of freedom in the analysis equations.5 Working Example 2 . based on SC capacitor equivalencies.774911.99029. Here. our first objective is concerned with the characterization process of the basic structure whereby we illustrate that the various SC elements of the circuit can be recognized even though a minimum switch configuration has been used.

H]] /* list of capacitors for SC equivalences */ cinpamp:[[C. Once the netlist of this basic structure is given the corresponding structural characterization is automatically generated.F..E] /* list of coupling capacitors */ cequal: [[ I.B.D.[G.[switch.D] /* list of integrating capacitors */ ccouple: [A.which can be implemented using the SC biquad section [12] represented in Fig.D]. } Frame 11-3: Instance of circdesc supporting the caracterization of the biquad represented in Fig.G].or F-damping and.o]. thus yielding the frame biquad represented in Frame 11-3.1.I-D. considering the output from either the first or the second operational amplifier.F.gnd..J]..[B. D. the characterization process generates all the symbolic information for the possible structures that may be obtained by selecting either E.C.H]..J = 1. Frame: biquad { inst :circdesc /* biquad is an instance of circedesc*/ netlist: [[switch. 11-18. cfeedb: [B.774911 D.J-A.H = 0. By equating the numerical transfer function in (11-5) to the symbolic transfer function generated automatically [17] we come to the analysis equations (11-6).[A.C. From this basic structure.89093 A.3.[capacitor.E. Thus.e].I.1.G.E]] /* voltage scaling */ .inps. 11-18.]. graph: .G-D.J]] /* capacitance scaling */ coutpamp:[[A.I = 0.89093 11-35 .. for each of them..1. we now proceed to the dimensioning process considering an E-damping biquad with the output taken from the second operational amplifier.

00694 I=J=0.E = 0.E = 9.G-I-J = 1.B.C+A.89093 (11-9) 0 2nd operational amplifier 11.H = 0.774911 J-A.00694 E=0.99723 (11-6) By pre-setting to unit the integrating capacitors we obtain equations (11-7).77e-3 (11-8) The final degree of freedom is removed based on the coupling capacitors.89093 A.5dB A=B=D=1.A.0 D.89093 A.71e-3 A.I = 1. and thus leading to equations (11-9).0e+03 2.I = 1.G-2.C+A.89093 -40 1st operational amplifier -80 -120 0 8.71e-3 G-2.E-2.71e-3 A.E = 2.0e+02 2.C+A.89093 C+E = 9.89093 A.e. so that the previously referred SC equivalence is applied and yielding equations (11-8).E = 2.0 C=0. i.00277 G=0.99029 D. I = 0.774911 E = 2.774911 I-A.H = 0.E = 9.D = -1.B-A. I = 0.B = 1.4e+03 a) b) 11-36 .77e-3 (11-7) Since the system still shows extra degrees of freedom. I = 0. by pre-setting to unit capacitor A. capacitor J is made equal to I.77e-3 I-H = 0.89093 A.

5035 I=J=10.6 Working Example 3 .0365 C=2.0 G=2. respectively.0e+03 2. The first set of values obtained from this last system of equations is shown in Fig.6 MHz 11-37 .3rd order ladder-based lowpass SC decimator In this example we shall consider the design of a 3rd order lowpass SC decimator with Chebyshev approximation.9613 B=12.Fig. 11-20b.5035 E=1.6. The final capacitance values obtained after capacitance scaling as well as the frequency response of the circuit are represented. in Fig.5 dB should be applied to the capacitors connected at the output of the first operational amplifier. 11-19a.7238 a) 1. 11-19: a) Unscaled capacitance values and b) frequency response of the resulting SC biquad. 30 10 -10 -30 1st operational amplifier -50 -70 -90 0.0e+00 2nd operational amplifier A=1. 11. nominal cutoff frequency of 3. 11-20a and in Fig. From the frequency response obtained at the output of both operational amplifiers we may conclude that a scaling factor of 11. b) Frequency response of the final biquad. 11-20: a) Capacitance values after capacitance scaling.0e+03 b) Fig.0 D=29.

0270359 − 4.11-21: 3rd order ladder-based SC decimator with a decimating factor of 2. with a decimating factor M = 2 [18].co2.25 dB maximum ripple in the passband.b 11 11 0.b inp Fig.b OP3 1 c1 1 0 Fig.2x10 . 2 b. Once the netlist of this basic structure is given the corresponding structural characterization is automatically generated.c l .036921z−4 H(z) = 3. represented in Fig.c o2.b 1. 11-21.1.x30 .b OP1 l2 1 OP2 b.150366z−2 + 0. yielding the decladder frame represented in Frame 11-4. 11-38 b.a 3 a.co1. A B 0.c s .co3.125776z −3 + 0.b 4 b.2x21.x 20.0.2x10.064237z−1 + 0.b .b 5 0.2x .b c3 6 b.and 0. For a decimating factor M = 2 the specifications given yield the z-domain transfer function 0.2x21.2x . 11-21.459719z −4 − z−6 (11-10) which is implemented using the ladder-based SC decimator.b 1. 11-22: Representation of the clocking scheme considered for the SC decimating structure of Fig.732152z−2 + 3.1.

cl.c1.cs+x30..[co1.l2+x30..z −i −i 4 (11-11) where the symbolic expressions of the numerator coefficients are n4 =x30.x20.l2].co2.co3+x20.cs.c1-x20.l2..co2.co1.x21]..l2 (11-12) 11-39 .inp.l2 n3 =-x11.co3.2.b.co3.1.l2-x30.cs. [c3.co3.co3+x21.cs n0 = -x20.] timeframe: .co2]]/* voltage scaling */ . } Frame 11-4: Instance of circdesc supporting the caracterization of the ladder-based SC decimator represented in Fig...co2 n1 = -x21.1.x11].c3.co3.c1.c1].. graph: .. 11-21.z i= o 3 ∑ ni .co1.gnd.cs] /* list of coupling capacitors */ cequal: [] /* list of capacitors for SC equivalences */ cinpamp:[[c1.c1-x30.cs].co3.cl..b.co3..[ampop.[c3.1.l2] /* list of integrating capacitors */ ccouple: [cl.cs. 11-22 and considering the output of the circuit at the output of op3 we arrive at the symbolic z-domain transfer function H(z) = i =0 ∑ d2.co3. cfeedb: [c1.[co2.l2-x30.i .c1.Frame: decladder { inst :circdesc /* decladder is an instance of circdesc*/ netlist: [pctsc.x30]]) /* capacitance scaling */ coutpamp:[[c1.0.c1 n2 = -x10.co2.x10].co1.l2+x30.c1-x21..co3.[capacitor.co3. For the clocking scheme represented in Fig.2].co2.x10.c1.

co3.co2+x20-3.l2+cs.co2.co3.c1 +cs.l2+cs.l2-cs.150366 -2.c1-cl.c1-x20.125776 -x10.l2-x30.c1.c1.co3.cs+x30.c1.l2-c3.co2.co2.064237 -2.c1-x21.l2 = -1 c3.l2-c3.l2+c3.l2+c3.c1.co3.co3+x20.l2-cs.c1+cs.c1-cl.l2.c1+cs. -x11.036921 -x11.c3+cl.c3-cs.c3+co1.l2.cs = 0.co2.l2.co3-cs.c1.cl.l2 By equating the symbolic transfer function to the numerical H(z) in (11-10) we obtain the system of equations represented in (11-14).l2 =0 -c3.c1-cl.co2+x21 =0.x20+2.c1=0.co2.c3-co2.c3-cs.cl d0 = c3.l2.c1.co3.cl = -4.co2.c1+cs.l2+cs.l2 d4 = c3.l2.cl.l2-x30.co3.l2-c3.l2+x30.co2.c1.c1-cl.064237 -x20.c1.cl.co3-cs.732152 c3.co3 = 0.c1= 3.0270359 By pre-setting to unit the integrating capacitors and the coupling capacitors co3 and cs1 we obtain the equations in (11-15).l2.c3co2.co2.co1.x21.c1.459719 -c3.c1.l2+co1.l2+co1.l2.c1.c3 +co2.c1.co1.co3.c1.and the symbolic expressions of the denominator coefficients are d6 = -c3.l2.co2 =0.co2.c1+cl.l2.co3.l2+c3.l2.c3+co1.x30+x30.l2+cs.c1.co3.co3.c1.cs.cs.c1.co2.c1+cl.l2.c1-x30.l2 =0.l2.c1.l2+x30.cl.c1.150366 -x21.c3+co2.l2.c1.c3-co1.l2.co2 =0.l2.c1 d2 = -c3.l2 = 3.l2+c3.c1.l2.l2-c3.125776 -x10.x30 =0 (11-15) (11-14) (11-13) 11-40 .c3-co1.c3+cl.co3+x21. x30.

X21=-0.40100 Co2= 0. in Fig. Solving the design equations (11-15) lead us to the capacitance values shown in Fig.cl = 1.918464 2.cl = 0.0 C1 = 1.513518 Cs1= 1.0 Cl3= 0. 11-41 .X11=-0.7982 dB at the output of the first operational amplifier.co2. co3 and cs1 were selected.0 L2 = 1.267848 2. once pre-set to unit. From this first dimensioning we then apply a scaling factor of 0.0 -20 -30 3rd operational amplifier -40 -50 0 9.co2-3.0270359 Among all the coupling capacitors of the circuit.co2-co2+cl= 3.0 C3 = 1.642374 X20= 0.0e+06 1.4733dB to the capacitors connected at the output of the second operational amplifier and a scaling factor of 2. 11-24b. 11-24a and Fig.43878 Co3= 1.0369215 X30= 0.co2+2.0369215 Co1= 1. 0 1st operational amplifier 2nd operational amplifier -10 2.cl+co1. 11-23a. 11-23 a) Unscaled capacitance values and b) frequency response of the resulting circuit.4-co1. lead to a system of equations with less terms containing products of variables.X10=-0. respectively.459719 -5+co1.719702 2.8e+07 a) b) Fig. The final capacitance values obtained after admittance scaling as well as the frequency response of the circuit obtained are represented. for these are the ones which.

11-42 .276172 2.9175992 L2= 28. we discussed the knowledge generated during both the analysis and dimensioning processes and presented a frame-based implementation of the system knowledge-base for capturing such knowledge.917599 C1 =1.90837 Cs1= 1.8e+07 a) b) Fig.601221 C3= 27.084490 1st operational amplifier -20 2nd operational amplifier -30 -40 3rd operational amplifier -50 0 9. Firstly. b) Frequency response of the final ladderbased SC decimator.0e+06 1.X21=-1.0 2.0 X30= 1.11. Then. In particular.7 Conclusions In this chapter we addressed the application of symbolic SFG computational techniques for the analysis and synthesis of SC networks.X10=-1. 11-24: a) Final Capacitance values.0 Co1= 2. we described the rule-based implementation of the pattern matching technique adopted for generating the SFG representation of an SC network.401283 Co3= 28. Various working examples were presented to methodologies described throughout this chapter.X11=-1. illustrate the techniques and -10 2. we discussed the corresponding SFG-based analysis and described the use of symbolic analyzers for carrying out step-by-step synthesis procedures as well as the automatic synthesis of SC networks.739837 X20= 1.055650 Co2=11.884132 C´o2=16.60122 Cl3= 13.

11-43 .

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