HY62UF16101C Series

64Kx16bit full CMOS SRAM

Document Title
64K x16 bit 3.0V Super Low Power Full CMOS Slow SRAM

Revision History
Revision No 03 History Divide output load into two factors - tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW - Others Add marking information Add 100ns speed Draft Date Dec.10. 2000 Remark Final

04

Dec.27. 2000

Final

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.04 /Dec. 00 Hyundai Semiconductor

7~3. super low power and 1M bit full CMOS SRAM organized as 65. Blank : Commercial.04 /Dec.HY62UF16101C Series DESCRIPTION The HY62UF16101C is a high speed. FEATURES • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup(LL/SL-part) -. 00 2 .7~3.3 55/70/85/100 HY62UF16101C-I 2. 48 . 1.7V~3. I : Industrial 2. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1. Operation Current/Icc(mA) 3 3 Standby Current(uA) LL SL 5 1 5 1 Temperature (°C) 0~70 -40~85(I) PIN CONNECTION /LB /OE A0 A1 A4 A6 A7 NC A2 NC A0 BLOCK DIAGRAM ROW DECODER SENSE AMP ADD INPUT BUFFER I/O1 IO9 /UB A3 IO10 IO11 A5 Vss IO12 NC Vcc IO13 NC /CS IO1 IO2 IO3 IO4 Vcc IO5 Vss COLUMNDECODER DATA I/O BUFFER MEMORY ARRAY 128K x 16 WRITE DRIVER IO15 IO14 A14 A15 IO6 IO7 IO16 NC NC A8 A12 A13 /WE IO8 A9 A10 A11 NC /CS /OE /LB /UB /WE CONTROL LOGIC A15 I/O16 48-FBGA(Top View) PIN DESCRIPTION Pin Name /CS /WE /OE /LB /UB Pin Function Chip Select Write Enable Output Enable Low Byte Control(I/O1~I/O8) Upper Byte Control(I/O9~I/O16) Pin Name I/O1~I/O16 A0~A15 Vcc Vss NC Pin Function Data Inputs / Outputs Address Inputs Power(2. Current value is max.FBGA Product Voltage Speed No.3 55/70/85/100 Note 1.2V. It is particularly well suited for used in high density low power system application.3V) Ground No Connection Rev. The HY62UF16101C uses high performance full CMOS process technology and designed for high speed low power circuit technology. (V) (ns) HY62UF16101C 2.536 words by 16bit.2V(min) data retention • Standard pin configuration -.

Exposure to the absolute maximum rating conditions for extended period may affect reliability.6 0 to 70 -40 to 85 -55 to 150 1. When /UB is LOW. When /LB is LOW. L=VIL. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. 00 2 . TRUTH TABLE /CS H X L L L /WE X X H H H /OE X X H H L /LB X H L X L H L L H L /UB X H X L H L L H L L Mode Deselected Deselected Output Disabled Output Disabled Read I/O I/O1~I/O8 High-Z High-Z High-Z High-Z DOUT Hi-Z DOUT DIN Hi-Z DIN I/O9~I/O16 High-Z High-Z High-Z High-Z Hi-Z DOUT DOUT Hi-Z DIN DIN Power Stand by Stand by Active Active Active L L X Write Active Note: 1.2 to 3. HY62UF16101CLLF HY62UF16101CLLF-I HY62UF16101CSLF HY62UF16101CSLF-I Speed 55/70/85/100 55/70/85/100 55/70/85/100 55/70/85/100 Power LL-part LL-part SL-part SL-part Temp. I/O 1 -I/O 8. I : Industrial ABSOLUTE MAXIMUM RATING (1) Symbol VIN.0 260 10 Unit V V °C °C °C W °C sec Remark HY62UF16101C HY62UF16101C-I Note 1.6 -0. data is written or read to the lower byte. H=VIH. /UB. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. /LB(Upper. I/O 9 -I/O 16. VOUT Vcc TA TSTG PD TSOLDER Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Lead Soldering Temperature & Time Rating -0. I I Package FBGA FBGA FBGA FBGA Note 1 Blank : Commercial. X=don't care(VIH or VIL) 2.HY62UF16101C Series ORDERING INFORMATION Part No. Rev. data is written or read to the Upper byte.2 to 4.04 /Dec.

0.1mA VOH Output High Voltage IOH = -1. /LB.Typical values are at Vcc = 3.0.4 - CAPACITANCE (Temp = 25°C. VIN = VIH or VIL ISB1 Standby Current /CS > Vcc .5 1 5 0.0mA Note : 1.HY62UF16101C Series RECOMMENDED DC OPERATING CONDITION Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. -1 -1 Typ.0V.0 0 Max.2V VOL Output Low Voltage IOL = 2. 1us Cycle Time. 00 3 .3 0 Vcc+0.2V. II/O = 0mA.5V for pulse width less than 30ns 2. VIN < 0. /UB = /LB = VIH Icc Operating Power Supply /CS = VIL. TA = 25°C 2. Min. VIN = VIH or VIL Cycle Time = Min. 1 1 Unit uA uA - - 3 5 mA mA - - 45 mA - 0. TA = 0°C to 70°C / -40°C to 85°C (I) Sym Parameter Test Condition ILI Input Leakage Current Vss < VIN < Vcc ILO Output Leakage Current Vss < VOUT < Vcc. DC ELECTRICAL CHARACTERISTICS Vcc = 2.0MHz) Symbol Parameter CIN Input Capacitance(Add. f= 1.04 /Dec.3V. /CS = VIH or /OE = VIH or /WE = VIL.2 -0.2V /CS = VIL.2V.5 0. VIN > Vcc . 3. VIN = VIH or VIL. 3.100% Duty. 2.Typical values are sampled and not 100% tested. /CS.3 0. VIL = -1. Undershoots are sampled and not 100% tested. 100% Duty II/O = 0mA ISB TTL Standby Current /CS = VIH or (TTL Input) /UB = /LB = VIH.4 - mA uA uA V V 2.7V~3.0.3(1) Typ. /WE.6 Unit V V V V Note : 1. /UB. 8 10 Unit pF pF Rev. /OE) COUT Output Capacitance(I/O) Note : These parameters are sampled and not 100% tested Condition VIN = 0V VI/O = 0V Max. Max.7 0 2. Current II/O = 0mA ICC1 Average Operating Current /CS < 0.2V or LL VIN < Vss + 0.2V or SL (CMOS Input) /UB = /LB > Vcc .

tOW Others Value 0.tBHZ. TA = 0°C to 70°C / -40°C to 85°C (I).04 /Dec. 00 4 .HY62UF16101C Series AC CHARACTERISTICS Vcc = 2. /UB Enable to Output in Low Z tCHZ Chip Deselection to Output in High Z tOHZ Out Disable to Output in High Z tBHZ /LB. Including jig and scope capacitance Rev. /UB Disable to Output in High Z tOH Output Hold from Address Change WRITE CYCLE tWC Write Cycle Time tCW Chip Selection to End of Write tAW Address Valid to End of Write tBW /LB.tCHZ.2V 5ns 1.tOLZ. unless otherwise specified -55 -70 # Symbol Parameter Min Max Min Max 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 READ CYCLE tRC Read Cycle Time tAA Address Access Time tACS Chip Select Access Time tOE Output Enable to Output Valid tBA /LB.5V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load AC TEST LOADS VTM=2.8V 1029 Ohm DOUT CL(1) 1728 Ohm Note 1.tBLZ.3V.tOHZ. unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ. /UB Access Time tCLZ Chip Select to Output in Low Z tOLZ Output Enable to Output in Low Z tBLZ /LB. /UB Valid to End of Write tAS Address Set-up Time tWP Write Pulse Width tWR Write Recovery Time tWHZ Write to Output in High Z tDW Data to Write Time Overlap tDH Data Hold from Write Time tOW Output Active from End of Write 55 10 5 5 0 0 0 10 55 50 50 50 0 45 0 0 25 0 5 55 55 35 55 30 30 30 20 70 10 5 5 0 0 0 10 70 60 60 60 0 50 0 0 30 0 5 70 70 40 70 30 30 30 25 -85 Min Max Min -10 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 85 10 5 5 0 0 0 10 85 70 70 70 0 55 0 0 35 0 5 85 85 45 85 30 30 30 30 - 100 20 5 10 0 0 0 15 100 80 80 80 0 75 0 0 45 0 10 100 100 50 100 30 30 30 35 - AC TEST CONDITIONS TA = 0°C to 70°C / -40°C to 85°C (I).tWHZ.4V to 2.7~3.

4. a low /CS1 and low /UB and/or /LB./ LB tOE tOLZ(3) tBLZ(3) tCLZ(3) Data Valid tBHZ(3) tOH /OE tOHZ(3) Data Out High-Z READ CYCLE 2(Note 1. a high /WE. low for active /UB and /LB in high for the standby.2.4) tRC ADDR tAA tACS /CS tCHZ(3) tBA /UB .2. Transition is measured + 200mV from steady state voltage. /LB tACS tCLZ(3) Data Out Data Valid tCHZ(3) Notes: A read occurs during the overlap of a low /OE.HY62UF16101C Series TIMING DIAGRAM READ CYCLE 1(Note 1. 00 5 . low for active Rev.4) /CS /UB. /OE = VIL 3. /CS in high for the standby. This parameter is sampled and not 100% tested. 2.04 /Dec.4) tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH READ CYCLE 3(Note 1.

A write occurs during the overlap of a low /WE.HY62UF16101C Series WRITE CYCLE 1(1.7) Data Out tDW Data Valid tOW (5) (6) tDH WRITE CYCLE 2 (Note 1. 6. low for active /UB and /LB in high for the standby.04 /Dec. 2. Transition is measured + 200mV from steady state. 5. a low /CS1 and low /UB and/or /LB. 7. /LB. 8./LB tWP /WE tAS Data In High-Z tWHZ(3. /LB and /UB low transition occur simultaneously with the /WE low transition or after the /WE transition. Q(data out) is the same phase with the write data of this write cycle.4. During this period.8) (/WE Controlled) tWC ADDR tWR(2) tCW /CS tAW tBW /UB. 4. If the /CS. /CS in high for the standby. This parameter is sampled and not 100% tested./LB tWP /WE tDW Data In High-Z Data Valid tDH tCW tWR(2) Data Out High-Z Notes: 1. /UB. or /WE going high to the end of write cycle. outputs remain in a high impedance state. I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. tWR is measured from the earlier of /CS.4. low for active Rev. 3.8) (/CS Controlled) tWC ADDR tAS /CS tAW tBW /UB. 00 6 . Q(data out) is the read data of the next address.

04 /Dec.HY62UF16101C Series DATA RETENTION ELECTRIC CHARACTERISTIC TA=0°C to 70°C / -40°C to 85°C (I) Symbol Parameter VDR Vcc for Data Retention Test Condition /CS > Vcc .2V.2V.2V or /UB = /LB > Vcc – 0.2V Vcc=1. 00 7 .5V. /CS > Vcc .0.0.3 Unit V ICCDR Data Retention Current 0 tRC(2) 0. tRC is read cycle time.0.7V tCDR DATA RETENTION MODE tR VDR CS or /UB &/LB VSS CS > VCC-0. VIN > Vcc . Typical values are under the condition of TA = 25°C. 2.2V See Data Retention Timing Diagram Min 1. VIN > Vcc .2V or SL VIN < Vss + 0.2V Rev.2V.2V or /UB = /LB > Vcc-0.0.2 Typ Max 3.5 - 2 1 - uA uA ns ns tCDR tR Chip Deselect to Data Retention Time Operating Recovery Time Notes: 1. LL /UB = /LB > Vcc-0. DATA RETENTION TIMING DIAGRAM VCC 2.2V or VIN < Vss + 0.

25 6.04 /Dec.3 6.9 0.2 0.3 0. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. DIMENSIONING AND TOLERANCING PER ASME Y14.1 6. 00 8 .35 1.75 3.25 - Max.1 1.2 - Typ. SM-1994. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 0. THIS IS A CONTROLLING DIMENSION.75 0. 5.3 0.1 0.3 0.HY62UF16101C Series PACKAGE INFORMATION 48ball Fine-Pitch Ball Grid Array Package(F) BOTTOM VIEW B A A1 CORNER INDEX AREA 6 A A B C D C E F G H C1/2 C1/2 C1 5 4 3 2 1 B1/2 TOP VIEW B1/2 B1 SIDE VIEW 5 C E1 E2 E SEATING PLANE A 4 r 3 D(DIAMETER) Note Symbol A B B1 C C1 D E E1 E2 r Min. 6.7 0. 4. 3.4 1.2 5.75 6. Rev. 6.4 0.0 0.8 0. ALL DIMENSIONS ARE MILLIMETERS. 2.

Small Letter : Year (ex : 00 = year 2000.85 .HY62UF16101C Series MARKING INSTRUCTION Package H Y Marking Example U F 6 1 1 C c FBGA s s t y y w w p x x x x x K O R Index • HYUF611Cc c : Part Name : Power Consumption -L -S : Speed .70 .10 • t : Temperature -C -I : 55ns : 70ns : 85ns : 100ns : Industrial ( -0 ~ 70 °C ) : Industrial ( -40 ~ 85 °C ) : Low Low Power : Super Low Power • ss • yy • ww • p • xxxxx • KOR Note .04 /Dec.55 . 01= year 2001) : Work Week ( ex : 12 = work week 12 ) : Process Code : Lot No.Capital Letter . : Origin Country : Fixed Item : Non-fixed Item Rev. 00 9 .