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Review - Canonical Forms

Standard form for a Boolean expression unique algebraic expression from a TT. Two Types:
Sum of Products Product of Sums

Sum of Products (disjunctive normal form, minterm expansion). Example:


minterms abc abc abc abc abc abc abc abc abc 000 001 010 011 100 101 110 111 f f 01 01 01 10 10 10 10 10

One product (and) term for each 1 in f: f = abc + abc + abc +abc +abc f = abc + abc + abc
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Canonical Forms
Product of Sums (conjunctive normal form, maxterm expansion). Example:
maxterms a+b+c a+b+c a+b+c a+b+c a+b+c a+b+c a+b+c a+b+c abc 000 001 010 011 100 101 110 111 f f 01 01 01 10 10 10 10 10

One sum (or) term for each 0 in f: f = (a+b+c)(a+b+c)(a+b+c) f = (a+b+c)(a+b+c)(a+b+c)(a+b+c)(a+b+c) Mapping from one form to the other: Derive TT then proceed.
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Two-level Logic Simplication


Key tool: The Uniting Theorem x (y + y) = x (1) = x ab 00 01 10 11 ab 00 01 10 11 f 0 0 1 1 g 1 0 1 0 f = ab + ab = a(b+b) = a

b values change within the on-set rows a values dont change b is eliminated, a remains

g = ab+ab = (a+a)b =b
b values stay the same a values changes b remains, a eliminated

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Boolean Cubes
Visual technique for identifying when the Uniting Theorem can be applied
1-cube 0 1 00 2-cube 01 xy y 10
000 001

3-cube 11
010 110 101 011 111

z
100

Sub-cubes of on nodes can be used for simplification.


On-set - filled in nodes, off-set - empty nodes
ab 00 01 10 11 f 0 0 1 1 g 1 0 1 0 01 b 00 f ab + ab' = a a 10 11 a asserted & unchanged b varies

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3-variable cube example


FA carry out:
(a' + a)bc

abc 000 001 010 011 100 101 110 111

cout 0 0 0 1 0 1 1 1

ab(c'+c)
011 010 110 111

a(b+b')c
101

b
000

001

c
100

cout = bc + ab + ac

What about larger sub-cubes?


011 010 110 111

abc + abc + abc + abc ac + ac + ab = a + ab = a Both b & c change, a is asserted & remains constant.
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b
000

001

101

c
100

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Karnaugh Map Method


K-map is an alternative method of representing the TT and to help visual the adjacencies.
a b 0 1 0 1 cd 00 01 11 10 5 & 6 variable k-maps possible ab 00 01 11 10

ab c 00 01 11 10 0 1

Examples:
a b 0 1 0 0 1 1 0 1 f=a ab c 00 01 11 10 0 0 0 1 0 1 0 1 1 1 cout = ab + bc + ac
Spring 2000 EECS150

a b 0 1 0 1 1 1 0 0 g = b' ab c 00 01 11 10 0 0 0 1 1 1 0 0 1 1 f=a
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K-maps (cont.)
ab c 00 01 11 10 0 1 0 0 1 1 0 0 1 1 f = b'c' + ac

ab cd 00 01 11 10 00 1 0 1 1 01 0 1 1 1 11 0 0 1 1 10 1 0 1 1 f = c + a'bd + b'd' (bigger groups are better)

Circling Zeros
ab cd 00 01 11 10 00 1 0 1 1 01 0 1 1 1 11 0 0 1 1 10 1 0 1 1

f = (b' + c + d)(a' + c + d')(b + c + d')

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BCD incrementer example


abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 w= wxyz 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 - - - - - - - - - - - - - - - - - - w
ab cd 00 01 11 10 00 0 0 0 0 01 0 0 1 0 11 11 1 0 cd 00 01 11 10 ab 00 0 0 1 0 01 1 1 0 1 11 11 0 0 -

ab cd 00 01 11 10 00 0 1 0 1

y
01 0 1 0 1 11 11 0 0 cd

ab 00 01 11 10 00 1 0 0 1

z
01 1 0 0 1 11 11 1 0 -

x=

y=

z=

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Higher Dimensional K-maps


de 00 10 11 10 00 01 11 a=0 00 10 11 10
ab = 10 ef 00 10 11 10 00 01 11 ab = 11 00 10 11 10 00 01 11 ab = 01 00 10 11 10 00 01 11 ab = 00 00 10 11 10 10 10 10 cd 00 01 11 10

bc 00 01 11

10

a=1

10

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Katz Chapter 3 - Multi-level Combinational Logic


Example: reduced sum-of-products form x = adf + aef + bdf + bef + cdf + cef + g implementation in 2-levels with gates:
a d f

cost: 7-input OR, 6 3-input AND 50 transistors + 25 wires (19 linteral plus 6 internal) delay: 3-input AND gate delay + 7-input OR gate delay

Factored form: x = (a + b +c)(d + e)f + g

cost: 1 3-input OR, 2 2-input OR, 1 3-input AND delay: 3-input OR + 3-input AND + 2-input OR Which is faster? In general: Using multiple levels (more than 2) will reduce the cost. Sometimes also delay. Sometime a tradeoff between cost and delay.
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a b c d e f g

Multi-level Combinational Logic


Example: F = abc + abd +acd + bcd a let x = ab y = c+d b c f = xy + xy a
b d a c d b c d
a b c d x f y

Example: result output functions from 4-bit adder

No convenient hand methods for multi-level logic simplication:


1 CAD Tools, example misII (UCB) 2 exploit some special structure, example adder
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NAND-NAND & NOR-NOR Networks


DeMorgans Law: (a + b) = a b b + b = (a b)
= =

(a b) = a + b (a b) = (a + b)
= =

push bubbles or introduce in pairs or remove pairs.

Mapping from AND/OR to NAND/NAND


a)
a b c d

b)

c)

d)

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NAND-NAND & NOR-NOR Networks


Mapping AND/OR to NOR/NOR
a b c d a b c d

a)

a b c d

b)

c)

Mapping OR/AND to NOR/NOR


a) b)

c)

pair

OR/AND to NAND/NAND

a' b' c' d'

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Multi-level Networks
F = a(b + cd) + bc
c d b a c' f

Convert to NANDs (note fanout)


a b c d

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EXOR Function
Parity, addition mod 2
x y xor xnor 00 0 1 01 10 11
x y

x xor y = xy + xy
x' y x y'

1 1 0

0 0 1

Another approach:
y

x 0 1 if x=0 then y else y'

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