You are on page 1of 201

ECEN654 Yield and Testing

Version 0.99993 (Beta Lecture)




First.. Testing Basics

VLSI realization process Verification and test Ideal and real tests Costs of testing Roles of testing A modern VLSI device - system-on-a-chip Lecture outline

» Part I: Introduction to testing » Part II: Test methods » Part III: Design for testability




VLSI Realization Process

Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer




Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.




Verification vs. Test
Verifies correctness of manufactured hardware. Two-part process:
» 1. Test generation: software process executed once during design » 2. Test application: electrical tests applied to hardware

Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design.

Test application performed on every manufactured device. Responsible for quality of devices.




Problems of Ideal Tests

Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.




Real Tests

Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.




Testing as Filter Process
Mostly good chips

Good chips Prob(pass test) = high Prob(good) Prob(good) = y Pr ow l ob = (fa t) il es t Fabricated t s est chips )= as p lo b( o w Pr Defective chips

Prob(bad) 1Prob(bad) = 1- y Prob(fail test) = high

Mostly bad chips




Costs of Testing Design for testability (DFT) » Chip area overhead and yield reduction » Performance overhead Software processes of test » Test generation and fault simulation » Test programming and debugging Manufacturing test » Automatic test equipment (ATE) capital cost » Test center operational cost ELEN654 A TM .

Motivation: Test generation complexity increases exponentially with the size of the circuit. bus Logic Logic PO PI block A block B Test output ATM Test input ELEN654 . avoids test generation for combined A and B blocks. Example: Test hardware applies tests to blocks A and B and to internal bus. Int.Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity.

024 x $3.024 digital pins: ATE purchase price » = $1. analog instruments.1.5-1.600) » = 4.5 cents/second ELEN654 A TM .Cost of Manufacturing Testing in 2000AD 0.272M Running cost (five-year linear depreciation) » = Depreciation + Maintenance + Operation » = $0.854M + $0.439M/(365 x 24 x 3.000 = $4.085M + $0.2M + 1.439M/year Test cost (24 hour ATE operation) » = $1.5M » = $1.0GHz.

ELEN654 A TM . Diagnosis: Identification of a specific fault that is present on DUT.Roles of Testing Detection: Determination whether or not the device under test (DUT) has some fault. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

A Modern VLSI Device System-on-a-chip (SOC) RAM ROM MixedMixedsignal Codec Data terminal DSP cor e InterInterface logic Transmission medium ELEN654 A TM .

Stuff we will cover Basic concepts and definitions Test process and ATE Test economics and product quality Fault modeling ELEN654 A TM .

More things Logic and fault simulation Testability measures Combinational circuit ATPG Sequential circuit ATPG Memory test Analog test Delay test and IDDQ test Scan design BIST Boundary scan and analog test bus System test and core-based design ELEN654 A TM .

VLSI Testing Process and Equipment Motivation Types of Testing Test Specifications and Plan Test Programming Test Data Analysis Automatic Test Equipment Parametric Testing Summary ELEN654 A TM .

VIH . IIH ELEN654 A TM . VOH . tr . IOH . IOL. and analog test in System-on-a-Chip (SOC) technology Need to understand parametric testing » Used to take setup. hold time measurements » Use to compute VIL . VOL .Motivation Need to understand some Automatic Test Equipment (ATE) technology » Influences what tests are possible » Serious analog measurement limitations at high digital frequency or in the analog domain » Need to understand capabilities for digital logic. IIL. td . memory. tf .

or design debug » Verifies correctness of design and of test procedure – usually requires correction to design Manufacturing testing » Factory testing of all manufactured chips for parametric faults and for random defects Acceptance testing (incoming inspection) » User (customer) tests purchased parts to ensure quality ELEN654 A TM .Types of Testing Verification testing. characterization testing.

Testing Principle ELEN654 A TM .

Automatic Test Equipment Components Consists of: » Powerful computer » Powerful Digital Signal Processor (DSP) for analog testing » Test Program (written in high-level language) running on the computer » Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) » Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad) ELEN654 A TM .

Diagnostics and Reasoning Ferociously expensive May comprise: » » » » » Scanning Electron Microscope tests Bright-Lite detection of defects Electron beam testing Artificial intelligence (expert system) methods Repeated functional tests ELEN654 A TM .

Characterization Test Worst-case test » » » » » Choose test that passes/fails chips Select statistically significant sample of chips Repeat test for every combination of 2+ environmental variables Plot results in Schmoo plot Diagnose and correct design errors Continue throughout production life of chips to improve design and process to increase yield ELEN654 A TM .

Schmoo Plot ELEN654 A TM .

Manufacturing Test Determines whether manufactured chip meets specs Must cover high % of modeled faults Must minimize test time (to control cost) No fault diagnosis Tests every device on chip Test at speed of application or speed guaranteed by supplier ELEN654 A TM .

Burn-in or Stress Test Process: » Subject chips to high temperature & over-voltage supply. while running production tests Catches: » Infant mortality cases – these are damaged chips that will fail in the first 2 days of operation – causes bad devices to actually fail before chips are shipped to customers » Freak failures – devices having same failure mechanisms as reliable devices ELEN654 A TM .

Incoming Inspection Can be: » Similar to production testing » More comprehensive than production testing » Tuned to specific systems application Often done for a random sample of devices » Sample size depends on device quality and system reliability requirements » Avoids putting defective device in a system where cost of diagnosis exceeds incoming inspection cost ELEN654 A TM .

Types of Manufacturing Tests Wafer sort or probe test – done before wafer is scribed and cut into chips » Includes test site characterization – specific test devices are checked with specific patterns to measure: – Gate threshold – Polysilicon field threshold – Poly sheet resistance. etc. Packaged device tests ELEN654 A TM .

etc. voltages. – fast and cheap Functional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive – main topic of tutorial ELEN654 A TM . currents.Sub-types of Tests Parametric – measures electrical properties of pin electronics – delay.

which determine whether hardware matches its specification – typically have low fault coverage (< 70 %) ELEN654 A TM .Two Different Meanings of Functional Test ATE and Manufacturing World – any vectors applied to cover high % of faults during manufacturing test Automatic Test-Pattern Generation World – testing with verification vectors.

Test Specifications & Plan Test Specifications: » » » » Functional Characteristics Type of Device Under Test (DUT) Physical Constraints – Package. etc. Environmental Characteristics – supply. humidity. failure rate. etc. etc. pin numbers. temperature. » Reliability – acceptance quality level (defects/million). Test plan generated from specifications » Type of test equipment to use » Types of tests » Fault coverage requirement ELEN654 A TM .

Test Programming ELEN654 A TM .

and find design and process weaknesses » Allows improvement of logic & layout design rules ELEN654 A TM .Test Data Analysis Uses of ATE test data: » Reject bad DUTS » Fabrication process information » Design weakness information Devices that did not fail are good only if tests covered 100% of faults Failure mode analysis (FMA) » Diagnose reasons for device failure.

ATE: Automatic Test Equipment Example: ADVANTEST Model T6682 ATE ELEN654 A TM .

T6682 ATE Block Diagram ELEN654 A TM .

T6682 ATE Specifications Uses 0.25 ps Pattern multiplexing: write 2 patterns in one ATE cycle Pin multiplexing: use 2 pins to control 1 DUT pin ELEN654 A TM . 500. or 1000 MHz Timing accuracy: +/.870 ps Clock settling resolution: 31.200 ps Drive voltage: -2.35 µm VLSI chips in implementation 1024 pin channels Speed: 250.5 to 6 V Clock/strobe accuracy: +/.

36 data bits » For memory test – has address descrambler » Has address failure memory Scan pattern generator (SCPG) supports JTAG boundary scan. vector width determined by # DUT pins Algorithmic pattern generator (ALPG): 32 independent address bits. greatly reduces test vector memory for full-scan testing » 2 Gvector or 8 Gvector sizes ELEN654 A TM .Pattern Generation Sequential pattern generator (SQPG): stores 16 Mvectors of patterns to apply to DUT.

Response Checking and Frame Processor Response Checking: » Pulse train matching – ATE matches patterns on 1 pin for up to 16 cycles » Pattern matching mode – matches pattern on a number of pins in 1 cycle » Determines whether DUT output is correct. changes patterns in real time Frame Processor – combines DUT input stimulus from pattern generators with DUT output waveform comparison Strobe time – interval after pattern application when outputs sampled ELEN654 A TM .

IH . VIL . VOH . touches chips through a socket (contactor) Uses liquid cooling Can independently set VIH . VOL .Probing Pin electronics (PE) – electrical buffering circuits. IL . put as close as possible to DUT Uses pogo pin connector at test head Test head interface through custom printed circuit board to wafer prober (unpackaged chip test) or package handler (packaged chip test). VT for each pin Parametric Measurement Unit (PMU) ELEN654 A TM .

Pin Electronics ELEN654 A TM .

Probe Card and Probe Needles or Membrane Probe card – custom printed circuit board (PCB) on which DUT is mounted in socket – may contain custom measurement hardware (current test) Probe needles – come down and scratch the pads to stimulate/read pins Membrane probe – for unpackaged wafers – contacts printed on flexible membrane. pulled down onto wafer with compressed air to get wiping action ELEN654 A TM .

monitor. & analyze VLSI chips ELEN654 A TM . micro-floppy. Ethernet Viewpoint software provided to debug. keyboard. CD-ROM. evaluate.T6682 ATE Software Runs Solaris UNIX on UltraSPARC 167 MHz CPU for nonreal time functions Runs real-time OS on UltraSPARC 200 MHz CPU for tester control Peripherals: disk. HP GPIB.


and memory test – supports scan-based test Modular – can be upgraded with additional instruments as test requirements change enVision Operating System 1 or 2 test heads per tester. power test.Specifications Intended for SOC test – digital. 1 GHz maximum test rate Maximum 64 Mvectors memory storage Analog instruments: DSP-based synthesizers. analog. digitizers.3 GHz) ELEN654 A TM . Radio Frequency (RF) source and measurement capability (4. time measurement. maximum of 1024 digital pins.

Multi-site Testing – Major Cost Reduction One ATE tests several (usually identical) devices at the same time For both probe and package test DUT interface board has > 1 sockets Add more instruments to ATE to handle multiple devices simultaneously Usually test 2 or 4 DUTS at a time. usually test 32 or 64 memory chips at a time Limits: # instruments available in ATE. type of handling equipment available for package ELEN654 A TM .

4. Probe test (wafer sort) – catches gross defects Contact electrical test Functional & layout-related test DC parametric test AC parametric test » » Unacceptable voltage/current/delay at pin Unacceptable device operation limits ELEN654 A TM . 2. 3.Electrical Parametric Testing Typical Test Program 1. 5.

DC Parametric Tests Contact Test

1. Set all inputs to 0 V 2. Force current Ifb out of pin (expect Ifb to be 100 to 250 µA) 3. Measure pin voltage Vpin. Calculate pin resistance R

Contact short (R = 0 Ω) No problem

Pin open circuited (R huge), Ifb and Vpin large




Power Consumption Test

1. 2.

Set temperature to worst case, open circuit DUT outputs Measure maximum device current drawn from supply ICC at specified voltage

» »

ICC > 70 mA (fails) 40 mA < ICC 70 mA (ok)




Output Short Current Test

1. 2. 3.

Make chip output a 1 Short output pin to 0 V in PMU Measure short current (but not for long, or the pin driver burns out)

» »

Short current > 40 µA (ok) Short current 40 µA (fails)




Output Drive Current Test

1. 2. 3.
IOL < 2.1 mA (fails) IOH < -1 mA (fails)

Apply vector forcing pin to 0 Simultaneously force VOL voltage and measure IOL Repeat Step 2 for logic 1






Increase input voltage in 0. write logic 0 followed by propagation 2.1 V steps until output value is wrong Repeat process. For each I/P pin. Read output.0 V (fails) ≤ ≥ A ELEN654 TM . but stepping down from logic 1 by 0.1 V until output value fails » » » » Wrong output when 0 input > 0.8 V (ok) Wrong output when 0 input 0.8 V (fails) Wrong output when 1 input < 2. pattern to output.Threshold Test 1.0 V (ok) Wrong output when 1 input 2.

AC Parametric Tests Rise/fall Time Tests ELEN654 A TM .

Set-up and Hold Time Tests ELEN654 A TM .

Apply standard output pin load (RC or RL) Apply input pulse with specific rise/fall Measure propagation delay from input to output Delay between 5 ns and 40 ns (ok) Delay outside range (fails) ELEN654 A TM . 3. 2.Propagation Delay Tests 1.

Summary Parametric tests – determine whether pin electronics system meets digital logic voltage. and delay time specs Functional tests – determine whether internal logic/analog subsystems behave correctly ATE Cost Problems » Pin inductance (expensive probing) » Multi-GHz frequencies » High pin count (1024) ATE Cost Reduction » Multi-Site Testing » DFT methods like Built-In Self-Test ELEN654 A TM . current.

Test Economics Economics defined Costs Production Benefit .cost analysis Economics of design-for-testability (DFT) Quality and yield loss Summary ELEN654 A TM .

overcoats. -. roads. concerts. capital goods such as machinery. and yachts) and to distribute them to various members of society for their consumption. labor. and technical knowledge) to produce various commodities (such as wheat.Paul Samuelson ELEN654 A TM .The Meaning of Economics Economics is the study of how men choose to use scarce or limited productive resources (land.

Engineering Economics Engineering Economics is the study of how engineers choose to optimize their designs and construction methods to produce objects and systems that will optimize their efficiency and hence the satisfaction of their clients. ELEN654 A TM .

+ 0.2x For traveling x miles 25.2 Total cost / x x A Fixed cost ELEN654 TM .000 Purchase price of car Gasoline. Variable cost 20 cents/mile maintenance.Costs Fixed cost Variable cost Total cost Average cost Example: Costs of running a car $25.2x Total cost $25.000 Average cost $ ----------.000 + 0. repairs 0.

2 = 45 cents/mile 50. $6.6. $0 resale value after 20 years 25.000 Case 3: 10.000 miles/yr.12.250 Average cost = $ ----------------------.250 resale value after 10 years 25.+ 0.000 .000 Case 2: 10.000 ELEN654 A TM .000 miles/yr.+ 0.000 .000 .+ 0.500 resale value after 5 years 25.000 miles/yr.0 Average cost = $ -----------------.5 cents/mile 200. $12.2 = 32.75 cents/mile 100.Simple Cost Analysis Case 1: 10.2 = 38.500 Average cost = $ ------------------------.

Total and Variable Fixed.000 20.00 0 40. Total and Variable Costs ($) Costs ($) Costs ($) Costs ($) 25. Total and Variable Fixed. Total and Variable Fixed.000 0 0 e bl r ia Va st co Cost Analysis Graph a ot T l st co Fixed cost 50 k 100k Miles Driven A Average cost 150k 0 200k 100 Average Cost (cents) Average Cost (cents) Average Cost (cents) Average Cost (cents) 50 TM .ELEN654 Fixed.

Q = f (x) Average product. enterprise.Production Inputs (x): Labor. dQ / dx ELEN654 A TM . energy (x may include both fixed and variable costs) Production output. capital. Q / x Marginal product. land.

eventually reaching a point beyond which increasing the inputs will cause progressively less increase in output. Q(x) Output. Q(x) Output. then the output may increase.Law of Diminishing Returns If one input of production is increased keeping inputs constant. Q(x) Input Resources. Output. Q(x) Output. x A ELEN654 TM .

--.---. 0. Eff. Tech.-. dx x 1. Eff.0 ELEN654 TM .5 0.Technological Efficiency Technological efficiency = Q/x where x = variable cost To maximize tech.----. x A dQ Q ---. Q/x dQ/dx Input Resources. Eff.= 0 x dx x2 or Q dQ --.0 Tech. Efficiency: 1 dQ Q -. Tech. Max.= 0. eff. Tech. Eff. tech.= ----x dx eff.

where X is the total (fixed + variable) cost.Economic Efficiency Maximum economic efficiency minimizes the total average cost X /Q. For average cost = marginal cost – Take variable cost to maximize technological efficiency – Take total cost to maximize economic efficiency ELEN654 A TM . X /Q = dX /dQ. Maximum economic efficiency is achieved when total average cost equals the marginal cost.

dx/dQ With zero fixed cost assumed Input resources A ELEN654 TM . economic efficiency Costs Costs Costs Costs Average cost.Maximum Efficiencies Max. X/Q Max. efficiency With actual fixed cost Marginal cost. tech.

eventually the law of diminishing returns applies.Mass Production Production can be increased at a faster rate than the increase of inputs. This is known as increasing returns to scale. Some reasons for increasing returns to scale – Technological factors – Specialization – Only some inputs are increased If increase of inputs continues. ELEN654 A TM .

training of personnel. reduced wastage. etc.> 1 Annual costs ELEN654 A TM . etc. Benefit/cost ratio Annual benefits B/C ratio = -------------------------. automation.Benefit-Cost Analysis Benefits: Savings in manufacturing costs (capital and operational) and time. Costs: Extra hardware.

yield loss due to non-functional tests – Benefit examples: Reduced ATE cost due to self-test. DFT on chip may impact the costs at board and system levels.Economics of Design for Testability (DFT) Consider life-cycle cost. Weigh costs against benefits – Cost examples: reduced yield due to area overhead. inexpensive alternatives to burn-in test ELEN654 A TM .

Cost saving +/+/.Benefits and Costs of DFT FabriFabrication Manuf. Manuf.Cost increase may balance cost reduction ELEN654 A TM . Maintenance Test test Diagnosis Service and repair interruption Level Design and test Chips +/+ - Boards +/+ - - System +/+ - - - - + Cost increase .

The overall benefit/cost ratio for design. test and manufacturing should be maximized. A DFT or test method should be selected to improve the product quality with minimal increase in cost due to area overhead and yield loss. ELEN654 A TM . It combines common sense.Summary Economics teaches us how to make the right trade-offs. one should select the most economic design over the cheapest design. experience and mathematical methods.

Yield Analysis & Product Quality Yield and manufacturing cost Clustered defect yield formula Yield improvement Defect level Test data analysis Example: SEMATECH chip Summary ELEN654 A TM .

VLSI Chip Yield A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. Cost of a chip: Cost of fabricating and testing a wafer --------------------------------------------------------------------------------------------------------------------------------------Yield x Number of chip sites on the wafer A ELEN654 TM . A chip with no manufacturing defect is called a good chip. Yield is denoted by symbol Y. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield.

77 Unclustered defects Wafer yield = 12/22 = 0.Clustered VLSI Defects Good chips Faulty chips Defects Wafer Clustered defects (VLSI) Wafer yield = 17/22 = 0.55 ELEN654 A TM .

(no clustering) Γ (α+x ) ELEN654 A TM .. ---------------------(1+Ad x ! Γ (α) (1+Ad /α) α+x where Γ is the gamma function =0. clustering) α = ∞ .Yield Parameters Defect density (d ) = Average number of defects per unit of chip area Chip area (A) Clustering parameter (α) α Negative binomial distribution of defects. p (x ) is Poisson distr. p (x ) is a delta function (max. α =0. p (x ) = Prob (number of defects on a chip = x ) (Ad (Ad /α) x = ------------.

5. α = ELEN654 TM . Y = 0.37 too pessimistic ! A Example: Ad = 1. Y = 0.58 Unclustered defects: α = ∞ . Y = e . α = 0.Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / α ) − α Example: Ad = 1.0.Ad ∞ .0.

Defect Level or Reject Ratio Defect level (DL) is the ratio of faulty chips among the chips that pass tests. DL is measured as parts per million (ppm). ELEN654 A TM . DL is a measure of the effectiveness of tests. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable. DL is a quantitative measure of the manufactured product quality.

Determination of DL From field return data: Chips failing in the field are returned to the manufacturer. From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL. The number of returned chips normalized to one million chips shipped is the DL. ELEN654 A TM .

0) remove all faulty chips. -β Y = Y (1) = (1 + Af / β) ELEN654 A TM . T The modified yield equation: Y (T ) = (1 + TAf / β) . f = average number of stuck-at faults per unit chip area – Fault clustering parameter. β – Stuck-at fault coverage.Modified Yield Equation Three parameters: – Fault density.β Assuming that tests with 100% fault coverage (T =1.

Y (1) DL (T ) = -------------------(T Y (T ) β ( β + TAf ) = 1 .-------------------β ( β + Af ) Where T is the fault coverage of tests. β is the fault clustering parameter. Af and β are determined by test data analysis. A ELEN654 TM .Defect Level Y (T ) . Af is the average number of faults on the chip of area A.

Example: SEMATECH Chip Bus interface controller ASIC fabricated and tested at IBM.5MHz test clock Data obtained courtesy of Phil Nigh (IBM) ELEN654 A TM . some parts 50MHz 0.3V.000 equivalent (2-input NAND) gates 304-pin package.4mm x 8. 99. Burlington. 9. 249 I/O Clock: 40MHz. Vermont 116.8mm area µ Full scan. 18.79% fault coverage Advantest 3381 ATE. 3.45µ CMOS.466 chips tested at 2.

ELEN654 Stuck-at fault coverage Stuck-at fault coverage Stuck-at fault coverage Stuck-at fault coverage Test Coverage from Fault Simulator Vector number A TM .

ELEN654 Measured Chip Fallout Measured chip fallout Measured chip fallout Measured chip fallout Measured chip fallout Vector number A TM .

T StuckA ELEN654 TM .7623 Measured chip fallout Y (T ) for Af = 2. fault coverage Y (1) = 0.1 and β = 0.Model Fitting Chip fallout vs.083 Chip fallout and computed 1-Y (T ) Chip fallout and computed 1-Y (T ) Chip fallout and computed 1-Y (T ) Chip fallout and computed 1-Y (T ) Stuck-at fault coverage.

23%) Defect level in ppm Defect level in ppm Defect level in ppm Defect level in ppm StuckStuck-at fault coverage (%) A ELEN654 TM .700 ppm (Y = 76.Computed DL 237.

defect density (d ) and clustering parameter (α) α Yield drops as chip area increases. low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm. fault coverage ~ 99% ELEN654 A TM .Summary VLSI yield depends on two process parameters.

Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults – – – – Transistor faults Summary ELEN654 A TM .

Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments ELEN654 A TM .

A ELEN654 TM .. Dielectric breakdown Electromigration ... Reliability and Degradation Semiconductor Devices and Circuits.Some Real Defects in Chips Missing contact windows Parasitic transistors Oxide breakdown .. Morgan. Contact degradation Seal leaks . Bulk defects (cracks. Wiley. 1981. Howes and D.. J. crystal imperfections) Surface impurities (ion migration) ..: M.. V. Processing defects Material defects Time-dependent failures Packaging failures Ref..

A ELEN654 TM . In-Circuit Testing. 1985.: J. Van Nostrand Reinhold.Observed PCB Defects Occurrence frequency (%) 51 1 6 13 6 8 5 5 5 Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Ref. Bateson.

bridging) Functional faults (processors) Delay faults (transition.4 (p. cross-point. path) Analog faults For more examples. 60-70) of the book. ELEN654 A TM .Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at. see Section 4.

Single Stuck-at Fault Three properties define a single stuck-at fault – Only one line is faulty – The faulty line is permanently set to 0 or 1 – The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value j s-a-0 0(1) c d g 1 1 a e h i 1(0) 0 z 1 b k f Test vector for h s-a-0 fault A ELEN654 TM .

A collapsed fault set contains one fault from each equivalence subset. where all faults in a subset are mutually equivalent. Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets.Fault Equivalence Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. ELEN654 A TM . If faults f1 and f2 are equivalent then the corresponding faulty functions are identical.

Equivalence Rules sa0 sa1 sa0 sa1 sa0 sa1 OR sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 NOR sa0 sa1 sa0 sa1 sa0 sa1 FANOUT sa0 sa1 sa0 sa1 A sa0 sa1 WIRE sa0 sa1 sa0 sa1 AND sa0 sa1 sa1 NOT sa0 sa0 sa1 NAND sa0 sa1 ELEN654 TM .

= 0.Equivalence Example sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 Faults in red removed by equivalence collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----.625 32 A sa0 sa1 sa0 sa1 sa0 sa1 ELEN654 TM .

ELEN654 A TM . it is sufficient to consider only the input faults of Boolean gates.Fault Dominance If all tests of some fault F1 detect another fault F2. Dominance fault collapsing: If fault F2 dominates F1. then F2 is removed from the fault list. In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set. When dominance fault collapsing is used. If two faults dominate each other then they are equivalent. See the next example. then F2 is said to dominate F1.

Dominance Example All tests of F2 001 110 000 101 100 s-a-1 s-a-1 s-a-1 s-a-0 A dominance collapsed fault set A F1 s-a-1 F2 s-a-1 010 011 Only test of F1 ELEN654 TM .

Total fault sites = 16 Checkpoints ( ) = 10 ELEN654 A TM . also detects all single (multiple) stuck-at faults in that circuit.Checkpoints Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit.

detection is probabilistic.Test generator is unable to find a test.Classes of Stuck-at Faults Following classes of single stuck-at faults are identified by fault simulators: – Potentially-detectable fault -. can be detected as a potentially-detectable fault.Fault prevents initialization of the faulty circuit. – Untestable fault -. ELEN654 A TM .Fault induces much internal signal activity without reaching PO.Test produces an unknown (X) state at primary output (PO). usually with 50% probability. – Initialization fault -.No test exists for the fault. – Redundant fault -. – Hyperactive fault -.

ELEN654 A TM . single fault tests cover a very large number of multiple faults.1) values. such masking of one fault by another is rare. A single fault test can fail to detect the target fault if another fault is also present. however.Multiple Stuck-at Faults A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0. The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1. Statistically.

Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).a single transistor is permanently shorted irrespective of its gate voltage.a single transistor is permanently stuck in the open state.Transistor (Switch) Faults MOS transistor is considered an ideal switch and two types of faults are modeled: – Stuck-open -. Detection of a stuck-open fault requires two vectors. ELEN654 A TM . – Stuck-short -.

Stuck-Open Example Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1) pMOS FETs VDD Stuckopen 1 0 A Two-vector s-op test can be constructed by ordering two s-at tests 0 0 B C 0 1(Z) Good circuit states Faulty circuit states A nMOS FETs ELEN654 TM .

Stuck-Short Example
Test vector for A s-a-0 pMOS FETs




IDDQ path in faulty circuit


0 (X)

Good circuit state


Faulty circuit state




Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technology-dependent faults require special tests. Memory and analog circuits need other specialized fault models and tests.




IDDQ Current Testing
Definition Faults detected by IDDQ tests Vector generation for IDDQ tests FullFull-scan Quietest Instrumentation difficulties Sematech study Limitations of IDDQ testing Summary





Early 1990’s – Fabrication Line had 50 to 1000 defects per million (dpm) chips

IBM wants to get 3.4 defects per million (dpm) chips (0 defects, 6 σ)

Conventional way to reduce defects:

Increasing test fault coverage Increasing burn-in coverage Increase Electro-Static Damage awareness

New way to reduce defects:

IDDQ Testing – also useful for Failure Effect Analysis




Basic Principle of IDDQ Testing » Measure IDDQ current through Vss bus A ELEN654 TM .

Faults Detected by IDDQ Tests ELEN654 A TM .

Stuck-at Faults Detected by IDDQ Tests Bridging faults with stuck-at fault behavior Levi – Bridging of a logic node to VDD or VSS – few of these Transistor gate oxide short of 1 KΩ to 5 KΩ Floating MOSFET gate defects – do not fully turn off transistor ELEN654 A TM .

NAND Open Circuit Defect – Floating gate ELEN654 A TM .

| Vtp | then detectable by IDDQ test ELEN654 A TM .Floating Gate Defects Small break in logic gate inputs (100 – 200 Angstroms) lets wires couple by electron tunneling Delay fault and IDDQ fault Large open results in stuck-at fault – not detectable by IDDQ test If Vtn < Vfn < VDD .

Multiple IDDQ Fault Example ELEN654 A TM .

Capacitive Coupling of Floating Gates Cpb – capacitance from poly to bulk Cmp – overlapped metal wire to poly Floating gate voltage depends on capacitances and node voltages If nFET and pFET get enough gate voltage to turn them on. then IDDQ test detects this defect K is the transistor gain ELEN654 A TM .

IDDQ Current Transfer Characteristic Segura et al. – 5 defective inverter chains (1-5) with floating gate defects ELEN654 A TM .

evaluated testing of bridges with 3 CMOS inverter chain IDDQRb tests fault when Rb > 50 KΩ or 0 Rb 100 KΩ Largest deviation when Vin = 5 V bridged nodes at opposite logic values ≤ ≤ ELEN654 A TM .Bridging Faults S1 – S5 Caused by absolute short (< 50 Ω) or higher R Segura et al.

Rb K |IDDQ| (µA) (kΩ Rb (kΩ) A ELEN654 TM .S1 IDDQ Depends on K.

CMOS Transistor Stuck-Open Faults IDDQ test can sometimes detect fault Works in practice due to body effect ELEN654 A TM .

Delay Faults Most random CMOS defects cause a timing delay fault. not catastrophic failure Many delay faults detected by IDDQ test – late switching of logic gates keeps IDDQ elevated Delay faults not detected by IDDQ test Resistive via fault in interconnect Increased transistor threshold voltage fault ELEN654 A TM .

S = source. B = bulk Assume that short does not change logic values ELEN654 A TM . fSD. D = drain. fBD.Leakage Faults Gate oxide shorts cause leaks between gate & source or gate & drain Mao and Gulati leakage fault model: Leakage path flags: fGS. fBG G = gate. fBS. fGD.

Weak Faults nFET passes logic 1 as 5 V – Vtn pFET passes logic 0 as 0 V + |Vtp| Weak fault – one device in C-switch does not turn on Causes logic value degradation in C-switch ELEN654 A TM .

Paths in Circuit ELEN654 A TM .

Transistor Stuck-Closed Faults Due to gate oxide short (GOS) k = distance of short from drain Rs = short resistance IDDQ2 current results show 3 or 4 orders of magnitude elevation ELEN654 A TM .

Gate Oxide Short ELEN654 A TM .

Logic / IDDQ Testing Zones ELEN654 A TM .

but may not handle inter-gate bridges Pseudo-stuck-at fault coverage Voltage stuck-at fault coverage that represents internal transistor short fault coverage and hard stuck-at fault coverage ELEN654 A TM .Fault Coverage Metrics Conductance fault model (Malaiya & Su) Monitor IDDQ to detect all leakage faults Proved that stuck fault test set can be used to generate minimum leakage fault test set Short fault coverage Handles intra-gate bridges.

Fault Coverages for IDDQ Fault Models ELEN654 A TM .

Vector Selection with Full Scan -.Perry Use voltage testing & full scan for IDDQ tests Measure IDDQ current when voltage vector set hits internal scan boundary Set all nodes. inputs & outputs in known state Stop clock & apply minimum IDDQ current vector Wait 30 ms for settling. measure IDDQ against 75 µA Limit. with 1 µA accuracy ELEN654 A TM .

Quietest Leakage Fault Detection – Mao and Gulati Sensitize leakage fault Detection – 2 transistor terminals with leakage must have opposite logic values. high-impedance states won’t work – current cannot go through them ELEN654 A TM . & be at driving strengths Non-driving.

Weak Fault Detection – P1 (N1) Open Elevates IDDQ from 0 µA to 56 µA ELEN654 A TM .

Second Weak Fault Detection Example Not detected unless I3 = 1 ELEN654 A TM .

Hierarchical Vector Selection Generate complete stuck-fault tests Characterize each logic component – relate input/output logic values & internal states: To leakage fault detection To weak fault sensitization/propagation Uses switch-level simulation Store information in leakage & weak fault tables Logic simulate stuck-fault tests – use tables to find faults detected by each vector No more switch-level simulation ELEN654 A TM .

Leakage Fault Table k = # component I/O pins n = # component transistors m = 2k (# of input / output combinations) m x n matrix M represents the table Each logic state – 1 matrix row Entry mi j = octal leakage fault information Flags fBG fBD fBS fSD fGD fGS Sub-entry mi j = 1 if leakage fault detected ELEN654 A TM .

Example Leakage Fault Table ELEN654 A TM .

Weak Fault Table Weak faults: Sensitized by input/output states of faulty component Propagated by either faulty component input/output states or input/output states of components driven by node with weak fault Use weak fault detection. sensitization. and propagation tables ELEN654 A TM .

select it for IDDQ measurement Example circuit: ELEN654 A TM .Quietest Results If vector tests 1 new leakage/weak fault.

Results – Logic & IDDQ Tests Time 99 199 299 399 499 599 699 Time 799 899 999 1099 1129 1299 1399 I1 I2 X1 O1 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 I1 I2 0 0 0 1 1 1 1 0 0 0 1 0 1 1 X1 O1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 IDDQ measurement vectors in bold & italics Time in units A ELEN654 TM .

3 % 0.99 % 90. 1 2 ELEN654 TM .5 % 94. 1 2 # of Weak Faults 1923 1497 # of % Leakage # of Tran.21 % 87.35 % 85.50 % % Weak Selected Fault Vectors Coverage 0.64 % A Ckt.84 % 42373 220571 0.Quietest Results Ckt.Leakage Selected Fault Sistors Faults Vectors Coverage 7584 39295 0.

Instrumentation Problems Need to measure < 1 µA current at clock > 10 kHz Off-chip IDDQ measurements degraded Pulse width of CMOS IC transient current Impedance loading of tester probe Current leakages in tester High noise of tester load board Much slower rate of current measurement than voltage measurement ELEN654 A TM .

Sematech Study IBM Graphics controller chip – CMOS ASIC. 0. IDDQ Tests ELEN654 A TM . 3 metal layers. 2 clocks Full boundary scan on chip Tests: Scan flush – 25 ns latch-to-latch delay test 99. 40 to 50 MHz Clock. 166.8 µm static CMOS.45 µm Lines (Leff).7 % scan-based stuck-at faults (slow 400 ns rate) 52 % SAF coverage functional tests (manually created) 90 % transition delay fault coverage tests 96 % pseudo-stuck-at fault cov.000 standard cells 0.

Scan-based Stuck-at Scan-based Stuck-at Scan-based Stuck-at Scan-based Stuck-at Functional Scan-based delay Scan-based delay Scan-based delay Scan-based delay µA limit) fail fail 1463 7 pass 34 1 pass 13 8 fail 1251 fail pass fail A pass fail pass fail IDDQ (5 pass pass 6 14 0 6 1 52 36 pass fail ELEN654 TM .Sematech Results Test process: Wafer Test Package Test Burn-In & Retest Characterize & Failure Analysis Data for devices failing some. tests. but not all.

Sematech Conclusions Hard to find point differentiating good and bad devices for IDDQ & delay tests High # passed functional test. failed IDDQ > 5 µA Large # passed stuck-at and functional tests Failed delay & IDDQ tests Large # failed stuck-at & delay tests Passed IDDQ & functional tests Delay test caught delays in chips at higher Temperature burn-in – chips passed at lower T. failed all others High # passed all tests. ELEN654 A TM .

Limitations of IDDQ Testing Sub-micron technologies have increased leakage currents Transistor sub-threshold conduction Harder to find IDDQ threshold separating good & bad chips IDDQ tests work: When average defect-induced current greater than average good IC current Small variation in IDDQ over test sequence & between chips Now less likely to obtain two conditions ELEN654 A TM .

Built in current detection ELEN654 A TM .. IDDQ.Summary IDDQ tests improve reliability. bridging. and delay fault testing combined Still uncertain whether IDDQ tests will remain useful as chip feature sizes shrink further Delta IDDQ testing not discussed. find defects causing: Delay. weak faults Chips damaged by electro-static discharge No natural breakpoint for current threshold Get continuous distribution – bimodal would be better Conclusion: now need stuck-fault.

Design for Testability (DFT): Full-Scan Definition Ad-hoc methods Scan design » » » » » » Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system Summary ELEN654 A TM .

DFT methods for digital circuits: » Ad-hoc methods » Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan – – – – DFT method for mixed-signal circuits: – Analog test bus ELEN654 A TM .Definition Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective.

Avoid redundant gates. – Test generation is often manual with no guarantee of high fault coverage.) Design reviews conducted by experts or design auditing tools. etc. Make flip-flops initializable. Provide test control for difficult-to-control signals. Consider ATE requirements (tristates. – Design iterations may be necessary. Avoid large fanin gates. ELEN654 A TM . Avoid gated clocks. Disadvantages of ad-hoc DFT methods: – Experts and tools not always available.Ad-Hoc DFT Methods Good design practices learnt through experience are used as guidelines: – – – – – – Avoid asynchronous (unclocked) feedback.

ELEN654 A TM . » Use combinational ATPG to obtain tests for all testable faults in the combinational logic.Scan Design » Circuit is designed using pre-specified design rules. – Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. » Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. – Make input/output of each scan shift register controllable/observable from PI/PO. » Test structure (hardware) is added to the verified design: – Add a test control (TC) primary input.

more pins. can be used.Scan Design Rules Use only clocked D-type of flip-flops for all state variables. Clocks must not feed data inputs of flip-flops. if available. At least one PI pin must be available for test. ELEN654 A TM . All clocks must be controlled from PIs.

Comb. logic D2 CK Comb. logic D1 Q FF Comb. logic D1 D2 CK FF Q Comb.Correcting a Rule Violation All clocks must be controlled from PIs. logic ELEN654 A TM .

SD selected t ELEN654 A TM . D selected Scan mode.Scan Flip-Flop (SFF) Master latch Slave latch Q D TC Logic overhead MUX SD Q CK D flip-flop CK Master open Slave open t TC Normal mode.

Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF) Master latch Q Slave latch D MCK D flip-flop MCK Logic overhead Q SCK SD TCK MCK TCK SCK t A Scan mode TCK Normal mode ELEN654 TM .

A ELEN654 TM .Adding Scan Structure PI Combinational logic SFF SFF SFF PO SCANOUT TC or TCK SCANIN Not shown: CK or MCK/SCK feed all SFFs.

Comb. Test Vectors PI I1 Combinational I2 O1 O2 PO SCANIN TC logic S1 S2 SCANOUT Present state N1 N2 Next state ELEN654 A TM .

Comb. Test Vectors PI I1 I2 Don’t care or random bits SCANIN S1 S2 TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0000000 PO O1 O2 SCANOUT N1 N2 Sequence length = (ncomb + 1) nsff + ncomb clock periods ncomb = number of combinational vectors nsff = number of scan flip-flops A ELEN654 TM .

01. . 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output.000 scan flip-flops. 500 comb. ELEN654 A TM . Total scan test length: (ncomb + 2) nsff + ncomb + 4 clock periods. of length nsff+4 in scan mode (TC=0) produces 00. total scan test length ~ 106 clocks. . Multiple scan registers reduce test length. A shift sequence 00110011 .Testing Scan Register Scan register must be tested prior to application of scan test sequences. Example: 2. vectors.

Just one test control (TC) pin is essential. Test sequence length is determined by the longest scan shift register. PI/SCANIN Combinational logic SFF SFF SFF M U X PO/ SCANOUT TC CK A ELEN654 TM . each having a separate scanin and scanout pin.Multiple Scan Registers Scan flip-flops can be distributed among any number of shift registers.

Example – ng = 100k gates. 5-6%. where ng = comb. overhead = 6.7%. nff = flip-flops. gates. Area overhead: » Gate overhead = [4 nsff/(ng+10nff)] x 100%. Performance overhead: » Multiplexer delay added in combinational path. » Flip-flop output loading due to one additional fanout. two gate-delays. approx.Scan Overheads IO pins: One pin necessary. nff = 2k flip-flops. ELEN654 A TM . » More accurate estimate must consider scan wiring and layout area. approx.

Hierarchical Scan Scan flip-flops are chained within subnetworks before chaining subnetworks. Advantages: – Automatic scan insertion in netlist – Circuit hierarchy preserved – helps in debugging and design changes Disadvantage: Non-optimum chip layout. Scanin SFF4 SFF1 Scanout Scanin SFF1 SFF3 Scanout SFF2 SFF3 SFF4 SFF2 Flat layout A Hierarchical netlist ELEN654 TM .

Optimum Scan Layout X SFF cell SCANIN X’ IO pad Flipflop cell Y Y’ TC SCAN OUT Routing channels Active areas: XY and X’Y’ A Interconnects ELEN654 TM .

) x 100% T y = track dimension. cell width S = total non-scan FF cell width s = fractional FF cell area = S/(C+S) α = SFF cell width fractional increase r = number of cell rows or routing channels β = routing fraction in active area T = cell height in track dimension y ELEN654 A TM .Scan Area Overhead Linear dimensions of active area: X = (C + S) / r X’ = (C + S + αS) / r Y’ = Y + ry = Y + Y(1--β) / T β Area overhead X’Y’--XY = -------------.x 100% XY 1--β β = [(1+αs)(1+ -------) – 1] x 100% α T 1--β β = (αs + ------. wire width+separation C = total comb.

α = 0. β = 0.24% Actual measured data: Scan implementation Area overhead Normalized clock rate ______________________________________________________________________ None 0.90% 1.0 16.000-gate CMOS chip Fractional area under flip-flop cells.93% 11.Example: Scan Layout 2. s = 0.00 0.91 Hierarchical Optimum layout ELEN654 A TM .471 Cell height in routing tracks.478 Scan flip-flop (SFF) cell width increase.87 0. T = 10 Calculated overhead = 17.25 Routing area fraction.

66% 4.1% 100. 200MHz processor Number of ATPG vectors Scan sequence length ELEN654 A TM .662 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II.603 214/228 99.781 0 179 15.781 179 0 0.0% 5s 585 105.0% 70.0% 4.ATPG Example: S5378 Original 2.9% 5.533 s 414 414 Full-scan 2.603 35/49 70.

timing verification Rule violations Combinational ATPG Combinational vectors Scan sequence and test program generation Test program Design and test data for manufacturing Mask data ELEN654 A TM . RTL.Automated Scan Design Behavior. and logic Design and verification Scan design rule audits Gate-level netlist Scan hardware insertion Scan netlist Scan chain order Chip layout: Scanchain optimization.

Large delays in scan path require slower scan clock. Random signal activity in combinational circuit during scan can cause excessive power dissipation. Dynamic multiplexers: Skew between TC and TC signals can cause momentary shorting of D and SD inputs. ELEN654 A TM .Timing and Power Small delays in scan path and clock skew can cause race condition.

. May be in 618 ELEN654 A TM .Summary Scan is the most popular DFT technique: – Rule-based design – Automated DFT hardware insertion – Combinational ATPG Advantages: – Design automation – High fault coverage. helpful in diagnosis – Hierarchical – scan-testable modules are easily combined into large scantestable systems – Moderate area (~10%) and speed (~5%) overheads Disadvantages: – Large test data volume and long test time – Basically a slow speed (DC) test Partial Scan. Random Scan. Self-Test and Coding uh.

Testability Measures Origins Controllability and observability SCOAP measures » Sources of correlation error » Combinational circuit example » Sequential circuit example Test vector length prediction High-Level testability measures Summary ELEN654 A TM .

Purpose Need approximate measure of: » » Difficulty of setting internal circuit lines to 0 or 1 by setting primary circuit inputs Difficulty of observing internal circuit lines by observing primary outputs Uses: » » » » Analysis of difficulty of testing internal circuit parts – redesign or add special test hardware Guidance for algorithms computing test patterns – avoid using hard-to-control lines Estimation of fault coverage Estimation of test vector length ELEN654 A TM .

COP » 1st probabilistic measures Seth.First definition of controllability Goldstein 1979 -.SCOAP » First definition of observability » First elegant formulation » First efficient algorithm to compute controllability and observability Parker & McCluskey 1975 » Definition of Probabilistic Controllability Brglez 1984 -.Origins Origins Control theory Rutman 1972 -. Pan & Agrawal 1985 – PREDICT » 1st exact probabilistic measures ELEN654 A TM .

is pointless – might as well use automatic test-pattern generation and testcalculate: Exact fault coverage Exact test vectors ELEN654 A TM . but no test vectors and no search algorithm Static analysis Linear computational complexity Otherwise.Testability Analysis Involves Circuit Topological analysis.

Types of Measures SCOAP – Sandia Controllability and Observability Analysis Program Combinational measures: CC0 – Difficulty of setting circuit line to logic 0 CC1 – Difficulty of setting circuit line to logic 1 CO – Difficulty of observing a circuit line Sequential measures – analogous: SC0 SC1 SO A ELEN654 TM .

Range of SCOAP Measures Controllabilities – 1 (easiest) to infinity (hardest) Observabilities – 0 (easiest) to infinity (hardest) Combinational measures: » Roughly proportional to # circuit lines that must be set to control or observe given line Sequential measures: » Roughly proportional to # times a flip-flop must be clocked to control or observe given line ELEN654 A TM .

Goldstein’s SCOAP Measures Goldstein’s SCOAP Measures AND gate O/P 0 controllability: output_controllability = min (input_controllabilities) +1 AND gate O/P 1 controllability: output_controllability = Σ (input_controllabilities) +1 XOR gate O/P controllability output_controllability = min (controllabilities of each input set) + 1 Fanout Stem observability: Σ or min (some or all fanout branch observabilities) ELEN654 A TM .

Controllability Examples Controllability Examples ELEN654 A TM .

More Controllability More Controllability Examples Examples ELEN654 A TM .

Observability Examples Observability Examples To observe a gate input: nonObserve output and make other input values non-controlling ELEN654 A TM .

More Observability Examples More Observability Examples To observe a fanout stem: Observe it through branch with best observability ELEN654 A TM .

CO (z) correlate x y z ELEN654 A TM . z are independent events » CC0 (x). CC1 (z) correlate » CO (x). CC0 (y). CO (y).Error Due to Stems & Reconverging Error Due to Stems & Reconverging Fanouts Fanouts SCOAP measures wrongly assume that controlling or observing x. y. CC1 (y). CC0 (z) correlate » CC1 (x).

) 8 (6) (6) 2.6) z 1. ) 8 A ELEN654 TM .6) y 2.Correlation Error Example Exact computation of measures is NP-Complete and impractical Italicized (green) measures show correct values – SCOAP measures are in red or bold CC0.3(4.1(5.1(6) 1. ) 6.1(5) 1.2(0) 4.3(4) x 2.2(0) 1.1(5.3(4.1(6) 1.1(4.CC1 (CO) 1.3(4) 2. ) 8 8 (5) (4.

Sequential Example ELEN654 A TM .

label the gate with the maximum of them + 1. & Queue logic gate driven by that fanout While queue is not empty: Dequeue next logic gate If all gate inputs have level #’s.Levelization Algorithm 6. requeue the gate A ELEN654 TM .1 Label each gate with max # of logic levels from primary inputs or with max # of logic levels from primary output Assign level # 0 to all primary inputs (PIs) fanout: For each PI fanout: Label that line with the PI level number. Else.

CC1) ELEN654 A TM .Controllability Through Level 0 Circled numbers give level number. (CC0.

Controllability Through Level 2 ELEN654 A TM .

Final Combinational Controllability ELEN654 A TM .

CC1) CO ELEN654 A TM . (CC0.Combinational Observability for Level 1 Number in square box is level from primary outputs (POs).

Combinational Observabilities for Level 2 ELEN654 A TM .

Final Combinational Observabilities ELEN654 A TM .

either forwards or SET.Sequential Measure Differences Combinational Increment CC0. C. Q. SET. to Q. or RESET Both Must iterate on feedback loops until controllabilities stabilize A ELEN654 TM . SC1. D. backwards. CO whenever you pass through a gate. SO only when you pass flipthrough a flip-flop. either forwards or backwards Sequential Increment SC0. CC1.

CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0 RESET) (RESET) SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0 RESET) (RESET) + 1 [CC1 RESET) CC0 (Q) = min [CC1 (RESET) + CC1 (C) + CC0 (C). CC0 (D) + CC1 (C) + CC0 (C)] SC0 (Q) is analogous CO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0 RESET) (RESET) SO (D) is analogous ELEN654 A TM .D Flip-Flop Equations Assume a synchronous RESET line.

RESET) CO (Q) + CC1 (Q) + CC1 (RESET) + C). CC1 (C) + CC0 (C).D Flip-Flop Clock and Reset RESET) RESET) CO (RESET) = CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C) RESET) SO (RESET) is analogous Three ways to observe the clock line: 1. Set Q to 1 and clock in a 0 from D flip2. CO (Q) + CC0 (Q) + CC0 (RESET) + RESET) CC1 (D) + CC1 (C) + CC0 (C)] SO (C) is analogous ATM ELEN654 . Reset the flip-flop and clock in a 1 from D CO (C) = min [ CO (Q) + CC1 (Q) + CC0 (D) + CC1 (C) + CC0 (C). Set the flip-flop and then reset it flip3.

convergence guaranteed For all POs.Iterate on loops until SC stabilizes -. CC0 = CC1 = SC0 = SC1 = 3. set CO = SO = CO. 7.Algorithm 6. SO) = min branch (CO. and controllabilities to get observabilities (CO CO. CC0 = CC1 = 1 and SC0 = SC1 = 0 2. that node is uncontrollable (unobservable) 8 8 8 8 8 8 8 8 TM ELEN654 . 5. 6. Go from PIs to POS. Fanout stem (CO. to get controllabilities -. Use CO. SO. SO. For all other nodes. SO) SO) If a CC or SC (CO or SO) is .2 Testability Computation 8 8 8 8 A 1. using CC and SC equations 4. Work from POs to PIs. For all PIs.

Sequential Example Initialization ELEN654 A TM .

After 1 Iteration ELEN654 A TM .

After 2 Iterations ELEN654 A TM .

After 3 Iterations ELEN654 A TM .

Stable Sequential Measures ELEN654 A TM .

Final Sequential Observabilities ELEN654 A TM .

Test Vector Length Prediction First compute testabilities for stuck-at faults » T (x sa0) = CC1 (x) + CO (x) » T (x sa1) = CC0 (x) + CO (x) » Testability index = log Σ T (f i) fi ELEN654 A TM .

Testability Index ELEN654 A TM .Number Test Vectors vs.

High Level Testability Build data path control graph (DPCG) for circuit Compute sequential depth -. registers. and POs Improve Register Transfer Level Testability with redesign ELEN654 A TM .# arcs along path between PIs.

Improved RTL Design ELEN654 A TM .

Summary Summary Testability approximately measures: » » Difficulty of setting circuit lines to 0 or 1 Difficulty of observing internal circuit lines Uses: » » » » Analysis of difficulty of testing internal circuit parts – Redesign circuit hardware or add special test hardware where measures show bad controllability or observability Guidance for algorithms computing test patterns – avoid using hard-tocontrol lines Estimation of fault coverage – 3-5 % error Estimation of test vector length ELEN654 A TM .

Next Lecture on Fault Tolerance Next Lecture on Fault Tolerance ELEN654 A TM .