VLSI Design II

CMOS Processing

Overview Processing steps processing step sequence Goal: You know the basics of integrated circuit processing steps and you are familiar with the processing sequence of a sample CMOS technology.
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Complementary MOS (CMOS) technology is becoming the dominant candidate for VLSI applications npCMOS provides both n-channel and p-channel MOS transistors on one chip on extremely expensive fabs cheap chips are produced each chip passes hundreds of different processing steps random process disturbances cause electrical parameter variations of the chips elements are never identical

Process technology pictures and text are copied from: Maly, Atlas of IC Technologies, W. Maly, The Benjamin Cummings 0-8053-6850Publishing Company, ISBN 0-8053-6850-7
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VLSI Circuit Fabrication
oxidize silicon to form thin and thick layers of SiO2 to serve as insulators. deposit thin layers of material and etch into desired pattern


n+ p

diffuse dopants into substrate to create P/N junctions

implant ions to set thresholds and achieve precise dopant profiles

Most fabrication steps require first creating a mask that determines layers where the operation will occur. Masks can either be existing layers on “selfthe IC (these masks are “self-aligned”) or created using a lithographic photoresist. process and photoresist. Design rules ensure that design is still functional in the face of sidemisalignments and various side-effects of the fabrication process.

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Overview of Processing Step Sequence n-well active poly Overview of Processing Steps making the wafers photolithography oxidation layer deposition etching diffusion implantation n-diffusion p-diffusion contacts metal1 via1 metal2 passivation
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Processing Steps: Making the wafers
the basic raw material used is a wafer or disk of silicon which varies from 3” to 12” in diameter wafers are cut in thin slices (less than 1mm) of semiconductor cylindrical ingots first step in IC processing is the production of a singlesingle-crystal ingot starting from a silicon melt with a controlled amount of impurities

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Processing Steps: Photolithography #1
Complementary Photolithography is a technique used in IC fabrication to transfer a desired pattern onto the surface of a silicon wafer. As such the photolithography is a key step in the entire circuit integration process.

alternative method for lower quantities: direct write (Eprocedure (E-beam)

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Processing Step: Photolithography #2

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Processing Steps: Oxidation #1
(Si Si) Thermal oxidation is a process in which silicon (Si) reacts with oxygen to form a continuous layer of high-quality silicon dioxide (SiO2) highoxidation of the silicon surface oxidation through a window in the oxide selective oxide growth oxidation of the silicon surface

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Processing Steps: Oxidation #2

oxidation through a window

selective oxide growth

birds bike
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Processing Steps: Layer Deposition - General
Thin layers of both conduction substances and insulation materials constitute an important part of any semiconductor device. epitaxy (single crystal deposition) PVD and CVD process (polycrystalline deposition)

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Processing Steps: Vapour Deposition


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Processing Steps: Etching
The process that immediately follows the photolithography step is the removal of material photoresist. from areas of the wafer unprotected by photoresist. Characterization by selectivity and anisotropy. wet etching

dry etching
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Solid state diffusion is a process which allows atoms to move within a solid at elevated temperatures.

Processing Steps: Diffusion

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Processing Steps: Implantation
The alternative to the diffusion technique of dopant introduction used in IC manufacturing is ion implantation.

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DriveN-Well Implant & Drive-in
nIn p substrate only n-channel fets can be processed. nTherefore an n-well has to be implanted in order to hold pfets. the p-channel fets.

Window in the mask and cross section illustrated.
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ChannelChannel-stop Implant
A “thick” (0.4um) layer of silicon dioxide, called field oxide, is formed on the surface by oxidation in wet oxygen. This is then etched to expose surface where we fets. want to make fets.

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Grow Field Oxide
npFormation of active regions for n-channel and p-channel fets of the CMOS process. The obtained bird’s beak causes the active area of the device to be significantly smaller.

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Grow Thin Oxide
Now grow a “thin” (0.01um = 100 Angstroms) layer of silicon dioxide, called gate oxide, on the surface by exposing the wafer to dry oxygen.

The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the gate oxide, the more oomph the fet will have (we’ll see why soon) but the harder it is to make it defect free.
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Deposit & Etch Polysilicon
On top of the thin oxide a 0.7um thick layer of polycrystalline silicon, called polysilicon or poly for short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and drain junctions will be formed:

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Implant Nfet Drain & Source
The entire surface is doped, either by diffusion or ion implantation, with phosphorus (an electron donor) which ncreates two n-type regions in the substrate and an ohmic ncontact in the n-well. The phosphorus also penetrates the poly reducing its resistance and affecting the nfet’s threshold.

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Effective Nfet Dimensions

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Parasitic Fets

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Implant Pfet Drain & Source
Once again the entire surface is doped, either by diffusion or ion implantation, with boron (an electron acceptor) pnwhich creates two p-type regions in the n-well and an ohmic contact in the substrate.

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Deposit SiO2 insulator
Finally an intermediate oxide layer is grown for isolation and then reflowed to flatten its surface.

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Etch contact cuts
Holes are etched in the oxide where contacts to poly/diff are wanted.

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Deposit & Etch Metal1
For interconnections aluminium is deposited, patterned and etched.

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Voila: a CMOS Inverter!
Finally a passivation layer protects the wafer surface from contamination and scratches. Pads are opened for bonding.

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Deposit & Etch Metal2

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DoubleN-well, Double-level Metal CMOS Process Steps
1. Grow barrier oxide Mask/Etch n2. Mask/Etch n-well window 3. P n-well implant driven4. Thermal drive-in to deepen n-well 5. Remove barrier oxide 6. Grow “pad” oxide 7. Deposit Si3N4 Mask/Etch 8. Mask/Etch leaving active region channel9. B channel-stop implant drive10. Grow field oxide (more drive-in!) 11. Remove Si3N4 12. Remove pad oxide 13. B or P implant to adjust VTH 14. Grow thin (gate) oxide 15. Deposit P-doped polysilicon Mask/Etch 16. Mask/Etch leaving poly wires 17. Etch exposed thin oxide p18. Mask off p-diffusion regions 19. Sb or As nfet source/drain nimplant, n-well contact too p20. Mask all but p-diffusion regions 21. B pfet source/drain implant 22. Thermal source/drain annealing 23. Deposit SiO2 using CVD Mask/Etch 24. Mask/Etch contacts through SiO2 25. Deposit first Al using PVD Mask/Etch 26. Mask/Etch leaving metal1 wires 27. Grow thick layer of SiO2 28. Spin on thick, flat layer of photoresist 29. Etch SiO2 and photoresist at same rate until only flat SiO2 remains Mask/Etch 30. Mask/Etch vias through SiO2 31. Deposit second using PVD Mask/Etch 32. Mask/Etch leaving metal2 wires 33. Deposit overglass to passivate circuit Mask/Etch 34. Mask/Etch pad windows

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Coming Up...
Next time: Mask layout: design rules, layout examples, structured and symbolic layout techniques, retargetable layouts. CAD tools for layout: design capture, design rule checking, extraction, network comparison. Readings for next time… Weste:
Chapter 3 thru 3.2.3

2 through 2.1 (CMOS processing)

transparency notes (process technology)

I3SStudy CBT course on the web or on I3S-CD: (Uni How a silicon integrated circuit is made (Uni Manchester)
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VLSIExercises: VLSI-14
Weste pp168: 3.8 ex 5 (difficulty: easy): Explain why substrate and well contacts are important in CMOS.

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