# Design of Reusable CMOS OTAs using CAD Tools

**José Luis Chávez-Hurtado 1, Esteban Martínez-Guerrero 2 and José Ernesto Rayas-Sánchez 3
**

Department of Electronics, Systems and Informatics, ITESO (Instituto Tecnológico y de Estudios Superiores de Occidente), Tlaquepaque, Jalisco, 45604 Mexico

1 2

josechavez@iteso.mx

3

emguerrero@iteso.mx erayas@iteso.mx

In recent years it has been reported some works on automation analog design approaches [1-8], each of them having different advantages and limitations. In this work, we propose a methodology for analog circuit design reuse based on the retargeting analog blocks for each new set of specifications, to assemble complex analog circuits that can be used for different applications. To this purpose, we have developed an interactive optimization algorithm to find the best analog building block in different fabrication technologies accordingly to the design specifications. The long-term main objective of this approach is to facilitate the design of complex analog functions. In this work the efficacy Keywords— Design automation, CAD, circuit optimization, of our algorithm is illustrated by designing one of the most widely used analog building blocks: Operational FDFC OTA with CMFB, analog cells. Transconductance Amplifier (OTA) circuits. I. INTRODUCTION In Section II the proposed structure of reusable analog cells The complexity of integrated electronic circuits being design is explained. Section III is focused on finding OTAs’ designed for nowadays applications is continuously increasing. performance limits for classical OTA topologies by SPICE The advances in process technology makes possible to design simulations, in Section IV a practical design example of a mixed-signal integrated systems on a chip (SoC). Most parts Fully Differential Folded Cascode (FDFC) OTA with of these SoC’s are completely digital rather than analog. This Common-Mode Feedback (CMFB) is presented, and finally is encouraged by that fact that logic synthesis, layout and some concluding remarks for this work are given. verification of digital circuits are highly suited for design II. APPROACH FOR DESIGNING REUSABLE ANALOG CELLS automation methodologies, which make easier for the designer Figure 1 shows our approach for designing reusable analog to implement the required functions and reduce the overall time-to-market. However, SoC designs need to include at least cells as applied to OTA cells. A mathematical optimizer some analog interfacing functions, whose design automation integrated to a circuit simulator is used as the core of this lags behind its digital counterpart and becomes in many cases design tool. The mathematical optimizer receives the design a limiting factor in accelerating SoC time-to-market [1, 2]. specifications and makes the calls to OTA library, technology Analog design automation is more difficult than digital design library, performance library and design constraints blocks for because analog cells are more influenced by noise and by the circuit sizing, by means of an iterative process, until the parasitic effects from layout [3]. On the other hand, as SoC’s circuit achieves the required design specifications and delivers becomes larger, a practical way to efficiently design such the best OTA topology in a specific fabrication technology. dense SoC’s is by embedding cores, also called intellectual property (IP) blocks, on these chips. Ideally, these cores Technology Performance Design OTA Library Library Library Constraints should be reusable, pre-characterized and pre-verified. This means that the same core can be used on different chip designs and in different technologies after migration. While the reusability concept is currently having some success on the digital side of mixed-signal systems, it is still extremely Mathematical Optimization and Circuit Simulation difficult to reuse an analog IP block in its current forms. To this end, analog cells would be migrated to these new Design Final Circuit technologies with minimal user intervention. While analog Specifications design automation methodologies are not yet widely accepted by analog designers, design reuse seems a viable way to efficiently design analog functions.

Abstract— In this paper an automation tool is proposed for OTA designs. The core of the tool is a combination of a mathematical tool and a circuit simulator. The automation tool contains four libraries: OTA topologies, technology parameters, performance limits and design constraints. Design of typical OTA topologies can be implemented in three fabrication technologies. The user introduces OTA specifications and the automation tool looks for the best OTA structure considering the cheapest fabrication technology available in the library, and delivers a sized circuit that fulfills design specifications. Our automation tool is illustrated by a complete design flow of an FDFC with CMFB OTA in AMIS 0.5 m CMOS technology.

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Authorized licensed use limited to: Old Dominion University. The next OTA topology is chosen if the previous criterion does not satisfy the desired design specifications. 0.18m in a . The technology library contains the process parameters that model the CMOS transistors for the following three technologies: 0. The design flow of this automation algorithm (Figure 2) begins by comparing the users design specification with the performance library to select the appropriated OTA topology and technology process. Single Ended Fully Cascode (SEFC) and Fully Differential Folded Cascode (FDFC) which are widely discussed in [9]. These process parameters can be acquired from IC foundries (e. This is carried out by generating a SPICE compatible archive through the optimization tool and launching WinSpice to obtain circuit simulation results for the calculated component values. power supply rejection ratio (PSRR). etc. Once an OTA topology is selected. 1: Proposed Structure for Automatic Analog Cells Design.. 1. etc.35m. BW). Miller. The first selection criterion is the cheapest technology process (e. Finally the design constraints limit in the automation tool the maximum and minimum variation of the component values for each MOS technology To make the interactive algorithm the first step is the integration of the optimization tools with WinSPICE simulator. etc.g. Notice the runtime of the optimization algorithm does not depend of the number of topologies in the library because the automation tool selects the OTA topology from a database that has the most proximity performance to the user desired design specifications. With this library we can improve the OTA topology selection method by immediately discarding those topologies whose limits do not achieve the required design performance.
WinSpice. bandwidth (BW). A. according to [7] and [8]. It is well known that for OTA designs there is always a tradeoff between its performance variables (e. At the end. and the objective function (OF) corresponds to a minimax formulation expressed in terms of the desired specifications. Berkeley (http://www. then the second criterion selection is to choose the simplest one. model library.winspice.The circuit simulator (WinSpice 1 ) can be settled to get responses of the optimized circuit by performing AC sweeps. it means that all the specifications are satisfied at that point. If the value of the objective function is less than zero at a solution x*. Dep. voltage sources. such as voltage gain (Av). In our current implementation. so even if the OTA Av limit and the OTA BW limit exceed the initial specification we can not be sure that this topology could achieve both specifications in the final design. PMmax. the optimization process begins according the required specifications. A second step is to determinate the OTAs performance limits for each technology process by optimizing every response of interest for the OTA.5m)..g.. and if more than one OTA topology is suitable for the design specifications. Restrictions apply.
Fig 2 Functionality flow diagram for reusable OTA design process based on circuit optimization.05. such us W and L of CMOS transistors. Av(x) (OTA Gain). as follows: e1(x) = 1 – Av(x)/Avmin e2(x) = 1 – BW(x)/BWmin e3(x) = 1 – PM(x)/PMmin e4(x) = 1 – PMmax/PM(x) e5(x) = 1 – VDC(x)/VDCout where PM(x) (Phase Margin).sp file. 0. MOSIS). BW(x) (Bandwidth) and VDC(x) (DC output voltage) contain the corresponding circuit simulated responses. BWmin PMmin.
. The optimal design is obtained by minimizing the following optimization problem: x * arg min max e1 x . which contains the OTA topology and the optimization variables which are varied by the optimization algorithm. creating a performance library for each technology process. Ver. the component values and the corresponding OTA performance are saved. EECS. An error function ek(x) is defined for the k-th upper and/or lower specification. of California. as well as the pre-assigned parameters.. U.5m. Downloaded on October 28. Our automation tool manipulates the Netlist.
design specifications. In our current implementation (for illustration purposes) we use only the following specifications: Avmin. which contains suitable design parameters according the OTA topology.g. DC sweeps or transient analyses. User can also select the next technology process even if the current OTA topology achieves
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Fig. the OTA Library contains circuit descriptions in netlist format of 5 typical OTA topologies: simple. e 5 x
x
where x* is the optimal solution found. Av vs.LIB compatible file in order to be managed by WinSpice. Every time that our automation tool finishes an OTA design. e 2 x . and 0.. if the automation process did not find a topology that achieves design specifications then the best circuit is delivered.04. balanced. Objective Function The optimization variables are assembled in a vector x. VDCout. Performance limits are stored in OTA_topology... 2009 at 13:48 from IEEE Xplore. common mode rejection ratio (CMRR). such as the load capacitance.

44 85.35µm Avd (dB) BW (MHz) 0.75m 0.46 165.4
Miller 43.50m 0.48 41.4
Balanced 36. 3: Schematics of the FDFC OTA with CMFB (dotted square).06 134.33
Miller 71. Optimization_Algorithm We have explored the three global optimization algorithms available in Matlab toolbox 2 : Genetic Algorithm (GA).5um. Here we apply the implemented algorithm to find the best performance of a typical OTA topology. CMFB FDFC OTA DESIGN A FDFC OTA with CMFB [10] (Fig. As expected. Tables II and III summarize the main characteristics of 5 OTA topologies.98 562.25
SEFC 43. With an automation tool these problems are alleviated and minimum time is spent on designs.89 40. CL = 1pF.66
SEFC 55.44 37.49 13. and error prone.5
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Balanced 36.
. The value of the load capacitance was 1pF. Isource = 28. 2009 at 13:48 from IEEE Xplore. When the optimization algorithm finds the global minimum of the objective function.1m 1.18m
TABLE II OTA OPTIMIZATION FOR MAXIMUM GAIN
Topology: 0. we check for the sign of the objective function.15 245.35µm Avd (dB) BW (MHz) 0.96
TABLE III OTA OPTIMIZATION FOR MAXIMUM BANDWIDTH
Topology: 0.5 -0. III.54 28. Note that it is not necessary to have an initial circuit with a specific performance.34 39. user’s guide”. and also it can be extended to other technologies and other design specification such as: PSRR. then by means of WinSpice simulator we can verify the performance of this circuit.95 96.21 147. the optimizer algorithm gives transistor sizes for this topology (Table IV).41 42.
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Cadence design software: http://www.51 64. 55° PM 65°.49 35. however the PS algorithm needs less time to achieve the same response.06 549. Slew Rate or power consumption optimized.19 58.36 501.43uA and Vcm = 0v.42 158.5 -1.9m
Lmin 0.46 165. Table I shows the OTA design constraints for each technology. This optimized circuit was also simulated using Spectre from
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TABLE I OTA DESIGN CONSTRAINTS
Vdd 0.32 724. but this becomes very time consuming.18m 2. the automation tool can start a new design from a very poor design.82 446.5m process (Table I).01 158.20 40.12 1412.15 204. The Math Works.05 134. The three algorithms yield similar results. CMRR. OTA performance limits were obtained for maximum gain or maximum bandwidth in 0.51 32.24 30.75 58. The initial values of transistor sizes for this OTA topology were the minimum allowed for AMIS 0. and iteratively calls the objective function described before. Downloaded on October 28.68 32.9
Wmax 300m 300m 300m
Wmin 2.0.5m 1. Restrictions apply.6m 0.
CadenceTM3 and minimum variation on its performance was
Matlab.46 96. IV.05 93.90
FDFC 142.01 158.47 88.37 933. If the sign is negative it means that all design specifications were achieved and this circuit is delivered as the final circuit.50m Avd (dB) BW (MHz) 0.17 32. because it is based on global optimization methods.B. Simulated Annealing (SA) and Pattern Search (PS). if it is positive it means that at least one specification was not achieved and other OTA topology is chosen.18µm Avd (dB) BW (MHz)
Simple 31.278 1445.20 5888.35um and 0.82 446.com/
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Authorized licensed use limited to: Old Dominion University.54 501.20 436.5m 1m
Lmax 2.50µm Avd (dB) BW (MHz) 0. so that we incorporated this optimization algorithm.9
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FDFC 95. These results allow us to choose the adequate OTA topology for a determined application. an increased Av and a reduction in BW for complex OTA topologies is obtained (see tables II and III). 3) was designed using our automation tool for Av > 50dB.5 1. “Genetic Algorithm and Direct Search ToolboxTM 2.35m 0.5 0. 2008.18um technologies. The optimization algorithm receives the seed values for the circuit design and the OTA design constraints. 0.79 38. After approximately 1 hour of the iterative process.18µm Avd (dB) BW (MHz)
Simple 50. PERFORMANCE LIMITS FOR TYPICAL OTA TOPOLOGIES In a traditional design procedure we solve equations related to a specific OTA topology for circuit sizing. BW > 800MHz.65 5.19 12.18 6.cadence. This is easy for simple topologies.01v.

1993. design specifications are fulfilled (that is: Av > 50dB.5µm 44. August 2005.6 v/µs SRFALL
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ACKNOWLEDGMENT The authors thank the Mexican Council of Science and Technology (CONACYT) for financial support (Grant 90750). [3] R. 1998.8 v/µs 2010.M15. ISBN-13 978-968-7938-03-5.6µm 142. Hershenson. M10 Mtail M11. J. 1991.100µm / 0. Other performance results (POW. [9] K. McGrawHill 1994.25 dB BW 851. M14.25dB. 4: Layout of FDFC OTA (left) with CMFB (rigth) circuit designed using Virtuoso Layout from Cadence TM. REFERENCES
[1] [2] S. As can be noticed from this figure.4/4. a complete design flow was carried out for an FDFC with CMFB OTA.3198v 1. 2008. Component Vcasp Vcasn Vp Vn R 264. Balkir.
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TABLE V PERFORMANCE OF THE OPTIMIZED FDFC OTA WITH CMFB PRE AND POST LAYOUT SIMULATION Pre Layout Post Layout Av 57. The masks for fabrication of this circuit were designed using Virtuoso Layout from CadenceTM and AMIS 0. and SR) of FDFC OTA can be also checked in Table V. Hernandez-Garduño.
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NCSU free PDK: http://www. [8] L. Peru.TABLE IV OPTIMAL VALUES FOUND FOR THE FDFC OTA WITH CMFB Transistor Optimized W and L M1.54°). PSRR.6µm 155.22 dB PSRRVSS 2244. M16 M17. BW = 724. 5: Bode plot of FDFC OTA with CMFB for Seed Values (Dotted line.1624 w 0.1578 w POW 50. application: Modulateur Delta-Sigma à très faible tension.50 dB PSRRVDD 51. 5 AC response of FDFC OTA with CMFB is presented before and after simulation. Mar.6µm 174. Kluwer Academic Publishers. IEEE Custom Integrated Circuits Conference. applying an interdigitation technique to minimize parasitic effects (Fig. “A system for analog circuit design that stores and reuses design procedures”. N.63 dB 57. Feb.ncsu. pp 1610 .6µm 33. [4] GG Gielen. pp. Av = 57. MA.6 v/µs 1871.1000µm / 0. 2001. Restrictions apply.218µm / 0. University licences of Cadence tools and licensed Matlab tool box were used for this work. 437-440. Av = -30. Rayas-Sánchez and E. IEEE SolidState Circuits Conference. Av = 57. Pérez-Acosta.1 MHz 724. 2009 at 13:48 from IEEE Xplore. pp.6240v -1. 2001.63dB) after Optimization (Dashed line. M12 M13. 2007. Computer Science and Microelectronics Department. Downloaded on October 28. [10] D. 296-303. “Continuos-Time Common-Mode Feedback for High Speed Switched-Capacitor Networks”. To illustrate our tool. M8 M9. Analog VLSI design automation text book. and 55° PM 65°) and also a minor parasitic effect in postlayout simulation is observed due to the layout technique.