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1ask Allocation in a Massively Parallel System Using

Finite Automata








Abstract- In this paper we are proposing a new approach for
tasks allocation in a massively parallel system using Finite
Automata. On the basis of task flow model of finite automata., we
find the turnaround time for a parallel system using finite
automata as a directed acyclic graph in the second section of the
paper we discuss regarding the finite automata and directed
acyclic graph after that we change finite automata into DAG for
massively parallel system. All the simulations are performing in
Intel C++ parallel compiler and compare these results with
several interesting scheduling algorithms and we get better
turnaround time.
Keywords- Finite Automata(FA), Directed Acyclic graph (DAC),
Avoidance Problem.
I. Introduction
In multiprocessor based systems the capability oI diIIerent-
diIIerent processor may be diIIer. The parallel tasks must be
assigning to the processors such that the total completion time
must be as reduce as possible |3, 10|.Optimal task scheduling
on multiprocessor systems is NP-complete |7|. The problem
oI assigning tasks in massively parallel system to some
processing unit has major impact on the resulting
perIormance. Here we are using Finite Automata as DAG Ior
Task Graph .A Iinite automaton is a collection oI states and
precedence relation between them. Here we can convert the
state diagram oI Iinite automata into task graph and using Intel
C parallel compiler Ior simulation oI parallel system Ior
calculating the execution time or turnaround time oI the tasks
in multiprocessor system. States oI Iinite automata are
considering as tasks in multiprocessor system to achieve the
Iollowing |6, 11|:





1) Allow speciIication oI a large number oI constraints,
2) Optimize the cost Iunction, and
3) Balance the utilization oI processing nodes.
In the next section oI the paper we are discussing about
Iinite automata and DAG Ior massively parallel system or
distributed system.
II. Related work
In the 1980s and early 1990s a lot oI research was done in
relation to database and transaction processing. The database
researchers during this period attempted to use the
transactional models to model workIlows. However, these
models were not practical Ior real world applications. But they
can be used as a primary baseline to model Task Ilow
applications in parallel and distributed system. We are going
to describe the transactional model Ior databases, the Task
Ilow graph Ior parallel ad distributed system and Iinite
Automata |4|.
A. Transaction Models
The concept oI transaction models |12, 13| allows an
application programmer to write applications without the need
to deal with consistency and reliability in presence oI Iailure
and concurrent users, since transaction provides the well-
known ACID properties |14, 13|. Traditionally, transactions
are characterized by simple application logic and short
duration activities that typically execute within a Iew minutes
or seconds. Traditional transactions models are built on the
concept oI ACID Properties |16|.

Zubair Khan
Department oI C.S.E.
Invertis University
Bareilly India
zubair.762001gmail.com
Ravindra Singh
Department oI C.S & I.T.
Rohilkhand University
Bareilly India
rsiet2002gmail.com
Sumit Sanwal
M.Tech. C.S.E.
Invertis University
Bareilly India
sanwalsumitgmail.com
Arun Gangwar
M.Tech. C.S.E.
Invertis University
Bareilly India
gangwar50gmail.com
Shabbir Alam
College oI CS&IS
Jazan University Jazan
Kingdom oI Saudi arabia
amushabbirgmail.com
611 978-1-4673-4529-3/12/$31.00 c 2012 IEEE
B. Formal Modeling and Specification for Task
flows
A Iormal speciIication provides a Iormal Iramework Ior
modeling and analysis oI Task Ilows (task Allocation), which
develops a higher conIidence in the correctness oI Task
allocation. A number oI Iormal modeling techniques have
been proposed |15, 16| Ior using in Task Ilows modeling or
task allocation Ior parallel and distributed system. Firstly the
research possess Iormal semantics despites their graphical
nature. Secondly, instead oI being purely event based, it can
explicitly model states, and lastly it is a theoretical proven
analysis technique. Now it`s time to explain the Iinite
automata Ior DAG as Iollow.
C. Finite Automata
Finite Automata (FA) is used to model discrete event
systems. The Iinite automata model is represented by directed
graph, in which a node represents the states oI Iinite automata
and arcs represent an order oI event execution. A Iinite
automata is a quintuple (Q, , , q
o
, F), where Q is the
set oI states oI Iinite automata, is a set oI input symbols, and
is a mapping Iunction (in NFA : Q ( U } P(Q) and
in DFA : Q Q), q
o
is the initial state belonging to the
states oI Iinite automata q
0
Q, and F is the subset oI Iinal
states F Q |1,2|.

Figure1. State diagram oI FA contains exactly (aba or bbaa) over the alphabet
a, b}
Example: In the Figure2, Finite automata consisting oI
three states (claim, under consideration, ready) and three
events (record, pay, send letter).This diagram model the
process Ior dealing with insurance claim. As the claim is
received, it is Iirst recorded, aIter which either a payment is
made or a letter is sent explaining the reason Ior rejection. The
ready state is marked, as it is the Iinal state oI the process |4|.



:
Claim Under consideration Ready

R Record, PPay, S Send letter.
x : R, P, S}
x Q: claim, under consideration, Ready}
x : (R claim under consideration), (P under
consideration Ready), (S under consideration
Ready)}
x q
o
: Claim}
x F: Ready}
In the next section we are going to explain the DAG Ior
parallel and distributed system
D. Directed Acvclic Graph
The directed acyclic graph (DAG) Ior tasks is the precedence
constraints between the tasks along with their execution time.
The DAG can be represented by the set oI the tasks and E
represent the edges among the nodes |3,5|.
1. Properties of DAG.

x Each edge connecting two vertices, such that there is
no way to start at some vertex v and Iollow a
sequence oI edges that eventually loops back to v
again. |17|
x The height oI task can be represented by

Height (Ti)



Here PRED (T
i
) is the set oI predecessors oI task T
i
.
s
0

s
1
s
I

R
P
S
Figure2. Insurance Claim Policy
0 iI PRED (Ti)
Otherwise (1)
1max height (T
j
)_T
j
PRED
(T
i
)
612 2013 3
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IEEE International Advance Computing Conference (IACC)

Figure3. DAG Ior a given Iinite automata
When we propose the system or technique FA to DAG we get
some illegal state or illegal string problem which violate task
Flow graph or task allocation graph we would like to explain
the avoidance problem which we used it in our propose
system.
E. Avoidance Problem
Those problems where certain states or events oI the system
are undesirable and hence needs to be avoided. In Iinite
automata we have to avoid those sequences oI events oI the
system which violate some conditions which is required Ior
the desired behavior oI the system. The avoidance problem
can be Iurther classiIied into state avoidance and path (string)
avoidance.
1. State Avoidance
In the state avoidance, some states oI the system are not
acceptable as they violate conditions that we wish to impose
on the system |4,8|. These states are termed as illegal state.
The idea oI state avoidance problem is presented in Figure3.

Fiureg4. State avoidance |8|
Assume that the state i in the above Iigure is an illegal state.
The illegal state i can be reached by a n number oI states by
executing one oI the events e3, e4, & e5 when the system is in
state i1, i2, i3 respectively. Hence illegal state i should be
removed and events e3, e4, & e5 that take the system to illegal
state i should be disabled at s state i1, i2, i3.
2. String Avoidance
Some strings oI the system are not acceptable as they
violate conditions that we wish to impose in the system |8|,
termed as illegal strings. The idea oI string avoidance problem
is presented in Figure 4.


Figure5. String Avoidance
In Figure4, state E can be reached Irom state A through a
number oI strings (ACE, ABE, ADE, ACDE and AE) i.e.
Iollowing a sequence oI events. The main objective oI string
avoidance is to avoid a string that contains an illegal event
(e
i
). The illegal event e
i
is shown with bold line in Figure. All
the dotted strings are acceptable. Hence the event ei is
disabled
III. Propose Model
Here we propose a way to implement states oI Iinite
automata on the multiprocessor system. In the below Iigure
shows the task Ilow oI our propose work. Here consider the
states oI Iinite automata as tasks and constructed the DAG Ior
the Iinite automata. We are going to explain it with Iollowing
method and a example oI Iee management Ior admission
procedure system to understand the system.
Method: let us consider Iee management system in a college
or university we are going to submitted the tuition Iee and
transportation Iee both are diIIerent process or task in a
system Once the tuition Iee is deposit it cannot be cancelled,
but cancellation oI transportation Iee is allowed. There are
three tasks-
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Task1- Submission Tuition Iee (t
c
),
Task2- Submission Transportation Iee ( t
b
), and
Task3- Cancel a submitted Transportation Iee ( t
b
).
Some Constraints are:
x Submission oI Transportation Iee can not start until
submitting the Tuition Iee (t
c
BD t
b
).
x II submission oI Transportation Iee aborts then
submitting college Iee must aborts too (t
b
AD t
c
).
x II submitting Tuition Iee aborts but Transportation
Iee commits, then submission oI bus Iee has to be
canceled (t
c
BAD (t
b
BAC t
c
))
A. Individual Task Automata.
A task begins with a start event st and terminates with commit
event (c), an abort event (a) or it doesn`t start. There is also a
pre-commit event (pc) that precedes commit and abort events.
Since the states Iollowing the terminating events and initial
state are Iinal states, they are marked Both task tc and tb are
modeled as separate automata Gc and Gb as shown in the
Iigure and these automata are then shuIIled to get a Task Ilow
model
G
cb
G
c
,,G
b
in the Iigure.

(a) (b)
Figure6. Individual Task Automata Ior (a) - Institute Iee submission (b) -
Transport Iee submission.

Tuition Iee submission task
x : st
c
, pc
c
, a
c
, Ia
c
, c
c
}
x Q: in
c
, ex
c
, dn
c
, ab
c
, cm
c
}
x : (st
c
in
c
exc), (pc
c
ex
c
dn
c
), (a
c
ex
c

ab
c
), (c
c
dn
c
cm
c
), (Ia
c
dn
c
ab
c
)}
x q
o
: inc}
x Q
I
: in
c
, ab
c
, cm
c
}
Transportation Iess submission task
x : st
b
, pc
b
, a
b
, Ia
b
, c
b
}
x Q: in
b
, ex
b
, dnb, ab
b
, cm
b
}
x : (st
b
in
b
ex
b
), (pc
b
ex
b
dn
b
), (a
b
ex
b

ab
b
), (c
b
dn
b
cm
b
), (Ia
b
dnc
b
ab
b
)}
x q
o
: in
b
}
x Q
I
: in
b
, ab
b
, cm
b
}



B. Identifving Illegal States and Illegal Events
Strong-casual and weak casual dependencies deIine
incompatibility between the states oI Iinite automata. Whereas
precedence dependency between the states deIines the
precedence order oI Iinite automata. On the basis oI this
speciIication, we classiIy and model strong-casual and weak-
casual dependencies as state avoidance problems and
precedence dependency as string avoidance problem.
For this scenario the dependencies which violate our
conditions are:
Figure8. Task Ilow model in parallel system
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IEEE International Advance Computing Conference (IACC)
x Dependency 1: Begin Dependency (BD): task t
b

cannot begin until task t
c
has begun.
x Illegal or incompatible state set: task tc is in initial
state and task t
b
is in execution state (1, 2).
x Dependency 2: Abort Dependency (AD): iI task t
b

aborts then task t
c
also aborts.
x Illegal or incompatible state: task t
b
is in abort state
and task t
c
is in commit state (5, 4).
x Dependency 3: Commit Dependency (CD): iI both
task t
c
and t
b
commit then the commitment oI t
c

precedes the commitment oI t
b
.
x Illegal event: task transportation Iee submission is in
done state and has an illegal event commit. That is,
event cc Irom state (3,5)

C. Removing Illegal States and Disabling Illegal
Events
AIter identiIying the illegal states and illegal events we have
to remove it Irom the state diagram. So we make a generator
model Ior the given Iinite automata in the Figure 7, to make
the undesirable states to unreachable states


Figure8. Generator Model
In the Figure8 the precedence arcs between the states cannot
reaches state (1, 3), (1, 4), (1, 5)} Irom the initial state, which
is undesirable.


D. Logical Correctness of the Model
When a system reaches an unmarked state such that no other
events can be executed, we say that the system is deadlocked
because it enters an absorbing state without terminating the
current task. Another important issue is when there is a set oI
states in Iinite automata that Iorms a strongly connected
component (i.e. these states can reach Irom one another) and
no transitions going out oI the set. When a system enters this
set oI states then we get a live lock |2, 4|. To check the
presence oI deadlock and live lock, we check the trim property
Ior the generator model given in the Figure8. II the generator
model is not trim then calculate the trim generator to get the
deadlock Iree state diagram.
DeIinition 1: Accessible states set (Q
a
): Set oI all states that
can be reached Irom the initial state is called accessible states
subsets |8|.
DeIinition 2:Co-accessible state set (Q
ca
): Set oI all states q
Irom which some marked state can be reached is called the co-
accessible states subset |8|.
DeIinition 3: Trim: The generator G is trim iI it is accessible
(i.e. Q Q
a
) and co-accessible (i.e. Q Q
ca
) |4|.
Example: Figure9 shows a DES model, where q0 represents
initial state and state q1 represent the marked state |9|.

Figure9. DES model |8|
For the above state diagram, Q q
o
, q
1
, q
2
, q
3
}, Q
a
q
0
, q
1
,
q
2
}, and Q
ca
q
0
, q
1
, q
2
}. Since Q is equal to Q
a
but not Q
ca
,
the given state diagram is not trim (not Iollow the property oI
DAG).
To check the trim property Ior the example oI Iee
management system reIer to Figure 10 below. All the states
that are green in color are co-accessible, whereas states that
are blue in color are both accessible and co-accessible.
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Q (1,1), (1,3), (1,4), (1,5), (2,1), (2,2), (2,3), (2,4), (2,5),
(3,1), (3,2), (3,3), (3,4), (3,5), (4,1), (4,2), (4,3), (4,4), (4,5),
(5,1), (5,2), (5,3), (5,4), (5,5)}
Q
a
(1,1), (2,1), (2,2), (2,3), (2,4), (2,5), (3,1), (3,2), (3,3),
(3,4), (3,5), (4,1), (4,2), (4,3), (4,4), (4,5), (5,1), (5,2), (5,3),
(5,5)}
Q
ca
(1,1), (1,4), (2,1), (2,2), (2,3), (2,4), (2,5), (3,1), (3,2),
(3,3), (3,4), (3,5), (4,1), (4,2), (4,3), (4,4), (5,1), (5,2), (5,3),
(5,4), (5,5)}
Since Q Q
a
Q
ca
so the given Iinite automata G
cbg
is not
trim; hence there is a deadlock and live lock in the system. To
get the deadlock Iree model we Iind a trim generator G
t
, A
trim generator can be obtained by replacing Q with Q
t
Qa
Qca.
Q
t
(1,1), (2,1), (2,2), (2,3), (2,4), (2,5), (3,1), (3,2), (3,3),
(3,4), (3,5), (4,1), (4,2), (4,3), (4,4), (4,5), (5,1), (5,2), (5,3),
(5,5)} (1,1), (1,4), (2,1), (2,2), (2,3), (2,4), (2,5), (3,1),
(3,2), (3,3), (3,4), (3,5), (4,1), (4,2), (4,3), (4,4), (5,1), (5,2),
(5,3), (5,4), (5,5)}
Q
t
(1,1), (2,1), (2,3), (2,4), (2,5), (3,1), (3,2), (3,3), (3,4),
(3,5), (4,1), (4,2), (4,3), (4,4), (5,1), (5,2), (5,3), (5,5)}
A trim generator consists oI states that are both accessible and
co-accessible (states with blue color in Figure 10).A trim
generator Ior Iee management system example shown in
Figure11.

Figure11. Trim Generator Gt

IV. RESULT
The Figure12 represents the graph which contains
comparison on among all other task scheduling algorithms.
Where it compares between number oI tasks and turnaround
time .Here we take three series oI perIormances with 20, 25,
and 30 number oI tasks.


Figure12. Chart between the turnaround time and number oI tasks
Here we simulate the task graph oI Iinite automata in Intel
C parallel compiler and to compare the perIormance we
take 20 task at a single time where automata task scheduling
Figure10. Generator Model Gcbg
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(ATS) took 18 milliseconds., Iuzzy took 20 milliseconds,
Round Robin took 24 milliseconds, and FCFS took 26
milliseconds thereIore we observe that Automata Task
Scheduling (ATS) works Iaster than others do, to perIorm
number oI tasks at same time on the same number oI
processors. Here we are considering three processors in the
homogenous environment; means all the processors takes
equal execution time to execute the task. The chart given in
the Figure12 shows that automata task scheduling algorithm
takes less turnaround time.

V. CONCLUSION
We have proposed a new way Ior task allocation oI Iinite
automata on a multiprocessor system by which we reduces the
turnaround around time oI the system. This is the new way to
minimizing the cost Iunction and Iull utilization oI processors.
Modeling oI a task Ilow should be done in a multiprocessor
system is easy and more intuitive to implement on a
multiprocessor system in distributed environment. IdentiIying
the result Irom the set oI processors and a set oI tasks would
be useIul Ior calculating the turnaround time oI a task Ilow
automata. We demonstrate this by using Intel C parallel
compiler as a simulation tool.

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2013 3
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IEEE International Advance Computing Conference (IACC) 617