BASICS OF PERIPHERAL DEVICES AND WORKING

Introduction
Microprocessor based system design involves interfacing of the processor with one or more peripheral devices for the purpose of communication with various input and output devices connected to it. During the early days of the microprocessor revolution, these techniques required complex hardware consisting of Medium scale integration devices making the design highly complex and time consuming. So, the manufacturers (INTEL) have developed a large number of general and special purpose peripheral devices most of them being single chip circuits. They are also programmable devices. Hence these peripheral devices are found to be of tremendous use to a system designer. Peripheral devices, can broadly be classified into two categories. (a) General purpose peripherals and (b) Special purpose peripherals (Dedicated function peripherals) General purpose peripherals are devices that perform a task but may be used for interfacing a variety of I/O devices to microprocessor. The general purpose devices are given below: Simple I/O Programmable peripheral Interface (PPI) Programmable Interrupt Controller Programmable DMA Controller Programmable Communication Interface Programmable Interval Timer - (Non-programmable) (8255) (8259) (8237/8257) (8251) (8253/8254)

Special function peripherals are devices that may be used for interfacing a microprocessor to a specific type of I/O device. These peripherals are more complex and therefore, relatively more expensive than general purpose peripherals. The special function peripherals (Dedicated function peripherals) are Programmable CRT Controller Programmable Floppy Disc Controller Programmable Hard Disc Controller Programmable Keyboard and display interface.

The functioning of these devices varies depending on the type of I/O device they are controlling. PROGRAMMABLE PERIPHERAL INTERPHASE - 8255A Introduction INTEL introduced this programmable peripheral interface (PPI) chip 8255A for interfacing peripheral devices to the 8085 system. This versatile chip 8255A is used as a general purpose peripheral device for parallel data transfer between microprocessor and a peripheral device by interfacing the device to the system data bus. The PPI has three programmable I/O ports viz., Port A, Port B and Port C each of 8 bit width. Port C can be treated as two ports

Port C upper (PC7-4) and Port lower (PC3 0) and these two can be independently programmed as INPUT or OUTPUT ports also.

Salient Features
i. It is a general purpose programmable I/O device which is compatible with all INTEL processors and also most other processors. ii. It provides 24 I/O pins which may be individually programmed in two groups. iii. This chip is also completely TTL compatible. iv. It is available in 40 pin DIP and 44 pin plastic leaded chip carrier (PLCC) packages. v. It has three 8 bit ports. Port A, Port B and Port C. Port C is treated as two 4 bit ports also. vi. This 8255 is mainly programmed in two modes (a) the I/O mode and (b) The bit set/reset mode (BSR) mode. The I/O mode is further divided into three modes: Mode 0, Mode 1, and Mode 2. vii. An 8 bit control resister is used to configure the modes of 8255. There is also another 8 bit port called control port, which decides the configuration of 8255 ports. This port is written by the microprocessor only.

Pin Description
The 8255A is a 40 pin DIP chip which works at single + 5V DC. The pin diagram of 8255A chip is shown in Fig. The pin details of the chip are given below.
PA3 PA2 PA1 PA0
RD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32

PA4 PA5 PA6 PA7

WR

CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2

Reset D0 D1 D2 D3 D4 D5 D6 D7 Vcc PB7 PB6 PB5 PB4 PB3

8255A

31 30 29 28 27 26 25 24 23 22 21

Pin Configuration of 8255 (Top view DIP Package)

Pin description of 8255A

Selection of 8255A Ports and their function

Block Diagram of the 8255A

The functional diagram of 8255A is shown in Fig. Each functional unit is explained below.

Functional Block Diagram of 8255A Programmable Peripheral Interface (PPI) Data Bus buffer This tri-state bidirectional 8 bit buffer is used to interface the data bus of 8255A to the system data bus. Data is transmitted or received by the buffer when the CPU executes input or output instructions control words and status information is also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all the internal and external transfers of both data and control or status words. It accepts inputs from the CPU and inturn issues commands to both of the control groups. Group A and Group B Controls Each of the group A and group B control blocks receives control words from the CPU and issues suitable commands to the ports associated to it. The group A control block controls port A and port C Upper (PC7 - PC4) where are group B control block, controls port B and port C lower (PC3 - PC0) Port A It has one 8 bit data output latch/buffer and one 8 bit input latch buffer. This port A can be configured in all the three modes: mode0, mode 1, mode 2. Port B This has an 8 bit data input/output latch/ buffer which can be programmed both in mode 0 and mode 1. Port C It has one 8 bit unlatched input buffer and an 8 bit output latch/buffer. This port can be divided into two 4 bit ports under the mode control. These two ports can be used as control signals for ports A and B in the handshake mode.

Operational Modes of 8255

8255 can be mainly configured in two modes. i) Input/Output mode (I/O mode) ii) Bit Set-Reset mode (BSR mode) Input/Output mode In I/O mode, the ports of 8255 acts as programmable ports, while in BSR mode only port C (PC0 - PC7) can be used to set or reset its individual port bits. The 8255 can programmed to operate in any one of the following modes. i) Mode 0 (simple mode) ii) Mode 1 (strobed mode)

iii) Mode 2 (bi-directional bus mode) Mode 0: Simple I/O Mode This is a simple I/O or basic mode in which no hand shake signals are used. Port A and Port B are used as two simple 8 bit I/O ports and port C as two 4 bit ports it is used with those I/O devices whose timing characteristics are clearly known. For example, if an I/O device sends a byte for every 10 ms, to the UP, we can execute the IN instruction for every 10 ms to receive the data. All the 3 ports can be programmed in Mode 0. Mode 1: Storbed Mode This is a handshake I/O mode (strobed mode) in which the data transfer is controlled by handshake signals. For example, when the microprocessor wish to transfer the data to a relatively slow device like printer, for proper transfer of data handshake signals are used to inform the processor whether the printer is ready to receive the data or not. The data transfer by handshake use both port A and port B as 8 bit input/output ports. Port A uses the upper three signals PC3, PC4 and PC5 where as port B uses the lower signals PC2, PC1 and PC0 for handshaking signals. The remaining two lines of port C are used in Mode 0. The unique feature of this mode is that the data transfer can take place without direct CPU intervention. When port A or port B are configured as input ports the three control signals used are IBF (Input Buffer Full), (strobe) and INTR (Interrupt request). Similarly when port A or port B are programmed as mode 1 output ports, the three control signals used are (Output Buffer Full), (Acknowledge) and INTR (Interrupt Request). A very important point to be remembered is that only port A and port B can be configured in mode 1. Mode 2: Bidirectional I/O (or) Strobed Bidirectional I/O In this mode port A alone can be configured to both, transmit and receive data. Place over a single 8 bit data bus using handshaking signals. This mode of operation is useful when transferring data between two computers. As it is bidirectional I/O, it needs more number of handshake signals i.e., 5 lines of port C, PC3 - PC7. The remaining lines of port C can be used by port B in Mode 1. So, when port A is programmed to operate in mode 2, port B can operate in mode0 or mode1.If programmed for mode 0, PC0 - PC2 can be programmed as mode 0 inputs or outputs. If port B is programmed for mode 1, PC0 - PC2 become handshake signals for this port. In conclusion, we can understand that, Port A can be in Mode 0, Mode 1 or Mode 2. Port B can be in Mode 0 or Mode 1 Port C can only be in Mode 0. Note: A high on reset line of 8255, resets all the ports A, B and C to work as input ports in mode 0. The reset pin of 8255 is generally connected to Reset Out pin of 8085. BSR (Bit Set/Reset) Mode

The BSR mode is related to only with the 8 bits of port C, which can be set or reset by writing an appropriate control word in the control register. A control word with bit D7 = 0 is treated as a BSR control word. It does not change any previously transmitted control word with bit D7=1.So, the I/O operations of port A and port B are not changed by a BSR control word. In BSR mode, individual bits of port C can be used for applications such as an ON/OFF switch.

Control Word
The 8255A has an 8 bit control register. The contents of this register called, the control word, decides the I/O function for each port. This register is allowed to write a control word when A0 and A1 lines are at logic 1. This register is not accessible for a read operation.

In the control word register, the bits D0 through D2 correspond to the group B control block as shown in Fig.4.3. Bit D0 configures the lower four lines of port C for input / output operation.

Control Word Format of 8255 and Control Bit Description

When

D0 = 0, port C Lower - output port

D0 = 1, port C Lower - input port. The bit D1 configures port B as an 8 bit wide input or output When D1 = 0, port B is output port. D1 = 1, port B is input port. The bit D2 is the mode select bit for port B and the lower 4 bits of port C. D2 = 0, selects Mode 0 D2 = 1, selects Mode 1. The bits D3 through D6 in the control register correspond to the group A control. Bits D3 and D4 of the control register are used to configure the operation of the upper half of port C and complete port A. When D3 = 0, port C upper is output port. or D3 = 1, port C upper is input port.

Similarly when D4 = 0, port A is output port. or D4 = 1, port A is input port. The bits D5 and D6 are used to select among the three modes of operation names mode 0, mode 1 and mode 2. D6 D5 = 00 selects mode 0 = 01 selects mode 1 = 1x selects mode 2. The last control register bit D7 is the mode set flag, which is shown in Fig.3. D7 D7 = 1 selects I/O mode and = 0 selects BSR mode.

BSR Mode Control Word Register Format

The bit set/reset function is not really a control word. Instead, it allows individual bits of port C to be set or reset. But only one bit can be set or reset at a time. One of the advantages of this mode is that individual bits of port C can be changed without changing any of the others. This is needed when port C is used to control the ON/OFF status of several external devices. For example, the device connected to PC4 can be turned ON without affecting the status of any devices connected to the other seven outputs. The bit set/reset function is used in mode 1 and 2 to enable interrupt outputs available in these modes.

Programmable Interval Timer - 8253/54

Introduction It is always possible to generate accurate time delays using the microprocessor system by using software loop programs. But that will waste the precious time of CPU. Hence INTEL introduced the chips 8253/8254 which is a hardware solution for the problem of generating accurate time delays. These chips can be used for applications such as a real-time clock, event counter, a digit alone shot, a square wave generator and also as a complex wave form generator. Salient Features 8254 is an upgraded version of 8253 and they are pin-compatible. The features of these chips are almost same except that, 8254 can operate with higher clock frequency ranging from DC to 8 MHz and 10 MHz, whereas the 8253 can operate with clock frequency from DC to 2 MHz. 8254 includes a status read-back command that can latch the count and the status of the counters. This command is not available in 8253. 8253 uses N-MOS technology where as 8254 uses H-MOS technology. The chips are packaged in 24 pin DIP and requires a single +5V DC power supply. Three identical 16 bit counters that can operate independently in any of the six modes are available. The counters are down counters. These chips are compatible with all INTEL and most of the other microprocessors. To operate a counter, a 16 bit count is loaded in its register and on command beings to decrement the count until it reaches 0. At the end of the count, it generates a pulse that can be used to interrupt the microprocessor. The counters can be programmed for either binary or BCD count. The read-back command of 8254 allows the user to check the count value and current status of the counter. Pin Description The chips 8253/54 is packaged in a 24 pin DIP and require a single +5V power supply. The pin diagram is shown in Fig. The description of each pin is given below.

Pin Diagram of 8253/54(Top view Dip)

Block Diagram of 8254 The block diagram of the Programmable Interval Timer is shown in Fig. The block diagram includes three counters - Counter 0, Counter 1 and Counter 2, a data bus buffer, read/write control logic and a control word register. Each counter has two input signals CLOCK and GATE and one OUTPUT signal-out.

Functional Block Diagram of 8253/8254 Data Bus Buffer This tri-state bidirectional 8 bit buffer is used to interface the 8253 to the system bus. Data is transmitted or received by the buffer upon execution of INPUT or OUTPUT CPU instructions. The data bus buffer has three basic functions. They are i. Programming the MODES of the 8253. ii. Loading the count registers and iii. Reading the count values. Read/Write Logic

The read/write logic accepts inputs from the system bus and in turn generates control signals for overall device operation. It is enabled or disabled by so that no operation can occur to change the function unless the device is selected by the system logic. RD : A low on this pin informs the 8253 that the CPU is inputting data in the form of counters value. WR : It is an active low pin. A low on this pin informs the 8253 that the CPU is outputting data in the form of mode information or loading counters. A0,A1: These two lines are address lines used to select one of the three counters and the control word register as shown in the table for mode selection. CS(Chip Select): It is an active low pin. A low on this input enables 8253. No read or write will occur unless the device is selected. The input has no effect on the actual operation of the counters.

Selection and function of 8253/54 Counters Control Word Register This register is selected when A0, A1 are at logic 1. It then accepts the information from the data bus buffer and stores it in a register. The information stored in this register controls the operation MODE of each counter, selection of binary or BCD counting and the loading of each count register. The control word register can only be written to into, but no read operation is possible. Counter 0, Counter 1, Counter 2 These three functional blocks are identical in operation. Each counter consists of a single 16 bit, pre-settable DOWN counter. The counter can operate in either binary or BCD and its input, gate and output are configured by the selection of modes stored in the control word

register. The counters are totally independent. The counter can be read by a simple READ operation for event count applications. Operational Description The complete functional operation of 8253 is programmed by the system software. A set of control words must be sent out by the CPU to initialize each counter of 8253/8254 with the desired MODE. Once programmed, the 8253 is ready to perform whatever timing tasks it is assigned to perform. The actual counting operation of each counter is totally independent and additional logic is provided on-chip so that the usual problems associated with efficient monitoring and management of external, asynchronous events or rates to the micro computer system have been eliminated. Programming 8253/54 Each counter of 8253/54 is individually programmed by writing a control word into control word register. The control word register is shown in Fig.below. The different bits of this 8 bit register are either set or reset for the operation of the counters. The various options are given below.

Control Word Format Counter selection is done by the D6, D7 bits.

The bits D4, D5 decides the counter READ/LOAD operations as shown below.

The bits D1, D2 and D3 decides the mode operation 8253/54 can be configured in six modes. This mode selection is done by these bits as shown below.

The D0 bit decides whether the counter is a 16 bit binary counter or a BCD counter. When D0 = 0 it acts as a 16 bit binary counter. D0 = 1 it acts as a binary coded decimal counter (BCD) While using 8253/54 we must write the control word to initialize the counter to be used. For every counter we use, the control word must be written and select the counter and set it up. 8253/54 can operate in six different modes. The modes of operation are explained below. Mode 0 (Interrupt on Terminal Count) The output of the counter will be initially low after the mode set operation. After the count is loaded into the selected counter register the output will remain low and the counter will count. When terminal count is reached, the output will go high and remain high until the selected count register is reloaded with the mode or a new count is loaded. Mode 1 (Programmable one shot) In this mode, the out signal is initially high. When the GATE is triggered, the OUT goes low, and when count reaches 0, the OUT goes high again. Thus a one shot signal is generated due to the signal on the GATE. Mode 2 (Rate Generator) It is a divide by N counter. In this mode, a pulse is generated that is equal to the clock period at a given interval controlled by the count that is loaded. When the count is loaded, the OUT signal stays high until the count reaches 1, at this point the OUT signal goes low for one clock period. Afterwards, the count is reloaded automatically and the cycle repeats, generating a continuous string of pulses. Mode 3 (Square-wave Generator) In this mode, when the count is loaded, the OUT signal is high. The count is then determined by two with each clock cycle. When the count reach 0 the OUT signal goes low and the count is reloaded automatically. As this is repeated continuously a square wave is generated on the OUT signal. The period of the square wave is controlled by the count value.

Mode 4 (Software Triggered Strobe) In this mode, the OUT signal is initially high and goes low for one clock period when the count reaches 0. So, one strobe pulse (low) is generated for each count. The count must be reloaded for more strobe signals. Mode 5 (Hardware - Triggered Strobe) This mode is similar to mode 4, except the strobe is hardware triggered with a signal on the GATE signal. The OUT signal is initially high. When the GATE signal goes from low to high, the count starts and when it reaches 0, the OUT signal goes low for one clock period. Read-Back Command The read-back command in the 8254 allows the user to read the count and the status of the counters (This command is not available in 8253). When the read-back command is selected in the control word (SC1 SC0 - 11) each of the counters specified is latched and then the count and/ or the status may be read for each counter latched. The command is written in the control register and the count of the specified counter(s) can be latched if COUNT (bit D5) is 0. A counter or a combination of counters is specified by making the respective CNT bits (D1, D2 and D3) high. The read-back command format is shown below.

D0 = 0 (Reserved for future expansion) CNT0, CNT1, CNT2 are counter select bits. Read back command format The STATUS of the counters can be read if D4 bit (STATUS) of Read-back command is 0. The Read-back command eliminates the need of writing separate counter latch commands for different counters.

Programmable Interrupt Controller - 8259

Introduction There is an absolute need of this Programmable Interrupt Controller for Interfacing I/O devices to the microprocessor The 8085 processor has 5 interrupt lines namely, Trap, RST 7.5, RST 6.5, RST 5.5 and INTR. So, we can interface five I/O devices, which can perform the interrupt driven data transfer safely. But, suppose we wish to connect more than five I/O devices, to the microprocessor, then we may have to connect more than one I/O device to the interrupt lines. This will affect the interrupt driven data transfer and the microprocessor has to perform polling. i.e, it has to check each device, which is in need of interrupt service. This polling has the dis-advantage of long time and slow interrupt response. Hence to overcome all

these problems, INTEL introduced the 28 pin DIP chip -8259. This device accepts interrupt requests from as many as 8 devices independently and as many as 64 I/O devices by cascading method. Salient Features INTEL 8259 is a single chip programmable interrupt controller which is compatible with 8085, 8086 and 8088 processors. It is a 28 pin DIP IC with N-Mos technology and requires a single +5 DC supply. It handles up to eight vectored priority interrupts for the CPU and cascadable for up to 64 vectored priority interrupts without the need of any additional circuitry. when two 8259s are cascaded through cascade lines the first 8259 will act as master and the second 8259 will act as a slave. Pin Description The pin diagram of 8259 is shown below . The pin details are given below

Pin Diagram of 8259

Block Diagram The block diagram of programmable interrupt controller is shown in Fig. below. The block diagram consists of eight sub units. They are Control logic, Read/write logic, Data bus

buffer. Three register (IRR, ISR and IMR), 5 priority resolver and cascade buffer. The functions of each unit are explained below.

Priority Resolver This logic unit determines the priorities of the bits set in the IRR. The highest priority is selected and strobed in to the corresponding bit of the ISR during pulse. Interrupt Mask Register (IMR) The IMR stores the bits which mask the interrupt lines. The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower priority.

Control Logic This unit has two pins. INT (Interrupt) as an output pin and (interrupt acknowledge) as an input pin. The INT is connected to the interrupt pin of the microprocessor unit. Whenever an interrupt is noticed by the CPU, it generates signal. Working of 8259 The 8259 accepts interrupt requests from any one of the 8 I/O lines (IR 0 - IR7). Then it ascertains the priority of the interrupt lines. Then it ascertains the priority of the interrupt lines. Suppose, the received interrupt has higher priority than currently serviced, it interrupts the microprocessor and after receiving the interrupt acknowledgement from microprocessor. It provides a 3 byte CALL instruction. The sequence of steps that occur when an interrupt request line of 8259 goes high is as follows. The 8259 accepts the requests on IR0 - IR7 in IRR. Then it checks the contents of IMR whether that request is masked or not. The 8259, then checks ISR to know the interrupt levels that are being currently serviced. After this 8259 sends a high INT to 8085 processor. Normally, it is the job of the priority resolver to check the contents of IRR, IMR and ISR and decide whether to activate INT output of 8259 or not. Now 8085 processor responds by suspending the program flow at the end of the current instruction and makes low. On receiving, 8259 sends code for CALL to the microprocessor on D7-0 bus. This code for CALL in IR register of 8259 causes the 8085 to issue two more signals. When goes low the second time, 8259 places LSB of ISS address on the data bus. When goes low the third time, 8259 places the MSB of ISS address ont he data bus. Now, the microprocessor branches to the ISS after saving the contents of program counter on the stack top. After finishing the ISS, the control returns to the main program by popping the top of stack to PC. Programming 8259 The 8259 requires two types of command words namely, Initialization Command Words (ICW) and Operational Command Words (OCW). The 8259 can be initialized with four ICWs, the first two are essential and the other two are optional based on the modes being used. These words must be issued in a sequence. Once the 8259 is initialized, the 8259 can operate in various modes by using three different OCWs.

Direct Memory Access (DMA)

When large amount of data is to be transferred between microprocessor and I/O device it is a very time consuming operation and the CPUs time is wasted. If the I/O port can directly access memory for data transfer, without CPU intervention, that will be more efficient. So, in any microprocessor system, if the data transfer occurs without the intervention of the CPU, that

method is known as Direct Memory Transfer technique (DMA).This is explained in the figure below.

As an example , the data transfer between a floppy disk and a R/W memory in a computer system is based on DMA. To perform the DMA transfer in 8085 based systems two pins HOLD and HLDA (Hold Acknowledge) are used. An I/O device which wishes to transfer data using DMA scheme, sends the HOLD signal to the CPU. On receiving the HOLD signal from an I/O device, the CPU sends a hold acknowledge signal (HLDA) to the I/O device to indicate that it has received the HOLD request and it will give-up the buses in the next machine cycle. The I/O device takes over the control of buses and directly transfer data to the memory or reads data from the memory. This data transfer can be shown by the Fig.4.14. There are two types of DMA schemes. They are a) Burst mode DMA b) Cycle stealing DMA Burst Mode DMA This method is used when a large data block is to be transferred between a I/O device and main memory. In each DMA cycle one byte will be transferred and the DMA controller givesup control of system buses only after all the data has been transferred. The DMA controller interrupts the microprocessor and HOLD request is withdrawn. This technique was widely used by magnetic disk drives. In case of magnetic disks data transfer can not be stopped or slowed down without loss of data. Hence burst mode data transfer scheme is useful. Cycle Stealing DMA This method is used when the I/O device is relatively slow. After a DMA cycle which results in a byte of data transfer, the I/O device withdraws the DMA request. So, the DMA controller withdraws the Hold request by making it low. So, the CPU comes out of HOLD mode and continues to execute the main program. After some time when the I/O device is again ready, it once again activates the data request I/P of DMA controller. So, DMA again activates the HOLD pin and waits for HLDA. Now the data transfer is performed again. In this way the

complete data is transferred. As the data transfer occurs during certain cycles of CPU, it is called cycle stealing DMA.

DMA Controller - Intel 8237/8257

In Direct Memory Access technique, the data transfer takes place without the intervention of CPU, so there must be a controller circuit which is programmable and which can perform the data transfer effectively. For this purpose Intel introduced the controller chip 8257 which is known as DMA controller. A DMA controller temporarily borrows the address bus, data bus and control bus from the microprocessor and transfers the data bytes directly from the port to memory devices. As the transfer is handled totally by hardware, it is much faster than software program instructions. A DMA controller can also transfer data from memory to a port. Salient Features Intel 8257 is a programmable, 4-channel direct memory access controller i.e., four peripheral devices can request data transfer at any instant. The request priorities are decided internally. Each channel has two signals, DRQ (DMA Request) and (DMA acknowledge). Each channel has two 16 bit registers. One for the memory address where the data transfer should being and the second for a 14-bit count. There are also two 8-bit registers one is the mode set register and the other is status register. It can operate both in slave and master mode. It is a totally TTL compatible chip. Pin Diagram: 8257 is a 40 pin IC package which requires a single +5V supply for its operation. The pin details are as follows. The pin diagram is shown in Fig below.

Pin Diagram of 8257

Block Diagram The functional block diagram is shown below. It consists of

 Data bus buffer Read/Write logic DMA channels Control logic Mode set Register Status Register Data Bus Buffer Three state bidirectional, 8 bit buffer interfaces the 8257 to the system data bus. When the 8257 is being programmed by the CPU, eight bits of data for DMA address register, a terminal count register or the mode set register are received on the data bus. When the CPU reads the DMA address register, a terminal count register or status register, the data is sent to the CPU over the data bus. When 8257 is operating as Master, during a DMA cycle, it gains control over the system buses. In this mode, the 8257 sends out the 8 MSBs of the DMA address register of the channel being serviced on the D0-D7 pins at the starting of each DMA cycle to the 8212 latch. After this, the bus is released to handle the memory data transfer during the remaining DMA cycle. Read/Write Logic

Pin and Block Diagram of 8257

In the slave mode, when the CPU reads data from or writes data to the 8257, the read/write logic accepts the I/OR (or) I/OW signals and decodes the least significant 4 address bits (A0 - A3). During DMA cycles, when 8257 is the master, the read/write logic generates the I/O read and memory write or I/O write and memory read signals which controls the data link with the peripheral that has been granted DMA cycle. The different signals are (I/O Read) It is active low bidirectional three-state line. In the slave mode, it is an input, which allows the 8-bit status register or upper/lower byte of a 16 bit DMA address register of terminal count register to be read. In the master mode, is a control output, which is used to access data from a peripheral during the DMA write cycle. (I/O Write) It is an active low bi-directional tri-state line. In slave mode, it is an input, which allows microprocessor to write. In the master mode, is a control output, which allows data to be ouput in the peripheral during DMA read cycle. CLK (Clock Input) This is the clock output of the microprocessor. RESET It is an asynchronous input from the microprocessor which disables all DMA channels by clearing the mode register and tri-states all control lines. A0 - A3 (Address Lines) These least significant four address lines are bidirectional. In the slave mode they are inputs, which select one of the registers to be read or programmed. In the master mode, they are outputs, which constitute the most significant 4 bits of the 16 bit memory address generated by the 8257. (Chip Select) It is an active low input which enables the I/O read or I/O write input when the 8257 is being read or programmed in the slave mode. In the master mode, is automatically disabled to prevent the chip from selecting while performing the DMA function. Control Logic Block This block controls the sequence operations during all DMA cycles by generating the appropriate control signals and 16 bit address that specifies the memory relations to be accessed. A4 - A7 (Address Lines) These four address lines are tri-stated outputs which contains 4 to 7 of the 16 bit memory address generated by the 8257 during all DMA cycles. READY This is an asynchronous input used to insert wait states during DMA read or write machine cycles. Wait states are included between S3 and S4 states of the duty transfer.

HRQ (Hold Request) This output line requests the control of the system bus. This is connected to the HOLD input of 8085. DMA Channels The 8257 has four separate DMA channels each channel with two 16 bit registers (1) a DMA address register (2) Counter register. Both these registers must be initialized before a channel is enabled. The DMA address register is loaded with the address of the first memory location to be accessed. The value loaded into the low order 14 bits of the terminal count register specifies the number of DMA cycles minus one before the terminal count output is activated. DRQ0 - DRQ3 (DMA Request) These are active low signals one for each of the four DMA channels. The output acts as a chip select for the peripheral device requesting service. The DACK line becomes 0 and then 1 for each byte of DMA data transfer. Mode Set Register This register is used to set the mode of operation of 8257. It is normally programmed by the CPU after the DMA address register and terminal count registers are initialized. This register is cleared by RESET input, by disabling all options. The mode set register is shown in Fig. By setting the 4th bit we can opt for rotating priority. Normally DRQ0 has highest priority and DRQ3 has lowest priority. But in the rotating priority mode the priority of the channels has a circular sequence and after each DMA cycle, the priority of each channel changes. If the rotating priority bit is reset, (is a zero) each DMA channel has a fixed priority in the fixed priority mode. i.e., channel 0 has highest priority and channel-3 has lowest priority. The terminal count (TC) bits (bits 0 - 4) for the four channels are set when the Terminal Count output goes high for a channel. The TC bits in the status word are cleared when the status word is read or when the 8257 receives a Reset input. The update flag is cleared when (i) 8257 is reset or (ii) the auto load option is set in the mode set register or (iii) when the update cycle is completed. The update flag is not affected by a status read operation. DMA Working In 8085 microprocessor two lines dedicated for DMA operation. They are HOLD and HLDA. If any device is in need of DMA service it activates a DRQ line. Now the 8257 in turn sends out HOLD request (HRQ) to microprocessor on HOLD line. The microprocessor then completes the current machine cycle and then goes to HOLD state, where the address bus, data bus and the related control bus signals are tri-stated. Now the HLDA signal is activated. The DMA controller which is a slave to the microprocessor so far will now become the master. The DMA controller resolves the priorities of the requesting I/O devices and accordingly sends a signal to the suitable I/O device. When the microprocessor is the master, D7-0 is used by the 8257 for communication with microprocessor and A3-0 are i/p lines to 8257 to select register for communication with microprocessor. But in the HOLD state the 8257 sends out most significant byte of memory address A15-8 on D7-0, sends out address information on A3-0 and also on A7-4. Now become

output lines of 8257. So, the 8257, after sending out a signal to the requesting I/O device, generates and signals if it is a DMA read operation. 8257 generates and signals for DMA write operation. Then a byte of data is transferred between I/O device and memory directly in 4 clock cycles. This is known as a DMA machine cycle, at the end of which, the number of bytes to be transferred is decremented by 1 in the count register and address register is incremented by 1 to point to the next memory address for data transfer.

USART-8251(Universal Synchronous Asynchronous Receiver Transmitter)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication. In a microprocessor system the CPU has to perform the data conversion like serial to parallel or parallel to serial and transmit the data to peripheral devices. This process will wastes the precious time of the CPU. In order to release the CPU from this burden and continue its processing work , INTEL introduced a 28-pin DIP chip called the programmable communication interface. This chip will take care of all the communication activities and lessens the burden of the Microprocessor .This chip is compatible with all the INTEL processors. This 8251 receives parallel data from the CPU and transmits serial data after conversion. Similarly it also receives serial data from conversion. The 8251 is a 28 pin DIP chip which works at 5 volts DC. The Pin diagram of 8251 is shown below. outside devices and transmits parallel data into the CPU after

The Block diagram of 8251 is shown below

sThe USART chip consists of four important

sections .They are

.

CPU Interface & Control Logic section Transmitter Section Receiver Section Modem Control Section

CPU Interface & Control Logic section : The CPU interface and control logic accepts signals from RD, WR, CLK, C/D, CS , D7-0 and RESET pins of the system and generates the necessary signals for controlling the device operation. It consists of three registers ,8-bit data buffer register ,one 16-bit control word register and one 8-bit status word register. The active low signals RD, WR, CS and C/D (Low) are used for read/write operations with these three registers. When C/D bar is high, the control register is selected for writing control word or reading status word. When C/D bar is low, the data buffer is selected for read/write operation. When the reset is high, it forces 8251A into the idle mode. The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section: The

transmitter section accepts parallel data from CPU and converts

them into serial data. This section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits. When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. If buffer register is empty, then TxRDY is goes to high. If output register is empty then TxEMPTY goes to high. The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. The clock frequency can be 1, 16 or 64 times the baud rate. Receiver Section: The receiver section accepts serial data and convert them into parallel data This receiver section is also double buffered with two registers. i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again. If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register. The CPU reads the parallel data from the buffer register. When the input register loads a parallel data to buffer register, the RxRDY line goes high. The clock signal RxC (low) controls the rate at which bits are received by the USART. During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission. During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character. MODEM Control Section: The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines. This unit takes care of handshake signals for MODEM interface. The Modem control signals are general purpose in nature and can be used for functions other than the Modem control if necessary.The Modem sends certain hand shake signals for proper communication between two devices. The DTR and RTS are the are the hand shake signals sent out by the 8251 to Modem and they are activated by using command instruction register. The DSR and CTS are the hand shake signals sent by the Modem to 8251.

__
DSR (Data Set Ready): This signal is general purpose in nature. This signal is used to normally test the Modem condition. The CPU reads its condition by Status read operation.

___

DTR (Data Terminal ready) :This is an output signal which is also a general purpose. The DTR signal is used to control the modem operation such as Data terminal ready or rate select.It can be set low by programming the appropriate bit in the command instruction word.

___
RTS (Request to Send):This output signal is normally used to control the Modem operations such as Request to send. This pin can be set low by programming the appropriate bit in the command instruction word. ___ CTS (Clear to Send) :A low on this pin enables the 8251 to transmit the serial data ,if the Tx EN bit in the command byte is set to one. This Modem control section will decrease the burden of the CPU by converting the 0 s and 1s into unique audio frequencies and transmit on the telephone network.

Programmable Keyboard/Display Interface - 8279

Intel 8279 is the programmable keyboard/display controller, used to interface the keyboard and the display unit to the Microprocessors. The advantage of 8279 is that it is able to drive the signals for both the keyboard and display and hence it is possible for the microprocessor to concentrate on its processing tasks without wasting time. The 8279 has two major sections. One is the Keyboard section and the other is the Display section. The 8279 chip provides four scan lines and eight return lines for interfacing keyboards and a set of eight output lines for interfacing a display. The 8279 scans a keyboard regularly and detects a key depression ,de-bounces the signal from the pressed key and stores the code for the pressed key in an internal RAM of size 8x8.The microprocessor reads this RAM on first in first out basis. Similarly the 8279 refreshes the multiplexed display consisting of7-segment LED digits. The 7-segment codes for the data to be displayed are stored in a display RAM of size 16x8 with in the 8279.The 8279 automatically sends the code for each data to be displayed one after the other until all digits have been displayed. The 8279 is available as a 40 pin DIP chip and it is compatible with all the INTEL basic processors. It works at +5 volts DC. The pin diagram of 8279 is shown below.

The keyboard section can interface to regular type-writer style keyboards or random toggle or thumb switches. The display section drives alphanumeric displays or a bank of indicator lights. So, the CPU is relieved from scanning the keyboard or refreshing the display continuously. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The keyboard portion interfaces an array of sensors or a strobed interface keyboard. Keyboard depressions can be 2-key lockout or N-key rollover. Keyboard entries are de-bounced and strobed in an 8charcter FIFO. If more than 8 characters are entered, over-run status is set. Key entries set the interrupt output line to the CPU. The display section provides a scanned display interface for any display device. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279 has 16*8 displays RAM which can be organized into dual 16*4. The RAM can be loaded or interrogated by the CPU. Both right entry, calculator and left entry typewriter display formats are possible. Both read and write of the display RAM can be done with auto-increment of the display RAM address.

Since the 8279 is directly connected to the microprocessor, the microprocessor can program all operating modes of 8279. The various input modes of the 8279 are scanned keyboard, scanned sensor matrix and strobed input. BLOCK DIAGRAM : The block diagram of the 8279 is shown below and each block is explained.

In scanned keyboard mode, a key depression generates a 6-bit encoding of the key position. Position and shift control status are stored in the FIFO. Keys are automatically de-bounced with 2-key lockout or N-key rollover. In the scanned sensor matrix, key status is stored in RAM addressable by the microprocessor. Data on return lines during control line strobe is transferred to FIFO in strobed input. In one output mode, 8 or 16 character multiplexed displays are organized as dual 4-bit or single 8-bit and another output mode deals with right entry or left entry display formats. The keyboard interface part of 8279 continuously scans the keyboard to check if any key has been pressed. If it finds that a particular key has been pressed it sends the code of the corresponding key to the microprocessor. The microprocessor uses 8279 to send the result to the display device. In other words, we can say that 8279 controller transmits the data received from the CPU to the display device. The major advantage of using 8279 is that both of these activities are done without the intervention of the microprocessor. The keyboard can be interfaced to the

microprocessor either in the polled mode or in the interrupt mode. In the polled mode the microprocessor reads an internal flag of 8279 to check if any key has been pressed. In the interrupt mode, the processor is requested service only if a key is pressed otherwise the microprocessor can proceed with its routine activities. 8279 permits a maximum of 64 keys to be present in the keyboard. This keyboard/display controller maintains an 8-byte First in First out Random Access Memory (FIFO RAM). If the FIFO contains a valid key entry, the CPU is interrupted (in interrupt mode) or the CPU checks the status (in polling mode) to read the entry. Once the CPU reads the key, the corresponding entry is deleted from the queue to generate space for the future keys that may be pressed. The 8279 normally provides a maximum of sixteen 7 segment display interface with CPU. It contains a 16-byte display RAM that can be used either as an integrated block of 16*8 bits or two 16*4 bit blocks of RAM. The data entry to RAM block is controlled by CPU using the command words of the 8279. The I/O control section controls the flow of data to/from the 8279. The data buffers interface the external bus of the system with internal bus of 8279. The I/O section is enabled only if RD (Active Low) is low. The pins A0, RD (Active Low), WR (Active Low) select the command, status or data read/write operations carried out by the microprocessor with 8279. Timing control registers store the keyboard and display modes and other operating conditions programmed by the processor. The registers are written with A0=1 and WR (Active Low) = 0. The timing and control unit controls the basic timings for the operation of the circuit. Scan counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies. The scan counter has two modes to scan the key matrix and refresh the display. In the encoded mode, the counter provides a binary count that is to be externally decoded to provide the scan lines for keyboard and display. In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3. The keyboard and the display both are in the same mode at a time. Another set of functional components is return buffers and keyboard debounce and control. These components scan for a key closure row wise. If it is detected, the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the debounce period, if the key continues to be detected the code of the key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status. Another block present in 8279 is the FIFO sensor RAM and Status Logic. FIFO is used to handle the quick pressings of the key. Each key code of the pressed key is entered in the order of the key, and in the meantime, read by the CPU, till the RAM becomes empty. The status logic generates an interrupt request after each FIFO read operation till the FIFO is empty. In scanned sensor matrix mode, this unit acts as the sensor RAM. Each row of the sensor RAM is loaded with the status of the corresponding row of sensors in the matrix. If a sensor changes its state, the IRQ line goes high to interrupt the CPU.

The display address registers hold the address of the word currently being written or read by the CPU to or from the display RAM. The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU. The 16-byte display RAM contains the 16-bytes of data to be displayed on the sixteen 7-segment displays in the encoded scan mode.

----------xxxxxxxxxxxxxxxx-------ACKNOWLEDGEMENTS : Thanks are due to Prof.K.Udaya Kumar ,Principal ,BNM College, Bangalore , a good friend and wellwisher who inspired me in microprocessor teaching during early 90s.