Table of Contents

LIST OF FIGURES ............................................................................................................................................ 2 LIST OF TABLES .............................................................................................................................................. 3 CHAPTER-1 .................................................................................................................................................... 4 1.1 INTRODUCTION ................................................................................................................................... 4 1.2 MOTIVATION ....................................................................................................................................... 5 1.3 DRAM .................................................................................................................................................. 6 1.3.1 Operations to read a data bit from a DRAM storage cell ............................................................ 6 1.3.2 To write to memory ..................................................................................................................... 8 1.3.3 Refresh rate.................................................................................................................................. 9 1.4 SRAM ................................................................................................................................................. 10 1.4.1 Design......................................................................................................................................... 10 1.4.2 SRAM Operation ........................................................................................................................ 11 CHAPTER-2 .................................................................................................................................................. 13 2.1 SOURCES AND REDUCTION OF POWER DISSIPATION IN MEMORY SUBSYSTEM ..................... 13

2.1.2 Multi-data-bit Configuration Chip.............................................................................................. 13 2.1.2 Small Package............................................................................................................................. 15 2.1.3 Low-voltage Data-bus Interface ................................................................................................. 16 2.2 SOURCES OF POWER DISSIPATION IN DRAM AND SRAM................................................................. 18 2.2.1 Active Power Sources ................................................................................................................. 18 2.2.2 Data Retention Power Sources .................................................................................................. 21 CHAPTER-3 .................................................................................................................................................. 23 3.1 Low Power DRAM Circuits ................................................................................................................ 23 3.1.1 Active power reduction.............................................................................................................. 23 3.1.2 Operating Voltage Reduction..................................................................................................... 25 3.1.3 DC current reduction ................................................................................................................. 26 3.1.4 Data Retention Power Reduction .............................................................................................. 27 3.1.5 Refresh time extension .............................................................................................................. 27 CONCLUSION............................................................................................................................................... 28 REFERENCES ................................................................................................................................................ 29 1

LIST OF FIGURES

Fig-1.2.1 – Principle of operation of DRAM read ,for simple 4 by 4 array…………………………………………8 Fig-1.3.1-A six transistor CMOS SRAM cell……………………………………………………………………………………….11 Fig-1.3.2-Four transistors SRAM cell…………………………………………………………………………………………………11 Fig-2.1.1-subsystem using multi-bit data configuration chip……………………………………………………….….14 Fig-2.1.2-advancement in packages………………………………………………………………………………………………….16 Fig-2.1.3-Typical TTL interface………………………………………………………………………………………………………….17 Fig-2.2.1-Sources of Power dissipation in a RAM chip………………………………………………………………………19 Fig-3.1.1-Low Power circuit advancement of DRAMs over the last decade……………………………………….23 Fig-3.1.2-Multi divided data line architecture with SA , shared I/O and shared y decoder………………….24 Fig-3.1.3-Voltage down converter ……………………………………………………………………………………………………….26 Fig-3.1.4-Pulse operation of column signal path circuitry…………………………………………………………………….27

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15 Table-2.1-comparison of determinants of active cell current between DRAMs and SRAMs…………….21 3 .1.LIST OF TABLES Table-2.1.2-5V DRAM chip a package advancement…………………………………………………………………………….1-5V DRAM subsystems with 32 bit data bit bus line……………………………………………………………..2..15 Table-2.

requires the design of very high-speed circuits. in order to cope with the throughput needed in modern high-performance processing applications. Portability imposes a strict limitation on power dissipation while still demands high computational speeds. delay and power dissipation. 4 . Various low power circuit technologies concerning reductions in charging capacitance . and scenarios .CHAPTER-1 1. In any event . Recently . operating voltage and static current have been developed . The three most widely accepted metrics to measure the quality of a circuit or to compare various circuit styles are area. operating frequencies. the ever increasing market segment of portable electronic devices demands the availability of low-power building blocks that enable the implementation of long-lasting battery-operated systems. In This report I will be discussing about the sources of power dissipation and the low power circuit designs of the DRAMs and SRAMs subsystems. in recent VLSI systems the power-delay product becomes the most essential metric of performance. Energy-efficiency is one of the most required features for modern electronic systems designed for high-performance and/or portable applications. The ever decreasing supply voltage requirements could result in ultra low power and extended battery life. On the other hand. since it dominates subsystem power. Hence.1 INTRODUCTION Much of the research efforts of the past years in the area of digital electronics has been directed towards increasing the speed of digital systems. the requirement of portability and the moderate improvement in battery performance indicate that the power dissipation is one of the most critical design parameters . Thus the primary concern is for CMOS technology to realize high-speed with minimum power . RAM chip power is a primary concern of the subsystem designer . The power-delay product (PDP) metric relates the amount of energy spent during the realization of a determined task. In one hand. and stands as the more fair performance metric when comparing optimizations of a module designed and tested using different technologies. the general trend of increasing operating frequencies and circuit complexity.

Dynamic power dissipation also includes short circuit currents. ynamic power dissipation is a result of the charging and discharging of load capacitances in addition to switching transient currents.1. Dynamic power dissipation of CMOS circuits is given by- Pdyn = αCLVdd2 f where α is the node transition activity factor. subthreshold currents can contribute to static power. However. and f is the clock frequency. static power dissipation is orders of magnitude below that of dynamic (or switching) power dissipation . Thus. we can generally ignore this short circuit current compared to the current due to charging of capacitors.it is easily seen that the lowest supply voltage is desirable. 5 . Thus we must consider both power reduction along with increased delay when looking at low power esign methodologies. the minimization of power dissipation in CMOS digital circuits is achieved by reducing the components of this equation. CL is the load capacitance. Vdd is the supply voltage. This is from the reverse bias leakage between diffusion regions and the substrate. Also. Superior approaches are ones that provide more decrease in power for a given increase in delay. Since the dynamic power has a quadratic dependence on the supply voltage Vdd . Static power dissipation is caused by leakage current drawn continuously from the supply. lowering the supply voltage induces a cost of increased gate delays. In most of today’s IC designs .2 MOTIVATION In CMOS digital circuits there are two main contributors to power dissipation: dynamic and static. However.

The main memory (the "RAM") in personal computers is dynamic RAM (DRAM). 2. conventionally called 0 and 1. Unlike flash memory. it is a dynamic memory as opposed to SRAM and other static memory . This allows DRAM to reach very high densities. The bit-lines are physically symmetrical to keep the capacitance equal.3. they have enough capacitance to maintain the precharged voltage for a brief time. 1.1. The bit-lines are precharged to exactly equal voltages that are in between high and low logic levels. 4. If the storage cell's capacitor is discharged. The desired row's word-line is then driven high to connect a cell's storage capacitor to its bit-line. Since capacitors leak charge. 3. the information eventually fades unless the capacitor charges refreshed periodically. The transistors and capacitors used are extremely small .3 DRAM Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged.1 Operations to read a data bit from a DRAM storage cell 1. and therefore the voltages are equal. The precharge circuit is switched off. DRAM is volatile memory. The sense amplifiers are disconnected. Because of this refresh requirement. these two states are taken to represent the two values of a bit. This is an example of dynamic logic. since it loses its data quickly when power is removed. it will greatly decrease the voltage on the bit-line as the precharge is used to charge the storage 6 . billions can fit on a single memory chip. Because the bit-lines are relatively long. This causes the transistor to conduct. transferring charge between the storage cell and the connected bit-line. compared to four or six transistors in SRAM. The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit. It is the RAM in laptop and workstation computers as well as some of the RAM of video game consoles.

and thus overlaps with one or more column reads. A column address then selects which latch bit to connect to the external data bus. All storage cells in the open row are sensed simultaneously. This occurs because of the high capacitance of the storage cell capacitor compared to the capacitance of the bit-line. the row is "open" (the desired cell data is available). all data has already been sensed and latched. 6. Reads of different columns in the same row can be performed without a row opening delay because. The sense amplifiers are connected to the bit-lines. Positive feedback then occurs from the cross-connected inverters. current is flowing back up the bitlines from the output of the sense amplifiers and recharging the storage cells. When done with reading all the columns in the current open row. and the bit lines are precharged again.e. While reading of columns in an open row is occurring. 7. Once this has happened. 7 . The sense amplifier is switched off. thereby amplifying the small voltage difference between the odd and even row bit-lines of a particular column until one bit line is fully at the lowest voltage and the other is at the maximum high voltage. or by keeping it discharged if it was empty. thus allowing the storage cell to determine the charge level on the bit-line.capacitor. This takes significant time past the end of sense amplification. This reinforces (i. "refreshes") the charge in the storage cell by increasing the voltage in the storage capacitor if it was charged to begin with. If the storage cell is charged. and the sense amplifier outputs latched. Note that due to the length of the bit-lines there is a fairly long propagation delay for the charge to be transferred back to the cell's capacitor. 8. 5. the bit-line's voltage only decreases very slightly. for the open row. the word-line is switched off to disconnect the storage cell capacitors (the row is "closed") from the bitlines.

a row is opened and a given column's sense amplifier is temporarily forced to the desired high or low voltage state. it will hold a bit-line at stable voltage even after the forcing voltage is removed.2 To write to memory To store data.Fig 1. so although only a single column's storage-cell capacitor charge is changed. for simple 4 by 4 array 1.Principle of operation of DRAM read. During a write to a particular cell. Due to the sense amplifier's positive feedback configuration. 8 . all the columns in a row are sensed simultaneously just as during reading.3.1 . thus causing the bit-line to charge or discharge the cell storage capacitor to the desired value. the entire row is refreshed (written back in).2.

Some systems refresh every row in a burst of activity involving all rows every 64 ms. For example.3 Refresh rate Typically. All methods require some sort of counter to keep track of which row is the next to be refreshed. A few real-time systems refresh a portion of memory at a time determined by an external timer function that governs the operation of the rest of a system. such as the vertical blanking interval that occurs every 10–20 ms in video equipment. Older types require external refresh logic to hold the counter. Refresh logic is provided in a DRAM controller which automates the periodic refresh. a system with 213 = 8192 rows would require a staggered refresh rate of one row every 7.1. Other systems refresh one row at a time staggered throughout the 64 ms interval. DRAM has much greater capacity per unit of surface than SRAM. that is no software or other hardware has to perform it.Under some conditions. 9 . This makes the controller's logic circuit more complicated.8 µs which is 64 ms divided by 8192 rows.3. Most DRAM chips include that counter. manufacturers specify that each row must have its storage cell capacitors refreshed every 64 ms or less. most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes. but this drawback is outweighed by the fact that DRAM is much cheaper per storage cell and because each storage cell is very simple.

10T. This storage cell has two stable states which are used to denote 0 and 1. Memory cells that use fewer than four transistors are possible — but such 3T or 1T cells are DRAM. M3.Access to the cell is enabled by the word line which controls the two access transistors M5 and M6 which.1. not SRAM (even the socalled 1T-SRAM). Four transistor SRAM provides advantages in density at the cost of manufacturing complexity. the bit line is connected to storage capacitors and charge 10 . the smaller each cell can be. SRAM exhibits data remanence . both the signal and its inverse are typically provided in order to improve noise margins . control whether the cell should be connected to the bit lines: BL and BL. Two additional access transistors serve to control the access to a storage cell during read and write operations. 1. The term static differentiates it from dynamic RAM (DRAM) which must be periodically refreshed.4. the fewer transistors needed per cell. 8T. or more transistors per bit. Although it is not strictly necessary to have two bit lines. This is sometimes used to implement more than one (read and/or write) port. They are used to transfer data for both read and write operations. During read accesses. in turn. M2. the bit lines are actively driven high and low by the inverters in the SRAM cell. allowing for very high-resistance pull-up resistors .4 SRAM Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. Generally. The resistors must have small dimensions and large values .1 Design A typical SRAM cell is made up of six MOSFETs. Since the cost of processing a silicon wafer is relatively fixed. Four-transistor SRAM is quite common in stand-alone SRAM devices (as opposed SRAM used for CPU caches). Each bit in an SRAM is stored on four transistors(M1. which may be useful in certain types of video memory and register files implemented with multiported SRAM circuitry. In addition to such six-transistor (6T) SRAM. but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. This improves SRAM bandwidth compared to DRAMs—in a DRAM. implemented in special processes with an extra layer of polysilicon . other kinds of SRAM chips use 4T. M4) that form two cross-coupled inverters. using smaller cells and so packing more bits on one wafer reduces the cost per bit of memory.

which makes small voltage swings more easily detectable.1 . It can be in: standby (the circuit is idle). Fig 1.4. reading (the data has been requested) and writing (updating the contents). The three different states work as follows: 11 . over the same package pins in order to keep their size and cost down.A six-transistor CMOS SRAM cell.2 SRAM Operation An SRAM cell has three different states. higher bits followed by lower bits.Four transistor SRAM 1. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time.3. or 2m × n bits. Fig 1. The SRAM to operate in read mode and write mode should have "readability" and "write stability" respectively.e.sharing causes the bit line to swing upwards or downwards. The symmetric structure of SRAMs also allows for differential signaling. i. By comparison. commodity DRAMs have the address multiplexed in two halves.The size of an SRAM with m address lines and n data lines is 2m words.3.2 .

the faster the speed of read operation is. The second step occurs when the values stored in Q and Q are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M1 and M5 to a logical 0 (i. the opposite would happen and BL would be pulled toward 1and BL toward 0. A 1 is written by inverting the values of the bit lines. e. i. Note that the reason this works is that the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself. the access transistors M5 and M6 disconnect the cell from the bit lines. which will sense which line has higher voltage and thus will tell whether there was 1 stored or 0. If the content of the memory was a 0. The higher the sensitivity of sense amplifier. The two cross-coupled inverters formed by M1 – M4 will continue to reinforce each other as long as they are connected to the supply.Standby If the word line is not asserted. then asserting the word line WL. the transistors M4 and M6 pull the bit line toward VDD. we would apply a 0 to the bit lines. This is similar to applying a reset pulse to an SR-latch. eventually being charged by the transistor M4 as it is turned on because Q is logically set to 0). setting BL to 1 and BL to 0. eventually discharging through the transistor M1 as it is turned on because the Q is logically set to 1). enabling both the access transistors. Careful sizing of the transistors in an SRAM cell is needed to ensure proper operation. On the BL side. stored at Q. e. Then these BL and BL will have a small difference of delta between them and then these lines reach a sense amplifier. which causes the flip flop to change state. WL is then asserted and the value that is to be stored is latched in. Writing The start of a write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0. 12 . The read cycle is started by precharging both the bit lines to a logical 1.e. a logical 1 (i. so that they can easily override the previous state of the cross-coupled inverters. Reading Assume that the content of the memory is a 1.

Other minor sources are the capacitances of the data-bus lines .2 Multi-data-bit Configuration Chip The multi-data-bit configuration is becoming important and more favorable for power reduction .CHAPTER-2 2.With multi-data-bit configuration . for a fixed memory capacity of the subsystem . as well as design flexibility . Active chip power and AC capacitive power have both been reduced by  low – power circuits  miniaturized device technology  multi-data-bit chip configuration  small package technology  low voltage interfaces 2. They cause a heavy capacitance compared with other lines because of there inherently large values in number and capacitance .This is due to the resultant lower chip count combined with low power chip technology .1 SOURCES AND REDUCTION OF POWER DISSIPATION IN MEMORY SUBSYSTEM Major sources of active power in a modern CMOS memory subsystem are active chips . whose power is a product of the activated chip power and the number of simultaneously activated chips .1. address lines and control lines on a memory board . as chip capacity increases . Example – a 4MByte . In particular .1 . data-bus lines are of special concern . 13 . the number of chips necessary is 8 for a 4-Mb chip(1-Mword x 4-bit) and 2 for a 1-Mb chip(1-Mword x 16-bit).2. As shown in fig 2. 32-bit data bus subsystem necessitates 32 memory chips for 1 Mb chip of 1-Mword x 1 bit configuration .

K.2 .”Trends in Low-Power RAM Circuit Technologies” Proc IEEE . Sasaki and Y .1. On the contrary .Nakagome. widening data-bit width increases chip power because of resultant increase increased number of column and sense circuits . However . April 1995 In addition to increasing memory capacity of a chip .Fig 2. 14 .Itoh.1 Subsystem using multi-bit-data configuration chip Source . This arrangement dramatically reduces subsystem power with less chip count . chip power has been suppressed with low power circuits .K. drastic reduction in subpower system is achieved with less chip count resulting from multi-data-bit configuration combined with large memory capacity and low-power chip technology advancement as shown in table 2. a fixed data-bit configuration gives a disadvantages such as large power as well as design inflexibility .1.

1.Table – 2. Common I/O pin assignment in which the data input (Din)pin and the data output (Dout) pin are common enables the use of small packages by halving the number of data pins that increase with multi-data-bit configuration .1. remarkable progress in package structure accommodates ever-enlarged chips at every successive generation ina small packages.1. 15 .2 Small Package Small package technology reduces the AC capacitive power by reducing the capacitance on the memory board .1 – 5V DRAM subsystems with 32 data-bit bus lines Table 2. A typical example is the LOC (LEAD ON CHIPS) package featuring a vertical structure of chip and inner leads as shown in fig 2.1.2 – 5V DRAM chip and package advancement 2. Furthermore .2 .

AC capacitive power of each databus line in 5 V TTL (Transistor -Transistor Logic) as shown in fig 2.any read information can be read out to the data output (Dout ) pin by strobing corresponding set of column address with another clock called column address strobe ( CAS ) .3 is expressed by - P=(½)C(∆V)2f 16 .As a result all the stored information of memory calls along the selected WL are read on the corresponding data lines .3 Low-voltage Data-bus Interface Further AC power reduction has been required because the ever-increased datathroughput of memory subsystems . resulting from the rapidly improved performance of microprocessors .1.1. as shown in fig a selected word line . In traditional address – multiplexed DRAM chip .Fig 2. is activated after strobing the corresponding set of row addresses with an external clock called Row addressing strobe( RAS ). Now evaluating AC capacitive power . increases AC power .2 –advancement in packages 2.1. WL . and then amplified by the corresponding amplifiers .

∆V = VDD – VT . Fig -2. Dec 1994 17 .Small-Amplitude I/O Interface Circuits for memory bus application “IEICE Trans.where C. although it is still small portion of total power .M. increases the internal node capacitance of the chip . ∆V and f are loading capacitance . Chip power increases as the DOUT transistor enlarge according to the to high speed driving of bus capacitance . this is due to additional on. Electron . since the gate voltage of the Dout transistor is usually equals VDD . CTT(Center Tapped Termination ) and Rambus interfaces featuring small amplitude impedance matched bus lines have been proposed . It is found that AC power of an 8-Mb. voltage swing and frequency respectively.chip interface circuits while the interface power component is still low enough in high speed region .. Taguchi “High-Speed . the chip power component dominates the total power . Even for new interfaces .The Power consumption of each CTT interface is roughly expressed as – P=(IOLVOL+RTI2OL)(1 – duty)+(IOH(VDD-VOH)+RTI2OH)duty+(½)C(∆V)2f Where IOL and IOH are currents for the low signal voltage(VOL) and the high signal voltage (VOH) respectively and RT is the termination resistance .Small amplitude minimizes AC capacitance power while impedance matching allows extremely high speed transmission .32-bit data-bus-line subsystem becomes relatively large as the width of data I/O increases .1. Recently new interfaces called GTL(Gunning Transceiver Logic) .3 Typical TTL interface Source.

 decoders(row and column )  periphery . All the m cells on one word line are simultaneously activated in the logical array model .2 SOURCES OF POWER DISSIPATION IN DRAM AND SRAM 2. a 18 . An unified active power equation for modern CMOS DRAMs and SRAMs is approximately given by – P= VDDIDD IDD = miact+m(n-1)ihld+(n+m)CDEVINT+CPTVINT+IDCP where VDD is external supply voltage IDD is the current of VDD Iact is effective current of a active or selected cells Ihld is effective data retention current of inactive or non selected cell CDE is the output node capacitance of each decoder VINT is the internal supply voltage CPT is the total capacitance of the CMOS logic and the driving circuitry IDCP total static(DC) or quasi-static current of the periphery Major sources of IDCP are the column circuitry and the differential amplifiers on the input output lines .2.2.other contributors are refresh related circuits and on chip voltage converters essential to DRAM operations : these includes a substrate back-bias generator .1 Active Power Sources The chip comprises three major blocks of power sources :  memory cell array .

Hence current is expressed as 19 . a voltage up converter .Small-Amplitude I/O Interface Circuits for memory bus application “IEICE Trans. Consequently .M. Fig-2. a data line is charged with a large voltage swing of ∆VD(usually 1.voltage-down converter . Dec 1994 DRAM . Electron . a voltage reference circuit and a half VDD generator .5V) and with charging current of CD∆VD where CD is the data line capacitance . is negligible evidence by the small cell leakage current and small periphery current necessary for the refresh operation in DRAMs.1 Sources of power dissipation in a RAM chip Source.5-2.At high frequency the data retention current m(n-1) ihld .IDD increases with increasing memory capacity that is with increased m and n.2. Taguchi “High-Speed .DRAM-Destructive read-out characteristics of a DRAM cell necessitate successive operations of amplification and restoration for a selected cell on every data line ..

In SRAM ∆V D is very small(=0. the static current charge .In addition to the active current described . Eventually . A partial activation scheme of a multi divided word line reduces the DRAM current down to the SRAM level .VINT . (iii)reducing the active current(IDCP). emphasis must be placed on reduction of the total data-line dissipation charge(mCD∆VD).CPT). should differs between SRAMs and DRAMs .S/N ratio is not so serious problem in SRAM because of ratio operations .DRAMs and SRAMs have evolved to use similar circuit technology . although emphasis on each of the three issues is different between both types of RAM . The signal Vs is approximately expressed as - Vs = (Cs/CD)VDD/2 = (Cs/CD)∆VD = QS/CD Reducing CD is effective for both reducing IDD and increasing VS. despite the IDD reduction .IDD = [mCD∆VD + CPTVINT] + IDCP Key to reduce active power is – (i)reducing the charging capacitance(mCD. although it is in experimental stage . allowing the elimination of a sense amplifier on each data line . Thus the current for read operation is expressed as - IDD =[miDC∆t + CPTVINT]f + IDCP To reduce power the three key points are same as was there in DRAMs . (ii)lowering the external and internal voltages (VDD.However dissipation charge must be reduced while maintaining an acceptable S/N ratio for stable operation .1V-0. while reducing ∆VD degrades VS . miDC∆t . Since it dominates the total active power . SRAM.The non destructive read-out characteristics of SRAM never require restoration of cell data . However . In particular .∆VD) . the subthreshold DC current of a MOSFET will be a source of active power dissipation for a future 20 .3V) although it is prominent for write operation .

2.Itoh. Note that n in the logic array responds to the number of refresh cycle .”Trends in Low-Power RAM Circuit Technologies” Proc IEEE . The frequency f at which the refresh current flows is n/tREF .2 Data Retention Power Sources DRAM – In the data retention mode .1 -Comparison of determinants of active cell current between DRAMs and SRAMs Source. the subthreshold current increases exponentially with decreasing VT .K.2. a memory chip is not accessed from outside and the data are retained by the refresh operation . Table -2. dominating the total chip current . A current flows every time m cells are refreshed at the same time .The subthreshold current generated from an overwhelming large number of inactive circuits would eventually be larger than AC current from the small number of inactive circuits . The refresh operation is performed by reading data of the m cells on a word line and restoring them for each of the n word lines in order . April 1995 2. where tREF is the refresh time of the cells in the retention mode and increases with reducing junction temperature .DRAMs and SRAMs . Sasaki and Y .K. Data retention current is given by – IDD = [mCD∆VD + CPTVINT](n/ tREF) + IDCP 21 .As VT becomes small enough to no longer cut off the transistor .Nakagome.

again posing a serious concern .IDCP becomes relatively large for other AC current components because of small n/ tREF . 22 . although a full CMOS 6-T cell provides the smallest Ihld . mnIhld .This implies the necessity of reducing both AC and DC components .This is because tREFmax is for the active mode when operating the memory at the maximum frequency of around 10MHz and where cell leakage current is maximized with highest junction temperature . SRAM – In low power CMOS SRAMs . subthreshold currents from almost all circuits in DRAMs and SRAMs could drastically increase the retention current . A high resistance polysilicon load cell has been widely used for its high-density and low Ihld characteristics . For ultra – low voltage operation involving scaled VT . is the major source of retention current because of the negligibly small IDCP . In any event . the static cell leakage current .

1 Active power reduction For a given memory capacity chip .ISO and ISO .CHAPTER-3 3.The shared SA provides an almost doubled cell signal with halved CD . Electron .1 Charging Capacitance Reduction Partial activation of multi-divided data lines is widely accepted . Fig.compared with the CMOS circuit presented in 1990 ..1.M.1 Low Power DRAM Circuits 3.In this method shared I/O divides a multi-divided data line into two .1.Kb generation in 1980 .3. The drastic reduction in power by about two orders of magnitude is due to many sophisticated circuits : partial activation of a multi-divided data-line and shared I/O which reduces mCD .1 Low power circuit advancement of DRAMs over the last decade Source.1. Taguchi “High-Speed . successive circuit advancements have produced a power reduction equivalent to 2 to 3 orders of magnitude over the last decade . The partial activation is performed by activating only one sense amplifier along the data line . Fig 3. Dec 1994 3. which are selected by the isolation switches .1 shows the power dissipation of a 64-Mb DRAM . Almost the same process and device technology are assumed. 23 .1.Small-Amplitude I/O Interface Circuits for memory bus application “IEICE Trans.1. hypothetically designed with the NMOS circuit of the 64.

However .In this method shared I/O divides a multi-divided data line into two . the number of divisions was increased by simply increasing the number of Y decoders by using additional chip area . Fig 3. This Y decoder division was applied to various sense amplifier (SA) arrangement such as one SA at each division and a shared SA .Partial activation of Multi-divided Data Line – A practical solution is to divide one data line into several sections and to active only one section . this division was almost exhausted at the 16-Mb generation with the combination of shared SA . The shared SA provides an almost doubled cell signal with halved CD . The partial activation is performed by activating only one sense amplifier along the data line . Partial activation of multi-divided data lines is widely accepted .1. This resulted to preserve the busy rate expressed as – ϒ = tRCmin/(tREFmax/n) = (M/m)(tRCmin/tREFmax) 24 . tREFmax . shared I/O and shared Y decoder Refresh time increase – Reduction of m is never achieved without without the help of increasing the maximum refresh time of the cell . shared and shared Y decoder . In the early years .2 Multi divided data line architecture with SA . which are selected by the isolation switches .

respectively . This eventually provides a low power (reduced by 1/k) with higher speed and smaller chip area . Hence .Qs)and common-source drive transistors(Q6) as shown in Fig -3. 3. Half VDD Data Line Precharge Half Vdd precharge halves the data-line power of full-Vdd precharge with halved data-line voltage swing .Where trcmin and M are the minimum cycle time and memory capacity .1. Is of 2 to 3 mA enables such a fast response time . the gate voltage of Q6 . On Chip Voltage down Converter An internal voltage . for a fixed M . VG has to be respond quickly when the output goes low . it is necessary to maintain mtREFmax to keep ϒ constant assuming a fixed tRCmin . Bias current source Ib is needed to clamp the output voltage when the load current becomes almost zero . half VDD data-line-precharge which has been widely used since commercial 1Mb DRAMs are well known as contributors to low power . An amplifier currents . For accuracy and load current driving capabilities . In full VDD precharge . it consists of a current-mirror differential amplifier (Q1-Q4.2 Operating Voltage Reduction VDD reduction from 12 to 5 V at the 64-Kb generation and then to 3.2 In order tpo minimize the output voltage drop YVDP . the voltage difference difference on the data lines is amplified by applying pulse and then resultant degraded high level is restored to full – VDD precharge with halved data-line voltage swing .3 V at the 64Mb generation . reduced by scaling the same electric field . VINT .A smaller ϒ is preferred since it involves less conflicts between refresh and normal operation .1. 25 .

The DC current are shut down with pulse-operation technique . a pair of I/O lines . “Stabilization of voltage limiter circuit for high density DRAM”. the main amplifier consumes DC current for amplifying the signal . a column switch .3 shows column signal path circuitry which is a main source of static current . Also .3 – Vottage down converter Source –H. The current reductions are essential especially for multi data bit chip because of the increased number of column circuitaries . It consists of a pair of data lines . because it usually employes the conventional current mirror differential amplifier .IEICE .3 DC current reduction Fig 3. DC current flows from I/O line load to data lines while the column switch is on .1. 26 .1992 3.Tanaka.Nov.1.Fig 3.1.

Extending the refresh time and reducing refresh charge reduce the AC current component . 27 .1. 3.1. a self. substrate back bias(VBB) generator .4 Data Retention Power Reduction Reduction of both DC and AC current components in data-retention mode is a prime concern. and half-VDD generator reduces the DC current component .4 Pulse operation of column signal path circuitary 3.refresh control with an on-chip temperature detection circuit and the use of a cell-leakage monitor circuit on the chip have been proposed . voltage up(VDH)converter .Fig 3.1. Minimizing the power of on-chip voltage converters such as VDC . VREF generator.5 Refresh time extension To extend the refresh time tREF according to a reduced junction temperature in data retention mode .

We looked at the architecture level issues such as partial activation of divided word and data lines and partial activation of divided power lines. We first examined some of the previous methods in designing low power RAMs. This method can be applied to electronic design automation tools to ease the burden on industry designers. one optimize it for the minimum power loses Future work looks promising . Also we explored the pulsed operation of word line circuitry. In this report every aspect of loses have been taken care of so that while designing DRAM . 28 .CONCLUSION We have presented a methodology for low power design of DRAM memories. The development till date has been discussed in respect to DRAM and SRAM . Next we looked at some circuit issues such as current mode operation and an on-chip voltage down converter .

April 1998 29 .Nakagome.K. April 1995 [3] M.K. Dec 1994 [4] ―Tools and Methodologies for Low Power Design‖Jerry Frenkil Sente. Electron .year of publication 1996 [2] . Proc IEEE .Rabaey and Massoud Pedram springer publications . Taguchi ―High-Speed .REFERENCES [1] ―Low Power Design Methodologies‖ by Jan M..‖Trends in Low-Power RAM Circuit Technologies‖ Proc IEEE . Sasaki and Y . Inc.Small-Amplitude I/O Interface Circuits for memory bus application ―IEICE Trans.Itoh.

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