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MSP430G2x53 MSP430G2x13

www.ti.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012

MIXED SIGNAL MICROCONTROLLER
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FEATURES
Low Supply-Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 230 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations – Internal Frequencies up to 16 MHz With Four Calibrated Frequency – Internal Very-Low-Power Low-Frequency (LF) Oscillator – 32-kHz Crystal – External Digital Clock Source Two 16-Bit Timer_A With Three Capture/Compare Registers Up to 24 Touch-Sense-Enabled I/O Pins • Universal Serial Communication Interface (USCI) – Enhanced UART Supporting Auto Baudrate Detection (LIN) – IrDA Encoder and Decoder – Synchronous SPI – I2C™ On-Chip Comparator for Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion 10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sampleand-Hold, and Autoscan (See Table 1) Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse On-Chip Emulation Logic With Spy-Bi-Wire Interface Family Members are Summarized in Table 1 Package Options – TSSOP: 20 Pin, 28 Pin – PDIP: 20 Pin – QFN: 32 Pin For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide (SLAU144)

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DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs. The MSP430G2x13 and MSP430G2x53 series are ultra-low-power mixed signal microcontrollers with built-in 16bit timers, up to 24 I/O touch-sense-enabled pins, a versatile analog comparator, and built-in communication capability using the universal serial communication interface. In addition the MSP430G2x53 family members have a 10-bit analog-to-digital (A/D) converter. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2011–2012, Texas Instruments Incorporated

MSP430G2x53 MSP430G2x13
SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.ti.com

Table 1. Available Options (1) (2)
Device MSP430G2553IRHB32 MSP430G2553IPW28 MSP430G2553IPW20 MSP430G2553IN20 MSP430G2453IRHB32 MSP430G2453IPW28 MSP430G2453IPW20 MSP430G2453IN20 MSP430G2353IRHB32 MSP430G2353IPW28 MSP430G2353IPW20 MSP430G2353IN20 MSP430G2253IRHB32 MSP430G2253IPW28 MSP430G2253IPW20 MSP430G2253IN20 MSP430G2153IRHB32 MSP430G2153IPW28 MSP430G2153IPW20 MSP430G2153IN20 MSP430G2513IRHB32 MSP430G2513IPW28 MSP430G2513IPW20 MSP430G2513IN20 MSP430G2413IRHB32 MSP430G2413IPW28 MSP430G2413IPW20 MSP430G2413IN20 MSP430G2313IRHB32 MSP430G2313IPW28 MSP430G2313IPW20 MSP430G2313IN20 MSP430G2213IRHB32 MSP430G2213IPW28 MSP430G2213IPW20 MSP430G2213IN20 MSP430G2113IRHB32 MSP430G2113IPW28 MSP430G2113IPW20 MSP430G2113IN20 1 1 1 256 2x TA3 8 1 LF, DCO, VLO 1 1 2 256 2x TA3 8 1 LF, DCO, VLO 1 1 4 256 2x TA3 8 1 LF, DCO, VLO 1 1 8 512 2x TA3 8 1 LF, DCO, VLO 1 1 16 512 2x TA3 8 1 LF, DCO, VLO 1 1 1 256 2x TA3 8 8 1 LF, DCO, VLO 1 1 2 256 2x TA3 8 8 1 LF, DCO, VLO 1 1 4 256 2x TA3 8 8 1 LF, DCO, VLO 1 1 8 512 2x TA3 8 8 1 LF, DCO, VLO 1 1 16 512 2x TA3 8 8 1 LF, DCO, VLO BSL EEM Flash (KB) RAM (B) Timer_A COMP_A+ Channel ADC10 Channel USCI_A0, USCI_B0 Clock I/O 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 24 24 16 16 Package Type 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP 32-QFN 28-TSSOP 20-TSSOP 20-PDIP

(1) (2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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Copyright © 2011–2012, Texas Instruments Incorporated

MSP430G2x53 MSP430G2x13
www.ti.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012

Device Pinout, MSP430G2x13 and MSP430G2x53, 20-Pin Devices, TSSOP and PDIP

DVCC P1.0/TA0CLK/ACLK/A0/CA0 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2 P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1

1 2 3 4 5 6 7 8 9 10

20 19 18 17

N20 PW20 (TOP VIEW)

16 15 14 13 12 11

DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK P2.5/TA1.2 P2.4/TA1.2 P2.3/TA1.0

NOTE: ADC10 is available on MSP430G2x53 devices only. NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.

Device Pinout, MSP430G2x13 and MSP430G2x53, 28-Pin Devices, TSSOP

DVCC P1.0/TA0CLK/ACLK/A0/CA0 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2 P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS P3.1/TA1.0 P3.0/TA0.2 P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P3.2/TA1.1 P3.3/TA1.2

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23

PW28 (TOP VIEW)

22 21 20 19 18 17 16 15

DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK P3.7/TA1CLK/CAOUT P3.6/TA0.2 P3.5/TA0.1 P2.5/TA1.2 P2.4/TA1.2 P2.3/TA1.0 P3.4/TA0.0

NOTE: ADC10 is available on MSP430G2x53 devices only.

Copyright © 2011–2012, Texas Instruments Incorporated

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1/TA1.2 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 RHB32 (TOP VIEW) 21 20 19 18 17 TEST/SBWTCK RST/NMI/SBWTDIO P1.4/TA1.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.2/TA1.2/TA1.1 P3.3/TA1.5/TA0.2/TA0.0/TA0.0 P2.1 XOUT/P2.6/TA0.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI P1.1 P2.ti. MSP430G2x13 and MSP430G2x53.3/TA1.5/TA1.0/UCB0CLK/UCA0STE/A5/CA5/TMS P3.2 NOTE: ADC10 is available on MSP430G2x53 devices only.2 Copyright © 2011–2012.com Device Pinout.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 P1. 4 Submit Documentation Feedback P2.0/UCA0RXD/UCA0SOMI/A1/CA1 P1.2 P3. Texas Instruments Incorporated .1 P3.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK P3.7/TA1CLK/CAOUT P3.7 32 31 30 29 28 27 26 25 P1.1 P2. QFN NC P1.0 P2.2 P3.0 P2.6/TA0.1/TA1.1/UCA0TXD/UCA0SIMO/A2/CA2 P1.1/TA0. 32-Pin Devices.0/TA1.6/TA0.4/TA0.0/TA0CLK/ACLK/A0/CA0 DVCC AVCC DVSS AVSS XIN/P2.5/TA0.0 P3.

Copyright © 2011–2012. I2C NOTE: Port P3 is available on 28-pin and 32-pin devices only. Autoscan 1 ch DMA ADC Port P1 8 I/O Interrupt capability pullup/down resistors Port P2 8 I/O Interrupt capability pullup/down resistors Port P3 8 I/O pullup/ pulldown resistors 16MHz CPU incl. IrDA.MSP430G2x53 MSP430G2x13 www. IrDA.x 8 P3. I2C NOTE: Port P3 is available on 28-pin and 32-pin devices only.x 8 P3. MSP430G2x53 XIN XOUT DVCC DVSS P1. SPI USCI B0 SPI.x 8 P2. 16 Registers Emulation 2BP JTAG Interface Spy-BiWire RST/NMI Brownout Protection Comp_A+ 8 Channels Watchdog WDT+ 15-Bit Timer0_A3 3 CC Registers Timer1_A3 3 CC Registers USCI A0 UART/ LIN.x 8 ACLK Clock System MCLK SMCLK Flash RAM 16KB 8KB 4KB 2KB MAB MDB 512B 256B Port P1 8 I/O Interrupt capability pullup/down resistors Port P2 8 I/O Interrupt capability pullup/down resistors Port P3 8 I/O pullup/ pulldown resistors 16MHz CPU incl.x 8 ACLK Clock System MCLK Flash SMCLK 16KB 8KB 4KB 2KB MAB MDB RAM 512B 256B 10-Bit 8 Ch. MSP430G2x13 XIN XOUT DVCC DVSS P1.ti. Functional Block Diagram.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Functional Block Diagram. 16 Registers Emulation 2BP JTAG Interface Spy-BiWire RST/NMI Brownout Protection Comp_A+ 8 Channels Watchdog WDT+ 15-Bit Timer0_A3 3 CC Registers Timer1_A3 3 CC Registers USCI A0 UART/ LIN. Texas Instruments Incorporated Submit Documentation Feedback 5 .x 8 P2. SPI USCI B0 SPI.

0/ UCB0CLK/ UCA0STE/ A5/ CA5/ TMS 7 7 5 I/O 6 6 4 I/O 5 5 3 I/O 4 4 2 I/O 3 3 1 I/O 2 2 31 I/O PW20. output General-purpose digital I/O pin SMCLK signal output USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10 analog input A4 (1) ADC10 positive reference voltage (1) Comparator_A+. CA4 input JTAG test clock.4/ SMCLK/ UCB0STE/ UCA0CLK/ A4/ VREF+/VEREF+/ CA4/ TCK P1. input terminal for device programming and test General-purpose digital I/O pin Timer0_A. Terminal Functions TERMINAL NO.ti.0/ UCA0RXD/ UCA0SOMI/ A1/ CA1 P1.5/ TA0.3/ ADC10CLK/ A3/ VREF-/VEREF-/ CA3/ CAOUT P1. N20 PW28 RHB32 General-purpose digital I/O pin Timer0_A. input terminal for device programming and test (1) I/O DESCRIPTION (1) 6 MSP430G2x53 devices only Submit Documentation Feedback Copyright © 2011–2012. Texas Instruments Incorporated . compare: Out0 output / BSL receive USCI_B0 clock input/output USCI_A0 slave transmit enable ADC10 analog input A5 (1) Comparator_A+.2/ TA0. conversion clock output (1) ADC10 analog input A3 (1) ADC10 negative reference voltage Comparator_A+.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. CA0 input General-purpose digital I/O pin Timer0_A. CA1 input General-purpose digital I/O pin Timer0_A. capture: CCI0A input.com Table 2. capture: CCI1A input. NAME P1. compare: Out1 output USCI_A0 UART mode: transmit data output USCI_A0 SPI mode: slave data in/master out ADC10 analog input A2 (1) Comparator_A+. CA5 input JTAG test mode select. compare: Out0 output / BSL transmit USCI_A0 UART mode: receive data input USCI_A0 SPI mode: slave data out/master in ADC10 analog input A1 (1) Comparator_A+. CA3 input Comparator_A+.1/ UCA0TXD/ UCA0SIMO/ A2/ CA2 P1. CA2 input General-purpose digital I/O pin ADC10.1/ TA0. clock signal TACLK input ACLK signal output ADC10 analog input A0 (1) Comparator_A+.0/ TA0CLK/ ACLK/ A0 CA0 P1.

com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 2. compare: Out0 output General-purpose digital I/O pin Timer1_A. capture: CCI0B input.MSP430G2x53 MSP430G2x13 www. NAME P1. compare: Out1 output ADC10 analog input A6 (1) Comparator_A+. compare: Out1 output General-purpose digital I/O Timer1_A.0 P2.7 P3. CA7 input Comparator_A+. compare: Out2 output Input terminal of crystal oscillator General-purpose digital I/O pin Timer0_A. capture: CCI0A input. capture: CCI1A input.1 P2.2/ TA1.2 P3. capture: CCI1B input.1 P3.1/ TA1.0 P2. This is due to the oscillator output driver connection to this pad after reset.0/ TA1.2/ TA1.3/ TA1. Terminal Functions (continued) TERMINAL NO. compare: Out0 output General-purpose digital I/O pin Timer1_A. compare: Out1 output General-purpose digital I/O pin Timer1_A.1 P2. compare: Out2 output General-purpose digital I/O Timer0_A. capture: CCI2B input. excess current flows until P2SEL.0 P3. capture: CCI2A input.2 XIN/ P2.1 XOUT/ P2.3/ TA1.7 is cleared.0/ TA0. compare: Out0 output I/O DESCRIPTION (2) (3) TDO or TDI is selected via JTAG instruction.1/ TA1. N20 PW28 RHB32 General-purpose digital I/O pin Timer0_A. output USCI_B0 SPI mode: slave in master out USCI_B0 I2C mode: SDA I2C data JTAG test data output terminal or test data input during programming and test (2) 8 9 10 11 12 13 10 11 12 16 17 18 9 10 11 15 16 17 I/O I/O I/O I/O I/O I/O General-purpose digital I/O pin Timer1_A. CA6 input USCI_B0 SPI mode: slave out master in USCI_B0 I2C mode: SCL I2C clock JTAG test data input or test clock input during programming and test General-purpose digital I/O pin ADC10 analog input A7 (1) Comparator_A+.6/ TA0. If XOUT/P2.2 P2. Texas Instruments Incorporated .1/ A6/ CA6/ UCB0SOMI/ UCB0SCL/ TDI/TCLK P1. compare: Out2 output General-purpose digital I/O pin Timer1_A.ti.0 18 26 9 8 13 14 15 25 7 6 12 13 14 I/O I/O I/O I/O I/O I/O 19 27 26 I/O 15 23 22 I/O 14 22 21 I/O PW20. capture: CCI2A input.4/ TA1.5/ TA1. compare: Out1 output General-purpose digital I/O pin Timer1_A.7 is used as an input. Submit Documentation Feedback 7 Copyright © 2011–2012.6/ TA0. compare: Out2 output General-purpose digital I/O pin Timer1_A. compare: Out1 output Output terminal of crystal oscillator (3) General-purpose digital I/O pin General-purpose digital I/O pin Timer0_A.7/ A7/ CA7/ CAOUT/ UCB0SIMO/ UCB0SDA/ TDO/TDI P2.2 P3. compare: Out0 output General-purpose digital I/O pin Timer1_A.4/ TA0.

Spy-Bi-Wire test clock input during programming and test Analog supply voltage Digital supply voltage Ground reference Not connected QFN package pad.2 P3.5/ TA0.com Table 2. Connection to VSS is recommended.1 P3. 28 8.7/ TA1CLK/ CAOUT RST/ NMI/ SBWTDIO TEST/ 17 SBWTCK AVCC DVCC DVSS NC QFN Pad NA 1 20 NA NA NA 1 28 NA NA 29 30 27. Terminal Functions (continued) TERMINAL NO. Texas Instruments Incorporated . output Reset Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. 32 Pad NA NA NA NA NA 25 24 I 16 24 23 I 21 20 I/O PW20. I/O DESCRIPTION 8 Submit Documentation Feedback Copyright © 2011–2012.ti. N20 PW28 19 20 RHB32 18 19 I/O I/O General-purpose digital I/O Timer0_A.6/ TA0. NAME P3.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. compare: Out1 output General-purpose digital I/O Timer0_A. compare: Out2 output General-purpose digital I/O Timer1_A. clock signal TACLK input Comparator_A+. The device protection fuse is connected to TEST.

--> M(TONI) Copyright © 2011–2012.R5 CALL R8 JNE OPERATION R4 + R5 ---> R5 PC -->(TOS). Four of the registers. D = destination S ✓ ✓ ✓ ✓ ✓ ✓ ✓ D ✓ ✓ ✓ ✓ SYNTAX MOV Rs. are dedicated as program counter. source-destination Single operands. All operations. and constant generator. Texas Instruments Incorporated Submit Documentation Feedback 9 .--> M(TONI) M(MEM) -. Table 3.MSP430G2x53 MSP430G2x13 www. Table 4 shows the address modes.--> M(Tab+R6) M(R10) -.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application.--> R11 M(2+R5) -. The register-toregister operation execution time is one cycle of the CPU clock.--> M(TCDAT) M(R10) -. address.&TCDAT MOV @Rn.TONI MOV @R10.--> R10 #45 -.Tab(R6) MOV @R10+.6(R6) OPERATION R10 -. R0 to R3. and can be handled with all instructions.R11 MOV #45. Each instruction can operate on word and byte data.Rm MOV #X. Each instruction can operate on word and byte data. The remaining registers are general-purpose registers. un/conditional EXAMPLE ADD R4. Address Mode Descriptions (1) ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate (1) S = source. destination only Relative jump.Rd MOV X(Rn). Table 3 shows examples of the three types of instruction formats. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Instruction Set The instruction set consists of 51 instructions with three formats and seven address modes.ti.TONI EXAMPLE MOV R10. stack pointer. R8--> PC Jump-on-equal bit = 0 Table 4. and control buses. are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. other than program-flow instructions. respectively.Y(Rm) MOV @Rn+.--> R11 R10 + 2-.Y(Rm) MOV EDE. The CPU is integrated with 16 registers that provide reduced instruction execution time. status register. Instruction Word Formats INSTRUCTION FORMAT Dual operands.TONI MOV &MEM. Peripherals are connected to the CPU using data.R11 MOV 2(R5).--> M(6+R6) M(EDE) -. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range.

and restore back to the low-power mode on return from the interrupt program. MCLK is disabled – DCO's dc generator is disabled if DCO not used in active mode • Low-power mode 2 (LPM2) – CPU is disabled – MCLK and SMCLK are disabled – DCO's dc generator remains enabled – ACLK remains active • Low-power mode 3 (LPM3) – CPU is disabled – MCLK and SMCLK are disabled – DCO's dc generator is disabled – ACLK remains active • Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK and SMCLK are disabled – DCO's dc generator is disabled – Crystal oscillator is stopped 10 Submit Documentation Feedback Copyright © 2011–2012. MCLK is disabled • Low-power mode 1 (LPM1) – CPU is disabled – ACLK and SMCLK remain active.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.com Operating Modes The MSP430 has one active mode and five software selectable low-power modes of operation. Texas Instruments Incorporated . An interrupt event can wake up the device from any of the low-power modes.ti. service the request. The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active • Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active.

In I2C mode: UCB0RXIFG.0 to P2IFG. Flags. the CPU goes into LPM4 immediately after power-up. flash is not programmed). If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example. In SPI mode: UCB0RXIFG. Interrupt Sources. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. Texas Instruments Incorporated Submit Documentation Feedback 11 . In I2C mode: UCALIFG. highest (non)-maskable (non)-maskable (non)-maskable maskable maskable maskable maskable (4) 0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 to 0. UCSTPIFG.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. ICSTTIFG. Multiple source flags (non)-maskable: the individual interrupt-enable bit can disable an interrupt event. In UART or SPI mode: UCB0TXIFG. UCB0TXIFG ADC10IFG (4) (2) (6) P2IFG. Interrupt flags are located in the module. Copyright © 2011–2012.MSP430G2x53 MSP430G2x13 www.0 to P1IFG. UCNACKIFG. TAIFG (2) (4) CAIFG (4) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh 31. A zero (0h) disables the erasure of the flash if an invalid password is supplied. Table 5.7 (2) (4) See See (1) (2) (3) (4) (5) (6) (7) (8) (7) (8) 0FFDEh 0FFDEh to 0FFC0h A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges. UCB0TXIFG. but the general interrupt enable cannot. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary. TAIFG UCA0RXIFG. and Vectors INTERRUPT SOURCE Power-Up External Reset Watchdog Timer+ Flash key violation PC out-of-range (1) NMI Oscillator fault Flash memory access violation Timer1_A3 Timer1_A3 Comparator_A+ Watchdog Timer+ Timer0_A3 Timer0_A3 USCI_A0/USCI_B0 receive USCI_B0 I2C status USCI_A0/USCI_B0 transmit USCI_B0 I2C receive/transmit ADC10 (MSP430G2x53 only) I/O Port P2 (up to eight flags) I/O Port P1 (up to eight flags) INTERRUPT FLAG PORIFG RSTIFG WDTIFG KEYV (2) NMIIFG OFIFG ACCVIFG (2) (3) TA1CCR0 CCIFG (4) TA1CCR2 TA1CCR1 CCIFG.ti.7 (2) (4) maskable maskable 0FFE6h 0FFE4h 0FFE2h 0FFE0h P1IFG. UCB0RXIFG (2) (5) UCA0TXIFG. lowest WDTIFG TA0CCR0 CCIFG (5) (4) maskable maskable maskable maskable maskable TA0CCR2 TA0CCR1 CCIFG.

MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.1): Bit can be read and written.1: rw-(0. Bit can be read and written. Inactive if watchdog mode is selected. Interrupt Flag Register 1 and 2 Address 02h 7 6 5 4 NMIIFG rw-0 WDTIFG OFIFG PORIFG RSTIFG NMIIFG Address 03h 3 RSTIFG rw-(0) 2 PORIFG rw-(1) 1 OFIFG rw-1 0 WDTIFG rw-(0) Set on watchdog timer overflow (in watchdog mode) or security key violation. Simple software access is provided with this arrangement. Flag set on oscillator fault.ti. It is reset or set by POR.com Special Function Registers (SFRs) Most interrupt and module enable bits are collected into the lowest address space. Power-On Reset interrupt flag. Interrupt Enable Register 1 and 2 Address 00h 7 6 5 ACCVIE rw-0 WDTIE OFIE NMIIE ACCVIE Address 01h 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0 Watchdog Timer interrupt enable. Legend rw: rw-0. Set via RST/NMI pin 7 6 5 4 3 UCB0TXIFG rw-1 2 UCB0RXIFG rw-0 1 UCA0TXIFG rw-1 0 UCA0RXIFG rw-0 UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG USCI_A0 receive interrupt flag USCI_A0 transmit interrupt flag USCI_B0 receive interrupt flag USCI_B0 transmit interrupt flag 12 Submit Documentation Feedback Copyright © 2011–2012. Special function register bits not allocated to a functional purpose are not physically present in the device. External reset interrupt flag. Table 6. Set on VCC power-up. Reset on VCC power-up. Texas Instruments Incorporated . It is reset or set by PUC. Bit can be read and written. Active if Watchdog Timer is configured in interval timer mode. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. SFR bit is not present in device. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable 7 6 5 4 3 UCB0TXIE rw-0 2 UCB0RXIE rw-0 1 UCA0TXIE rw-0 0 UCA0RXIE rw-0 UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE USCI_A0 receive interrupt enable USCI_A0 transmit interrupt enable USCI_B0 receive interrupt enable USCI_B0 transmit interrupt enable Table 7. Set on a reset condition at RST/NMI pin in reset mode.

Segments A to D are also called information memory. Access to the MSP430 memory via the BSL is protected by user-defined password.ti.1 7 .5 Flash Memory The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. BSL Function Pins BSL FUNCTION Data transmit Data receive 20-PIN PW PACKAGE 20-PIN N PACKAGE 3 . • Segments A to D can be erased individually or as a group with segments 0 to n.P1.P1. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. Each segment in main memory is 512 bytes in size.P1. Texas Instruments Incorporated Submit Documentation Feedback 13 . Memory Organization MSP430G2153 MSP430G2113 Memory Main: interrupt vector Main: code memory Information memory Size Flash Flash Size Flash RAM Size 1kB 0xFFFF to 0xFFC0 0xFFFF to 0xFC00 256 Byte 010FFh to 01000h 256 Byte 0x02FF to 0x0200 Peripherals 16-bit 8-bit 8-bit SFR 01FFh to 0100h 0FFh to 010h 0Fh to 00h MSP430G2253 MSP430G2213 2kB 0xFFFF to 0xFFC0 0xFFFF to 0xF800 256 Byte 010FFh to 01000h 256 Byte 0x02FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h MSP430G2353 MSP430G2313 4kB 0xFFFF to 0xFFC0 0xFFFF to 0xF000 256 Byte 010FFh to 01000h 256 Byte 0x02FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h MSP430G2453 MSP430G2413 8kB 0xFFFF to 0xFFC0 0xFFFF to 0xE000 256 Byte 010FFh to 01000h 512 Byte 0x03FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h MSP430G2553 MSP430G2513 16kB 0xFFFF to 0xFFC0 0xFFFF to 0xC000 256 Byte 010FFh to 01000h 512 Byte 0x03FF to 0x0200 01FFh to 0100h 0FFh to 010h 0Fh to 00h Bootstrap Loader (BSL) The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface.5 28-PIN PACKAGE PW 3 . For complete description of the features of the BSL and its implementation.1 5 . The CPU can perform single-byte and single-word writes to the flash memory.1 7 .P1.MSP430G2x53 MSP430G2x13 www. • Segments 0 to n may be erased in one step. Copyright © 2011–2012. see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319). or each segment may be individually erased.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Memory Organization Table 8. After reset segment A is protected against programming and erasing.P1.5 32-PIN PACKAGE RHB 1 . Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each.P1. Table 9. • Segment A contains calibration data.

sourced either from a 32768-Hz watch crystal or the internal LF oscillator.DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL. Main DCO Characteristics • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1. Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. • Main clock (MCLK). Texas Instruments Incorporated .DCO) × fDCO(RSEL..ti.DCO) is used for the remaining cycles. an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A. • DCO control bits DCOx have a step size as defined by parameter SDCO. the system clock used by the CPU. The basic clock module provides the following clock signals: • Auxiliary clock (ACLK). For complete module descriptions.DCO+1) MOD × fDCO(RSEL. The frequency is an average equal to: faverage = 32 × fDCO(RSEL. . • Modulation control bits MODx select how often fDCO(RSEL.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. • Sub-Main clock (SMCLK). RSELx = 14 overlaps RSELx = 15.DCO+1) 14 Submit Documentation Feedback Copyright © 2011–2012..DCO) + (32 – MOD) × fDCO(RSEL. see the MSP430x2xx Family User's Guide (SLAU144). the sub-system clock used by the peripheral modules. address. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs.com Peripherals Peripherals are connected to the CPU through data. and control buses and can be handled using all instructions.

TA = 30°C REF2_5 = 0. • Each I/O has an individually programmable pullup or pulldown resistor.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Calibration Data Stored in Information Memory Segment A Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure. WDT+ Watchdog Timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. Tags Used by the ADC Calibration Tags NAME TAG_DCO_30 TAG_ADC10_1 TAG_EMPTY ADDRESS 0x10F6 0x10DA VALUE 0x01 0x10 0xFE ADC10_1 calibration tag Identifier for empty memory areas DESCRIPTION DCO frequency calibration at VCC = 3 V and TA = 30°C at calibration Table 11. • Each I/O has an individually programmable pin oscillator enable bit to enable low-cost touch sensing. Labels Used by the ADC Calibration Tags LABEL CAL_ADC_25T85 CAL_ADC_25T30 CAL_ADC_25VREF_FACTOR CAL_ADC_15T85 CAL_ADC_15T30 CAL_ADC_15VREF_FACTOR CAL_ADC_OFFSET CAL_ADC_GAIN_FACTOR CAL_BC1_1MHZ CAL_DCO_1MHZ CAL_BC1_8MHZ CAL_DCO_8MHZ CAL_BC1_12MHZ CAL_DCO_12MHZ CAL_BC1_16MHZ CAL_DCO_16MHZ ADDRESS OFFSET 0x0010 0x000E 0x000C 0x000A 0x0008 0x0006 0x0004 0x0002 0x0009 0x0008 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 SIZE word word word word word word word word byte byte byte byte byte byte byte byte CONDITION AT CALIBRATION / DESCRIPTION INCHx = 0x1010. IVREF+ = 1 mA INCHx = 0x1010. If the selected time interval expires. TA = 30°C. TA = 85°C INCHx = 0x1010.ti. TA = 30°C. fADC10CLK = 5 MHz External VREF = 1. Copyright © 2011–2012. TA = 30°C REF2_5 = 1. • Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available). output.MSP430G2x53 MSP430G2x13 www. REF2_5 = 0. Texas Instruments Incorporated Submit Documentation Feedback 15 . REF2_5 = 1. REF2_5 = 0.5 mA External VREF = 1.5 V. • Any combination of input. IVREF+ = 0. If the watchdog function is not needed in an application. and interrupt condition (port P1 and port P2 only) is possible. Digital I/O Up to three 8-bit I/O ports are implemented: • All individual I/O bits are independently programmable. fADC10CLK = 5 MHz - Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. Table 10.5 V. the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. REF2_5 = 1. • Read/write access to port-control registers is supported by all instructions. TA = 85°C INCHx = 0x1010. a system reset is generated.

3-14 P2.2-2 TA0. N20 P1.4-12 P2.0-8 P2. Timer1_A3 Signal Connections INPUT PIN NUMBER PW20.6-22 P2.2 TA0.2-12 CCR0 TA0 P2.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. and interval timing.2-12 P3.6-21 P2.5-18 P3.3-15 P3. PWM outputs.7-21 P2.2-2 P1.0-7 PinOsc TA0.6-27 P3.1-10 P2.0 TA1.7-21 RHB32 P3.7-20 P2.3-11 P3. Texas Instruments Incorporated .2-12 P2.1 VSS VCC P2.0 ACLK VSS VCC P1.0-7 P3. Table 12. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.2-10 P2.1-11 P2.2 VSS VCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 CCR1 TA1 P1.0-8 P2.5-18 P2.1-8 P2.0-10 P2.2 VSS VCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 P2.4-17 P2.5-13 P2.4-16 P2. Timer_A3 can support multiple capture/compares. N20 PW28 P3.4-14 Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER PW20.2-13 P2.7-20 DEVICE INPUT SIGNAL TACLK ACLK SMCLK P2.5-13 P2.0-9 P2.1-1 TACLK TA0.1-10 P2.3-16 P3.0-2 RHB32 P1.5-19 P3.0-10 P2.1-1 P1.2-4 P1. Timer0_A3 Signal Connections INPUT PIN NUMBER PW20.3-13 CCR1 TA1 P2.5-17 TA1.2 TA1.3-11 P2.0-31 DEVICE INPUT SIGNAL TACLK ACLK SMCLK PinOsc P1.1-3 PinOsc P1.ti.2-11 P3.0-9 P3.0-9 PinOsc PinOsc P3. TA1) Timer0/1_A3 is a 16-bit timer/counter with three capture/compare registers.4-15 P1. Timer_A3 also has extensive interrupt capabilities.4-17 P2.4-12 P2.2-10 P2.2-4 P1.5-18 P3.1 CAOUT VSS VCC P3.1-3 P1.1-3 PinOsc P1.6-20 P1.com Timer_A3 (TA0.2-11 TA1.1-9 P2.5-7 P1.1-9 P2.2-4 P1.1-3 P1.0 VSS VCC P2.6-26 P3.5-5 P3. N20 PW28 RHB32 Table 13.3-12 TACLK TA1.1-11 P2.5-17 P3.6-19 P1.6-19 CCR0 TA0 P1.0-9 P2. N20 PW28 RHB32 16 Submit Documentation Feedback Copyright © 2011–2012.3-16 P3.2-4 P1.6-14 P2.1-6 Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER PW20.5-7 P3.0-2 PW28 P1.4-16 P2.1 TA1.

sample select control. Not all packages support the USCI functionality. allowing ADC samples to be converted and stored without any CPU intervention. The module implements a 10-bit SAR core. USCI_B0 provides support for SPI (3 or 4 pin) and I2C. enhanced UART.MSP430G2x53 MSP430G2x13 www. and IrDA.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Universal Serial Communications Interface (USCI) The USCI module is used for serial data communication. and monitoring of external analog signals. reference generator. Copyright © 2011–2012. enhanced UART with automatic baudrate detection (LIN). The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C. and asynchronous communication protocols such as UART. and IrDA. Comparator_A+ The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions. Texas Instruments Incorporated Submit Documentation Feedback 17 . ADC10 (MSP430G2x53 Only) The ADC10 module supports fast 10-bit analog-to-digital conversions. battery-voltage supervision.ti. USCI_A0 provides support for SPI (3 or 4 pin). and data transfer controller (DTC) for automatic conversion result handling. UART.

MSP430G2x53 MSP430G2x13
SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.ti.com

Peripheral File Map Table 14. Peripherals With Word Access
MODULE ADC10 (MSP430G2x53 devices only) REGISTER DESCRIPTION ADC data transfer start address ADC memory ADC control register 1 ADC control register 0 Timer1_A3 Capture/compare register Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Timer0_A3 Capture/compare register Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Flash Memory Flash control 3 Flash control 2 Flash control 1 Watchdog Timer+ Watchdog/timer control REGISTER NAME ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 TA1CCR2 TA1CCR1 TA1CCR0 TA1R TA1CCTL2 TA1CCTL1 TA1CCTL0 TA1CTL TA1IV TA0CCR2 TA0CCR1 TA0CCR0 TA0R TA0CCTL2 TA0CCTL1 TA0CCTL0 TA0CTL TA0IV FCTL3 FCTL2 FCTL1 WDTCTL OFFSET 1BCh 1B4h 1B2h 1B0h 0196h 0194h 0192h 0190h 0186h 0184h 0182h 0180h 011Eh 0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh 012Ch 012Ah 0128h 0120h

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MSP430G2x53 MSP430G2x13
www.ti.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012

Table 15. Peripherals With Byte Access
MODULE USCI_B0 REGISTER DESCRIPTION USCI_B0 transmit buffer USCI_B0 receive buffer USCI_B0 status USCI B0 I2C Interrupt enable USCI_B0 bit rate control 1 USCI_B0 bit rate control 0 USCI_B0 control 1 USCI_B0 control 0 USCI_B0 I2C slave address USCI_B0 I2C own address USCI_A0 USCI_A0 transmit buffer USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_A0 auto baud rate control ADC10 (MSP430G2x53 devices only) ADC analog enable 0 ADC analog enable 1 ADC data transfer control register 1 ADC data transfer control register 0 Comparator_A+ Comparator_A+ port disable Comparator_A+ control 2 Comparator_A+ control 1 Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control Port P3 (28-pin PW and 32-pin RHB only) Port P3 selection 2. pin Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 Port P2 selection 2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input
Copyright © 2011–2012, Texas Instruments Incorporated

REGISTER NAME UCB0TXBUF UCB0RXBUF UCB0STAT UCB0CIE UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCB0SA UCB0OA UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCTL UCA0ABCTL ADC10AE0 ADC10AE1 ADC10DTC1 ADC10DTC0 CAPD CACTL2 CACTL1 BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL P3SEL2 P3REN P3SEL P3DIR P3OUT P3IN P2SEL2 P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN

OFFSET 06Fh 06Eh 06Dh 06Ch 06Bh 06Ah 069h 068h 011Ah 0118h 067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh 04Ah 04Bh 049h 048h 05Bh 05Ah 059h 053h 058h 057h 056h 043h 010h 01Bh 01Ah 019h 018h 042h 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 19

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Table 15. Peripherals With Byte Access (continued)
MODULE Port P1 REGISTER DESCRIPTION Port P1 selection 2 Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 REGISTER NAME P1SEL2 P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN IFG2 IFG1 IE2 IE1 OFFSET 041h 027h 026h 025h 024h 023h 022h 021h 020h 003h 002h 001h 000h

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8 V.6 V V °C UNIT The MSP430 CPU is clocked directly with MCLK. Recommended Operating Conditions MIN During program execution VCC VSS TA Supply voltage Supply voltage Operating free-air temperature I version VCC = 1. Safe Operating Area Copyright © 2011–2012. Flash program or erase operations require a minimum VCC of 2.ti. during flash memory programming 12 MHz Supply voltage range . Texas Instruments Incorporated Submit Documentation Feedback 21 .com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin (2) Diode current at any device pin Storage temperature range. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.3 V ±2 mA Unprogrammed device Programmed device –55°C to 150°C –55°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Figure 1. The JTAG fuse-blow voltage.2 V Supply Voltage . The voltage is applied to the TEST pin when blowing the JTAG fuse. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency.8 2. Modules might have a different maximum input clock specification. during program execution 6 MHz 1.6 3.3 V to 4. VFB.V 3. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied.MSP430G2x53 MSP430G2x13 www.8 V 2.3 V 3. Tstg (1) (2) (3) (3) –0.MHz Supply voltage range . Duty cycle = 50% ± 10% (1) (2) –40 dc dc dc During flash programming or erase 1.7 V. See the specification of the respective module in this data sheet. Duty cycle = 50% ± 10% fSYSTEM Processor frequency (maximum MCLK frequency) (1) (2) VCC = 2.3 V. These are stress ratings only.2 0 85 6 12 16 MHz NOM MAX 3. All voltages referenced to VSS.6 V Note: Minimum processor frequency is defined by system clock. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Duty cycle = 50% ± 10% VCC = 3.2 V.3 V to VCC + 0.7 V 2.1 V –0. is allowed to exceed the absolute maximum rating. Legend : 16 MHz System Frequency .

fACLK = 0 Hz.0 f DCO = 8 MHz f DCO = 1 MHz 1.0 4. OSCOFF = 0 TA VCC 2.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.0 8. The internal and external load capacitance is chosen to closely match the required 9 pF. CPUOFF = 0.2 V MIN TYP 230 µA MAX UNIT IAM.0 1. Typical Characteristics. Outputs do not source or sink any current.5 3. Active Mode Current vs DCO Frequency 22 Submit Documentation Feedback Copyright © 2011–2012.0 VCC = 2.ti.0 2.0 3.0 16. Active Mode Supply Current (Into VCC) 5.2 V 0.0 0. Texas Instruments Incorporated .0 f DCO = 12 MHz 2.0 0.0 VCC = 3 V TA = 85 °C TA = 25 °C 1. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.0 2. DCOCTL = CALDCO_1MHZ. Program executes in flash.0 VCC − Supply Voltage − V f DCO − DCO Frequency − MHz Figure 2.0 4.0 TA = 85 °C TA = 25 °C 3.5 4.1MHz Active mode (AM) current at 1 MHz 3V 330 420 (1) (2) All inputs are tied to 0 V or to VCC. Active Mode Current vs VCC. BCSCTL1 = CALBC1_1MHZ. SCG0 = 0. TA = 25°C Figure 3.0 12.5 2.0 4. SCG1 = 0.0 Active Mode Current − mA f DCO = 16 MHz Active Mode Current − mA 3.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS fDCO = fMCLK = fSMCLK = 1 MHz.

Texas Instruments Incorporated Submit Documentation Feedback 23 . CPUOFF = 1. SCG1 = 0.25 2.1MHz Low-power mode 0 (LPM0) current (3) 25°C 2. Current for brownout included.50 1.MSP430G2x53 MSP430G2x13 www. Outputs do not source or sink any current. fACLK = 0 Hz. BCSCTL1 = CALBC1_1MHZ.7 0.8 V Vcc = 2.25 0. CPUOFF = 1.LFXT1 Low-power mode 3 (LPM3) current (4) 25°C 2.1 0. CPUOFF = 1.75 2. OSCOFF = 0 fMCLK = fSMCLK = 0 MHz.00 0.5 0. SCG1 = 1. fACLK = 32768 Hz.75 0.8 µA (1) (2) (3) (4) (5) All inputs are tied to 0 V or to VCC. Current for brownout and WDT clocked by ACLK included.50 2.5 1. OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz.25 0.75 1. OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz. fDCO = 1 MHz. SCG1 = 1.2 V 0. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. SCG0 = 1. fACLK from internal LF oscillator (VLO).2 V 22 µA ILPM3. CPUOFF = 1. DCOCTL = CALDCO_1MHZ. SCG1 = 1.50 ILPM3 – Low-Power Mode Current – µA 2.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS fMCLK = 0 MHz.25 1. CPUOFF = 1.50 0. SCG0 = 0.2 V 0. SCG1 = 1. DCOCTL = CALDCO_1MHZ.50 0.25 2. fSMCLK = fDCO = 1 MHz.ti.00 1. LPM4 Current vs Temperature Copyright © 2011–2012.00 2.2 V 60 80 TA – Temperature – °C TA – Temperature – °C Figure 4.2 V 56 µA ILPM2 Low-power mode 2 (LPM2) current (4) 25°C 2.7 µA ILPM4 Low-power mode 4 (LPM4) current (5) 2. OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz.5 µA ILPM3.8 V -20 0 20 40 60 80 Vcc = 3.00 1.6 V Vcc = 3 V Vcc = 2.00 -40 -20 0 20 40 Vcc = 1.00 -40 Vcc = 1. OSCOFF = 1 TA VCC MIN (2) TYP MAX UNIT ILPM0.50 1. Typical Characteristics.7 1. LPM3 Current vs Temperature Figure 5.2 V 0.00 0.75 0. fACLK = 32768 Hz. SCG0 = 0. SCG0 = 1. Current for brownout and WDT clocked by SMCLK included. BCSCTL1 = CALBC1_1MHZ.2 V Vcc = 3. (LPM3) (4) 25°C 25°C 85°C 2. fACLK = 32768 Hz.VLO Low-power mode 3 current. The internal and external load capacitance is chosen to closely match the required 9 pF.75 1. SCG0 = 1. Low-Power Mode Supply Currents over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 3.25 Vcc = 3 V 1.6 V ILPM4 – Low-Power Mode Current – µA 2.

unless otherwise noted.65 1 50 UNIT V V V kΩ pF Leakage Current.25 0. I(OHmax) and I(OLmax). CL = 20 pF. RL = 1 kΩ Px. Texas Instruments Incorporated .45 VCC 1. Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ VIT– Vhys RPull CI Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ – VIT–) Pullup/pulldown resistor Input capacitance For pullup: VIN = VSS For pulldown: VIN = VCC VIN = VSS or VCC TEST CONDITIONS VCC 3V 3V 3V 3V MIN 0.3 VSS + 0.35 0. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.ti.25 VCC 0.y) (1) (2) High-impedance leakage current (1) (2) TEST CONDITIONS VCC 3V MIN MAX ±50 UNIT nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s). Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fPx. Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL (1) High-level output voltage Low-level output voltage TEST CONDITIONS I(OHmax) = –6 mA (1) I(OLmax) = 6 mA (1) VCC 3V 3V MIN TYP VCC – 0. The output is connected to the center tap of the divider.3 20 35 5 TYP MAX 0.y. for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. The port pin is selected for input and the pullup/pulldown resistor is disabled.75 VCC 2. CL = 20 pF (2) (1) (2) VCC 3V 3V MIN TYP 12 16 MAX UNIT MHz MHz A resistive divider with two 0. The leakage of the digital port pins is measured individually.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.3 MAX UNIT V V The maximum total current.5-kΩ resistors between VCC and VSS is used as load. 24 Submit Documentation Feedback Copyright © 2011–2012.55 VCC 1.y fPort_CLK (1) (2) Port output frequency (with load) Clock output frequency TEST CONDITIONS Px. Output Frequency. Outputs.y. Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.com Schmitt-Trigger Inputs.75 0.

TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE −10 −20 −15 TA = 85°C −20 −30 TA = 85°C −40 TA = 25°C −50 0 0. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 I OH − Typical High-Level Output Current − mA I OH − Typical High-Level Output Current − mA VCC = 2.5 2 2.5 2 2.2 V P1.7 −10 Figure 7.7 −5 0 VCC = 3 V P1.5 2 2. Texas Instruments Incorporated Submit Documentation Feedback 25 .2 V P1. Figure 9.5 −25 0 TA = 25°C 0.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Typical Characteristics.5 1 1.7 40 TA = 85°C 30 TA = 25°C TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 20 15 20 10 5 10 0 0 0.5 2 2.5 1 1.5 VOL − Low-Level Output Voltage − V 0 0 0.7 25 TA = 85°C TA = 25°C 50 VCC = 3 V P1.5 1 1.MSP430G2x53 MSP430G2x13 www.ti.5 3 3. Copyright © 2011–2012.5 3 3. Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 30 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA VCC = 2.5 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V Figure 8.5 VOL − Low-Level Output Voltage − V Figure 6.5 1 1.

RL = 100 kΩ (1) (2) P2. One output active at a time.60 0.50 fosc − Typical Oscillation Frequency − MHz 1.y..00 10 50 100 CLOAD − External Capacitance − pF P1. Typical Characteristics. RL = 100 kΩ (1) (2) P2.50 1. P2.y.6/7 foP3. RL = 100 kΩ P3. P2.7 VCC = 2.0 to P2.7.90 0.20 1.45 0.7 fosc − Typical Oscillation Frequency − MHz VCC = 3.20 1. A. Texas Instruments Incorporated .6 and P2. Figure 10. RL = 100 kΩ (1) (2) P3.. CL = 20 pF. P2. One output active at a time.0 to P2.05 0.75 0.0 ..00 10 50 100 CLOAD − External Capacitance − pF P1..x foP2.30 0. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.x foP2. Figure 11.2 V TYPICAL OSCILLATING FREQUENCY vs LOAD CAPACITANCE A. RL = 100 kΩ (1) (2) (1) (2) 3V 3V A resistive divider with two 0.5. The output is connected to the center tap of the divider.6.5.75 0.5-kΩ resistors between VCC and VSS is used as load.5 P2. RL = 100 kΩ (1) (2) VCC 3V MIN TYP 1400 900 1800 1000 700 1800 1000 MAX UNIT kHz kHz kHz kHz P1.60 0.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.15 0. Pin-Oscillator Frequency TYPICAL OSCILLATING FREQUENCY vs LOAD CAPACITANCE 1. CL = 20 pF.y. CL = 10 pF. 26 Submit Documentation Feedback Copyright © 2011–2012. P2.0 V 1.y P2.5 P2.com Pin-Oscillator Frequency – Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER foP1.ti. RL = 100 kΩ (1) (2) P2. CL = 20 pF.y.90 0. CL = 20 pF. CL = 10 pF.45 0.35 1. CL = 10 pF.05 0.30 0.35 1.x (1) (2) Port output oscillation frequency Port output oscillation frequency Port output oscillation frequency Port output oscillation frequency TEST CONDITIONS P1.0 .y P2.15 0.6.

The voltage level V(B_IT–) + Vhys(B_IT–)is ≤ 1. POR/Brownout Reset (BOR) vs Supply Voltage Copyright © 2011–2012.2 V 2 TEST CONDITIONS dVCC/dt ≤ 3 V/s dVCC/dt ≤ 3 V/s dVCC/dt ≤ 3 V/s VCC MIN TYP 0.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 POR/Brownout Reset (BOR) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(start) V(B_IT–) Vhys(B_IT–) td(BOR) t(reset) (1) See Figure 12 See Figure 12 through Figure 14 See Figure 12 See Figure 12 Pulse length needed at RST/NMI pin to accepted reset internally 2.7 × V(B_IT--) 1.8 V. Texas Instruments Incorporated Submit Documentation Feedback 27 .35 140 2000 MAX UNIT V V mV µs µs The current consumption of the brownout module is already included in the ICC current consumption data.MSP430G2x53 MSP430G2x13 www. VCC Vhys(B_IT−) V(B_IT−) VCC(start) 1 0 t d(BOR) Figure 12.ti.

001 t f = tr 1 t pw − Pulse Width − µs 1000 tf tr Typical Conditions 3V t pw t pw − Pulse Width − µs Figure 14.5 1 VCC(drop) 0.ti. POR/Brownout Reset (BOR) 2 VCC = 3 V Typical Conditions VCC(drop) − V 1.5 0 0. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 VCC = 3 V VCC(drop) − V 1. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal 28 Submit Documentation Feedback Copyright © 2011–2012.5 0 0.001 VCC(drop) VCC 3V t pw 1 t pw − Pulse Width − µs 1000 1 ns 1 ns t pw − Pulse Width − µs Figure 13.com Typical Characteristics.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. Texas Instruments Incorporated .5 1 0.

2 3 0. DCOx = 3. MODx = 0 RSELx = 3.08 50 7. MODx = 0 RSELx = 15.3) fDCO(15.3) fDCO(12.14 0.3) fDCO(14.3) fDCO(5. Texas Instruments Incorporated Submit Documentation Feedback 29 .80 1.3) fDCO(10. DCOx = 3. MODx = 0 RSELx = 13.3 3. DCOx = 3. MODx = 0 RSELx = 0.3) fDCO(11.3) fDCO(3.8 0.3) fDCO(2. MODx = 0 RSELx = 10.DCO) Measured at SMCLK output 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 4. 3) DCO frequency (3. DCOx = 3.21 0.7) SRSEL SDCO Supply voltage DCO frequency (0. 3) DCO frequency (11.41 0. MODx = 0 RSELx = 14.06 0.17 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ratio ratio % V UNIT Copyright © 2011–2012. MODx = 0 RSELx = 12.30 9. MODx = 0 RSELx = 6. 3) DCO frequency (1. 3) DCO frequency (10.35 1. MODx = 0 RSELx = 15. DCOx = 3. DCOx = 0.6 0. DCOx = 3.DCO)/fDCO(RSEL. 0) DCO frequency (0.9 18.0 16.3) fDCO(8.0 1.15 0. 3) DCO frequency (6. 3) DCO frequency (12.0) fDCO(0.3) fDCO(13.00 8.DCO+1)/fDCO(RSEL.3) fDCO(7.50 TYP MAX 3. MODx = 0 RSELx = 8. DCOx = 3.07 0.8 2.25 7. 3) DCO frequency (14. 3) DCO frequency (4.60 13. DCOx = 3. MODx = 0 RSELx = 9.3) fDCO(1.30 6.ti.0 TEST CONDITIONS VCC MIN 1. DCOx = 3.DCO) SDCO = fDCO(RSEL. 3) DCO frequency (15.MSP430G2x53 MSP430G2x13 www. 3) DCO frequency (9. 3) DCO frequency (15. DCOx = 3.3) fDCO(15. MODx = 0 RSELx = 2. MODx = 0 RSELx = 7.6 2.58 1. DCOx = 3. DCOx = 7.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER RSELx < 14 VCC fDCO(0. 7) Frequency step between range RSEL and RSEL+1 Frequency step between tap DCO and DCO+1 Duty cycle RSELx = 14 RSELx = 15 RSELx = 0.6 3. DCOx = 3.5 26. DCOx = 3. 3) DCO frequency (2. 3) DCO frequency (13. DCOx = 3.3) fDCO(9. MODx = 0 RSELx = 1. 3) DCO frequency (8. DCOx = 3. 3) DCO frequency (5.60 12. 3) DCO frequency (7.6 3.30 0.3) fDCO(6.4 4. DCOx = 3.54 0. MODx = 0 SRSEL = fDCO(RSEL+1. MODx = 0 RSELx = 5. MODx = 0 RSELx = 4. MODx = 0 RSELx = 11.3) fDCO(4.06 1.

DCOCTL = CALDCO_16MHZ.5 +3 % 30°C 2.7 V to 3.com Calibrated DCO Frequencies.ti.6 V -3 ±2 +3 % 1-MHz tolerance overall 8-MHz tolerance over temperature (1) 8-MHz tolerance over VCC -40°C to 85°C 1. DCOCTL = CALDCO_1MHZ.2 V to 3.3 V to 3. DCOCTL = CALDCO_8MHZ.5 +3 % 30°C 2. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_8MHZ. DCOCTL = CALDCO_12MHZ. DCOCTL = CALDCO_16MHZ.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. DCOCTL = CALDCO_8MHZ.6 V -6 ±3 +6 % 0°C to 85°C 3V -3 ±0. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_1MHZ.6 V -6 ±3 +6 % 0°C to 85°C 3V -3 ±0. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_16MHZ. DCOCTL = CALDCO_1MHZ.8 V to 3.5 MAX +3 UNIT % 30°C 1. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_1MHZ. DCOCTL = CALDCO_16MHZ. DCOCTL = CALDCO_8MHZ. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_16MHZ.2 V to 3. DCOCTL = CALDCO_1MHZ.6 V -6 ±3 +6 % This is the frequency change from the measured frequency at 30°C over temperature. Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER 1-MHz tolerance over temperature (1) 1-MHz tolerance over VCC TEST CONDITIONS BCSCTL1 = CALBC1_1MHZ.6 V -3 ±2 +3 % 8-MHz tolerance overall 12-MHz tolerance over temperature (1) 12-MHz tolerance over VCC -40°C to 85°C 2. DCOCTL = CALDCO_12MHZ.7 V to 3. Texas Instruments Incorporated . calibrated at 30°C and 3 V BCSCTL1 = CALBC1_8MHZ.8 V to 3. calibrated at 30°C and 3 V TA 0°C to 85°C VCC 3V MIN -3 TYP ±0. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_8MHZ.3 V to 3. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_12MHZ.6 V -6 ±3 +6 % 0°C to 85°C 3V -3 ±0. 30 Submit Documentation Feedback Copyright © 2011–2012.6 V -3 ±2 +3 % 16-MHz tolerance overall (1) -40°C to 85°C 3. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_12MHZ. DCOCTL = CALDCO_12MHZ.5 +3 % 30°C 3.6 V -3 ±2 +3 % 12-MHz tolerance overall 16-MHz tolerance over temperature (1) 16-MHz tolerance over VCC -40°C to 85°C 2. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_16MHZ. calibrated at 30°C and 3 V BCSCTL1 = CALBC1_12MHZ.

DCOCTL = CALDCO_1MHz VCC 3V MIN TYP 1.15 0.ti. DCO Clock Wake-Up Time From LPM3/4 10.00 RSELx = 12.LPM3/4 (1) (2) DCO clock wake-up time from LPM3/4 (1) CPU wake-up time from LPM3/4 (2) TEST CONDITIONS BCSCTL1 = CALBC1_1MHz. Texas Instruments Incorporated Submit Documentation Feedback 31 .LPM3/4 tCPU..g..00 DCO Wake Time − µs RSELx = 0. DCO Wake-Up Time From LPM3 vs DCO Frequency Copyright © 2011–2012.LPM3/4 MAX UNIT µs The DCO clock wake-up time is measured from the edge of an external wake-up signal (e. Parameter applicable only if DCOCLK is used for MCLK..10 1. port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK).com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tDCO.5 1/fMCLK + tClock.00 DCO Frequency − MHz 10.11 1...MSP430G2x53 MSP430G2x13 www. Typical Characteristics.00 Figure 15.10 0.

cap Timer_A input clock frequency Timer_A capture timing TEST CONDITIONS SMCLK. LFXT1Sx = 0. Includes parasitic bond and package capacitance (approximately 2 pF per pin). XCAPx = 0.5 11 2.8 V to 3.com Crystal Oscillator. LF mode 0. XT1. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fVLO dfVLO/dT VLO frequency VLO frequency temperature drift TA -40°C to 85°C -40°C to 85°C 25°C VCC 3V 3V 1. LFXT1Sx = 0. LF mode XTS = 0. LFXT1Sx = 3 LF mode Oscillation allowance for LF crystals XTS = 0. duty cycle = 50% ± 10% TA0.6 V 10000 MIN TYP 32768 32768 500 kΩ 200 1 5.eff = 6 pF XTS = 0. fLFXT1.8 V to 3.2 V 2.8 V to 3. XCAPx = 1 XTS = 0. Since the PCB adds additional capacitance. LFXT1Sx = 3 (4) OALF CL. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. XCAPx = 3 Duty cycle. it is recommended to verify the correct load by measuring the ACLK frequency. XCAPx = 2 XTS = 0. Measured at P2.5 8.6 V 1.eff = 12 pF XTS = 0. LFXT1Sx = 0 or 1 VCC 1. XTS = 0. fLFXT1.0/ACLK.6 V MIN 4 TYP 12 0. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. Frequencies above the MAX specification do not set the fault flag. This signal is no longer required for the serial programming adapter. 1 TEST CONDITIONS XTS = 0. the effective load capacitance should always match the specification of the used crystal.LF = 32768 Hz XTS = 0.LF. (b) Design a good ground plane around the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. ensure that it does not induce capacitive/resistive leakage between the oscillator pins.LF fLFXT1. the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. TA1 3V 20 VCC MIN TYP fSYSTEM MAX UNIT MHz ns 32 Submit Documentation Feedback Copyright © 2011–2012.LF = 32768 Hz. CL. CL. (f) If conformal coating is used. Frequencies in between might set the flag. LF mode (3) (2) (3) (4) To improve EMI on the XT1 oscillator. XCAPx = 0 XTS = 0. fLFXT1. LF mode (2) fFault.2 V 30 10 50 70 10000 % Hz pF 50000 MAX UNIT Hz Hz LFXT1 oscillator logic level square wave input frequency. Frequencies below the MIN specification set the fault flag.eff Integrated effective load capacitance. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. Texas Instruments Incorporated .5 4 MAX 20 UNIT kHz %/°C %/V dfVLO/dVCC VLO frequency supply voltage drift Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fTA tTA.LF = 32768 Hz. XCAPx = 0. Measured with logic-level input frequency but also applies to operation with crystals.ti. Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fLFXT1.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. For a correct setup.LF (1) Oscillator fault frequency.logic LFXT1 oscillator crystal frequency.

BITCLK tτ (1) (2) USCI input clock frequency Maximum BITCLK clock frequency (equals baudrate in MBaud) (1) UART receive deglitch time (2) TEST CONDITIONS SMCLK. their duration should exceed the maximum specification of the deglitch time. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized. CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU. duty cycle = 50% ± 10% VCC 3V 3V 3V MIN 75 0 TYP MAX fSYSTEM UNIT MHz ns ns 20 ns Figure 16. CL = 20 pF 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU.MI Figure 17.MI SOMI tHD.MI tHD.MO tVALID.MSP430G2x53 MSP430G2x13 www.MI SOMI tHD. SPI Master Mode. Texas Instruments Incorporated Submit Documentation Feedback 33 .com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI fmax. duty cycle = 50% ± 10% 3V 3V 2 50 100 600 VCC MIN TYP fSYSTEM MAX UNIT MHz MHz ns The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.MO SIMO tHD.MO tVALID.MO SIMO TEST CONDITIONS SMCLK.MO USCI input clock frequency SOMI input data setup time SOMI input data hold time SIMO output data valid time UCLK edge to SIMO valid. SPI Master Mode. CKPH = 1 Copyright © 2011–2012.ti. USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16 and Figure 17) PARAMETER fUSCI tSU.MI tHD.MI tVALID.

SI tSU. CL = 20 pF 3V tSTE.SI tHD.com USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18 and Figure 19) PARAMETER tSTE.SI SIMO tHD. CKPH = 0 tSTE.ACC SOMI tHD. STE low to SOMI data out STE disable time. STE high to SOMI high impedance SIMO input data setup time SIMO input data hold time SOMI output data valid time tSTE. Texas Instruments Incorporated .SO tSTE.DIS Figure 18.DIS tSU.ACC SOMI tSTE. SPI Slave Mode. Last clock to STE high STE access time.DIS Figure 19.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.LAG ns tSTE. STE low to clock STE lag time.ti.SO tVALID.SO STE lead time.LAG tSTE.SI tHD.LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD. CKPH = 1 34 Submit Documentation Feedback Copyright © 2011–2012.LAG tSTE.LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU.LEAD tSTE.SI tVALID.MO tVALID. SPI Slave Mode.SI SIMO tSTE.SO TEST CONDITIONS VCC 3V 3V 3V 3V 3V 3V MIN 10 TYP 50 50 50 MAX UNIT ns ns ns ns ns ns 15 10 50 75 UCLK edge to SOMI valid.ACC tSTE.

25 VCC node) / VCC (Voltage at 0. CAREF = 1.DAT tSU. Without filter: CAF = 0 TA = 25°C.7 120 VCC-1 V mV mV mV ns µs Input hysteresis Response time (low-high and high-low) 3V t(response) 3V 1. CARSEL = 1. CAREF = 0 CAON = 1.STO Figure 20. Overdrive 10 mV. CAREF = 2. CARSEL = 0.5 (1) (2) The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.5 VCC node) / VCC See Figure 21 and Figure 22 Offset voltage (2) CAON = 1 PCA0 = 1.STA tSU.STA SDA tLOW SCL tHIGH tSP tSU. or 3. The two successive measurements are then summed together.DAT tSU.0 0. Texas Instruments Incorporated Submit Documentation Feedback 35 .STA tHD. Overdrive 10 mV.ti. TA = 85°C CAON = 1 TA = 25°C.24 0.DAT tSU.DAT tHD.48 490 ±10 0. Copyright © 2011–2012. No load at CA0 and CA1.STA tHD.MSP430G2x53 MSP430G2x13 www. CAREF = 3. I2C Mode Timing Comparator_A+ over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER I(DD) (1) I(Refladder/ RefDiode) TEST CONDITIONS CAON = 1.7 0.STO tSP USCI input clock frequency SCL clock frequency Hold time (repeated) START Setup time for a repeated START Data hold time Data setup time Setup time for STOP Pulse width of spikes suppressed by input filter tHD. duty cycle = 50% ± 10% VCC 3V MIN 0 4.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20) PARAMETER fUSCI fSCL tHD. No load at CA0 and CA1 PCA0 = 1.STA TEST CONDITIONS SMCLK.6 4.y) specification. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. CARSEL = 0. No load at CA0 and CA1 PCA0 = 1. CAREF = 1. CARSEL = 1. CARSEL = 1. With filter: CAF = 1 0 0. No load at CA0 and CA1 VCC 3V 3V 3V 3V 3V 3V 3V MIN TYP 45 45 MAX UNIT µA µA V(IC) V(Ref025) V(Ref050) V(RefVT) V(offset) Vhys Common–mode input voltage (Voltage at 0. 2.0 50 TYP MAX fSYSTEM 400 UNIT MHz kHz µs µs ns ns µs fSCL ≤ 100 kHz fSCL > 100 kHz fSCL ≤ 100 kHz fSCL > 100 kHz 3V 3V 3V 3V 3V 3V 100 600 ns tBUF tSU.6 0 250 4.

2 V Short Resistance – kW VCC = 1.4 0. V(RefVT) vs Temperature. V(RefVT) vs Temperature.8 1 VIN/VCC – Normalized Input Voltage – V/V Figure 23.8 V VCC = 2.6 0.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. Short Resistance vs VIN/VCC 36 Submit Documentation Feedback Copyright © 2011–2012. Texas Instruments Incorporated .ti.com Typical Characteristics – Comparator_A+ 650 VCC = 3 V V(RefVT) – Reference Voltage – mV 650 VCC = 2.2 0.2 V V(RefVT) – Reference Voltage – mV 600 Typical 550 600 Typical 550 500 500 450 450 400 -45 -25 -5 15 35 55 75 TA – Free-Air Temperature – °C 95 115 400 -45 -25 -5 15 35 55 75 TA – Free-Air Temperature – °C 95 115 Figure 21. VCC = 2.6 V 1 0 0.2 V 10 VCC = 3 V VCC = 3. VCC = 3 V 100 Figure 22.

unless a conversion is active. Reference buffer supply ADC10ON = 0.0 fADC10CLK = 5. The REFON bit enables the built-in reference to settle before starting an A/D conversion. current with ADC10SR = 1 (4) REF2_5V = 0. REFON = 1.25 25°C 3V 0. ADC10ON = 1.1 mA IREFB. ADC10ON = 0. REFON = 0. ADC10SHT1 = 0. Power Supply and Input Range Conditions (MSP430G2x53 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER VCC VAx Analog supply voltage Analog input voltage (2) TEST CONDITIONS VSS = 0 V All Ax terminals.MSP430G2x53 MSP430G2x13 www. REFOUT = 1. ADC10SHT0 = 1. REF2_5V = 1.5 mA CI RI (1) (2) (3) (4) 25°C 25°C 3V 3V 1000 27 pF Ω The leakage current is defined in the leakage current table with Px.2 TYP MAX 3. ADC10ON = 0. REFON = 1. Consumption is independent of the ADC10ON control bit.0 MHz. current with ADC10SR = 0 (4) REF2_5V = 0. The internal reference supply current is not included in current consumption parameter IADC10.25 mA IREF+ Reference supply current.6 VCC UNIT V V 3V 0 IADC10 ADC10 supply current (3) 25°C 3V 0.6 mA 0.0 MHz.0 MHz.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 10-Bit ADC.0 MHz. Analog inputs selected in ADC10AE register fADC10CLK = 5. ADC10SR = 0 fADC10CLK = 5. REFOUT = 0 fADC10CLK = 5. REFOUT = 0 TA VCC MIN 2. REFON = 1. reference buffer disabled (4) IREFB. Reference buffer supply ADC10ON = 0.1 25°C 3V 0. REFOUT = 1. REF2_5V = 0. Copyright © 2011–2012. ADC10DIV = 0 fADC10CLK = 5. The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.0 MHz.y/Ax parameter. ADC10SR = 1 Input capacitance Input MUX ON resistance Only one terminal Ax can be selected at one time 0 V ≤ VAx ≤ VCC 25°C 3V 1. The internal reference current is supplied via terminal VCC. Texas Instruments Incorporated Submit Documentation Feedback 37 . REFON = 1.ti.

VREF+ TEST CONDITIONS VCC MIN 2.65 ±1 ±2 3V ±2 LSB TYP MAX UNIT V V mA IVREF+ ≤ 1 mA. ADC10SR = 0 1. Analog input voltage VAx ≉ 0.9% VREF 3V 400 ns 3V 3V 3. REFON = 1.5 × VREF+.5 2.ti.com 10-Bit ADC. REF2_5V = 0 IVREF+ ≤ IVREF+max.5 mA.5 1. REF2_5V = 1. VAx ≉ 0. REF2_5V = 1 Positive built-in reference voltage Maximum VREF+ load current IVREF+ ≤ IVREF+max. REFOUT = 1 IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA IVREF+ = 0. REF2_5V = 1 IVREF+ = 100 µA→900 µA. Error of conversion result ≤ 1 LSB.REF+ VREF+ ILD.9 3V 3V IVREF+ = 500 µA ± 100 µA.5 mA. REFON = 0 → 1 IVREF+ = 0.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.6 V 100 ±100 30 pF ppm/ °C µs tREFBURST (1) 3V 2 µs Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)) 38 Submit Documentation Feedback Copyright © 2011–2012. ADC10SR = 0 IVREF+ ≤ ±1 mA. Built-In Voltage Reference (MSP430G2x53 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC. REF2_5V = 0 IVREF+ = 500 µA ± 100 µA.25 V. REFBURST = 1.35 1. REF2_5V = 1 VREF+ load regulation VREF+ load regulation response time CVREF+ TCREF+ tREFON Maximum capacitance at pin VREF+ Temperature coefficient (1) Settling time of internal reference voltage to 99. REF2_5V = 0 Positive built-in reference analog supply voltage range IVREF+ ≤ 1 mA. Analog input voltage VAx ≉ 1.2 2.9% VREF Settling time of reference buffer to 99.59 2. REFON = 1.41 2. REF2_5V = 0.75 V. Texas Instruments Incorporated .

5 6. The reference and input signal are already settled. Texas Instruments Incorporated Submit Documentation Feedback 39 .06 13 × ADC10DIV × 1/fADC10CLK 100 TYP MAX 6.51 µs UNIT MHz MHz ADC10DIVx = 0. fADC10CLK = fADC10OSC tCONVERT Conversion time fADC10CLK from ACLK. CI.5 LSB.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 10-Bit ADC.45 3. SREF0 = 1 (3) VEREF+ > VEREF– VEREF+ > VEREF– (5) VCC MIN 1. Higher reference voltage levels may be applied with reduced accuracy requirements. The reference buffer is active and requires the reference buffer supply current IREFB. The accuracy limits the minimum positive external reference voltage. The current consumption can be limited to the sample and conversion period with REBURST = 1. SREF1 = 1. SREF0 = 0 VEREF– ≤ VEREF+ ≤ VCC – 0. MCLK.15 V. 10-Bit ADC. Lower differential reference voltage levels may be applied with reduced accuracy requirements.4 0 1. The input capacitance. 10-Bit ADC. ADC10SSELx = 0. SREF1 = 1.ti.MSP430G2x53 MSP430G2x13 www. SREF0 = 1 (3) 0 V ≤ VEREF– ≤ VCC 3V IVEREF– (1) (2) (3) (4) (5) Static input current into VEREF– The external reference is used during conversion to charge and discharge the capacitance array. The accuracy limits the minimum external differential reference voltage. Timing Parameters (MSP430G2x53 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fADC10CLK fADC10OSC ADC10 input clock frequency ADC10 built-in oscillator frequency TEST CONDITIONS For specified performance of ADC10 linearity parameters ADC10SR = 0 ADC10SR = 1 VCC 3V 3V 3V MIN 0.2 VCC ±1 µA 3V 3V 0 ±1 µA V V VEREF– ΔVEREF IVEREF+ Static input current into VEREF+ 0 V ≤ VEREF+ ≤ VCC.3 1.1 ±2 MIN TYP MAX ±1 ±1 ±1 ±2 ±5 UNIT LSB LSB LSB LSB LSB Copyright © 2011–2012. is also the dynamic load for an external reference during conversion. or SMCLK: ADC10SSELx ≠ 0 (1) tADC10ON (1) Turn-on settling time of the ADC ns The condition is that the error in a conversion started after tADC10ON is less than ±0.45 0. ΔVEREF = VEREF+ – VEREF– TEST CONDITIONS VEREF+ > VEREF–.15 V ≤ 3 V. Linearity Parameters (MSP430G2x53 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER EI ED EO EG ET Integral linearity error Differential linearity error Offset error Gain error Total unadjusted error Source impedance RS < 100 Ω TEST CONDITIONS VCC 3V 3V 3V 3V 3V ±1. Lower reference voltage levels may be applied with reduced accuracy requirements. SREF1 = 1. Under this condition the external reference is internally buffered. External Reference (1) (MSP430G2x53 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Positive external reference input voltage range (2) Negative external reference input voltage range (4) Differential external reference input voltage range. fADC10CLK = fADC10OSC ADC10 built-in oscillator. SREF0 = 0 0 V ≤ VEREF+ ≤ VCC – 0. The accuracy limits the maximum negative external reference voltage. SREF1 = 1. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.4 TYP MAX VCC UNIT VEREF+ V 3 1. ADC10SSELx = 0.4 1.3 3.7 2.

When REFON = 0.sensor [mV] or VSensor.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV] The typical equivalent impedance of the sensor is 51 kΩ. Error of conversion result ≤ 1 LSB 30 (4) µA V ns 1.2 V/3.6 V 20 104 100 1 1 5 7 10 105 30 25 18 6 10593 4819 tBlock. VMID ≉ 0.5 × VCC ADC10ON = 1. no additional on time is needed. INCHx = 0Bh ADC10ON = 1. 40 Submit Documentation Feedback Copyright © 2011–2012.2 V/3.typ = TCSensor (273 + T [°C] ) + VOffset. Texas Instruments Incorporated .2 V/3.55 MAX UNIT µA mV/°C µs ADC10ON = 1. ISENSOR is included in IREF+.ti.6 V 2. This parameter applies to all programming methods: individual word/byte write and block write modes. ISENSOR applies during conversion of the temperature sensor input (INCH = 0Ah). INCHx = 0Bh. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG). Temperature Sensor and Built-In VMID (MSP430G2x53 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ISENSOR TCSENSOR tSensor(sample) IVMID VMID tVMID(sample) (1) (2) Sample time required if channel 10 is selected (3) Current into divider at channel 11 VCC divider at channel 11 Sample time required if channel 11 is selected (5) Temperature sensor supply current (1) TEST CONDITIONS REFON = 0. 1-63 tBlock. 0 TEST CONDITIONS VCC MIN 2. The following formula can be used to calculate the temperature sensor output voltage: VSensor. INCHx = 0Ah (2) VCC 3V 3V 3V 3V 3V 3V MIN TYP 60 3. INCHx = 0Bh. When REFON = 1. The on-time tVMID(on) is included in the sampling time tVMID(sample).5 1220 (3) (4) (5) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). INCHx = 0Ah. Error of conversion result ≤ 1 LSB ADC10ON = 1.com 10-Bit ADC.2 257 TYP MAX 3.2 V/3. TA = 25°C ADC10ON = 1. The VMID is used during sampling. The sample time required includes the sensor-on time tSENSOR(on).6 V 2.6 V 2. No additional current is needed.6 476 UNIT V kHz mA mA ms ms cycles years tFTG tFTG tFTG tFTG tFTG tFTG Program and erase supply voltage Flash timing generator frequency Supply current from VCC during program Supply current from VCC during erase Cumulative program time (1) Cumulative mass erase time Program/erase endurance Data retention duration Word or byte program time Block program time for first byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Segment erase time TJ = 25°C (2) (2) (2) (2) (2) (2) 2. Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(PGM/ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock. End tMass Erase tSeg Erase (1) (2) The cumulative program time must not be exceeded when writing to a 64-byte flash block. INCHx = 0Ah.

JTAG Fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(FB) VFB IFB tFB (1) Supply voltage during fuse-blow condition Voltage level on TEST for fuse blow Supply current into TEST during fuse blow Time to blow fuse TEST CONDITIONS TA = 25°C MIN 2. and JTAG is switched to bypass mode. fTCK may be restricted to meet the timing requirements of the module selected.2 V 2.6 MAX UNIT V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. Spy-Bi-Wire. no further access to the JTAG/Test.5 6 7 100 1 MAX UNIT V V mA ms Once the fuse is blown. Texas Instruments Incorporated Submit Documentation Feedback 41 .ti. Copyright © 2011–2012.2 V 2.Low tSBW.MSP430G2x53 MSP430G2x13 www.En tSBW.2 V 2.En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage (1) TEST CONDITIONS CPU halted MIN 1.2 V 2.025 TYP MAX 20 15 1 100 5 90 UNIT MHz µs µs µs MHz kΩ Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW. JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fSBW tSBW.2 V 2. and emulation feature is possible.2 V 15 0 25 60 MIN 0 0.Ret fTCK RInternal (1) (2) Spy-Bi-Wire input frequency Spy-Bi-Wire low clock pulse duration Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) Spy-Bi-Wire return to normal operation time TCK input frequency (2) Internal pulldown resistance on TEST TEST CONDITIONS VCC 2. No program execution should happen during this supply voltage condition.

y From Timer 0 TAx.y PxOUT.y PxSEL.com PORT SCHEMATICS Port P1 Pin Schematic: P1.ti.y 1 0 1 2 3 Direction 0: Input 1: Output 0 1 0 1 DVSS DVCC 0 1 2 Bus Keeper EN 0 1 1 PxSEL2.y From Timer 1 From USCI PxSEL2. MSP430G2x13 devices have no ADC10.y PxIES.y PxSEL.0 to P1.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.0/UCA0RXD/ UCA0SOMI/A1*/CA1 P1.1/UCA0TXD/ UCA0SIMO/A2*/CA2 EN To Module D PxIE. 42 Submit Documentation Feedback Copyright © 2011–2012.y PxSEL.1/TA0.y Interrupt Edge Select EN Set * Note: MSP430G2x53 devices only.y TAxCLK PxIN.y * PxSEL2.2/TA0.y or ADC10AE0.0/TA0CLK/ACLK/ A0*/CA0 P1.2.y Q PxIFG.y PxREN.y PxIRQ.y PxDIR.y 3 P1. Input/Output With Schmitt Trigger To Comparator From Comparator To ADC10 * INCHx = y * CAPD. Texas Instruments Incorporated .y PxSEL.

x=1 (2) 0 0 0 1 (y = 0) 0 0 0 0 0 0 0 1 (y = 1) 0 0 0 0 0 0 0 1 (y = 2) 0 0 CAPD.0/ UCA0RXD/ UCA0SOMI/ A1 (2)/ CA1/ Pin Osc P1.CCI1A 2 UCA0TXD UCA0SIMO A2 CA2 Capacitive sensing FUNCTION P1DIR. Port P1 (P1.0/ TA0CLK/ ACLK/ A0 / CA0/ Pin Osc P1.0 to P1.TACLK 0 ACLK A0 CA0 Capacitive sensing P1.1/ TA0.x (I/O) TA0.CCI0A 1 UCA0RXD UCA0SOMI A1 CA1 Capacitive sensing P1. O: 1 0 1 X X X I: 0. Texas Instruments Incorporated Submit Documentation Feedback 43 .y 0 0 0 0 1 (y = 0) 0 0 0 0 0 0 0 1 (y = 1) 0 0 0 0 0 0 0 1 (y = 2) 0 X = don't care MSP430G2x53 devices only Copyright © 2011–2012.x INCH.0 TA0.x (I/O) TA0. O: 1 1 0 from USCI from USCI X X X P1SEL.MSP430G2x53 MSP430G2x13 www.x 0 0 0 X X 1 0 0 0 1 1 X X 1 0 0 0 1 1 X X 1 ADC10AE.x 0 1 1 X X 0 0 1 1 1 1 X X 0 0 1 1 1 1 X X 0 P1SEL2. O: 1 1 0 from USCI from USCI X X X I: 0.2) Pin Functions PIN NAME (P1.2/ TA0.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 16.ti.1 TA0.x) P1.x (I/O) TA0.1/ UCA0TXD/ UCA0SIMO/ A2 (2)/ CA2/ Pin Osc (1) (2) (2) CONTROL BITS AND SIGNALS (1) x P1.x I: 0.

y PxSEL.3. MSP430G2x13 devices have no ADC10.y PxSEL.y 0.y PxIN.ti.y TAxCLK 3 Bus Keeper EN P1.3 1 Direction 0: Input 1: Output PxSEL2.y PxREN. 44 Submit Documentation Feedback Copyright © 2011–2012.com Port P1 Pin Schematic: P1.y 1 0 1 0 1 DVSS DVCC PxOUT.y PxIRQ.2.* To Comparator from Comparator To ADC10 * INCHx = y * CAPD.y From ADC10 * 0 1 2 From Comparator TAx.y or ADC10AE0. Texas Instruments Incorporated . Input/Output With Schmitt Trigger SREF2 * To ADC10 VREF.y EN To Module D PxIE.y 0 1 VSS PxSEL2.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.y PxSEL.3/ADC10CLK*/CAOUT/ A3*/VREF-*/VEREF-*/CA3 0 1 1 PxSEL2.y Q PxIFG.y PxIES.y Interrupt Edge Select EN Set * Note: MSP430G2x53 devices only.y PxSEL.y * PxDIR.

(2)/ VEREF.MSP430G2x53 MSP430G2x13 www. O: 1 1 1 X X X X X P1SEL.3) Pin Functions PIN NAME (P1.x (I/O) ADC10CLK CAOUT 3 A3 VREFVEREFCA3 Capacitive sensing FUNCTION P1DIR.x=1 (2) 0 0 0 1 (y = 3) 1 1 0 0 CAPD.x) P1.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 17.x I: 0.x INCH.(2)/ CA3/ Pin Osc (1) (2) (2) CONTROL BITS AND SIGNALS (1) x P1.y 0 0 0 0 0 0 1 (y = 3) 0 X = don't care MSP430G2x53 devices only Copyright © 2011–2012. Texas Instruments Incorporated Submit Documentation Feedback 45 . Port P1 (P1.3/ ADC10CLK (2)/ CAOUT/ A3 / VREF.ti.x 0 0 1 X X X X 1 ADC10AE.x 0 1 1 X X X X 0 P1SEL2.

y PxIFG.y SMCLK From Module TAx. 46 Submit Documentation Feedback Copyright © 2011–2012.y TAxCLK PxIN. Input/Output With Schmitt Trigger From/To ADC10 Ref+ * To Comparator from Comparator To ADC10 * INCHx = y * CAPD.y PxOUT.y PxSEL.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.y PxSEL.y PxIES.y PxIRQ.y * PxDIR.y PxREN.y EN To Module D PxIE. Texas Instruments Incorporated .ti.4.com Port P1 Pin Schematic: P1.y 1 0 1 0 1 DVSS DVCC 0 1 2 3 Bus Keeper EN P1.y PxSEL.y PxSEL.y 0 1 Direction 0: Input 1: Output PxSEL2.y or ADC10AE0.4/SMCLK/UCB0STE/UCA0CLK/ A4*/VREF+*/VEREF+*/CA4/TCK 0 1 1 PxSEL2. MSP430G2x12 devices have no ADC10.y From JTAG To JTAG Interrupt Edge Select EN Q Set * Note: MSP430G2x52 devices only.

O: 1 1 from USCI from USCI X X X X X X P1SEL.ti.x 0 0 1 1 X X X X X 1 ADC10AE.4) Pin Functions PIN NAME (P1.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 18. Texas Instruments Incorporated Submit Documentation Feedback 47 .4/ SMCLK/ UCB0STE/ UCA0CLK/ VREF+ (2)/ VEREF+ (2)/ A4 / CA4 TCK/ Pin Osc (1) (2) (2) CONTROL BITS AND SIGNALS (1) x FUNCTION P1.x INCH.y 0 0 0 0 0 0 0 1 (y = 4) 0 0 X = don't care MSP430G2x53 devices only Copyright © 2011–2012.x (I/O) SMCLK UCB0STE UCA0CLK VREF+ 4 VEREF+ A4 CA4 TCK Capacitive sensing P1DIR.x 0 1 1 1 X X X X X 0 P1SEL2.MSP430G2x53 MSP430G2x13 www.x) P1.x I: 0.x=1 (2) 0 0 0 0 1 1 1 (y = 4) 0 0 0 JTAG Mode 0 0 0 0 0 0 0 0 1 0 CAPD. Port P1 (P1.

MSP430G2x13 devices have no ADC10.y PxIFG.y 1 0 1 0 1 DVSS DVCC 0 1 1 PxSEL2.6/TA0.y * PxSEL2.y ADC10AE0.7/CAOUT/UCB0SIMO/UCB0SDA/ A7*/CA7/TDO/TDI 48 Submit Documentation Feedback Copyright © 2011–2012.y PxDIR.y PxSEL. Texas Instruments Incorporated .y From JTAG To JTAG * Note: MSP430G2x53 devices only.y PxIES. Input/Output With Schmitt Trigger To Comparator From Comparator To ADC10 * INCHx = y * CAPD.0/UCB0CLK/UCA0STE/ A5*/CA5/TMS P1.y PxIRQ.y From Module 0 1 2 3 Direction 0: Input 1: Output From Module PxSEL2.y PxREN.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.ti.y TAxCLK PxIN.y From Module From Module 0 1 2 3 Bus Keeper EN TAx.y EN To Module D PxIE.y PxSEL.1/UCB0SOMI/UCB0SCL/ A6*/CA6/TDI/TCLK P1.5 to P1.y PxSEL.5/TA0.y PxSEL. Q EN Set Interrupt Edge Select P1.com Port P1 Pin Schematic: P1.y PxOUT.7.

MSP430G2x53 MSP430G2x13 www. Texas Instruments Incorporated Submit Documentation Feedback 49 .1 UCB0SOMI UCB0SCL 6 A6 CA6 TDI/TCLK Capacitive sensing P1. Port P1 (P1.7) Pin Functions PIN NAME (P1.x (I/O) TA0.x I: 0.0/ UCB0CLK/ UCA0STE/ A5 (2)/ CA5 TMS Pin Osc P1.x) P1.5/ TA0.x (I/O) UCB0SIMO UCB0SDA A7 CA7 CAOUT TDO/TDI Capacitive sensing P1DIR.y 0 0 0 0 0 1 (y = 5) 0 0 0 0 0 0 0 1 (y = 6) 0 0 0 0 0 0 1 (y = 7) 0 0 0 X = don't care MSP430G2x53 devices only Copyright © 2011–2012.x 0 0 1 1 X X X 1 0 0 1 1 X X X 1 0 1 1 X X 0 X 1 ADC10AE. O: 1 1 from USCI from USCI X X X X I: 0.1/ UCB0SOMI/ UCB0SCL/ A6 / CA6 TDI/TCLK/ Pin Osc P1. O: 1 1 from USCI from USCI X X X X I: 0.ti.x (I/O) TA0.6/ TA0.x INCH.x=1 (2) 0 0 0 0 1 (y = 5) 0 0 0 0 0 0 0 1 (y = 6) 0 0 0 0 0 0 1 (y = 7) 0 0 0 0 JTAG Mode 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 CAPD.5 to P1.x 0 1 1 1 X X X 0 0 1 1 1 X X X 0 0 1 1 X X 1 X 0 P1SEL2.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 19.0 UCB0CLK UCA0STE 5 A5 CA5 TMS Capacitive sensing P1. O: 1 from USCI from USCI X X 1 X X P1SEL.7/ UCB0SIMO/ UCB0SDA/ A7 (2)/ CA7 CAOUT TDO/TDI/ Pin Osc (1) (2) 7 (2) CONTROL BITS AND SIGNALS (1) x FUNCTION P1.

4/TA1.y 1 DVSS DVCC PxOUT.y TAxCLK PxIN.y PxSEL.0 to P2.y PxSEL. Input/Output With Schmitt Trigger PxSEL.2/TA1.5.0 P2.y PxSEL.y 1 0 1 0 PxSEL2. Texas Instruments Incorporated .y PxIRQ.1 P2.com Port P2 Pin Schematic: P2.y PxIES.y Interrupt Edge Select EN Q Set 50 Submit Documentation Feedback Copyright © 2011–2012.5/TA1.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.ti.1 P2.1/TA1.0 P2.y PxREN.y EN To Module D PxIE.y From Timer 0 1 2 0 3 P2.3/TA1.2 0 1 1 TAx.y PxDIR.y PxIFG.y 0 1 Direction 0: Input 1: Output PxSEL2.2 P2.0/TA1.

x 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 Copyright © 2011–2012.CCI1A Timer1_A3.0/ Pin Osc P2.TA0 Capacitive sensing P2. O: 1 0 1 X I: 0. O: 1 0 1 X I: 0.CCI0A Timer1_A3.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 20.TA2 Capacitive sensing FUNCTION CONTROL BITS AND SIGNALS (1) P2DIR.5/ TA1.2/ TA1. O: 1 0 1 X I: 0.x (I/O) Timer1_A3.TA0 Capacitive sensing P2.TA1 Capacitive sensing P2.0 to P2.x (I/O) Timer1_A3.x (I/O) Timer1_A3.4/ TA1. Port P2 (P2.CCI2A Timer1_A3.1/ Pin Osc P2.TA1 Capacitive sensing P2.CCI1B Timer1_A3.x (I/O) Timer1_A3.x (I/O) Timer1_A3. O: 1 0 1 X I: 0.TA2 Capacitive sensing P2. O: 1 0 1 X P2SEL.CCI2B Timer1_A3.1/ TA1.2/ Pin Osc P2.x) P2.CCI0B Timer1_A3.x I: 0.0/ TA1.5) Pin Functions PIN NAME (P2.1/ Pin Osc P2.MSP430G2x53 MSP430G2x13 www.3/ TA1.x 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 P2SEL2.2/ Pin Osc (1) X = don't care 5 4 3 2 1 0 x P2.0/ Pin Osc P2. O: 1 0 1 X I: 0.ti.x (I/O) Timer1_A3. Texas Instruments Incorporated Submit Documentation Feedback 51 .

y 1 0 1 0 1 DVSS DVCC PxOUT.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.1 0 1 1 PxSEL2.y 52 Submit Documentation Feedback Copyright © 2011–2012.y EN To Module D PxIE.6.y Interrupt Edge Select Q EN Set XIN/P2.y PxIES. Input/Output With Schmitt Trigger LF off PxSEL.LFXT1Sx = 11 XOUT/P2.com Port P2 Pin Schematic: P2.y TAxCLK PxIN.y PxIFG.y 0 1 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.ti.7 LFXT1CLK PxSEL.6 and PxSEL.y PxREN.y From Module 0 1 2 3 TAx.y PxIRQ.6/TA0.y PxDIR. Texas Instruments Incorporated .7 BCSCTL3.y PxSEL.y PxSEL.

1 Pin Osc (1) X = don't care Timer0_A3.ti.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 21. O: 1 P2SEL. Port P2 (P2.6 P2SEL.6) Pin Functions PIN NAME (P2.x) XIN P2. Texas Instruments Incorporated Submit Documentation Feedback 53 .7 0 0 0 0 0 0 1 X XIN P2.7 1 1 0 X 1 0 0 X P2SEL2.TA1 Capacitive sensing 1 X CONTROL BITS AND SIGNALS (1) x FUNCTION P2DIR.x 0 I: 0.x (I/O) Copyright © 2011–2012.6 P2SEL2.6 6 TA0.MSP430G2x53 MSP430G2x13 www.

ti.y TAxCLK XOUT/P2.7. Input/Output With Schmitt Trigger LF off PxSEL.y Q PxIFG.7 BCSCTL3.y 1 0 1 0 1 DVSS DVCC 0 1 2 3 TAx.LFXT1Sx = 11 XIN LFXT1CLK PxSEL.y PxIES.y Interrupt Edge Select EN Set 54 Submit Documentation Feedback Copyright © 2011–2012.y PxREN.6 Direction 0: Input 1: Output PxSEL2.6 and PxSEL.com Port P2 Pin Schematic: P2.y PxOUT.y PxSEL.y PxIRQ.7 0 1 1 PxSEL2.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.y PxSEL.y PxDIR.y PxSEL.y 0 1 0 1 from P2.y EN To Module D PxIE.y From Module PxIN. Texas Instruments Incorporated .

7 1 1 0 X 0 X P2SEL2.x 1 I: 0.7/ Pin Osc (1) X = don't care 7 CONTROL BITS AND SIGNALS (1) x FUNCTION P2DIR. O: 1 X P2SEL.ti.7 0 0 0 0 1 X XOUT P2. Port P2 (P2. Texas Instruments Incorporated Submit Documentation Feedback 55 .MSP430G2x53 MSP430G2x13 www.6 P2SEL2.6 P2SEL.x) XOUT/ P2.7) Pin Functions PIN NAME (P2.x (I/O) Capacitive sensing Copyright © 2011–2012.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 22.

2 P3.y 1 0 1 0 PxSEL2.y From Module 0 1 2 3 P3.y PxSEL.0 P3.2 P3.2 P3.ti.7/TA1CLK/CAOUT 0 1 1 Direction 0: Input 1: Output TAx.y TAxCLK PxIN.1 P3. Texas Instruments Incorporated .y 1 DVSS DVCC PxOUT.0 to P3.y EN To Module D 56 Submit Documentation Feedback Copyright © 2011–2012.1 P3.1/TA1.7.2/TA1.y PxREN.5/TA0.0 P3.6/TA0.y 0 1 PxSEL2. Input/Output With Schmitt Trigger (28-Pin PW and 32-Pin RHB Packages Only) PxSEL.4/TA0.0/TA0.y PxSEL.3/TA1.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www.y PxDIR.com Port P3 Pin Schematic: P3.

x (I/O) Timer0_A3.x (I/O) Timer0_A3.0 to P3.x 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 P3SEL2.MSP430G2x53 MSP430G2x13 www.x (I/O) Timer1_A3.ti.com SLAS735G – APRIL 2011 – REVISED AUGUST 2012 Table 23.3/ TA1.TACLK Comparator output Capacitive sensing FUNCTION CONTROL BITS AND SIGNALS (1) P3DIR.1/ TA1.TA0 Capacitive sensing P3.x 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 Copyright © 2011–2012.x) P3.5/ TA0.CCI2A Timer0_A3. O: 1 1 X I: 0.TA1 Capacitive sensing P3. O: 1 1 X I: 0. O: 1 1 X I: 0.x I: 0.x (I/O) Timer1_A3.2/ Pin Osc P3. Port P3 (P3.0/ Pin Osc P3.TA2 Capacitive sensing P3.2/ Pin Osc P3.x (I/O) Timer0_A3.1/ Pin Osc P3.4/ TA0.TA2 Capacitive sensing P3.7/ TA1CLK/ CAOUT/ Pin Osc (1) X = don't care 7 6 5 4 3 2 1 0 x P3. O: 1 1 X I: 0.TA1 Capacitive sensing P3.x (I/O) Timer0_A3.x (I/O) Timer1_A3. O: 1 0 1 X I: 0.TA0 Capacitive sensing P3.7) Pin Functions (28-Pin PW and 32-Pin RHB Packages Only) PIN NAME (P3.TA2 Capacitive sensing P3.6/ TA0.0/ TA0. O: 1 0 1 X P3SEL.0/ Pin Osc P3. O: 1 1 X I: 0. O: 1 1 X I: 0. Texas Instruments Incorporated Submit Documentation Feedback 57 .1/ Pin Osc P3.2/ Pin Osc P3.2/ TA1.x (I/O) Timer1_A3.

to -55°C to 150°C in Absolute Maximum Ratings.y mux) in Port Schematics. Corrected signal names on Port P1 Pin Schematic: P1. pin 29) to Table 2 Terminal Functions.7. Texas Instruments Incorporated . Added PW28 to available packages. Removed mention of USART module from fSYSTEM description. Added note on TCREF+ in 10-Bit ADC.com REVISION HISTORY REVISION SLAS735 SLAS735A Initial release Changed Control Bits / Signals column in Table 18 Changed Pin Name and Function columns in Table 23 Changed Storage temperature range limit in Absolute Maximum Ratings Added BSL functions to P1. Changed all port schematics (added buffer after PxOUT. Added CAOUT information to Table 17.1 and P1. Changed TAG_ADC10_1 value to 0x10 in Table 10. DESCRIPTION SLAS735B SLAS735C SLAS735D SLAS735E SLAS735F SLAS735G 58 Submit Documentation Feedback Copyright © 2011–2012.4.MSP430G2x53 MSP430G2x13 SLAS735G – APRIL 2011 – REVISED AUGUST 2012 www. Built-In Voltage Reference (MSP430G2x53 Only). Recommended Operating Conditions. Corrected typo in P3. Changed Tstg. Table 5 and Table 14. Input/Output With Schmitt Trigger. Corrected Timer_A register names. Added AVCC (RHB package only.0 to P3. Port P3 Pin Schematic: P3.5 in Table 2. Input/Output With Schmitt Trigger (28-Pin PW and 32-Pin RHB Packages Only).ti.7/TA1CLK/CAOUT description in Table 2. Programmed device. Corrected PW28 terminal assignment in Input and Output Pin Number columns in Table 13.

ti.com 23-Jul-2012 PACKAGING INFORMATION Orderable Device MSP430G2153IN20 MSP430G2153IPW20 MSP430G2153IPW20R MSP430G2153IPW28 MSP430G2153IPW28R MSP430G2153IRHB32R MSP430G2153IRHB32T MSP430G2213IN20 MSP430G2213IPW20 MSP430G2213IPW20R MSP430G2213IPW28 MSP430G2213IPW28R MSP430G2213IRHB32R MSP430G2213IRHB32T MSP430G2253IN20 MSP430G2253IPW20 MSP430G2253IPW20R MSP430G2253IPW28 Status (1) Package Type Package Drawing PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP N PW PW PW PW RHB RHB N PW PW PW PW RHB RHB N PW PW PW Pins 20 20 20 28 28 32 32 20 20 20 28 28 32 32 20 20 20 28 Package Qty 20 70 2000 50 2000 3000 250 20 70 2000 50 2000 3000 250 20 70 2000 50 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 .PACKAGE OPTION ADDENDUM www.

PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2012 Orderable Device MSP430G2253IPW28R MSP430G2253IRHB32R MSP430G2253IRHB32T MSP430G2313IN20 MSP430G2313IPW20 MSP430G2313IPW20R MSP430G2313IPW28 MSP430G2313IPW28R MSP430G2313IRHB32R MSP430G2313IRHB32T MSP430G2353IN20 MSP430G2353IPW20 MSP430G2353IPW20R MSP430G2353IPW28 MSP430G2353IPW28R MSP430G2353IRHB32R MSP430G2353IRHB32T MSP430G2413IN20 MSP430G2413IPW20 Status (1) Package Type Package Drawing TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP PW RHB RHB N PW PW PW PW RHB RHB N PW PW PW PW RHB RHB N PW Pins 28 32 32 20 20 20 28 28 32 32 20 20 20 28 28 32 32 20 20 Package Qty 2000 3000 250 20 70 2000 50 2000 3000 250 20 70 2000 50 2000 3000 250 20 70 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 .

ti.PACKAGE OPTION ADDENDUM www.com 23-Jul-2012 Orderable Device MSP430G2413IPW20R MSP430G2413IPW28 MSP430G2413IPW28R MSP430G2413IRHB32R MSP430G2413IRHB32T MSP430G2453IN20 MSP430G2453IPW20 MSP430G2453IPW20R MSP430G2453IPW28 MSP430G2453IPW28R MSP430G2453IRHB32R MSP430G2453IRHB32T MSP430G2513IN20 MSP430G2513IPW20 MSP430G2513IPW20R MSP430G2513IPW28 MSP430G2513IPW28R MSP430G2513IRHB32R MSP430G2513IRHB32T Status (1) Package Type Package Drawing TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN PW PW PW RHB RHB N PW PW PW PW RHB RHB N PW PW PW PW RHB RHB Pins 20 28 28 32 32 20 20 20 28 28 32 32 20 20 20 28 28 32 32 Package Qty 2000 50 2000 3000 250 20 70 2000 50 2000 3000 250 20 70 2000 50 2000 3000 250 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 3 .

OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan . PREVIEW: Device has been announced but is not in production.1% by weight in homogeneous material) (3) MSL. Pb-Free (RoHS Exempt). Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package. and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.PACKAGE OPTION ADDENDUM www.The planned eco-friendly classification: Pb-Free (RoHS). TBD: The Pb-Free/Green conversion plan has not been defined. and peak solder temperature. Peak Temp. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances.ti. Where designed to be soldered at high temperatures. NRND: Not recommended for new designs. -.please check http://www. and a lifetime-buy period is in effect.ti. Addendum-Page 4 . Samples may or may not be available.com 23-Jul-2012 Orderable Device MSP430G2553CY MSP430G2553CYS MSP430G2553GACYS MSP430G2553IN20 MSP430G2553IPW20 MSP430G2553IPW20R MSP430G2553IPW28 MSP430G2553IPW28R MSP430G2553IRHB32R MSP430G2553IRHB32T Status (1) Package Type Package Drawing DIESALE Y YS YS N PW PW PW PW RHB RHB Pins 0 0 0 20 20 20 28 28 32 32 Package Qty 405 Eco Plan (2) Lead/ Ball Finish Call TI Call TI Call TI MSL Peak Temp N / A for Pkg Type Call TI Call TI (3) Samples (Requires Login) PREVIEW Green (RoHS & no Sb/Br) TBD TBD Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) PREVIEW WAFERSALE PREVIEW WAFERSALE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PDIP TSSOP TSSOP TSSOP TSSOP QFN QFN 1 20 70 2000 50 2000 3000 250 CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. or Green (RoHS & no Sb/Br) . Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible).1% by weight in homogeneous materials.The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications. LIFEBUY: TI has announced that the device will be discontinued. but TI does not recommend using this part in a new design.com/productcontent for the latest availability information and additional product content details. TI Pb-Free products are suitable for use in specified lead-free processes. or 2) lead-based die adhesive used between the die and leadframe. Device is in production to support existing customers. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. including the requirement that lead not exceed 0.

PACKAGE OPTION ADDENDUM www.com 23-Jul-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.ti. and thus CAS numbers and other limited information may not be available for release. and makes no representation or warranty as to the accuracy of such information. TI bases its knowledge and belief on information provided by third parties. TI and TI suppliers consider certain information to be proprietary. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 5 . Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

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