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Radar & SDR I/O

RAD AR & SDR I/O - PMC/XMC RADAR


MODEL
7150 7151 7152 7153 7156 7158 Cobalt 71620 Cobalt 71621 Cobalt 71630 Cobalt 71640 Cobalt 71641 Cobalt 71650 Cobalt 71651 Cobalt 71660 Cobalt 71661 Cobalt 71662 Cobalt 71670 Cobalt 71671 Cobalt 71690 Onyx 71720 Onyx 71760

DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - PMC/XMC Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - XMC 1 GHz A/D and D/A, Virtex-6 FPGA - XMC 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - XMC 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Wideband DDC, Virtex-6 FPGA - XMC Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - XMC 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - XMC 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - XMC 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMC 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-7 FPGA - XMC 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - XMC Customer Information

RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR

& & & & &

SDR SDR SDR SDR SDR

I/O I/O I/O I/O I/O

CompactPCI PCI x16 PCI Express x 8 PCI Express 3U VPX

Last updated: February 2013


www.pentek.com

Model 7150

Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC


General Information
Model 7150 is a quad, high-speed data converter suitable for connection as the HF or IF input of a communications system. It features four 200 MHz, 16-bit A/Ds supported by an array of data processing and transport resources ideally matched to the requirements of high-performance systems. Model 7150 uses the popular PMC format and supports the emerging VITA 42 XMC standard for switched-fabric interfaces. DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7150 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs the P4 PMC connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O.

A/D Converter Stage


The front end accepts four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other module resources.

Virtex-5 FPGAs
The Model 7150 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factoryshipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters,

Features

Complete software radio interface solution VITA 42.0 XMC compatible with switched fabric interfaces Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

Clocking and Synchronization


The Model 7150 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus.

RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

Clock/Sync Bus

TTL In

200 MHz 16 bit A/D

200 MHz 16 b t A/D

200 MHz 16 bit A/D

200 MHz 16 bit A/D

LVPECL Bus
XTL OSC To All Sections Control/ PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T, LX155T or FX100T
LVDS GTP GTP GTP

Timing Bus

Status

32 DDR2 SDRAM 512 MB

32 DDR2 SDRAM 512 MB

8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T


LVDS PCI X GTP

4X
GTP

4X

4X

PMC P4 FPGA I/O (Option -104)

32

32

PCI-X BUS (64 Bits, 100 MHz)

64

4X

P15 XMC VITA 42.x (Option -5xx)

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7150

Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PMC/XMC


Clocking and Synchronization
The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7150s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. More modules can be synchronized with an external clock and sync generator.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs P4 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.

XMC Interface
The Model 7150 complies with the VITA 42.0 XMC specification for carrier boards. This emerging standard provides serial data links with up to 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7150 achieves up to 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.

PCI-X Interface
The Model 7150 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66, 100 MHz are supported.

Optional PCI Express Interface


For systems that require a PCI Express board interface, the Model 7150 can be optionally factory-configured with x4 PCI Express in the interface FPGA. Other serial protocols as well as different bus widths can be accommodated with custom IP cores.

Ordering Information
Model 7150 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs PMC/XMC

Options: -104 FPGA I/O through the P4 connector -5xx XMC interface

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7151

256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC


General Information
Model 7151 is a 4-channel, high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a highperformance 256-channel installed DDC (digital downconverter) IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. Model 7151 uses the industry standard PMC daughtercard format compatible with numerous carrier boards for VME, PCI, and CompactPCI.

Decimation and Filtering


All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 156.25 kHz to 1.25 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 64. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

A/D Converter Stage Features


256 channels of DDC Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization

The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

DDC Input Selection and Tuning


The Model 7151 employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 256 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

Output Multiplexers and FIFOs


Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI-X bus.

CH 1 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 2 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024

CH 1 I+Q
M U X

FIFO 1

CH 3 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D

CH 2
M U X DIGITAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024

CH 3 CH 4

I+Q

M U X

FIFO 2

PCI-X BUS Sample Clock In PPS In TTL In LVPECL Bus Timing Bus Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 4: CH 193-256 DEC: 128 - 1024

CH 1 TIMING BUS GENERATOR CH 2 CH 3 CH 4


M U X DIGITAL DOWNCONVERTER BANK 3: CH 129-192 DEC: 128 - 1024

CH 3 I+Q
M U X

FIFO 3

PCI-X INTERFACE Xilinx XC5VLX30T

CH 4 I+Q
M U X

FIFO 4

XILINX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7151

256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC


Clocking and Synchronization
The Model 7151 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7151s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. More modules can be synchronized with an external clock and sync generator.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 133 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: Standard: 0 to 50 C L2 Extended Temp (Option -702): 20 to 65 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.

PCI-X Interface
The Model 7151 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 133 MHz are supported.

Ordering Information
Model 7151 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC

Options: -702 L2 Extended temperature operation -730 Two-slot heat sink

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7152

32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC


General Information
Model 7152 is a 4-channel, high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a highperformance 32-channel installed DDC (digital downconverter) IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. Model 7152 uses the industry standard PMC daughtercard format compatible with numerous carrier boards for VME, PCI, and CompactPCI.

Decimation and Filtering


All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

Features

32 channels of DDC in four banks of 8 channels Four 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all 32 channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Common decimation factor within each DDC bank Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multimodule synchronization

A/D Converter Stage


The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

DDC Input Selection and Tuning


The Model 7152 employs an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 32 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

Power Meters and Threshold Detectors


The 7152 features 32 power meters that continuously measure the individual average power output of each of the 32 DDC channels. The time constant of the averaging interval for each meter is programmable up to 16K samples. In addition, 32 threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.

CH 1 RF In

RF XFORMR

200 MHz 16-bit A/D


8X4 CHANNEL SUMMATION M U X DIGITAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 - 8192

CH 1 I+Q
M U X F I F 0 1 F I F 0 2

CH 2 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHOLD DETECTORS

CH 3 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D

CH 2
M U X

CH 3 CH 4

M U X

DIGITAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 - 8192

I+Q
POWER METER & THRESHOLD DETECTORS

PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4

Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 3: CH 17-24 DEC: 16 - 8192

I+Q
POWER METER & THRESHOLD DETECTORS

PCI-X INTERFACE Xilinx XC5VLX30T

TTL In

CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 4: CH 25-32 DEC: 16 - 8192

CH 4
M U X

LVPECL Bus

I+Q
POWER METER & THRESHOLD DETECTORS

XTAL OSC

Timing Bus

XILINX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7152

32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC


Output Multiplexers and FIFOs
Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI-X bus.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.

Clocking and Synchronization


The Model 7152 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7152s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. For larger systems, many more modules can be synchronized with an external clock and sync generator.

PCI-X Interface
The Model 7152 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Ordering Information
Model 7152 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PMC

Options: -730 Two-slot heat sink

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7153

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PMC/XMC


General Information
Model 7153 is a 4-channel, high-speed software radio module designed for processing baseband RF or IF signals. It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel DDC (digital downconverter) and a complete set of beamforming functions. With built-in multiboard synchronization, it is ideally matched to the requirements of real-time software radio and radar systems. Model 7153 uses the industry standard PMC daughtercard format compatible with numerous carrier boards for VME, PCI, and CompactPCI. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sampling frequency.

Decimation and Filtering


Each of the four DDC channels can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. The DDC core can be configured in four-channel mode with each channel offering decimations between 2 and 256, or in two-channel mode with each channel having a decimation range of 2 to 65536, for applications that require a wider range of decimations. The decimating filter for each DDC channel accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N.

A/D Converter Stage Features

Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization

The front end accepts four full scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling to four Texas Instruments ADS5485 200 MHz, 16-bit A/Ds. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

DDC Input Selection and Tuning


The Model 7153 employs an advanced FPGA-based digital downconverter engine consisting of two or four DDC channels. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC channel. In this way, many different configurations can be achieved including one A/D driving all four DDC channels and each of the four A/Ds driving its own DDC bank.

Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.
SUM IN SUM OUT 4X 4X P15 XMC
F I F 0 1 F I F 0 2

CH 1 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER

AURORA G GAB T SERIAL INTERFACE

CH 2 RF In

RF XFORMR

200 MHz 16-bit A/D

I+Q CH 1
M U X

CH 3 RF In

RF XFORMR

200 MHz 16-bit A/D

D G TAL DOWNCONVERTER CH 1 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

CH 4 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 3 CH 4
M U X

CH 2
M U X

D G TAL DOWNCONVERTER CH 2 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4

Sample Clock In PPS In TTL In LVDS Bus Timing Bus

CH 1 TIM NG BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4


M U X D G TAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*

CH 2 CH 3 CH 4

M U X

D G TAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

PCI-X NTERFACE

XILINX XC5VLX30T

CH 4
M U X

I+Q
POWER METER & THRESHOLD DETECTORS

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

XILINX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7153

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PMC/XMC


Beamformer
In addition to the A/Ds and DDCs, the 7153 includes essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI-X bus. For larger systems, multiple 7153s can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.

Clocking and Synchronization


The Model 7153 architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven from the internal crystal oscillator, a front panel reference or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7153s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. More modules may be synchronized with an external clock and sync generator.

XMC Interface
The Model 7153 complies with the VITA 42.0 XMC specification. This standard provides serial data links between the XMC module and the carrier board. The 7153 beamformer architecture uses this link to create a board-to-board summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

Output Multiplexers and FIFOs


Four output MUXs can be independently switched to deliver either A/D or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the channels and to enable efficient block transfers to the PCI-X bus.

PCI-X Interface
The Model 7153 includes an industrystandard PCI-X interface. The interface includes four separate DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

GAIN

I Q

I Q

I
Q

I
Q

DIG TAL DOWNCONVERTER A

Weigh Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT A

AURORA PORT

SUMMAT ON EXPANSION CHAIN IN 1 25 GByte/sec x4 Au ora Link

F om P evious Board

P15
GAIN

DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

I
Q

I
Q

I
Q

I
Q

DIG TAL DOWNCONVERTER B

Weigh Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT B

SUMMAT ON CHAIN BIT GROWTH COMPENSAT ON

I Q

I Q

I Q

To FIFO 1 (Final Result or Intermediate Result

GAIN

(DECIMATION: 2-256)*

I Q

I Q

I
Q

I
Q

Summation Chain Gain POWER METER & THRESHO D DETECT C

SUMMATION POWER METER & THRESHO D DETECT

DIG TAL DOWNCONVERTER C

Weigh Phase I Weight Phase Q Weight Gain PHASE SHIFT

AURORA PORT

SUMMAT ON EXPANS ON CHAIN OUT 1 25 GByte/sec x4 Au ora Link

To Next Boa d

GAIN

P15 I Q

(DECIMATION: 2-256)*

I Q

I Q

I Q

DIG TAL DOWNCONVERTER D

Weigh Phase I Weight Phase Q Weight Gain

POWER METER & THRESHO D DETECT D

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

BEAMFORMER DATA FLOW DETAIL

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7153

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PMC/XMC


Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, userprogrammable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI Interface Type: IP core in Xilinx FPGA PCI-X Bus: 64 bits, 100 MHz and 64 or 32 bits at 33 or 66 MHz DMA: 4-channel demand mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.

Ordering Information
Model 7153 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - PMC/XMC

Options: -730 Two-slot heat sink

Contact Pentek for available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7156

Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
General Information
Model 7156 is a dual-channel, highspeed data converter suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters, two Virtex-5 FPGAs and two banks of DDR2 SDRAM. The Model 7156 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces.

Virtex-5 FPGAs
The Model 7156 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR

A/D Converter Stage


The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other module resources.

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution Two 400 MHz, 14-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O on P14

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus

400 MHz 14 BIT A/D

400 MHz 14 BIT A/D

800 MHz 16 BIT D/A

800 MHz 16 BIT D/A

TTL Gate / Tr g TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS

DIGITAL UPCONVERTER

D/A Clock Bus


14 To All Sections 14 32

Timing Bus

VCXO

Control/ Status
32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX 5 LX50T, LX155T, SX50T, SX95T or FX100T


LVDS GTP GTP GTP

32 DDR2 SDRAM 512 MB

8 64 FLASH 32 MB 4X
GTP

4X

4X

INTERFACE FPGA VIRTEX 5 LX30T, SX50T or FX70T


LVDS PCI X GTP

P14 PMC FPGA I/O

32

32

PCI-X BUS (64 Bits, 100 MHz)

64

4X

P15 XMC VITA 42.x (PCIe, etc.)

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7156

Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds the P14 PMC connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the P14 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.

XMC Interface
The Model 7156 complies with the VITA 42.0 XMC specification for carrier boards. This standard provides, among others, for a 4X link with a 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7156 achieves 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7156s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

PCI-X Interface Ordering Information


Model 7156 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC

The Model 7156 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Options: -104 FPGA I/O through the P14 connector -5xx XMC interface

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7158

Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
General Information
Model 7158 is a dual-channel, highspeed data converter suitable for connection to HF or IF ports of a communications system. It includes two A/D and two D/A converters, two Virtex-5 FPGAs and two banks of DDR2 SDRAM. The Model 7158 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces.

Virtex-5 FPGAs
The Model 7158 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR

A/D Converter Stage


The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5463 12-bit 500 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other module resources.

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution Two 500 MHz, 12-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O on P14

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus

500 MHz 12 BIT A/D

500 MHz 12 BIT A/D

800 MHz 16 BIT D/A

800 MHz 16 BIT D/A

TTL Gate / Trig TTL Sync / PPS Sample C k Sync Clk Gate A Gate B Sync PPS

DIGITAL UPCONVERTER

D/A Clock Bus


14 To A l Sections 14 32

Timing Bus

VCXO

Control/ Status
32 DDR2 SDRAM 256 MB

PROCESSING FPGA VIRTEX 5 LX50T, LX155T, SX50T, SX95T or FX100T


LVDS GTP GTP GTP

32 DDR2 SDRAM 256 MB

8 64 FLASH 32 MB 4X
GTP

4X

4X

INTERFACE FPGA VIRTEX 5 LX30T, SX50T or FX70T


LVDS PCI X GTP

P14 PMC FPGA I/O

32

32

PCI-X BUS (64 Bits, 100 MHz)

64

4X

P15 XMC VITA 42.x (PCIe, etc.)

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7158

Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds the P14 PMC connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the P14 connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard PMC module, 2.91 in. x 5.87 in.

XMC Interface
The Model 7158 complies with the VITA 42.0 XMC specification for carrier boards. This standard provides, among others, for a 4X link with a 3.125 GHz bit clock between the XMC module and the carrier board. With two 4X links, the 7158 achieves 2.5 GB/sec streaming data transfer rate independent of the PCI interface and supports switched fabric protocols such as Serial RapidIO and PCI Express.

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can also be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7158s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

Ordering Information
Model 7158 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PMC/XMC

PCI-X Interface
The Model 7158 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Options: -104 FPGA I/O through the P14 connector -140 1 GB DDR2 SDRAM -5xx XMC interface

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71620

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - XMC
General Information
Model 71620 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71620 includes general purpose and gigabit serial connectors for application-specific I/O . nization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71620 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules, ideally matched to the boards analog interfaces. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchro-

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF In

RF In

RF Out

RF Out

RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


GTX
GTX

GTX

LVDS

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

8X

4X

4X

40

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

Memory Banks 1 & 2

Memory Banks 3 & 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71620
A/D Acquisition IP Modules
The 71620 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - XMC
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Memory Resources
The 71620 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
to D/A D/A loopback
TEST SIGNAL GENERATOR

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.
from A/D Ch 1 from A/D Ch 2 from A/D Ch 3

D/A Waveform Playback IP Module


The Model 71620 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either onboard memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

MEMORY CONTROL

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71620

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - XMC
modules DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

XMC Interface
The Model 71620 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71620 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.

PCI Express Interface


The Model 71620 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Ordering Information
Model 71620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits

Options: -062 -064 -104 -105 -150

-160

-155

-165

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71621

3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
General Information
Model 71621 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71621 includes a general purpose connector for application-specific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71621 factory installed functions include three A/D acquisition and a D/A waveform playback IP modules. Each of the three acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
RF In RF In RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


GTX
GTX

GTX

LVDS

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

8X

4X

4X

40

Sum to next board x8 PCIe Aurora Gigabit Serial P16 XMC FPGA GPIO (option 104) P14 PMC

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

P15 XMC

Memory Banks 1 & 2

Memory Banks 3 & 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71621
A/D Acquisition IP Modules
The 71621 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.

Beamformer IP Core
In addition to the DDCs, the 71621 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average

D/A Waveform Playback IP Module


The Model 71621 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or off- board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3 D/A loopback

to D/A

INPUT MULTIPLEXER

TEST SIGNAL GENERATOR

DDC DEC: 2 TO 65536

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to
MUX

POWER METER & THRESHOLD DETECT

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

8X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71621

3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to create a total range from 2x to 524,288x.

Memory Resources
The 71621 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

XMC Interface
The Model 71621 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71621 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beamforming accross multiple modules.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator.

PCI Express Interface


The Model 71621 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71621

3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Ordering Information
Model 71621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA XMC

Options: -062 -064 -104 -150 XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

-160

-155

-165

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71630

1 GHz A/D and 1 GHz D/A, Virtex-6 FPGA - XMC


General Information
Model 71630 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71630 includes optional general purpose and gigabit serial card connectors for application-specific I/O. and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 71630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF Out

Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Sync In

1 GHz 12-BIT A/D

A/D Sync Bus


Gate In Sync In

D/A Clock/Sync Bus


12

1 GHz 16-BIT D/A 16

D/A Sync Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


GTX
GTX

GTX

LVDS

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 Config FLASH 64 MB

8X

4X

4X

40

Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB

Memory Banks 3 & 4 DDR3 option 165

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

QDRII+ option 150

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71630

1 GHz A/D and 1 GHz D/A, Virtex-6 FPGA - XMC


A/D Converter Stage
vide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. Two front panel 7-pin LVPECL Sync connectors allows multiple modules to be synchronized. One connector for the A/D and one for the D/A each provide sync and gate signals.

A/D Acquisition IP Module


The 71630 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, a test signal generator, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

D/A Converter Stage


The 71630 features a TI DAC5681Z 1 GHz, 16-bit D/A. The converter has an input sample rate of 1 GSPS, allowing it to acept full rate data from the FPGA. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connector.

Memory Resources
The 71630 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to pro-

from A/D D/A loopback


TEST SIGNAL GENERATOR

to D/A

D/A Waveform Playback IP Module


The Model 71630 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back waveforms stored in either on-board memory or off- board host memory to the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROLLER MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP) 8X PCIe Gigabit Serial I/O 4X 4X 40

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

FPGA GPIO

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71630

1 GHz A/D and 1 GHz D/A, Virtex-6 FPGA - XMC


XMC Interface
The Model 71630 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71630 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 7-pin connectors, LVPECL bus for sync and gate, one A/D connector and one D/A connector External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8; Gen 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

PCI Express Interface


The Model 71630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be locked to an external 4 to 200 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock

Ordering Information
Model 71630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - XMC

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71640

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
General Information
Model 71640 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71640 includes optional general purpose and gigabit serial connectors for application-specific I/O. and a PCIe interface complete the factoryinstalled functions and enable the 71640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71640 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchronization functions, a test signal generator

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support other serial protocols.

Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multimodule synchronization PCI Express Gen. 2 interface x8 wide Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF In

Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Reset In Ref Clk In Ref Clk Out

3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-Bit A/D


12 12

Sync Bus

VIRTEX-6 FPGA LX130T, LX240T or SX315T


GTX
GTX

GTX

LVDS

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

8X

4X

4X

40

Memory Banks 1 & 2

Memory Banks 3 & 4

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71640

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 71640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 71640s can be synchronized using the Cobalt high speed sync module to drive the sync bus.

Memory Resources
The 71640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

A/D Acquisition IP Module


The 71640 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

XMC Interface
The Model 71640 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 5 GHz bit clock. With dual XMC connectors, the 71640 supports x8 PCIe on the first XMC connector leaving the optional second connector free to support user-installed transfer protocols specific to the target application.

Clocking and Synchronization


The 71640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple modules to be synchronized, ideal for larger multichanel

from A/D

from A/D
TEST SIGNAL GENERATOR

VIRTEX-6 FPGA DATAFLOW DETAIL


(Two channel mode shown) INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE

MEMORY CONTROLLER PCIe INTERFACE

MEMORY CONTROLLER

(supports user installed IP) to Mem Bank 1 to Mem Bank 2 8X PCIe Gigabit Serial I/O 4X 4X 40 to Mem Bank 3 to Mem Bank 4

FPGA GPIO

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71640

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC
PCI Express Interface
The Model 71640 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock

Ordering Information
Model 71640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - XMC

Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71641

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - XMC
General Information
Model 71641 is a member of the Cobalt family of high-performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, Model 71641 includes an optional connection to the Virtex-6 FPGA for custom I/O . controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 71641 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O.

A/D Converter Stage


The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 71641 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71641 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a

Features

Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds Programmable one- or twochannel DDC (Digital Downconverter) 2 GB of DDR3 SDRAM Sync bus for multimodule synchronization PCI Express Gen. 2 interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF In

Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Reset In Ref Clk In Ref Clk Out

3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-Bit A/D


12 12

Sync Bus

VIRTEX-6 FPGA SX315T


GTX
LVDS

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

8X

40

Memory Banks 1 & 2

Memory Banks 3 & 4

x8 PCIe

FPGA GPIO (option 104) P14 PMC

P15 XMC

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71641
A/D Acquisition IP Module
The 71641 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - XMC
DDC IP Cores
Within the FPGA is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the A/D at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the A/Ds 1.8 GHz two-channel operation . In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 16-bit I + 16-bit Q samples at a rate of s/N.

Clocking and Synchronization


The 71641 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple modules to be synchronized, ideal for multichannel systems. The sync bus includes gate, reset, and in and out reference clock signals. Two 71641s can be synchronized with a simple cable. For larger systems, multiple 71641s can be synchronized using the Cobalt 7192 highspeed sync module to drive the sync bus.

Memory Resources
The 71641 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.

from A/D

from A/D

VIRTEX-6 FPGA DATAFLOW DETAIL


*Two channel mode shown. Programmable decimation of 8, 16 or 32 available in one channel mode.
INPUT MULTIPLEXER TEST SIGNAL GENERATOR DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT

DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT

DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE MEMORY CONTROLLER A/D ACQUISITION IP MODULE PCIe INTERFACE to MEM CONTROL

DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER

to Mem Bank 1

to Mem Bank 2

8X PCIe

FPGA GPIO

40

to Mem Bank 3

to Mem Bank 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71641

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - XMC
PCI Express Interface
The Model 71641 complies with the VITA 42.3 XMC specification and includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. Sample Clock Sources: Front panel SSMC connector Sync Bus: Multipin front panel connector, includes gate, reset, and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include trigger and gate Field Programmable Gate Array: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation

Ordering Information
Model 71641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D with Wideband DDC, Virtex-6 FPGA - XMC

Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T LVDS FPGA I/O through P14 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71650

Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC
General Information
Model 71650 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes two A/Ds, one DUC (Digital Upconverter), two D/As, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71650 includes optional general-purpose and gigabit serial card connectors for application-specific I/O. memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable the 71650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71650 factory-installed functions include two A/D acquisition and one D/A waveform playback IP modules. In addition, IP modules for either DDR3 or QDRII+
RF In

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.
RF In RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

500 MHz 12-BIT A/D

500 MHz 12-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


GTX
GTX

Timing Bus
GTX
LVDS

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

8X

4X

4X

40

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

Memory Banks 1 & 2

Memory Banks 3 & 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71650

Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC
A/D Converter Stage
Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

A/D Acquisition IP Modules


The 71650 features two A/D Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfers, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

The front end accepts two full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Memory Resources
The 71650 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.

from A/D Ch 1

from A/D Ch 2 D/A loopback TEST SIGNAL GENERATOR

to D/A

INPUT MULTIPLEXER

D/A Waveform Playback IP Module


The Model 71650 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back waveforms stored in either on-board memory or off- board host memory to the dual D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

MEMORY CONTROL

to Mem Bank 3

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71650

Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - XMC
modules DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1 or Gen.2, x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

XMC Interface
The Model 71650 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71650 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.

PCI Express Interface


The Model 71650 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Ordering Information
Model 71650 Description Two 500 MHz A/Ds, one DUC, Two 800 MHz D/As with Virtex-6 FPGA - XMC

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits

Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240 FPGA XC6VSX315 FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71651

2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
General Information
Model 71651 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes two A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71651 includes a general purpose connector for application-specific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71651 factory installed functions include two A/D acquisition and a D/A waveform playback IP modules. Each of the two acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
RF In RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

500 MHz 12-BIT A/D

500 MHz 12-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

VCXO

VIRTEX-6 FPGA LX240T or SX315T


GTX
GTX

Timing Bus
GTX
LVDS

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

8X 4X Sum from previous board x8 PCIe

4X

40

Sum to next board Aurora Gigabit Serial P16 XMC FPGA GPIO (option 104) P14 PMC

Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB

Memory Banks 3 & 4 DDR3 option 165

P15 XMC

QDRII+ option 150

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71651
A/D Acquisition IP Modules
The 71651 features two A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.

Beamformer IP Core
In addition to the DDCs, the 71651 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average

D/A Waveform Playback IP Module


The Model 71651 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or off- board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

from A/D Ch 1

from A/D Ch 2 D/A loopback


INPUT MULTIPLEXER

to D/A

TEST SIGNAL GENERATOR

DDC DEC: 2 TO 131027

DDC DEC: 2 TO 131027


POWER METER & THRESHOLD DETECT

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MUX

POWER METER & THRESHOLD DETECT

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

VIRTEX-6 FPGA DATAFLOW DETAIL

8X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71651

2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to create a total range from 2x to 524,288x.

Memory Resources
The 71651 architecture supports up to three independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

XMC Interface
The Model 71651 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71651 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beamforming accross multiple modules.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator.

PCI Express Interface


The Model 71651 includes an industrystandard interface fully compliant with PCI Express Gen. 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71651

2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - XMC
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Ordering Information
Model 71651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA XMC

Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71660

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMC


General Information
Model 71660 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71660 includes general purpose and gigabit serial connectors for application-specific I/O . generator, and a PCIe interface complete the factory-installed functions and enable the 71660 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71660 factory-installed functions include four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF In

RF In

RF In

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


GTX
GTX

GTX

LVDS

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

8X

4X

4X

40

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

Memory Banks 1 & 2

Memory Banks 3 & 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71660

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMC


A/D Converter Stage
The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71660s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

Memory Resources
The 71660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the

A/D Acquisition IP Modules


The 71660 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

XMC Interface
The Model 71660 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71660

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3

from A/D Ch 4

TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

PCIe

8X

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71660

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - XMC


supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

PCI Express Interface


The Model 71660 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock

Ordering Information
Model 71660 Options: -062 -064 -104 -105 -150 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - XMC

-160

-155

-165

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71661

4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC
General Information
Model 71661 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs (digital downconverters), it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71661 includes a general purpose connector for application-specific I/O. for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 71661 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71661 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable DDC (Digital Downconverter) IP core. IP modules

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O.
RF In RF In RF In RF In

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


GTX
GTX

GTX

LVDS

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

8X x8 PCIe

4X

4X

40

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Aurora Gigabit Serial I/O

Sum from previous board


P15 XMC

Sum to next board


P16 XMC

FPGA GPIO (option 104) P14 PMC

Memory Banks 1 & 2

Memory Banks 3 & 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71661
A/D Acquisition IP Modules
The 71661 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.

A/D Converter Stage


The front end accepts four analog HF or IF inputs on front panel SSMC connectors with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources.

Beamformer IP Core
In addition to the DDCs, the 71661 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3

from A/D Ch 4

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536

TEST SIGNAL GENERATOR

INPUT MULTIPLEXER

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

MUX

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

8X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71661

4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC
controlled crystal oscillator. In this mode,
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

XMC Interface
The Model 71661 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71661 supports x8 PCIe on the first XMC connector. The second connector is used for the Aurora interface and provides a dedicated board-to board interface for beamforming accross multiple boards.

Memory Resources
The 71661 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

PCI Express Interface


The Model 71661 includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Ordering Information
Model 71661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - XMC XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation

Options: -062 -064 -104 -150

-160

-155

-165

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71662

4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC
General Information
Model 71662 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. interface complete the factory-installed functions and enable the 71662 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71662 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of all data clocking, synchronization, gate and trigger functions, a test signal generator, voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable serial gigabit interfaces Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF In

RF In

RF In

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


GTX
GTX

GTX

LVDS

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

8X

4X

4X

40

Memory Banks 1 & 2 DDR3 option 155

Memory Banks 3 & 4 DDR3 option 165

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71662
A/D Acquisition IP Modules
The 71662 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC
available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a reference clock, typically 10 MHz, for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71662s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

A/D Converter Stage


The front end accepts four analog HF or IF inputs on front panel SSMC connectors with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources.

Memory Resources
The 71662 architecture supports up to four independent memory banks which can be configured with DDR3 SDRAM.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3

from A/D Ch 4

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the

TEST SIGNAL GENERATOR

INPUT MULTIPLEXER

DIGITAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 TO 8192


.

DIGITAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 TO 8192


.

DIGITAL DOWNCONVERTER BANK 3: CH 17-24 DEC: 16 TO 8192


.

DIGITAL DOWNCONVERTER BANK 4: CH 18-32 DEC: 16 TO 8192


.

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

32 Memory Bank 1

32 Memory Bank 2

32 Memory Bank 3

32 Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71662

4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC
Each DDR3 SDRAM bank can be up to
512 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

XMC Interface
The Model 71662 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71662 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.

PCI Express Interface


The Model 71662 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation

Ordering Information
Model 71662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - XMC XC6VLX240T XC6VSX315T LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Options: -062 -064 -104 -105 -155

-165

Contact Pentek for availability of ruged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71670

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC


General Information
Model 71670 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71670 includes general purpose and gigabit serial connectors for application-specific I/O . a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 71670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71670 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions,

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support serial protocols.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF Out

RF Out

RF Out

RF Out

RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

Clock/Sync Bus A Clock/Sync Bus B

Gate In Sync In

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

mSync Bus A
Gate In Sync In

mSync Bus B

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


GTX
GTX

GTX

LVDS

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

8X

4X

4X

40

Memory Banks 1 & 2

Memory Banks 3 & 4

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71670

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC


Digital Upconverter and D/A Stage
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. Analog output is through four front panel SSMC connectors. A pair of front panel Sync connectors allows multiple modules to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave 71670 module. For larger systems, the Pentek Model 7191 Cobalt Synchronizer can drive multiple 71670s enabling large, multichannel synchronous configurations.

Memory Resources
The 71670 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator.
16
TEST SIGNAL GENERATOR

XMC Interface
The Model 71670 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 3.125 GHz bit clock. With dual XMC connectors, the 71670 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.
16 to D/A Ch 3 & 4

D/A Waveform Playback IP Module


The Model 71670 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked list controllers support waveform generation to the four D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.

to D/A Ch 1 & 2

DATA INTERLEAVER

DATA INTERLEAVER

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

MEMORY CONTROL

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 1

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 2

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 3

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71670

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - XMC


PCI Express Interface
The Model 71670 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as two 4X or one 8X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference

Ordering Information
Model 71670 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - XMC

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71671

4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
General Information
Model 71671 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O . SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 71671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71671 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support serial protocols.
RF Out RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multimodule synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF Out

RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

Clock/Sync Bus A Clock/Sync Bus B

Gate In Sync In

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

mSync Bus A
Gate In Sync In

mSync Bus B

VCXO

VIRTEX-6 FPGA LX240T or SX315T


GTX
GTX

GTX

LVDS

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

8X

4X

4X

40

Memory Banks 1 & 2

Memory Banks 3 & 4

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71671

4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
Digital Upconverter and D/A Stage
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, the 71671 features an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog output is through four front panel SSMC connectors. SSMC connector. This clock can be used directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A pair of front panel Sync connectors allows multiple modules to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave 71671 module. For larger systems, the Pentek Model 7191 Cobalt Synchronizer can drive multiple 71671s enabling large, multichannel synchronous configurations.

Memory Resources
The 71671 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the modules DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
16 to D/A Ch 3 & 4

Clocking and Synchronization D/A Waveform Playback IP Module


The Model 71671 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linkedlist controllers support waveform generation to the four D/As from tables stored in either onboard memory or off-board host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming. An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel
16
TEST SIGNAL GENERATOR

to D/A Ch 1 & 2

DATA INTERLEAVER

DATA INTERLEAVER

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

MEMORY CONTROL

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 1

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 2

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 3

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 4

VIRTEX-6 FPGA DATAFLOW DETAIL


Memory Bank 1 Memory Bank 2 Memory Bank 3 Memory Bank 4

PCIe INTERFACE

(supports user installed IP)

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71671

4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC
XMC Interface
The Model 71671 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 3.125 GHz bit clock. With dual XMC connectors, the 71671 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as two 4X or one 8X gigabit serial links to the FPGA Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

PCI Express Interface


The Model 71671 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module.

Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15

Ordering Information
Model 71671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - XMC

Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector -105 Gigabit serial FPGA I/O through P16 connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71690

L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMC


General Information
Model 71690 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A 2-Channel high-speed data converter, it is suitable for connection directly to the RF port of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes an L-Band RF tuner, two A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 71690 includes general purpose and gigabit serial connectors for application-specific I/O . generator, and a PCIe interface complete the factory-installed functions and enable the 71690 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71690 factory-installed functions include two A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal
Ref In

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 installs the P14 PMC connector with 20 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.
RF In
MAX2112

Features

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA boosts LNB (low-noise block) antenna signal levels with up to 60 dB gain Programmable analog downconverter provides I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two 200 MHz 16-bit A/Ds digitize the I + Q signals synchronously Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multimodule synchronization VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Ref Out GC
12-BIT D/A

Sample Clk / Reference Clk In Trigger 1 Trigger 2 TIMING GENERATOR Clock / Sync / Gate / PPS

Ref A/D Clock/Sync

Control
I 200 MHz 16-BIT A/D Q 200 MHz 16-BIT A/D

TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B

16

16
IC
2

Timing Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


GTX
GTX

GTX

LVDS

16
QDRII+ SRAM 8 MB

16

16
QDRII+ SRAM 8 MB

16

16
QDRII+ SRAM 8 MB

16

16
QDRII+ SRAM 8 MB

16

16
Config FLASH 64 MB

8X

4X

4X

40

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

x8 PCIe

Gigabit FPGA Serial I/O GPIO (option 105) (option 104) P16 XMC P14 PMC

P15 XMC

Memory Banks 1 & 2

Memory Banks 3 & 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71690

L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMC


RF Tuner Stage
A front panel SSMC connector accepts L-Band signals between 925 MHz and 2175 MHz from an antenna LNB (low noise block). A Maxim MAX2112 tuner directly converts these L-Band signals to baseband using a broadband I/Q downconverter. The device includes an RF variable-gain LNA (low noise amplifier), a PLL (phaselocked loop) synthesized local oscillator, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cutoff frequency, and variable-gain baseband amplifiers. The fractional-N PLL synthesizer locks its VCO to the timing generator output, or to an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the RF LNA offer a programmable linear gain range of 60 dB. An integrated lowpass filter with variable bandwidth provides bandwidths ranging from 4 to 40 MHz, programmable with 8 bits of resolution.

A/D Clocking and Synchronization


An internal timing generator provides all timing, gating, triggering and synchronization functions required by the A/D converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the A/D sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillator). In this mode, the front panel SSMC clock input connector accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generator uses a front panel LVPECL 26-pin clock/sync connector for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the module. In the master mode, the LVPECL bus drives output timing signals to synchronize multiple slave modules, supporting synchronous sampling and sync functions across all connected modules.

A/D Acquisition IP Modules


The 71690 features two A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

A/D Converter Stage


The analog baseband I and Q analog tuner outputs are then applied to two Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

Memory Resources
The 71690 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.

from A/D (I)

from A/D (Q)

TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

to Mem Bank 1

to Mem Bank 2

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

PCIe

8X

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71690

L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - XMC


Each QDRII+ SRAM bank can be up to
8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board timing generator/synthesizer A/D Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Input Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus: 26-pin front panel connector LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Input Quantity: 2 Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T, or XC6VSX315T Custom I/O Option -104: Installs the PMC P14 connector with 20 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2 x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

XMC Interface
The Model 71690 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to a 6 GHz bit clock. With dual XMC connectors, the 71690 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.

PCI Express Interface


The Model 71690 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Ordering Information
Model 71690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Specifications
Front Panel Analog Signal Input Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuner Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution

Options: -062 -064 -104 -105 -150

-160

-155

-165

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71720

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - XMC
General Information
Model 71720 is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71720 includes general-purpose and gigabit-serial connectors for application-specific I/O . IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71720 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Onyx Architecture


Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71720 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules for simplifying data capture and data transfer.

Xilinx Virtex-7 FPGA


The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs the P14 PMC connector with 24 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support serial protocols.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 VITA 42.0 XMC compatible with switched-fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O

RF In

RF In

RF In

RF Out

RF Out

RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

16

Timing Bus

VCXO

VIRTEX-7 FPGA VX330T or VX690T


GTX
GTX

GTX

LVDS

CONFIG FLASH 1 GB

FPGA Config Bus

PCIe Gen. 3 x8

4X

4X

48

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

GATEXPRESS PCIe CONFIGURATION MANAGER

PCIe Gen. 3 x8 P15 XMC

Gigabit Serial I/O (option 105) P16 XMC

FPGA GPIO (option 104) P14 PMC

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71720
A/D Acquisition IP Modules
The 71720 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - XMC
GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA-PCIe configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a PCIe target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCIe discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCIe interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCIe interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded through PCIe as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCIe configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.

A/D Converter Stage


The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other module resources.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3 D/A loopback


TEST SIGNAL GENERATOR

to D/A

D/A Waveform Playback IP Module


The Model 71720 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either onboard memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

MEMORY CONTROL

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-7 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

48

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71720
Memory Resources
The 71720 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factoryinstalled functions, custom userinstalled IP within the FPGA can take advantage of the memories for many other purposes.

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-7 FPGA - XMC
When operating as a DUC, it interpolates
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs the PMC P14 connector with 24 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71720s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

XMC Interface
The Model 71720 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 GB/sec per lane. With dual XMC connectors, the 71720 supports x8 PCIe on the first XMC connector leaving the second connector free to support user-installed transfer protocols specific to the target application.

PCI Express Interface


The Model 71720 includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Ordering Information
Model 71720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA XMC XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation

Options: -073 -076 -104 -105

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 71760

4-Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA - XMC


General Information
Model 71760 is a member of the Onyx family of high-performance XMC modules based on the Xilinx Virtex-7 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its builtin data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71760 includes general-purpose and gigabitserial connectors for application-specific I/O. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable the 71760 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Onyx Architecture


Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 71760 factory-installed functions include four A/D acquisition IP modules for simplifying data capture and data transfer.

Xilinx Virtex-7 FPGA


The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs the P14 PMC connector with 24 pairs of LVDS connections to the FPGA for custom I/O. Option -105 installs the P16 XMC connector with dual 4X gigabit links to the FPGA to support serial protocols.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCIe Four 200 MHz 16-bit A/Ds 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization PCI Express (Gen. 1, 2 & 3) interface up to x8 Advanced reconfigurability features VITA 42.0 XMC compatible with switched fabric interfaces Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-7 FPGA for custom I/O

RF In

RF In

RF In

RF In

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-7 FPGA VX330T or VX690T


GTX
GTX

GTX

LVDS

CONFIG FLASH 1 GB

FPGA Config Bus

PCIe Gen. 3 x8

4X

4X

48

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

GATEXPRESS PCIe CONFIGURATION MANAGER

PCIe Gen. 3 x8 P15 XMC

Gigabit Serial I/O (option 105) P16 XMC

FPGA GPIO (option 104) P14 PMC

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71760

4-Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA - XMC


GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA-PCIe configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a PCIe target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCIe discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCIe interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCIe interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded through PCIe as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCIe configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.

A/D Converter Stage


The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other module resources.

A/D Acquisition IP Modules


The 71760 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3

from A/D Ch 4

TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

VIRTEX-7 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

PCIe

8X

Gigabit Serial I/O

4X

4X

FPGA GPIO

48

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 71760

4-Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA - XMC


external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71760s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.
A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Installs the PMC P14 connector with 24 LVDS pairs to the FPGA Option -105: Installs the XMC P16 connector configurable as one 8X or two 4X gigabit serial links to the FPGA Memory Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8 Gen. 3 available only with the VX330T-2 and VX690T-2 FPGAs Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard XMC module, 2.91 in. x 5.87 in.

Memory Resources
The 71760 architecture supports four independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

XMC Interface
The Model 71760 complies with the VITA 42.0 XMC specification. Two connectors each provide dual 4X links or a single 8X link with up to 10 Gb/sec per lane. With dual XMC connectors, the 71760 supports x8 PCIe on the first XMC connector leaving the second connector free to support userinstalled transfer protocols specific to the target application.

Ordering Information
Model 71760 Options: -073 -076 -104 -105 XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS FPGA I/O through P14 connector Gigabit serial FPGA I/O through P16 connector Description 4-Channel 200 MHz A/D with Virtex-7 FPGA - XMC

PCI Express Interface


The Model 71760 includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the module.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz

Contact Pentek for availability of rugged and conduction-cooled versions

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

RAD AR & SDR I/O - CompactPCI RADAR


MODEL
7250, 7350 7251, 7351 7252, 7352 7253, 7353 7256, 7356 7258, 7358 Cobalt 72620, 73620, 74620 Cobalt 72621, 73621, 74621 Cobalt 72630, 73630, 74630 Cobalt 72640, 73640, 74640 Cobalt 72641, 73641, 74641 Cobalt 72650, 73650, 74650 Cobalt 72651, 73651, 74651 Cobalt 72660, 73660, 74660 Cobalt 72661, 73661, 74661 Cobalt 72662, 73662, 74662 Cobalt 72670, 73670, 74670 Cobalt 72671, 73671, 74671 Cobalt 72690, 73690, 74690 Onyx 72720, 73720, 74720 Onyx 72760, 73760, 74760

DESCRIPTION
Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - 6U/3U cPCI 256- or 512-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - 6U/3U cPCI 32- or 64-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - 6U/3U cPCI 4/8-Channel DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - 6U/3U cPCI Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U/3U cPCI Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U/3U cPCI 3/6-Ch 200 MHz A/D, 2/4-Ch 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 3/6-Ch 200 MHz A/D, DDCs, DUC, 2/4-Ch. 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 1 GHz A/D and 1/2-Ch 1 GHz D/A, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 3.6 GHz or 2/4-Ch 1.8 GHz 12-bit A/D, Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch 3.6 GHz or 2/4-Ch 1.8 GHz 12-bit A/D, DDC, Virtex-6 FPGA - 6U/3U cPCI 2/4 500 MHz A/Ds, 1/2 DUCs, 2/4 800 MHz D/As, Virtex-6 FPGA - 6U/3U cPCI 2/4-Ch 500 MHz A/D w. DDC, DUC w. 2/4-Ch 800 MHz D/A, Virtex-6 FPGA - 6U/3U cPCI 4/8-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 200 MHz A/D with DDCs, Beamformer and Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 200 MHz A/D with 32/64-Ch DDC and Virtex-6 FPGA - 6U/3U cPCI 4/8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - 6U/3U cPCI 4/8-Ch 1.25 GHz D/A with DUC, Extend. Interpol. and Virtex-6 FPGA - 6U/3U cPCI 1/2-Ch L-Band RF Tuner, 2/4-Ch 200 MHz A/D, Virtex-6 FPGA - 6U/3U cPCI 3/6-Ch 200 MHz A/D, 2/4-Ch 800 MHz D/A, Virtex-67FPGA - 6U/3U cPCI 4/8-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - 6U/3U cPCI Customer Information

RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR

& & & & &

SDR SDR SDR SDR SDR

I/O I/O I/O I/O I/O

PMC/XMC PCI x16 PCI Express x 8 PCI Express 3U VPX

Last updated: February 2013


www.pentek.com

Models 7250, 7250D and 7350

Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - cPCI
General Information
Models 7250 and 7350 are cPCI Quad 200 MHz A/Ds. They consist of one Model 7150 Quad A/D mounted on a cPCI carrier. The Model 7250 is a 6U cPCI board, while the Model 7350 is a 3U cPCI board. Model 7250D is the same as the Model 7250, except it contains two 7150s rather than one. different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Models 7250 and 7350 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs the J3 connector (Model 7250) or the J2 connector (Model 7350) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O. With Model 7250D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA.

A/D Converter Stage


The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into Xilinx Virtex-5 FPGAs for routing, formatting and DDC signal processing operations.

Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory-shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of

Model 7350

Model 7250D

Clocking and Synchronization


The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus.
RF In
RF XFORMR

Features

Complete software radio interface solutions Four or eight 200 MHz, 16-bit A/Ds Up to 1 or 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D 200 or 135 MHz 16 BIT A/D

TTL In

Clock/Sync Bus

LVPECL Bus
XTL OSC

To All Sections

Timing Bus

Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T or LX155T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X LVDS

PCI X INTERFACE
64

Model 7250 and 7350 Block Diagram Model 7250D doubles all resources except the PCI Bridge

FPGA I/O (Option -104)

32

PCI-X BUS

Model 7250 uses J3 Model 7350 uses J2 Model 7250D uses J3 and J5
PCI BUS

PCI-TO-PCI BRIDGE

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7250, 7250D and 7350

Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - cPCI
Clocking and Synchronization
The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to two slave 7250Ds and three slave 7350s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

Specifications
Model 7250 or Model 7350: 4 A/Ds Model 7250D: 8 A/Ds Model 7250D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XCV5FX100T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Memory DDR2 SDRAM: Up to 2 GB in four banks PCI Interface PCI Bus: 32- or 64-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.

PCI Interface
Both Models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, and 66 MHz are supported.

Ordering Information
Model 7250 Description Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs 6U cPCI Octal 200 MHz, 16-bit A/D with four Virtex-5 FPGAs 6U cPCI Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs 3U cPCI FPGA I/O through cPCI J3 for 7250 or J2 for 7350; cPCI J3 and J5 for 7250D

Optional PCI Express Interface


For systems that require a PCI Express board interface, these Models can be optionally factory-configured with x4 PCI Express in the interface FPGA. Other serial protocols as well as different bus widths can be accommodated with custom IP cores.

7250D

7350

Options: -104

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7251, 7251D and 7351

256 or 512-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - cPCI


General Information
Models 7251 and 7351 are high-speed software radio cPCI boards. They consist of one Model 7151 Quad A/D digitizer with a factory-installed high-performance 256-channel DDC IP Core mounted on a cPCI carrier board. The Model 7251 is a 6U cPCI board, while the Model 7351 is a 3U cPCI board. Model 7251D is the same as the Model 7251, except it contains two 7151s rather than one.

Decimation and Filtering


All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 156.25 kHz to 1.25 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 64. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

A/D Converter Stage


The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into Xilinx Virtex-5 FPGAs for routing, formatting and DDC signal processing operations.

Model 7351

Model 7251D

Features

256 or 512 channels of DDC Four or eight 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization

DDC Input Selection and Tuning


These Models employ an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 256 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

Output Multiplexers and FIFOs


Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

Model 7251 and 7351 Block Diagram Model 7251D doubles all resources except the PCI Bridge
CH 1 RF In
RF XFORMR 200 MHz 16-bit A D

CH 2 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024

CH 1 I+Q
M U X

FIFO 1

CH 3 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A D

CH 2
M U X D G TAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024

CH 3 CH 4

I+Q

M U X

FIFO 2

PCI-X BUS CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 4: CH 193-256 DEC: 128 - 1024

CH 3
M U X D G TAL DOWNCONVERTER BANK 3: CH 129-192 DEC: 128 - 1024

CH 2 CH 3 CH 4

I+Q

M U X

FIFO 3

PCI-X NTERFACE Xilinx XC5VLX30T

PCI BUS 64 bits/ 66 MHz PCI-TO PCI BRIDGE

TTL In

CH 4 I+Q
M U X

FIFO 4

LVPECL Bus

XTAL OSC

XILINX XC5VSX95T
Timing Bus

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7251, 7251D and 7351

256 or 512-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - cPCI


Clocking and Synchronization
The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to two slave 7251Ds or three slave 7351s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

Specifications
Model 7251 or 7351: 4 A/Ds, 256-channel DDC Model 7251D: 8 A/Ds, 512-channel DDC Model 7251D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI Bus: 32 or 64 bits at 66 MHz and 32 or 64 bits at 33 MHz DMA: 8 channel demand-mode and chaining controller Local Bus: 64 bits at 33, 66 and 100 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: standard 6U cPCI board

PCI Interface
Both models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.

Ordering Information
Model 7251 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - 6U cPCI 512-Channel DDC with eight 200 MHz, 16-bit A/Ds - 6U cPCI 256-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U cPCI

7251D

7351

Options: -730 Two-slot heat sink

Contact Pentek for available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7252, 7252D and 7352

32 or 64-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - cPCI


General Information
Models 7252 and 7352 are high-speed software radio cPCI boards. They consist of one Model 7152 Quad A/D digitizer with a factory-installed high-performance 32-channel DDC IP Core mounted on a cPCI carrier board. The Model 7252 is a 6U cPCI board, while the Model 7352 is a 3U cPCI board. Model 7252D is the same as the Model 7252, except it contains two 7152s rather than one.

Decimation and Filtering


All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

A/D Converter Stage


The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into Xilinx Virtex-5 FPGAs for routing, formatting and DDC signal processing operations.

Model 7352

Model 7252D

Features

32 or 64-channel DDC with four or eight banks of 8 channels Four or eight 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths: 20 kHz to 10 MHz Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multiboard synchronization

DDC Input Selection and Tuning


These Models employ an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 32 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

Power Meters and Threshold Detectors


These models feature 32 power meters that continuously measure the individual average power output of each of the 32 DDC channels. The time constant of the averaging interval for each meter is programmable up to 16K samples. In addition, 32 threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.

Model 7252 and 7352 Block Diagram Model 7252D doubles all resources except the PCI Bridge
CH 1 RF In

RF XFORMR

200 MHz 16-bit A D


8X4 CHANNEL SUMMAT ON M U X DIG TAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 - 8192

CH 1 I+Q
M U X F I F 0 1 F I F 0 2

CH 2 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHO D DETECTORS

CH 3 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A D

CH 2
M U X

CH 3 CH 4

M U X

DIG TAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 - 8192

I+Q
POWER METER & THRESHO D DETECTORS

PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4

PCI BUS 64 bits/ 66 MHz

CH 1 Sample Clk In PPS In T M NG BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4


M U X D G TAL DOWNCONVERTER BANK 4: CH 25-32 DEC: 16 - 8192

CH 2 CH 3 CH 4

M U X

D G TAL DOWNCONVERTER BANK 3: CH 17-24 DEC: 16 - 8192

I+Q
POWER METER & THRESHO D DETECTORS

PCI-X NTERFACE Xilinx XC5VLX30T

TTL In

PCI-TO-PCI BRIDGE

CH 4
M U X

I+Q
POWER METER & THRESHO D DETECTORS

LVPECL Bus

XTAL OSC

Timing Bus

XILINX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7252, 7252D and 7352

32 or 64-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - cPCI


Output Multiplexers and FIFOs
Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

Specifications
Model 7252 or 7352: 4 A/Ds, 32-channel DDC Model 7252D: 8 A/Ds, 64-channel DDC Model 7252D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI Bus: 32 or 64 bits at 66 MHz and 32 or 64 bits at 33 MHz DMA: 8 channel demand-mode and chaining controller Local Bus: 64 bits at 33, 66 and 100 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board

Clocking and Synchronization


The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to two slave 7252Ds or three slave 7352s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

PCI Interface
Both models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.

Ordering Information
Model 7252 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - 6U cPCI 64-Channel DDC with eight 200 MHz, 16-bit A/Ds - 6U cPCI 32-Channel DDC with four 200 MHz, 16-bit A/Ds - 3U cPCI

7252D

7352

Options: -730 Two-slot heat sink

Contact Pentek for available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7253, 7253D and 7353

4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - cPCI


General Information
Models 7253 and 7353 are high-speed software radio boards designed for processing baseband RF or IF signals from a communications receiver. They feature four 200 MHz 16-bit A/Ds (Models 7253 and 7353) or eight A/Ds (Model 7253D). Each group of four A/Ds is supported by a high-performance 4-channel installed DDC and a complete set of beamforming functions. With built-in multiboard synchronization, they are ideally matched to the requirements of real-time software radio and radar systems. Model 7253 is a 6U cPCI board while Model 7353 is a 3U cPCI board. Model 7253D is the same as the 7253 except it provides twice the resources. achieved including one A/D driving all four DDC channels and each of the four A/Ds driving its own DDC bank. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency.

Decimation and Filtering


Each of the four DDC channels can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. The DDC core can be configured in four-channel mode with each channel offering decimations between 2 and 256, or in two-channel mode with each channel having a decimation range of 2 to 65536, for applications that require a wider range of decimations. The decimating filter for each DDC channel accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N.

Model 7353

Model 7253D

A/D Converter Stage


The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into Xilinx Virtex-5 FPGAs for routing, formatting and signal processing.

Features

Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel 6U and 3U cPCI boards 2 or 4 (Models 7253 and 7353) and 4 or 8 (Model 7753D) channels of DDC Four or eight 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 LVPECL clock/sync bus for multiboard synchronization

DDC Input Selection and Tuning


These Models employ an advanced FPGA-based digital downconverter engine consisting of two or four DDC channels. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC channel. In this way, many different configurations can be

Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the

Model 7253 and 7353 Block Diagram Model 7253D doubles all resources except the PCI Bridge
CH 1 RF In
RF XFORMR 200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER

SUM IN SUM OUT

AURORA G GAB T SERIAL NTERFACE F I F 0 1 F I F 0 2

4X 4X P15 XMC

CH 2 RF In

RF XFORMR

200 MHz 16-bit A D

I+Q CH 1
M U X

CH 3 RF In

RF XFORMR

200 MHz 16-bit A D

DIGITAL DOWNCONVERTER CH 1 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHO D DETECTORS

CH 4 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4
M U X

CH 2
M U X

DIGITAL DOWNCONVERTER CH 2 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHO D DETECTORS

PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4

PCI BUS

Sample Clock In PPS In TTL In LVDS Bus Timing Bus

CH 1 TIM NG BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4


M U X DIGITAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*

CH 2 CH 3 CH 4

M U X

DIGITAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHO D DETECTORS

PCI-X INTERFACE

XIL NX XC5VLX30T

PCI-TO-PCI BRIDGE

CH 4
M U X

I+Q
POWER METER & THRESHO D DETECTORS

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

XIL NX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7253, 7253D and 7353

4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - cPCI


calculated power levels exceed or fall

Clocking and Synchronization


The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to two slave 7253Ds or three slave 7353s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

below user-programmable thresholds, ideal for scanning and monitoring applications.

Beamformer
In addition to the A/Ds and DDCs, these Models include essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI bus. For larger systems, multiple Models can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.

XMC Interface
For large systems, multiple 7253s, 7353s or 7253Ds can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

Output Multiplexers and FIFOs


Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

PCI Interface
These models include an industry-standard interface fully compliant with PCI bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the boards. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.

PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

GA N

I Q

I Q

I
Q

I
Q

DIGITAL DOWNCONVERTER A

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT A

AURORA PORT

SUMMAT ON EXPANS ON CHAIN IN 1 25 GByte/sec x4 Au ora Link

From Previous Boa d

P15
GA N

DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

I
Q

I
Q

I
Q

I
Q

DIGITAL DOWNCONVERTER B

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT B

SUMMATION CHAIN BIT GROWTH COMPENSAT ON

I Q

I Q

I Q

To FIFO 1 (Final Result or Intermediate Result

GA N

I
Q

I
Q

I
Q

(DECIMATION: 2-256)*

Summa ion Chain Gain POWER METER & THRESHO D DETECT C

SUMMAT ON POWER METER & THRESHO D DETECT

DIGITAL DOWNCONVERTER C

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

AURORA PORT

SUMMAT ON EXPANS ON CHAIN OUT 1 25 GByte/sec x4 Au ora Link

To Next Board

GA N

P15 I
Q

(DECIMATION: 2-256)*

I Q

I Q

I
Q

DIGITAL DOWNCONVERTER D

Weight Phase I Weight Phase Q Weight Gain

POWER METER & THRESHO D DETECT D

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

BEAMFORMER DATA FLOW DETAIL

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7253, 7253D and 7353

4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - cPCI


Specifications
Model 7253 or 7353: 4-Channel Beamformer Model 7253D: 8-Channel Beamformer Model 7253D shown in the Specifications Front Panel Analog Signal Inputs (8) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources (4): Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clocks (4) Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 4 or 8 Center Frequency Tuning: 8 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, userprogrammable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four or eight channels onboard; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Eight FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI Interface PCI Bus: 32 or 64 bits at 66 MHz and 32 or 64 bits at 33 MHz DMA: 8 channel demand-mode and chaining controller Local Bus: 64 bits at 33, 66 and 100 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board

Ordering Information
Model 7253 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - 6U cPCI 8-Channel DDC with eight 200 MHz, 16-bit A/Ds and Beamformers - 6U cPCI 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - 3U cPCI

7253D

7353

Options: -730 Two-slot heat sink

Contact Pentek for available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7256, 7256D and 7356

Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
General Information
Models 7256 and 7356 are cPCI boards that include two 400 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. They consist of one Model 7156 PMC module mounted on a cPCI carrier. The Model 7652 is a 6U cPCI board, while the Model 7356 is a 3U cPCI board. Model 7256D is the same as the Model 7652, except it contains two 7156s rather than one.

Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR

A/D Converter Stage


The front end accepts two or four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other board resources. Model 7356 Model 7256D

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution Two or four 400 MHz, 14-bit A/Ds One or two digital upconverters Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus

400 MHz 14 BIT A/D

400 MHz 14 BIT A D

800 MHz 16 BIT D/A

800 MHz 16 BIT D A

TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS

DIGITAL UPCONVERTER

D/A Clock Bus


14 To All Sections 14 32

Timing Bus

VCXO

Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32

4X

Model 7256 and 7356 Block Diagram Model 7256D doubles all resources except the PCI Bridge

PCI X INTERFACE
64

PGA /O (Option -104)

32

PCI-X BUS

Model 7256 uses J3 Model 7356 uses J2 Model 7256D uses J3 and J5

PCI-TO PC BRIDGE

PCI BUS

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7256, 7256D and 7356

Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs the J3 connector (Model 7256) or the J2 connector (Model 7356) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O. With Model 7256D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs to the interface FPGA.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4) Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters (4) Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs (4) Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Environmental Specifications Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board

PCI Interface
All Models include an industrystandard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to two slave 7256Ds and three slave 7356s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources Ordering Information


Model 7256 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U cPCI

7256D

Up to four independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

7356

Specifications
Models 7256 or 7356: Dual version Model 7256D: Quad version Model 7256D shown in the Specifications Front Panel Analog Signal Inputs (4) Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB

Options: -104 FPGA I/O through cPCI J3 for 7256 or J2 for 7356; cPCI J3 and J5 for 7256D

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7258, 7258D and 7358

Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
General Information
Models 7258 and 7358 are cPCI boards that include two or four 500 MHz A/Ds and 800 MHz D/As and Virtex-5 FPGAs. They consist of one Model 7158 PMC module mounted on a cPCI carrier. The Model 7258 is a 6U cPCI board, while the Model 7358 is a 3U cPCI board. Model 7258D is the same as the Model 7258, except it contains two 7158s rather than one.

Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR

A/D Converter Stage


The front end accepts two or four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5463 12-bit 500 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other board resources. Model 7358 Model 7258D

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution Two or four 500 MHz, 12-bit A/Ds One or two digital upconverters Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus

500 MHz 12 BIT A/D

500 MHz 12 BIT A D

800 MHz 16 BIT D/A

800 MHz 16 BIT D A

TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS

DIGITAL UPCONVERTER

D/A Clock Bus


14 To All Sections 14 32

Timing Bus

VCXO

Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 256 MB

PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32

4X

Model 7258 and 7358 Block Diagram Model 7258D doubles all resources except the PCI Bridge

PCI X INTERFACE
64

PGA /O (Option -104)

32

PCI-X BUS

Model 7258 uses J3 Model 7358 uses J2 Model 7258D uses J3 and J5

PCI-TO PC BRIDGE

PCI BUS

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7258, 7258D and 7358

Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - cPCI
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs the J3 connector (Model 7258) or the J2 connector (Model 7358) with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O. With Model 7258D, the option provides an additional 16 pairs of LVDS connections through the J5 connector to the processing FPGA and 16 pairs to the interface FPGA.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4) Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters (4) Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs (4) Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (4) Processing FPGA: Two Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Two Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs the J3 and J5 cPCI connectors with 32 pairs of LVDS connections to the processing FPGA and 32 pairs of LVDS connections to the interface FPGA for custom I/O Environmental Specifications Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U cPCI board

PCI Interface
All Models include an industrystandard interface fully compliant with PCI bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported.

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to two slave 7258Ds and three slave 7358s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Ordering Information
Model 7258 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 6U cPCI Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - 3U cPCI

Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

7258D

7358

Options: -104 FPGA I/O through cPCI J3 for 7258 or J2 for 7358; cPCI J3 and J5 for 7258D -140 1 GB DDR2 SDRAM, Models 7258 and 7358; 2 GB DDR2 SDRAM, Model 7258D

Specifications
Models 7258 or 7358: Dual version Model 7258D: Quad version Model 7258D shown in the Specifications Front Panel Analog Signal Inputs (4) Input Type: Transformer-coupled, front panel female SMC connectors

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72620 73620 and 74620

3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
General Information
Models 72620, 73620 and 74620 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71620 XMC modules mounted on a cPCI carrier board. Model 72620 is a 6U cPCI board while the Model 73620 is a 3U cPCI board; both are equipped with one Model 71620 XMC. Model 74620 is a 6U cPCI board with two XMC modules rather than one. These models include three or sixA/Ds, one or two DUCs, two or four D/As and four or eight banks of memory. clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include three or six A/D acquisition and one or two D/A waveform playback IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73620; J3 connector, Model 72620; J3 and J5 connectors, Model 74620.

Model 74620 Model 73620

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three or six 200 MHz 16-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72620 Model 74620 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In

RF In

RF In

RF In

RF Out

RF Out

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

MODEL 73620 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

40

x4 PCIe

4X

GTX

QDRII+ option 150 40

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74620

Optional FPGA I/O (Option -104) J2

PCIe to PCI BRIDGE

DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

PCI/PCI-X BUS 32-bit, 33/66 MHz

Memory Banks 1 & 2

Memory Banks 3 & 4

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72620 73620 and 74620


A/D Acquisition IP Modules
These models feature three or six A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts three or six fullscale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three or six Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Digital Upconverter and D/A Stage


One or two TI DAC5688 DUCs (digital upconverters) and D/As accept baseband real or complex data streams from the FPGA and provide that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes, the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.
from A/D Ch 1 from A/D Ch 2 from A/D Ch 3

to D/A D/A loopback


TEST SIGNAL GENERATOR

D/A Waveform Playback IP Modules


These models include one or two factory-installed sophisticated D/A Waveform Playback IP modules. Linked-list controllers allow users to easily play back to the dual D/As waveforms stored in either on-board memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

MEMORY CONTROL

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

4X PCIe

40 FPGA I/O

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72620 73620 and 74620

3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
Each QDRII+ SRAM bank can be up
to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73620; J3 connector, Model 72620; J3 and J5 connectors, Model 74620 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73620: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73620: 32 bits only.

Specifications
Model 72620 or Model 73620: 3 A/Ds, 1 DUC, 2 D/As Model 74620: 6 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz

Ordering Information
Model 72620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 6U cPCI 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA 3U cPCI 6-Channel 200 MHz A/D and 4-Channel 800 MHz D/A and two Virtex-6 FPGAs - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73620; J3 connector, Model 72620; J3 and J5 connectors, Model 74620 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

73620

74620

Options: -062 -064 -104

-150

-160

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 72621, 73621 and 74621

3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
General Information
Models 72621, 73621 and 74621 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71621 XMC modules mounted on a cPCI carrier board. Model 72621 is a 6U cPCI board while the Model 73621 is a 3U cPCI board; both are equipped with one Model 71621 XMC. Model 74621 is a 6U cPCI board with two XMC modules rather than one. These models include three or six A/Ds, three or six multiband DDCs, one ot two DUCs, two or four D/As and four or eight banks of memory. ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include three or six A/D acquisition and one or two D/A waveform playback IP modules. Each of the acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core,
Block Diagram, Model 72621 Model 74621 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In

Model 74621 Model 73621

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed.
RF In RF In RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three or six 200 MHz 16-bit A/Ds Three or six multiband DDCs (digital downconverters) One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization

RF In

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


GTX

MODEL 73621 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

4X

4X

x4 PCIe

4X

GTX

QDRII+ option 150

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Aurora 4X I/O Sum from previous board J2

4X

Sum to next board

PCIe to PCI BRIDGE

DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Aurora Gigabit Serial I/O

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74621

Sum from previous board

Sum to next board

PCI to PCI BRIDGE

PCI/PCI-X BUS 32-bit, 33/66 MHz

Memory Banks 1 & 2

Memory Banks 3 & 4

J3

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 72621, 73621 and 74621


A/D Acquisition IP

3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple boards can be chained together via the built-in Xilinx Aurora gigabit serial interfaces through the J3 and J5 connectors. This allows summation across channels on multiple boards.

Modules
These models feature three or six A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

Beamformer IP Cores
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers.

D/A Waveform Playback IP Modules


The factory-installed functions include sophisticated D/A Waveform Playback IP modules. Linked-list controllers allow users to easily play back to the dual D/As waveforms stored in either on-board memory or off- board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3 D/A loopback

to D/A

INPUT MULTIPLEXER

TEST SIGNAL GENERATOR

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC.
MEMORY CONTROL

MUX

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

4X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 72621, 73621 and 74621

3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts three or six analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three or six Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Digital Upconverter and D/A Stage


One or two TI DAC5688 DUCs (digital upconverters) and D/As accept baseband real or complex data streams from the FPGA and provide that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to create a total range from 2x to 524,288x.

Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alter-

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73621: 32 bits only.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 72621, 73621 and 74621

3 or 6-Channel 200 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
Specifications
Model 72621 or Model 73621: 3 A/Ds, 3 DDCs, 1 DUC, 2 D/As Model 74621: 6 A/Ds, 6 DDCs, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (3 or 6) Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolators (1 or 2) Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformers (1 or 2) Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via J3 connector using Aurora protocol; via J3 and J5 for Model 74621 Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs (2 or 4) Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73621: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Ordering Information
Model 72621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 6U cPCI 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 3U cPCI 6-Channel 200 MHz A/D with DDCs, DUCs with 4-Channel 800 MHz D/A, and two Virtex-6 FPGAs 6U cPCI XC6VLX240T XC6VSX315T Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

73621

74621

Options: -062 -064 -150

-160

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72630, 73630 and 74630

1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/A with Virtex-6 FPGA - cPCI
General Information
Models 72630, 73630 and 74630 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71630 XMC modules mounted on a cPCI carrier board. Model 72630 is a 6U cPCI board while the Model 73630 is a 3U cPCI board; both are equipped with one Model 71630 XMC. Model 74630 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 1 GHz A/D and D/A converters and four or eight banks of memory clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these modles to operate as complete turnkey solutions, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include one or two A/D acquisition and one or two D/A waveform playback IP module. IP modules for either DDR3 or QDRII+ memories, controllers for all data

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73630; J3 connector, Model 72630; J3 and J5 connectors, Model 74630.

Model 74630

Model 73630

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One or two 1 GHz 12-bit A/D One or two 1 GHz 16-bit D/A Up to 2 or 4 GB of DDR3 SDRAM; or: 16 MB or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL sync bus for multimodule synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72630 Model 74630 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In

RF Out

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Sync In

1 GHz 12-BIT A/D

A/D Sync Bus


Gate In Sync In

D/A Clock/Sync Bus


12

1 GHz 16-BIT D/A 16

D/A Sync Bus


VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

MODEL 73630 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 Config FLASH 64 MB

40

x4 PCIe

4X

GTX

40

Memory Banks 1 & 2 DDR3 option 155 PCIe QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB

Memory Banks 3 & 4 DDR3 option 165

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74630

to PCI Optional BRIDGE FPGA I/O (Option -104)

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

QDRII+ option 150

J2

PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72630, 73630 and 74630


A/D Acquisition IP Module
These models feature one or two A/D Acquisition IP Modules for easy capture and data moving. The IP module can receive data from the A/D, a test signal generator, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/A with Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts one or two analog HF or IF input on front panel SSMC connectors with transformer coupling into one or two Texas Instruments ADS5400 1 GHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. Two or four front panel 7-pin LVPECL Sync connectors allow multiple boards to be synchronized. One connector for the A/D and one for the D/A provide sync and gate signals.

D/A Converter Stage


The 71630 features one or two TI DAC5681Z 1 GHz, 16-bit D/As. The converters have an input sample rate of 1 GSPS, allowing them to acept full rate data from the FPGA. Additionally, the D/As include a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through front panel SSMC connectors.

Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to

from A/D D/A loopback


TEST SIGNAL GENERATOR

to D/A

D/A Waveform Playback IP Modules


The factory-installed functions include one or two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users to easily play back waveforms stored in either on-board memory or offboard host memory to the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROLLER MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP) 4X PCIe 40 FPGA I/O

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72630, 73630 and 74630

1- or 2-Channel 1 GHz A/D, 1- or 2-Channel 1 GHz D/A with Virtex-6 FPGA - cPCI
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73630: 32 bits only. External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus (1 or 2): 7-pin connectors, LVPECL bus for sync and gate, one A/D connector and one D/A connector External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73630; J3 connector, Model 72630; J3 and J5 connectors, Model 74630 Memory Banks (1 or 2) Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73630: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Specifications
Model 72630 or Model 73630: 1 A/D, 1 D/A Model 74630: 2 A/Ds, 2 D/As Front Panel Analog Signal Inputs (1 or 2) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converters (1 or 2) Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converters (1 or 2) Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs (1 or 2) Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources (1 or 2) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be locked to an external 4 to 200 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock

Ordering Information
Model 72630 73630 74630 Options: -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73630; J3 connector, Model 72630; J3 and J5 connectors, Model 74630 -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required -002* -062 -064 -104 Description 1 GHz A/D and D/A, Virtex-6 FPGA - 6U cPCI 1 GHz A/D and D/A, Virtex-6 FPGA - 3U cPCI Two 1 GHz A/D and D/A, Virtex-6 FPGA - 6U cPCI

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72640, 73640 and 74640

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - cPCI
General Information
Models 72640, 73640 and 74640 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71640 XMC modules mounted on a cPCI carrier board. Model 72640 is a 6U cPCI board while the Model 73640 is a 3U cPCI board; both are equipped with one Model 71640 XMC. Model 74640 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit A/D converters and four or eight banks of memory. generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include one or two A/D acquisition IP modules. In addition, IP modules for DDR3 memories, controllers for all data clocking and synchronization functions, a test signal

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640.

Model 74640

Model 73640

Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One or two 1-channel mode with 3.6 GHz, 12-bit A/Ds Two or four 2-channel mode with 1.8 GHz, 12-bit A/Ds 2 or 4 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72640 Model 74640 doubles all resources except the PCI-to-PCI Bridge
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In

RF In

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Reset In Ref Clk In Ref Clk Out

3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-bit A/D


12 12

Sync Bus

VIRTEX-6 FPGA LX130T, LX240T or SX315T MODEL 73640 INTERFACES ONLY VIRTEX-6 FPGA
LVDS LVDS

GTX

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

40

GTX

x4 PCIe

4X

40

to PCI Optional BRIDGE FPGA I/O (Option -104)

PCIe

Memory Banks 1 & 2

Memory Banks 3 & 4

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74640

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

J2

PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72640, 73640 and 74640

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing these models to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple boards can be synchronized using the Cobalt high speed sync board to drive the sync bus.

Memory Resources
The Cobalt architecture supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

A/D Acquisition IP Modules


These models feature one or two A/D Acquisition IP Modules for easy capture and data moving. The IP modules can receive data from the A/Ds, or a test signal generator. The IP modules have associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73640: 32 bits only.

Clocking and Synchronization


These models accept a 1.8 GHz dualedge sample clock via front panel SSMC connectors. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple boards to be

from A/D

from A/D
TEST SIGNAL GENERATOR

VIRTEX-6 FPGA DATAFLOW DETAIL


(Two channel mode shown) INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE

MEMORY CONTROLLER PCIe INTERFACE

MEMORY CONTROLLER

(supports user installed IP) to Mem Bank 1 to Mem Bank 2 4X PCIe 40 FPGA I/O to Mem Bank 3 to Mem Bank 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72640, 73640 and 74640

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - cPCI
Specifications
Model 72640 or Model 73640: One A/D Model 74640: Two A/Ds Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources (1 or 2) Front panel SSMC connector Sync Bus (1 or 2) Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 Memory Banks (1 or 2) Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73640: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Ordering Information
Model 72640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 3U cPCI 2-Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - 6U cPCI

73640

74640

Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS I/O between the FPGA and J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72641, 73641 and 74641

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - cPCI
General Information
Models 72641, 73641 and 74641 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71641 XMC modules mounted on a cPCI carrier board. Model 72641 is a 6U cPCI board while the Model 73641 is a 3U cPCI board; both are equipped with one Model 71641 XMC. Model 74641 is a 6U cPCI board with two XMC modules rather than one. These models include one or two 3.6 GHz, 12-bit A/D converters and four or eight banks of memory. and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73641; J3 connector, Model 72641; J3 and J5 connectors, Model 74641.

A/D Converter Stage


The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 71641 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple modules. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include one or two A/D acquisition IP modules. In addition, IP modules for DDR3 memories, controllers for all data clocking

Model 74641

Model 73641

Features

Ideal radar and software radio interface solution One or two 1-channel mode with 3.6 GHz, 12-bit A/Ds Two or four 2-channel mode with 1.8 GHz, 12-bit A/Ds Programmable one- or twochannel DDC (Digital Downconverter) 2 or 4 GB of DDR3 SDRAM Sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72641 Model 74641 doubles all resources except the PCI-to-PCI Bridge
Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In

RF In

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Reset In Ref Clk In Ref Clk Out

3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-bit A/D


12 12

Sync Bus

VIRTEX-6 FPGA SX315T MODEL 73641 INTERFACES ONLY VIRTEX-6 FPGA


LVDS LVDS

GTX

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

40

GTX

x4 PCIe

4X

40

to PCI Optional BRIDGE FPGA I/O (Option -104)

PCIe

Memory Banks 1 & 2

Memory Banks 3 & 4

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74641

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

J2

PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72641, 73641 and 74641


A/D Acquisition IP Modules
These models feature one or two A/D Acquisition IP Modules for easy capture and data moving. The IP modules can receive data from the A/Ds, or a test signal generator. The IP modules have associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - cPCI
DDC IP Cores
Within the FPGA is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the A/D at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the A/Ds 1.8 GHz two-channel operation . In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 16-bit I + 16-bit Q samples at a rate of s/N.

Clocking and Synchronization


These models accept a 1.8 GHz dualedge sample clock via front panel SSMC connectors. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multipin sync bus connector allows multiple boards to be synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple boards can be synchronized using the Cobalt high-speed sync board to drive the sync bus.

Memory Resources
The Cobalt architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.

from A/D

from A/D

VIRTEX-6 FPGA DATAFLOW DETAIL


*Two channel mode shown. Programmable decimation of 8, 16 or 32 available in one channel mode.
INPUT MULTIPLEXER TEST SIGNAL GENERATOR DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT

DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT

DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE MEMORY CONTROLLER A/D ACQUISITION IP MODULE PCIe INTERFACE to MEM CONTROL

DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER

to Mem Bank 1

to Mem Bank 2

4X 4x PCIe

FPGA GPIO

40

to Mem Bank 3

to Mem Bank 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72641, 73641 and 74641

1- or 2-Channel 3.6 GHz and 2- or 4-Channel 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - cPCI
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73641: 32 bits only. Sample Clock Sources (1 or 2) Front panel SSMC connector Sync Bus (1 or 2) Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input (1 or 2) Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 Memory Banks (1 or 2) Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73641: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Specifications
Model 72641 or Model 73641: One A/D Model 74641: Two A/Ds Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converters (1 or 2) Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters (2 or 4) Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation

Ordering Information
Model 72641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 6U cPCI 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 3U cPCI 2-Ch. 3.6 GHz or 4-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - 6U cPCI

73641

74641

Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T LVDS I/O between the FPGA and J2 connector, Model 73640; J3 connector, Model 72640; J3 and J5 connectors, Model 74640 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72650, 73650 and 74650

2- or 4-Channel 500 MHz A/D, DUC with 2-or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
General Information
Models 72650, 73650 and 74650 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71650 XMC modules mounted on a cPCI carrier board. Model 72650 is a 6U cPCI board while the Model 73650 is a 3U cPCI board; both are equipped with one Model 71650 XMC. Model 74650 is a 6U cPCI board with two XMC modules rather than one. These models include two or four A/Ds, one or two DUCs, two or four D/As and four banks of memory. clocking and synchronization functions, a test signal generator and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these modles include two or four A/D acquisition and one or two D/A waveform playback IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73650; J3 connector, Model 72650; J3 and J5 connectors, Model 74650.

Model 74650 Model 73650

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two or four 500 MHz 12-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72650 Model 74650 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In

RF In

RF Out

RF Out

A/D Clock/Sync Bus

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

500 MHz 12-BIT A/D

500 MHz 12-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

Timing Bus

MODEL 73650 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

40

x4 PCIe

4X

GTX

QDRII+ option 150 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74650

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

Memory Banks 1 & 2

Memory Banks 3 & 4

J2

PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72650, 73650 and 74650


A/D Acquisition IP Modules
These models feature two A/D Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

2- or 4-Channel 500 MHz A/D, DUC with 2-or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts two or four full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two or four Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Digital Upconverter and D/A Stage


One or two TI DAC5688 DUCs and D/As accept a baseband real or complex data streams from the FPGA and provide that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.
from A/D Ch 1 from A/D Ch 2

to D/A D/A loopback TEST SIGNAL GENERATOR

D/A Waveform Playback IP Modules


These models include one or two factory-installed sophisticated D/A Waveform Playback IP modules. Linked-list controllers allow users to easily play back waveforms stored in either on-board memory or off- board host memory to the dual D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

MEMORY CONTROL

to Mem Bank 3

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

4X PCIe

40 FPGA I/O

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72650, 73650 and 74650

2- or 4-Channel 500 MHz A/D, DUC with 2-or 4-Channel 800 MHz D/A, Virtex-6 FPGA - cPCI
boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin front panel connector LVPECL bus includes, clock/sync/ gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73650; J3 connector, Model 72650; J3 and J5 connectors, Model 74650 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73650: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73650: 32 bits only.

Specifications Ordering Information


Model 72650 Description Two 500 MHz A/Ds, One DUC, Two 800 MHz D/As with Virtex-6 FPGA - 6U cPCI Two 500 MHz A/Ds, One DUC, Two 800 MHz D/As with Virtex-6 FPGA - 3U cPCI Four 500 MHz A/Ds, Two DUCs, Four 800 MHz D/As with Virtex-6 FPGA - 6U cPCI

73650

74650

Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73650; J3 connector, Model 72650; J3 and J5 connectors, Model 74650 -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required

Models 72650 and 73650: 2 A/Ds, 1 DUC, 2 D/As Model 74650: 4 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) (2 or 4) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) (2 or 4) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 72651, 73651 and 74651

2 or 4-Channel 500 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
General Information
Models 72651, 73651 and 74651 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71651 XMC modules mounted on a cPCI carrier board. Model 72651 is a 6U cPCI board while the Model 73651 is a 3U cPCI board; both are equipped with one Model 71651 XMC. Model 74651 is a 6U cPCI board with two XMC modules rather than one. These models include two or four A/Ds, two or four multiband DDCs, one ot two DUCs, two or four D/As and three or six banks of memory. ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include two or four A/D acquisition and one or two D/A waveform playback IP modules. Each of the acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core,
Block Diagram, Model 72651 Model 74651 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

Model 74651 Model 73651

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed.
RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two or four 500 MHz 12-bit A/Ds Two or four multiband DDCs (digital downconverters) Two or four 800 MHz 16-bit D/As One or two DUCs (digital upconverters) One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or 16 or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization

RF In

RF In

RF Out

A/D Clock/Sync Bus

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

500 MHz 12-BIT A/D

500 MHz 12-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

VCXO

VIRTEX-6 FPGA LX240T or SX315T


GTX

Timing Bus

MODEL 73651 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

4X

4X

4X
PCIe to PCI BRIDGE

GTX

QDRII+ option 150

QDRII+ option 160

Aurora 4X I/O Sum from previous board J2

4X

PCIe to PCI Sum to BRIDGE

DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Aurora Gigabit Serial I/O

From/To Other XMC Module of MODEL 74650

next board

Sum from previous board

Sum to next board

PCI to PCI BRIDGE

Memory Banks 1 & 2

PCI/PCI-X BUS 32-bit, 33/66 MHz

J3

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 72651, 73651 and 74651


A/D Acquisition IP Modules
These models feature two or four A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

2 or 4-Channel 500 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
frequency. Each DDC can have its own unique decimation setting, supporting as many as two or four different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple models can be chained together via a built-in Xilinx Aurora gigabit serial interface through the dual 4X serial connector. This allows summation across channels on multiple boards.

Beamformer IP Core
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average

D/A Waveform Playback IP Modules


The factory-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. A linked-list controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or offboard host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

from A/D Ch 1

from A/D Ch 2 D/A loopback


INPUT MULTIPLEXER

to D/A

TEST SIGNAL GENERATOR

DDC DEC: 2 TO 131027


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 131027


POWER METER & THRESHOLD DETECT

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MEMORY CONTROL

MUX

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

VIRTEX-6 FPGA DATAFLOW DETAIL

4X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 72651, 73651 and 74651

2 or 4-Channel 500 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
A/D Converter Stage
The front end accepts two or four analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two or four Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Digital Upconverter and D/A Stage


One or two TI DAC5688 DUCs (digital upconverters) and D/As accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to create a total range from 2x to 524,288x.

Memory Resources
The Cobalt architecture supports up to three or six independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boardss DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alter-

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73651: 32 bits only.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 72651, 73651 and 74651

2 or 4-Channel 500 MHz A/D with DDC, DUC with 2- or 4-Channel 800 MHz D/A, with Virtex-6 FPGA - cPCI
Specifications
Model 72651 or Model 73651: 2 A/Ds, 2 DDCs, 1 DUC, 2 D/As Model 74651: 4 A/Ds, 4 DDCs, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (2 or 4) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) (2 or 4) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (Option -014) (2 or 4) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters (2 or 4) Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolators (1 or 2) Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformers (1 or 2) Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via a dual 4X connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs (2 or 4) Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/ A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Memory (1 or 2) Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73651: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Ordering Information
Model 72651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 6U cPCI 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA 3U cPCI 4-Channel 500 MHz A/D with DDCs, DUCs with 4-Channel 800 MHz D/A, and two Virtex-6 FPGAs 6U cPCI

73651

74651

Options: 002* -014 -062 -064 -150 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72660, 73660 and 74660

4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - cPCI


General Information
Models 72660, 73660 and 74660 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71660 XMC modules mounted on a cPCI carrier board. Model 72660 is a 6U cPCI board while the Model 73660 is a 3U cPCI board; both are equipped with one Model 71660 XMC. Model 74660 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds and four or eight banks of memory. generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features Virtex-6 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factoryinstalled functions of these models include four or eight A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73660; J3 connector, Model 72660; J3 and J5 connectors, Model 74660.

Model 74660

Model 73660

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds Up to 2 or 4 GB of DDR3 SDRAM; or: 32 or 64 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72660 Model 74660 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In

RF In

RF In

RF In

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

MODEL 73660 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

40

4X
PCIe to PCI BRIDGE

GTX

From/To Other XMC Module of MODEL 74660

QDRII+ option 150 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

J2

PCI/PCI-X BUS 32-bit, 33/66 MHz

Memory Banks 1 & 2

Memory Banks 3 & 4

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72660, 73660 and 74660

4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - cPCI


A/D Converter Stage
The front end accepts four or eight full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the

A/D Acquisition IP Modules


These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73660: 32 bits only.
from A/D Ch 3 from A/D Ch 4

from A/D Ch 1

from A/D Ch 2

TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

4X PCIe

40 FPGA I/O

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72660, 73660 and 74660

4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - cPCI


Specifications
Model 72660 or Model 73660: 4 A/Ds Model 74660: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources (1 or 2) On-board clock synthesizers Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin front panel connector; LVPECL bus includes, clock/ sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73660; J3 connector, Model 72660; J3 and J5 connectors, Model 74660 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73660: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Ordering Information
Model 72660 Description 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA 6U cPCI 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA 3U cPCI 8-Channel 200 MHz 16-bit A/D with two Virtex-6 FPGAs - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73660; J3 connector, Model 72660; J3 and J5 connectors, Model 74660 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

73660

74660

Options: -062 -064 -104

-150

-160

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72661, 73661 and 74661

4- or 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - cPCI
General Information
Models 72661, 73661 and 74661 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71662 XMC modules mounted on a cPCI carrier board. Model 72661 is a 6U cPCI board while the Model 73661 is a 3U cPCI board; both are equipped with one Model 71661 XMC. Model 74661 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds, four or eight multiband DDCs and four or eight banks of memory. QDRII+ memories, controllers for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory- installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include four or eight A/D acquisition IP modules. Each of the acquisition IP modules contains a powerful, programmable DDC IP core. IP modules for either DDR3 or

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed.

Model 74661

Model 73661

Block Diagram, Model 72661 Model 74661 doubles all resources except the PCI-to-PCI Bridge

RF In

RF In

RF In

RF In

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds Four or eight multiband DDCs (digital downconverters) One or two multiboard programmable beamformers Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


GTX

MODEL 73661 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

4X

4X

x4 PCIe

4X

GTX

QDRII+ option 150

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Aurora 4X I/O Sum from previous board J2

4X

Aurora Gigabit Serial I/O

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74661

Sum to next board

PCIe to PCI BRIDGE

DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Sum from previous board

Sum to next board

PCI to PCI BRIDGE

PCI/PCI-X BUS 32-bit, 33/66 MHz

Memory Banks 1 & 2

Memory Banks 3 & 4

J3

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72661, 73661 and 74661


A/D Acquisition IP Modules
These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

4- or 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - cPCI
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 71661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.

Beamformer IP Cores
In addition to the DDCs, these models feature one or two complete beamforming subsystems. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation

A/D Converter Stage


The front end accepts four or eight analog HF or IF inputs on front panel SSMC connectors with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources.

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage
from A/D Ch 2 from A/D Ch 3 from A/D Ch 4

from A/D Ch 1

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536

TEST SIGNAL GENERATOR

INPUT MULTIPLEXER

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

MUX

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

4X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72661, 73661 and 74661

4- or 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - cPCI
controlled crystal oscillator. In this mode,
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation Beamformers (1 or 2) Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73661: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73661: 32 bits only.

Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Ordering Information
Model 72661 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 6U cPCI 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - 3U cPCI 8-Channel 200 MHz A/D with DDCs and Virtex-6 FPGAs - 6U cPCI XC6VLX240T XC6VSX315T Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Specifications
Model 72661 or Model 73661: 4 A/Ds Model 74660: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (4 or 8) Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients

73661

74661

Options: -062 -064 -150

-160

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72662, 73662 and 74662

4- or 8-Channel 200 MHz A/D with 32- or 64-Channel DDC and Virtex-6 FPGA - cPCI
General Information
Models 72662, 73662 and 74662 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71662 XMC modules mounted on a cPCI carrier board. Model 72662 is a 6U cPCI board while the Model 73662 is a 3U cPCI board; both are equipped with one Model 71662 XMC. Model 74662 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds, 32 or 64 multiband DDCs and four or eight banks of memory. trigger functions, a test signal generator, voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include four or eight A/D acquisition IP modules. Each of the acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of all data clocking, synchronization, gate and

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73662; J3 connector, Model 72662; J3 and J5 connectors, Model 74662.

Model 74662

Model 73662

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 200 MHz 16-bit A/Ds 32 or 64 channels of multiband DDCs (digital downconverters) Up to 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72662 Model 74662 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In

RF In

RF In

RF In

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


LVDS

MODEL 73662 INTERFACES ONLY


32 32 DDR3 SDRAM 512 MB 32 DDR3 SDRAM 512 MB 32 DDR3 SDRAM 512 MB 16 Config FLASH 64 MB

GTX

VIRTEX-6 FPGA
LVDS

40

GTX

DDR3 SDRAM 512 MB

x4 PCIe

4X

40

to PCI Optional BRIDGE FPGA I/O (Option -104)

PCIe

Memory Banks 1 & 2 DDR3 option 155

Memory Banks 3 & 4 DDR3 option 165

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74662

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

J2

PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72662, 73662 and 74662


A/D Acquisition IP Modules
These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

4- or 8-Channel 200 MHz A/D with 32- or 64-Channel DDC and Virtex-6 FPGA - cPCI
of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a reference clock, typically 10 MHz, for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

A/D Converter Stage


The front end accepts four or eight analog HF or IF inputs on front panel SSMC connectors with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources.
from A/D Ch 1

Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with DDR3 SDRAM.
from A/D Ch 2 from A/D Ch 3 from A/D Ch 4

TEST SIGNAL GENERATOR

INPUT MULTIPLEXER

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps
DIGITAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 TO 8192
.

DIGITAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 TO 8192


.

DIGITAL DOWNCONVERTER BANK 3: CH 17-24 DEC: 16 TO 8192


.

DIGITAL DOWNCONVERTER BANK 4: CH 18-32 DEC: 16 TO 8192


.

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

32 Memory Bank 1

32 Memory Bank 2

32 Memory Bank 3

32 Memory Bank 4

4X PCIe

40 FPGA I/O

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72662, 73662 and 74662

4- or 8-Channel 200 MHz A/D with 32- or 64-Channel DDC and Virtex-6 FPGA - cPCI
Each DDR3 SDRAM bank can be up to
512 MB deep and is an integral part of the Boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array (1 or 2) Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73662; J3 connector, Model 72662; J3 and J5 connectors, Model 74662 MemoryBanks (1 or 2) Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73662: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73662: 32 bits only.

Specifications
Model 72662 or Model 73662: 4 A/Ds, 32 DDCs Model 74660: 8 A/Ds, 64 DDCs Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters (32 or 64) Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation

Ordering Information
Model 72662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 6U cPCI 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - 3U cPCI 8-Ch 200 MHz A/D with 64-Ch DDC and Virtex-6 FPGA - 6U cPCI XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73662; J3 connector, Model 72662; J3 and J5 connectors, Model 74662 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

73662

74662

Options: -062 -064 -104

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72670, 73670 and 74670

4- or 8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - cPCI


General Information
Models 72670, 73670 and 74670 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71670 XMC modules mounted on a cPCI carrier board. Model 72670 is a 6U cPCI board while the Model 73670 is a 3U cPCI board; both are equipped with one Model 71670 XMC. Model 74670 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight D/As, four or eight DUCs, and four or eight banks of memory. controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions in these models include four or eightD/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories,

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73670; J3 connector, Model 72670; J3 and J5 connectors, Model 74670.

Model 74670 Model 73670

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 1.25 GHz 16-bit D/As Four or eight digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-or Quad Sync clock/ sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72670 Model 74670 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Trigger In

RF Out

RF Out

RF Out

RF Out

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

Clock/Sync Bus A Clock/Sync Bus B

Gate In Sync In

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

mSync Bus A
Gate In Sync In

mSync Bus B

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

MODEL 73670 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

40

x4 PCIe

4X

GTX

Memory Banks 1 & 2 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe

Memory Banks 3 & 4

PCIe to PCI BRIDGE

From/To Other XMC Module of Model 74670

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

J2

PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72670, 73670 and 74670

4- or 8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - cPCI


Digital Upconverter and D/A Stage
Two or four Texas Instruments DAC3484s provide four or eight DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. Analog output is through four front panel SSMC connectors. provide a 10 MHz reference clock for synchronizing the internal oscillator. A pair of front panel Sync connectors allows multiple boards to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave board. For larger systems, the Pentek Model 7291, 7391 and 7291D Cobalt Synchronizers can drive multiple 72670s 73670s and 74670s respectively, thereby enabling large, multichannel synchronous configurations.

Memory Resources
The architecture of these models supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to
16
TEST SIGNAL GENERATOR

D/A Waveform Playback IP Module


The factory-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. Four or eight linked list controllers support waveform generation to the four or eight D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4, as well as to the other four channels of Model 74670. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 or 128 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths
16 to D/A Ch 3 & 4

to D/A Ch 1 & 2

DATA INTERLEAVER

DATA INTERLEAVER

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

MEMORY CONTROL

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 1

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 2

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 3

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

4X PCIe

40 FPGA I/O

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72670, 73670 and 74670

4- or 8-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - cPCI


of 32 or 64 bits and data rates of 33 and
66 MHz are supported. Model 73670: 32 bits only. External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus (1 or 2): 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73670; J3 connector, Model 72670; J3 and J5 connectors, Model 74670 Memory Banks (1 or 2) Four or eight 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73670: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Specifications
Models 72670 and 73670: 4-Channel DUC, 4-channel D/A Model 74670: 8-Channel DUC, 4-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference

Ordering Information
Model 72670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 6U cPCI 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - 3U cPCI 8-Channel 1.25 GHz D/A with Virtex-6 FPGA - 6U cPCI

73670

74670

Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73670; J3 connector, Model 72670; J3 and J5 connectors, Model 74670 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72671, 73671 and 74671

4- or 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - cPCI
General Information
Models 72671, 73671 and 74671 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71671 XMC modules mounted on a cPCI carrier board. Model 72671 is a 6U cPCI board while the Model 73671 is a 3U cPCI board; both are equipped with one Model 71671 XMC. Model 74671 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight D/As with a wide range of programmable interpolation factors, four or eight DUCs, and four or eight banks of memory. modules for DDR3 SDRAM memories, controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions in these models include four or eight D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73671; J3 connector, Model 72671; J3 and J5 connectors, Model 74671.

Model 74671 Model 73671

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four or eight 1.25 GHz 16-bit D/As Four or eight digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 or 4 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-or Quad Sync clock/ sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72671 Model 74671 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Trigger In

RF Out

RF Out

RF Out

RF Out

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

Clock/Sync Bus A Clock/Sync Bus B

Gate In Sync In

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

mSync Bus A
Gate In Sync In

mSync Bus B

VCXO

VIRTEX-6 FPGA LX240T or SX315T


LVDS

MODEL 73671 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

40

x4 PCIe

4X

GTX

Memory Banks 1 & 2 40

Memory Banks 3 & 4

PCIe to PCI BRIDGE

From/To Other XMC Module of Model 74671

Optional FPGA I/O (Option -104) J2

PCIe to PCI BRIDGE

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72671, 73671 and 74671

4- or 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - cPCI
Digital Upconverter and D/A Stage
Two or four Texas Instruments DAC3484s provide four or eight DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. In addition to the DAC3484, these models feature an FPGA-based interpolation engine which adds two additonal interpolation stages programmable from 2x to 256x. The combined interpolation results in a range from 2x to 1,048,576x for each D/A channel and is ideal for matching the digital downconversion and data reduction used on the receiving channels of many communications systems. Analog outputs are through front panel SSMC connectors. SSMC connector. This clock can be used directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A pair of front panel Sync connectors allows multiple boards to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave board. For larger systems, the Pentek Model 7291, 7391 and 7291D Cobalt Synchronizers can drive multiple 72671s 73671s and 74671s respectively, thereby enabling large, multichannel synchronous configurations.

Memory Resources
The architecture of these models supports four or eight independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked-list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
16 to D/A Ch 3 & 4

D/A Waveform Playback IP Module


The factory-installed functions in these models include one or two sophisticated D/A Waveform Playback IP modules. Four or eight linked-list controllers support waveform generation to the four or eight D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4, as well as to the other four channels of Model 74671. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 or 128 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.

Clocking and Synchronization


An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel
16
TEST SIGNAL GENERATOR

to D/A Ch 1 & 2

DATA INTERLEAVER

DATA INTERLEAVER

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

MEMORY CONTROL

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 1

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 2

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 3

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 4

VIRTEX-6 FPGA DATAFLOW DETAIL


Memory Bank 1 Memory Bank 2 Memory Bank 3 Memory Bank 4

PCIe INTERFACE

(supports user installed IP)

4X PCIe

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72671, 73671 and 74671

4- or 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - cPCI
PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73671: 32 bits only. External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus (1 or 2): 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Arrays (1 or 2) Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73671; J3 connector, Model 72671; J3 and J5 connectors, Model 74671 Memory Banks (1 or 2) Four or eight 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73671: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Specifications
Models 72671 and 73671: 4-Channel DUC, 4-channel D/A Model 74671: 8-Channel DUC, 8-channel D/A D/A Converters (4 or8) Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Front Panel Analog Signal Outputs (4 or 8) Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference

Ordering Information
Model 72671 Description 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 6U cPCI 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 3U cPCI 8-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - 6U cPCI

73671

74671

Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73671; J3 connector, Model 72671; J3 and J5 connectors, Model 74671 -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72690, 73690 and 74690

One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D, Virtex-6 FPGA - cPCI
General Information
Models 72690, 73690 and 74690 are members of the Cobalt family of high performance CompactPCI boards based on the Xilinx Virtex-6 FPGA. They consist of one or two Model 71690 XMC modules mounted on a cPCI carrier board. Model 72690 is a 6U cPCI board while the Model 73690 is a 3U cPCI board; both are equipped with one Model 71690 XMC. Model 74690 is a 6U cPCI board with two XMC modules rather than one. These models include one ot two L-Band RF tuners, two or four A/Ds and four or eight banks of memory. test signal generator, and a PCIe interface complete the factory-installed functions and enable these models to operate as complete turnkey solutions without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions in these models include two or four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, controllers for all data clocking and synchronization functions, a

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74690.

Model 74690

Model 73690

Features

One or two L-Band tuners accept RF signals from 925 MHz to 2175 MHz One or two programmable LNAs boost LNB (low-noise block) antenna signal levels with up to 60 dB gain One or two programmable analog downconverters provide I + Q baseband signals with bandwidths ranging from 4 to 40 MHz Two or four 200 MHz 16-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs Up to 2 or 4 GB of DDR3 SDRAM; or: 32 MB or 64MB of QDRII+ SRAM Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72690 Model 74690 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Trigger 1 Trigger 2 TIMING GENERATOR Clock / Sync / Gate / PPS

Ref In

RF In
MAX2112

Ref Out GC
12-BIT D/A

Ref A/D Clock/Sync

Control
I 200 MHz 16-BIT A/D Q 200 MHz 16-BIT A/D

TTL Gate / Trig TTL Sync / PPS Sample Clk Ref In Gate A Gate B Sync / PPS A Sync / PPS B

16

16
IC
2

Timing Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

MODEL 73690 INTERFACES ONLY VIRTEX-6 FPGA


LVDS

GTX

16
QDRII+ SRAM 8 MB

16

16
QDRII+ SRAM 8 MB

16

16
QDRII+ SRAM 8 MB

16

16
QDRII+ SRAM 8 MB

16

16
Config FLASH 64 MB

40

x4 PCIe

4X

GTX

QDRII+ option 150 40 to PCI Optional BRIDGE FPGA I/O (Option -104) PCIe DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

PCIe to PCI BRIDGE

From/To Other XMC Module of MODEL 74690

Optional FPGA I/O (Option -104) J3

PCI to PCI BRIDGE

J2

PCI/PCI-X BUS 32-bit, 33/66 MHz

Memory Banks 1 & 2

Memory Banks 3 & 4

PCI/PCI-X BUS 32-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72690, 73690 and 74690

One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D, Virtex-6 FPGA - cPCI
RF Tuner Stage
One or two front panel SSMC connectors accept L-Band signals between 925 MHz and 2175 MHz from the antenna LNBs (low noise blocks). The Maxim MAX2112 tuners directly convert these L-Band signals to baseband using broadband I/Q downconverters. The devices include RF variable-gain LNAs (low noise amplifiers), PLL (phaselocked loops) synthesized local oscillators, quadrature (I + Q) downconverting mixers, baseband lowpass filters with programmable cutoff frequency, and variable-gain baseband amplifiers. The fractional-N PLL synthesizers lock their VCOs to the timing generator output, or to an external reference input between 12 and 30 MHz. Together, the baseband amplifiers and the RF LNA offer a programmable linear gain range of 60 dB. The integrated lowpass filters with variable bandwidths provide bandwidths ranging from 4 to 40 MHz, programmable with 8 bits of resolution.

A/D Clocking and Synchronization


An internal timing generator provides all timing, gating, triggering and synchronization functions required by the A/D converters. It also serves as an optional source for the L-Band tuner reference. The front panel SSMC clock input can be used directly as the A/D sample clock. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (voltage-controlled crystal oscillator). In this mode, the front panel SSMC clock input connector accepts a 10 MHz reference signal for synchronizing the VCXO using a PLL. The timing generator uses a front panel LVPECL 26-pin clock/sync connector for one clock, two sync, and two gate/trigger signals. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate/ trigger signals within the bosrd. In the master mode, the LVPECL bus drives output timing signals to synchronize multiple slave bosrds, supporting synchronous sampling and sync functions across all connected boards.

A/D Acquisition IP Modules


These models feature two or fourA/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from either of the two A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

A/D Converter Stage


The analog baseband I and Q analog tuner outputs are then applied to two or four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources.

Memory Resources
The Cobalt architecture supports up to four or eight independent memory banks which can be configured with all QDRII+ SRAM, all DDR3 SDRAM, or as combination of two banks of each type of memory.

from A/D (I)

from A/D (Q)

TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

to Mem Bank 1

to Mem Bank 2

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

4X PCIe

40 FPGA I/O

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72690, 73690 and 74690

One or two L-Band RF Tuners, 2- or 4-Channel 200 MHz A/D, Virtex-6 FPGA - cPCI
Each QDRII+ SRAM bank can be up to 8
MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. The factory-installed A/D acquisition modules use memory banks 1 & 2. Banks 3 & 4 can be optionally installed to support custom user-installed IP within the FPGA . Sample Clock Sources (1 or 2) On-board timing generator/synthesizer A/D Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, for the A/D clock Timing Generator External Clock Inputs (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 200 MHz (up to 800 MHz when Timing Generator divider is enabled) or PLL system reference Timing Generator Bus (1 or 2): 26-pin front panel connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/ PPS inputs External Trigger Inputs (2 or 4) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or2) Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74950 Memory Banks (1 or 2) Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73690: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

PCI-X Interface
The models include an industry-standard interface compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73690: 32 bits only.

Specifications
Model 72690 or Model 73690: 1 RF tuner, 2 A/Ds Model 74690: 2 RF tuners, four A/Ds Front Panel Analog Signal Inputs (1 or 2) Connector: Front panel female SSMC Impedance: 50 ohms L-Band Tuners (1 or 2) Type: Maxim MAX2112 Input Frequency Range: 925 MHz to 2175 MHz Monolithic VCO Phase Noise: -97 dBc/Hz at 10 kHz Fractional-N PLL Synthesizer: freqVCO = (N.F) x freqREF where integer N = 19 to 251 and fractional F is a 20-bit binary value PLL Reference (freqREF): Front panel SSMC connector or on-board 27 MHz crystal (Option -100), 12 to 30 MHz LNA Gain: 0 to 65 dB, controlled by a programmable 12-bit D/A converter* Baseband Amplifier Gain: 0 to 15 dB, in 1 dB steps* *Usable Full-Scale Input Range: 50 dBm to +10 dBm Baseband Low Pass Filter: Cutoff frequency programmable from 4 to 40 MHz with 8-bit resolution A/D Converters (2 or 4) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits

Ordering Information
Model 71690 Description L-Band RF Tuner with 2-Channel 200 MHz A/D and Virtex-6 FPGA - XMC XC6VLX240T FPGA XC6VSX315T FPGA LVDS I/O between the FPGA and J2 connector, Model 73690; J3 connector, Model 72690; J3 and J5 connectors, Model 74690 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Options: -062 -064 -104

-150

-160

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72720 73720 and 74720

3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-7 FPGA - cPCI
General Information
Models 72720, 73720 and 74720 are members of the Onyx family of high-performance CompactPCI boards based on the Xilinx Virtex-7 FPGA. They consist of one or two Model 71720 XMC modules mounted on a cPCI carrier board. Model 72720 is a 6U cPCI board while the Model 73720 is a 3U cPCI board; both are equipped with one Model 71720 XMC. Model 74720 is a 6U cPCI board with two XMC modules rather than one. These models include three or sixA/Ds, one or two DUCs, two or four D/As and four or eight banks of memory. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCI-X interface complete the factoryinstalled functions and enable these models to operate as a complete turnkey solutions, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Onyx Architecture


Based on the proven design of the Pentek Cobalt family, Onyx raises the processing performance with the new flagship family of Virtex-7 FPGAs from Xilinx. As the central feature of the board architecture, the FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include three A/D acquisition and a D/A waveform playback IP modules for simplifying data capture and data transfer.
RF In

Xilinx Virtex-7 FPGA


The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73720; J3 connector, Model 72720; J3 and J5 connectors, Model 74720.

Model 74720 Model 73720

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus Three or six 200 MHz 16-bit A/Ds One or two DUCs (digital upconverters) Two or four 800 MHz 16-bit D/As Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Block Diagram, Model 72720 Model 74720 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In

RF In

RF Out

RF Out

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

A/D Clock/Sync Bus

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus


VCXO

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

16

Timing Bus

MODEL 73620 INTERFACES ONLY VIRTEX-7 FPGA


LVDS

VIRTEX-7 FPGA VX330T or VX690T


LVDS

GTX

GTX

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

40

FPGA I/O (Option -104)

FPGA Config Bus


CONFIG FLASH 1 GB

40 CONFIG FLASH 1 GB

x4 PCIe

FPGA Config Bus

x4 PCIe

GATEXPRESS PCIe CONFIGURATION MANAGER

GATEXPRESS PCIe CONFIGURATION MANAGER

From/To Other XMC Module of Model 74720

x4 PCIe
PCIe to PCI BRIDGE

Optional FPGA I/O (Option -104) J3

x4 PCIe
PCIe to PCI BRIDGE PCI to PCI BRIDGE

J2 PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72720 73720 and 74720


A/D Acquisition IP Modules
These models feature three or six A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-7 FPGA - cPCI
GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCI-X discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCI-X interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCI-X interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCI-X configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.

A/D Converter Stage


The front end accepts three or six fullscale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three or six Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.

Digital Upconverter and D/A Stage


One or two TI DAC5688 DUCs (digital upconverters) and D/As accept baseband real or complex data streams from the FPGA and provide that input to the upconvert, interpolate and dual D/A stages.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3 D/A loopback


TEST SIGNAL GENERATOR

to D/A

D/A Waveform Playback IP Modules


These models include one or two factory-installed sophisticated D/A Waveform Playback IP modules. Linked-list controllers allow users to easily play back to the dual D/As waveforms stored in either on-board memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 or 128 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

MEMORY CONTROL

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-7 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

4X PCIe

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72720 73720 and 74720

3- or 6-Channel 200 MHz A/D, 2- or 4-Channel 800 MHz D/A, Virtex-7 FPGA - cPCI
When operating as a DUC, it interpolates
and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes, the DAC5688 provides interpolation factors of 2x, 4x and 8x. D/A Converters (2 or 4) Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs (2 or 4) Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources (2 or 4) On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus (1 or 2): 26-pin connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: Provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73720; J3 connector, Model 72720; J3 and J5 connectors, Model 74720 Memory Banks (1 or 2) Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73620: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Memory Resources
The architecture supports four or eight independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factoryinstalled functions, custom userinstalled IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73620: 32 bits only.

Ordering Information
Model 72720 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex7 FPGA 6U cPCI 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-7 FPGA 3U cPCI 6-Channel 200 MHz A/D and 4-Channel 800 MHz D/A and two Virtex-7 FPGAs - 6U cPCI XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73720; J3 connector, Model 72720; J3 and J5 connectors, Model 74720

Specifications
Model 72620 or Model 73620: 3 A/Ds, 1 DUC, 2 D/As Model 74620: 6 A/Ds, 2 DUCs, 4 D/As Front Panel Analog Signal Inputs (3 or 6) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (3 or 6) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits

73720

74720

Options: -073 -076 -104

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Models 72760, 73760 and 74760

4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA - cPCI


General Information
Models 72760, 73760 and 74760 are members of the Onyx family of high-performance CompactPCI boards based on the Xilinx Virtex-7 FPGA. They consist of one or two Model 71760 XMC modules mounted on a cPCI carrier board. Model 72760 is a 6U cPCI board while the Model 73760 is a 3U cPCI board; both are equipped with one Model 71760 XMC. Model 74760 is a 6U cPCI board with two XMC modules rather than one. These models include four or eight A/Ds and four or eight banks of memory. IP modules for DDR3 SDRAM memories, controllers for all data clocking and synchronization functions, a test signal generator, and a PCIe interface complete the factoryinstalled functions and enable these models to operate as complete turnkey solutions without the need to develop FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Onyx Architecture


The Pentek Onyx Architecture features Virtex-7 FPGAs. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Onyx family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The factory-installed functions of these models include four or eight A/D acquisition IP modules for simplifying data capture and data transfer.

Xilinx Virtex-7 FPGA


The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73760; J3 connector, Model 72760; J3 and J5 connectors, Model 74760.

Model 74760

Model 73760

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-7 VXT FPGAs GateXpress supports dynamic FPGA reconfiguration across PCI/PCI-X bus Four or eight 200 MHz 16-bit A/Ds Four or eight GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-7 FPGA for custom I/O

Block Diagram, Model 72760 Model 74760 doubles all resources except the PCI-to-PCI Bridge
Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF In

RF In

RF In

RF In

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16 VCXO

16

16

16

Timing Bus

MODEL 73760 INTERFACES ONLY VIRTEX-7 FPGA


LVDS

VIRTEX-7 FPGA VX330T or VX690T


LVDS

GTX

GTX

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

32 DDR3 SDRAM 1 GB

40

FPGA I/O (Option -104)

FPGA Config Bus


CONFIG FLASH 1 GB

40 CONFIG FLASH 1 GB

x4 PCIe

FPGA Config Bus

x4 PCIe

GATEXPRESS PCIe CONFIGURATION MANAGER

GATEXPRESS PCIe CONFIGURATION MANAGER

From/To Other XMC Module of Model 74760

x4 PCIe
PCIe to PCI BRIDGE

Optional FPGA I/O (Option -104) J3

x4 PCIe
PCIe to PCI BRIDGE PCI to PCI BRIDGE

J2 PCI/PCI-X BUS 32-bit, 33/66 MHz

PCI/PCI-X BUS 32/64-bit, 33/66 MHz

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72760, 73760 and 74760

4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA - cPCI


GateXpress for FPGA Configuration
The Onyx architecture includes GateXpress, a sophisticated FPGA configuration manager for loading and reloading the FPGA. At power up, GateXpress immediately presents a target for the host computer to discover, effectively giving the FPGA time to load from FLASH. This is especially important for larger FPGAs where the loading times can exceed the PCI-X discovery window, typically 100 msec on most PCs. The boards configuration FLASH can hold four FPGA images. Images can be factory-installed IP or custom IP created by the user, and programmed into the FLASH via JTAG using Xilinx iMPACT or through the boards PCI-X interface. At power up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the FPGA with a new IP image. The first is the option to load an alternate image from FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the FPGA image must be loaded directly through the PCI-X interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the FPGA IP may need to change many times during the course of a mission, images can be stored on the host computer and loaded as needed. The third option, typically used during development, allows the user to directly load the FPGA through JTAG using Xilinx iMPACT. In all three FPGA loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the PCI-X configuration space allowing dynamic FPGA reconfiguration without needing to reset the host computer to rediscover the board. After the reload, the host simply continues to see the board with the expected device ID.

A/D Converter Stage


The front end accepts four or eight fullscale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four or eight Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-7 FPGA for signal processing, data capture or for routing to other board resources.

A/D Acquisition IP Modules


These models feature four or eight A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of four A/Ds or the test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3

from A/D Ch 4

TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

VIRTEX-7 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

4X PCIe

40 FPGA I/O

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 72760, 73760 and 74760

4- or 8-Channel 200 MHz, 16-bit A/D with Virtex-7 FPGA - cPCI


Clocking and Synchronization
An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An onboard clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple boards can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. A/D Converters (4 or 8) Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: (1 or 2) On-board clock synthesizer Clock Synthesizers (1 or 2) Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clocks (1 or 2) Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus (1 or 2) 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Inputs (1 or 2) Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Arrays (1 or 2) Standard: Xilinx Virtex-7 XC7VX330T-2 Optional: Xilinx Virtex-7 XC7VX690T-2 Custom I/O Option -104: provides 20 LVDS pairs between the FPGA and the J2 connector, Model 73760; J3 connector, Model 72760; J3 and J5 connectors, Model 74760 Memory Banks (1 or 2) Type: DDR3 SDRAM Size: Four banks, 1 GB each Speed: 800 MHz (1600 MHz DDR) PCI-X Interface PCI-X Bus: 32 or 64 bits at 33 or 66 MHz Model 73760: 32 bits only Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard 6U or 3U cPCI board

Memory Resources
The Onyx architecture supports four or eight independent DDR3 SDRAM memory banks. Each bank is 1 GB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Ordering Information
Model 72760 Description 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA 6U cPCI 4-Channel 200 MHz 16-bit A/D with Virtex-7 FPGA 3U cPCI 8-Channel 200 MHz 16-bit A/D with two Virtex-7 FPGAs - 6U cPCI XC7VX330T-2 FPGA XC7VX690T-2 FPGA LVDS I/O between the FPGA and J2 connector, Model 73760; J3 connector, Model 72760; J3 and J5 connectors, Model 74760

PCI-X Interface
These models include an industry-standard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33 and 66 MHz are supported. Model 73760: 32 bits only.

73760

74760

Specifications
Model 72760 or Model 73760: 4 A/Ds Model 74760: 8 A/Ds Front Panel Analog Signal Inputs (4 or 8) Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz

Options: -073 -076 -104

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

RAD AR & SDR I/O - PCI RADAR


MODEL
7650 7651 7652 7653 7656 7658

DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PCI 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - PCI Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI Customer Information

RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR

& & & & &

SDR SDR SDR SDR SDR

I/O I/O I/O I/O I/O

PMC/XMC CompactPCI x16 PCI Express x 8 PCI Express 3U VPX

Last updated: February 2013


www.pentek.com

Model 7650

Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PCI


General Information
Model 7650 is a half-length PCI Quad 200 MHz A/D. It consists of one Model 7150 Quad A/D mounted on a PCI carrier board. The Model 7650 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel. programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7650 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. A second Virtex-5 FPGA provides board interfaces including PCI-X or PCI Express. Implementing the PCI interfaces in this second FPGA, keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but additional processing resources up to an additional 640 DSP48E Slices. Option -104 installs a 64-pin DIN connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs of LVDS connections to the interface FPGA for custom I/O.

A/D Converter Stage


The front end accepts four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other module resources.

Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory-shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA,

Clocking and Synchronization


The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus.

Features

Complete software radio interface solution Four or 200 MHz, 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS 200 or 135 MHz 16 BIT A/D

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

TTL In

Clock/Sync Bus

200 or 135 MHz 16 BIT A/D

200 or 135 MHz 16 BIT A/D

200 or 135 MHz 16 BIT A/D

LVPECL Bus
XTL OSC

To A l Sections

Timing Bus

Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX 5 LX50T, SX50T, SX95T or LX155T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X LVDS

PCI X INTERFACE
64

LVDS 32 32

32

PCI-X BUS

64-pin DIN FPGA I/O (Option -104) PCI-X BUS

PCI-TO-PCI BRIDGE

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7650

Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - PCI


Clocking and Synchronization
The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 pairs of LVDS connections to the processing FPGA and 16 pairs to the interface FPGA for custom I/O Memory DDR2 SDRAM: Up to 1 GB in two banks PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI card

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.

PCI-X Interface
The Model 7650 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Optional PCI Express Interface


For systems that require a PCI Express board interface, the Model 7650 can be optionally factory-configured with x4 PCI Express in the interface FPGA. Other serial protocols as well as different bus widths can be accommodated with custom IP cores.

Ordering Information
Model 7650 Description Quad 200 MHz, 16-bit A/D with two Virtex-5 FPGAs PCI FPGA I/O through a 64-pin DIN connector

Options: -104

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7651

256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI


General Information
Model 7651 is a high-speed software radio half-length PCI board. It consists of one Model 7151 Quad A/D digitizer with a factory- installed high-performance 256-channel DDC IP Core mounted on a PCI carrier board. The Model 7651 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.

Decimation and Filtering


All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 156.25 kHz to 1.25 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 64. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

A/D Converter Stage


The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

Features

DDC Input Selection and Tuning


The Model 7651 employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 256 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

256 channels of DDC Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization

Output Multiplexers and FIFOs


Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI-X bus.

CH 1 RF In

RF XFORMR

200 MHz 16-bit A D

CH 2 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024

CH 1 I+Q
M U X

FIFO 1

CH 3 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A D

CH 2
M U X D G TAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024

CH 3 CH 4

I+Q

M U X

FIFO 2

PCI-X BUS CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
M U X D GITAL DOWNCONVERTER BANK 4: CH 193-256 DEC: 128 - 1024

PCI-X BUS

CH 3
M U X D GITAL DOWNCONVERTER BANK 3: CH 129-192 DEC: 128 - 1024

CH 2 CH 3 CH 4

I+Q

M U X

FIFO 3

PCI-X INTERFACE Xilinx XC5VLX30T PCI-TO-PCI BRIDGE

TTL In

CH 4 I+Q
M U X

FIFO 4

LVPECL Bus

XTAL OSC

XILINX XC5VSX95T
Timing Bus

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7651

256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI


Clocking and Synchronization
The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. For larger systems, many more boards can be synchronized with an external clock and sync generator.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Local Bus: 64-bit, 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI card

PCI-X Interface
The Model 7651 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Ordering Information
Model 7651 Description 256-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI

Options: -732 Two-slot heat sink

Contact Pentek for available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7652

32-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI


General Information
Model 7652 is a high-speed softwaare radio half-length PCI board. It consists of one Model 7152 Quad A/D digitizer with a factory- installed high-performance 32-channel DDC IP Core mounted on a PCI carrier board. The Model 7652 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.

Decimation and Filtering


All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

A/D Converter Stage


The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

Features

32 channels of DDC in four banks of 8 channels Four 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all 32 channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Common decimation factor within each DDC bank Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multiboard synchronization

DDC Input Selection and Tuning


The Model 7652 employs an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the 32 DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

Power Meters and Threshold Detectors


The 7652 features 32 power meters that continuously measure the individual average power output of each of the 32 DDC channels. The time constant of the averaging interval for each meter is programmable up to 16K samples. In addition, 32 threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.

CH 1 RF In

RF XFORMR

200 MHz 16-bit A/D


8X4 CHANNEL SUMMATION M U X D G TAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 - 8192

CH 1 I+Q
M U X F I F 0 1 F I F 0 2

CH 2 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHO D DETECTORS

CH 3 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D

CH 2
M U X

CH 3 CH 4

M U X

D G TAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 - 8192

I+Q
POWER METER & THRESHO D DETECTORS

PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4

PCI-X BUS

CH 1 Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4
M U X D G TAL DOWNCONVERTER BANK 4: CH 25-32 DEC: 16 - 8192

CH 2 CH 3 CH 4

M U X

D G TAL DOWNCONVERTER BANK 3: CH 17-24 DEC: 16 - 8192

I+Q
POWER METER & THRESHO D DETECTORS

PCI-X NTERFACE X linx XC5VLX30T

TTL In

PCI-TO PCI BRIDGE

CH 4
M U X

I+Q
POWER METER & THRESHO D DETECTORS

LVPECL Bus

XTAL OSC

Timing Bus

XILINX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7652

32-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI


Output Multiplexers and FIFOs
Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI-X bus.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, and XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface in the standard unit; optional FPGA: XC5VSX50T PCI Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller Local Bus: 64-bit, 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board

Clocking and Synchronization


The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three 7652s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

PCI-X Interface
The Model 7652 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Ordering Information
Model 7652 Description 32-Channel DDC with four 200 MHz, 16-bit A/Ds - PCI

Options: -732 Two-slot heat sink

Contact Pentek for available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7653

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PCI


General Information
Model 7653 is a 4-channel, high-speed software radio board designed for processing baseband RF or IF signals. It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel DDC (digital downconverter) and a complete set of beamforming functions. With built-in multiboard synchronization, it is ideally matched to the requirements of real-time software radio and radar systems. The Model 7653 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency.

Decimation and Filtering


Each of the four DDC channels can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. The DDC core can be configured in four-channel mode with each channel offering decimations between 2 and 256, or in two-channel mode with each channel having a decimation range of 2 to 65536, for applications that require a wider range of decimations. The decimating filter for each DDC channel accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N.

A/D Converter Stage Features


Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization

The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing operations.

DDC Input Selection and Tuning


The Model 7653 employs an advanced FPGA-based digital downconverter engine consisting of two or four DDC channels. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC channel. In this way, many different configurations can be achieved including one A/D driving all four DDC channels and each of the four A/Ds driving its own DDC bank.

Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.

CH 1 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER

SUM IN SUM OUT

AURORA G GABIT SERIAL NTERFACE F I F 0 1 F I F 0 2

4X 4X P15 XMC

CH 2 RF In

RF XFORMR

200 MHz 16-bit A D

I+Q CH 1
M U X

CH 3 RF In

RF XFORMR

200 MHz 16-bit A D

D GITAL DOWNCONVERTER CH 1 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

CH 4 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4
M U X

CH 2
M U X

D GITAL DOWNCONVERTER CH 2 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

PCI-X BUS CH 3
M U X F I F 0 3 F I F 0 4

PCI-X BUS

Sample Clock In PPS In TTL In LVDS Bus Timing Bus

CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4


M U X D GITAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*

CH 2 CH 3 CH 4

M U X

D GITAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

PCI-X NTERFACE

XILINX XC5VLX30T

PCI-TO-PCI BRIDGE

CH 4
M U X

I+Q
POWER METER & THRESHOLD DETECTORS

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

XILINX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7653

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PCI


Beamformer
In addition to the A/Ds and DDCs, the 7653 includes essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI-X bus. For larger systems, multiple 7653s can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.

Clocking and Synchronization


The architecture includes a flexible timing and synchronization circuit that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three 7653s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

XMC Interface
For large systems, multiple 7653s can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

Output Multiplexers and FIFOs


Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI-X bus.

PCI-X Interface
The Model 7653 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes four separate DMA controllers for efficient transfers to and from the board. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

GAIN

I Q

I Q

I
Q

I
Q

DIG TAL DOWNCONVERTER A

Weigh Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT A

AURORA PORT

SUMMAT ON EXPANSION CHAIN IN 1 25 GByte/sec x4 Au ora Link

F om P evious Board

P15
GAIN

DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

I
Q

I
Q

I
Q

I
Q

DIG TAL DOWNCONVERTER B

Weigh Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT B

SUMMAT ON CHAIN BIT GROWTH COMPENSAT ON

I Q

I Q

I Q

To FIFO 1 (Final Result or Intermediate Result

GAIN

(DECIMATION: 2-256)*

I Q

I Q

I
Q

I
Q

Summation Chain Gain POWER METER & THRESHO D DETECT C

SUMMATION POWER METER & THRESHO D DETECT

DIG TAL DOWNCONVERTER C

Weigh Phase I Weight Phase Q Weight Gain PHASE SHIFT

AURORA PORT

SUMMAT ON EXPANS ON CHAIN OUT 1 25 GByte/sec x4 Au ora Link

To Next Boa d

GAIN

P15 I Q

(DECIMATION: 2-256)*

I Q

I Q

I Q

DIG TAL DOWNCONVERTER D

Weigh Phase I Weight Phase Q Weight Gain

POWER METER & THRESHO D DETECT D

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

BEAMFORMER DATA FLOW DETAIL

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7653

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - PCI


Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, user-programmable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI Interface PCI-X Bus: 64 bits, 100 MHz and 64 or 32 bits at 33 or 66 MHz DMA: 4-channel demand-mode and chaining controller Local Bus: 64-bit, 66 MHz Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board

Ordering Information
Model 7653 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - PCI

Options: -732 Two-slot heat sink

Contact Pentek for available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7656

Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
General Information
Model 7656 is a half-length PCI board that includes two 400 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. It consists of one Model 7156 PMC module mounted on a PCI carrier board. The Model 7656 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.

Virtex-5 FPGAs
The Model 7656 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR

A/D Converter Stage


The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other board resources.

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution Two 400 MHz, 14-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus

400 MHz 14 BIT A/D

400 MHz 14 BIT A/D

800 MHz 16 BIT D/A

800 MHz 16 BIT D/A

TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS

DIGITAL UPCONVERTER

D/A Clock Bus


14 To All Sections 14 32

Tim ng Bus

VCXO

Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X

LVDS

PCI X INTERFACE
64

LVDS 32 32

32

PCI-X BUS

64-pin DIN PGA /O (Option -104) PCI-X BUS

PCI-TO-PCI BRIDGE

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7656

Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds a 64-pin DIN connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7656s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

PCI-X Interface
The Model 7656 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Ordering Information
Model 7656 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI

Options: -104 FPGA I/O through a 64-pin DIN connector

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7658

Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
General Information
Model 7658 is a half-length PCI board that includes two 500 MHz A/Ds, 800 MHz D/As and Virtex-5 FPGAs. It consists of one Model 7158 PMC module mounted on a PCI carrier board. The Model 7658 attaches directly to computer motherboards with PCI bus slots. Front panel connectors are brought out on the rear panel.

Virtex-5 FPGAs
The Model 7658 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR

A/D Converter Stage


The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5463 12-bit 500 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing, data capture or routing to other board resources.

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution Two 500 MHz, 12-bit A/Ds One digital upconverter Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus

500 MHz 12 BIT A/D

500 MHz 12 BIT A/D

800 MHz 16 BIT D/A

800 MHz 16 BIT D/A

TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS

DIGITAL UPCONVERTER

D/A Clock Bus


14 To All Sections 14 32

Tim ng Bus

VCXO

Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 265 MB

PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T LVDS 8 64 FLASH 32 MB INTERFACE FPGA VIRTEX 5 LX30T or SX50T LVDS 32 4X

LVDS

PCI X INTERFACE
64

LVDS 32 32

32

PCI-X BUS

64-pin DIN PGA /O (Option -104) PCI-X BUS

PCI-TO-PCI BRIDGE

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7658

Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 adds a 64-pin DIN connector with 16 pairs of LVDS connections to each FPGA for custom I/O.
Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: One Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: One Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Installs a 64-pin DIN connector with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA mapped as two 16-bit read/write registers Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Standard half-length PCI board

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7658s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

PCI-X Interface Ordering Information


Model 7658 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - PCI

Options: -104 FPGA I/O through a 64-pin DIN connector -140 1 GB DDR2 SDRAM

The Model 7658 includes an industrystandard interface fully compliant with PCI-X bus specifications. The interface includes multiple DMA controllers for efficient transfers to and from the module. Data widths of 32 or 64 bits and data rates of 33, 66 and 100 MHz are supported.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

RAD AR & SDR I/O - x16 PCI Express RADAR


MODEL
7750 7751 7752 7753 7756 7758

DESCRIPTION
Quad or Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x16 PCIe 256- or 512-Channel DDC with 4 or 8 200 MHz, 16-bit A/Ds - x16 PCIe 32- or 64-Channel DDC with 4or 8 200 MHz, 16-bit A/Ds - x16 PCIe 4/8-Channel DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - x16 PCIe Dual/Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x16 PCIe Dual/Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x16 PCIe Customer Information

RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR RAD AR RADAR

& & & & &

SDR SDR SDR SDR SDR

I/O I/O I/O I/O I/O

PMC/XMC CompactPCI PCI x 8 PCI Express 3U VPX

Last updated: February 2013


www.pentek.com

Models 7750, 7750D

Quad/Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x16 PCIe
General Information
Model 7750 is a high-speed data converter suitable for connection as the HF or IF input of a communications system. It features either four 200 MHz, 16-bit A/Ds (Model 7750) or eight A/Ds (Model 7750D). These are supported by an array of data processing and transport resources ideally matched to requirements of high-performance systems. The 7750 attaches to motherboards with full length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. There are two FPGA types on the 7750: processing and interface. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, these Models can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. The interface FPGA provides board connections including PCI-X or PCI Express. Implementing the PCI interfaces in this FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to each processing FPGA, and 16 pairs of LVDS connections to each interface FPGA for custom I/O.

Model 7750D

A/D Converter Stage


The front end accepts four or eight full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other module resources.

Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x16 wide Four or eight 200 MHz 16-bit A/Ds Up to 2 GB of DDR2 SDRAM Two or Four Xilinx Virtex-5 FPGAs Up to 5.12 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization Up to 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

Virtex-5 FPGAs
The Model 7750 architecture includes two (Model 7750) or four (Model 7750D) Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering, and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user- created IP with the factory-shipped functions.
RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR Sample Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS To All Sections

Sample Clk In PPS In TTL In TIMING BUS GENERATOR Clock / Sync / Gate / PPS To All Sections

Clock/Sync Bus

200 MHz 16-bit A/D

200 MHz 16-bit A/D

200 MHz 16-bit A/D

200 MHz 16-bit A/D

200 MHz 16-bit A/D

200 MHz 16-bit A/D

200 MHz 16-bit A/D

200 MHz 16-bit A/D

Clock/Sync Bus

PPS In

TTL In

LVPECL Bus XTL OSC

Control/ Status
32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX-5 LX50T, SX50T, SX95T, LX155T or FX100T


GTP GTP GTP LVDS LVDS

PROCESSING FPGA VIRTEX-5 LX50T, SX50T, SX95T, LX155T or FX100T


GTP GTP GTP

Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB

LVPECL Bus
XTL OSC

Timing Bus

32 DDR2 SDRAM 512 MB

8
4X 4X

8 4X
GTP

64

64

4X
GTP

4X

4X

Timing Bus

FLASH 32 MB

FLASH 32 MB

INTERFACE FPGA VIRTEX-5 LX30T or SX50T


GTP PCI-X LVDS

INTERFACE FPGA VIRTEX-5 LX30T or SX50T


LVDS PCI-X GTP

4X

64

32

32

PCI-X BUS 1 (64 Bits, 100 MHz)

32

32

PCI-X BUS 2 (64 Bits, 100 MHz)

64

4X

GPIO 1 (68-Pin)
4X Gbit Serial 4X Gbit Serial 4X 4X
PCI TO PCIe BRIDGE

GPIO 2 (68-Pin)
PCI TO PCIe BRIDGE

4X Gbit Serial 4X

4X Gbit Serial

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

x4 PCIe

4X

Model 7750D

x16 PCI Express


SER I/O A SER I/O B SER I/O C SER I/O D

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7750, 7750D

Quad/Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x16 PCIe
Clocking and Synchronization
The Model 7750 architecture includes a flexible timing and synchronization circuit for each bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. One or two front panel 26-pin LVPECL Clock/Sync connectors allow multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7750s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More bords can be synchronized with an external clock and sync generator.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T (one for 7750, two for 7750D); optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: Xilinx Virtex-5 XC5VLX30T (one for 7750, two for 7750D); optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks per processing FPGA (2 GB max.) PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: two x4 ports per FPGA one x4 port per PCI bus one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe , 4.38 in. x 12.3 in.

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.

PCI Express Interface Ordering Information


Model 7750 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs Full-length x16 PCIe Octal 200 MHz, 16-bit A/D with Virtex-5 FPGAs Full-length x16 PCIe

7750D

Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit Serial I/O - two full duplex 4X paths (Model 7750) or four full duplex 4X paths (Model 7750D)

The 7750 includes a multiple port, 48-lane Gen 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x16 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with two x4 PCIe connections provided to each FPGA, as well as one x4 connection to each 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7751, 7751D

256/512-Channel DDC with 4/8 200 MHz, 16-bit A/Ds - x16 PCIe
General Information
Model 7751 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features either four 200 MHz 16-bit A/Ds (Model 7751) or eight A/Ds (Model 7751D). Each bank of four A/Ds is supported by a high-performance 256-channel installed DDC IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 7751 attaches to motherboards with full length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. Each of the DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

Decimation and Filtering


All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 156.25 kHz to 1.25 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 64. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

Model 7751D

A/D Converter Stage Features


256 or 512 DDC channels Four or eight 200 MHz 16-bit A/Ds PCI Express 2.0 (Gen. 2) Interface up to x16 wide Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization

The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.

DDC Input Selection and Tuning


Each of the Model 7751 SX95T FPGAs employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the attached four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank.

Output Multiplexers and FIFOs


Four output MUXs in each SX95T FPGA can be independently switched to deliver either A/D or DDC data into each output FIFO. This allows users to view either wideband A/D data or narrowband DDC data, depending on the application.

CH 1 RF In

RF XFORMR

200 MHz 16 bit A/D

200 MHz 16 b t A/D

RF XFORMR

CH 5 RF In

CH 2 RF In

RF XFORMR

200 MHz 16 bit A/D

CH 1 CH 2 CH 3 CH 4
M U X DIGITAL DOWNCONVERTER BANK 1 CH 1 64 DEC 128 1024

CH 1 I+Q
M U X

CH 5 FIFO 1 FIFO 5
M U X

CH 5 I+Q
DIGITAL DOWNCONVERTER BANK 5 CH 257 320 DEC 128 1024 M U X

CH 6 CH 7 CH 8

200 MHz 16 bit A/D

RF XFORMR

CH 6 RF In

CH 3 RF In

RF XFORMR

200 MHz 16 bit A/D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16 bit A/D

CH 2
M U X DIGITAL DOWNCONVERTER BANK 2 CH 65 128 DEC 128 1024

CH 6
M U X

200 MHz 16 bit A/D

RF XFORMR

CH 7 RF In

CH 3 CH 4

I+Q

FIFO 2

FIFO 6

M U X

CH 5 I+Q
DIGITAL DOWNCONVERTER BANK 6 CH 321 384 DEC 128 1024 M U X

CH 6 CH 7 CH 8
200 MHz 16 b t A/D RF XFORMR

CH 8 RF In

Sample Clock In PPS In TTL In LVPECL Bus Timing Bus

CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4


M U X DIGITAL DOWNCONVERTER BANK 4 CH 193 256 DEC 128 1024

CH 3
M U X DIGITAL DOWNCONVERTER BANK 3 CH 129 192 DEC 128 1024

CH 7
M U X

CH 2 CH 3 CH 4

I+Q

FIFO 3

FIFO 7

M U X

CH 5 I+Q
DIGITAL DOWNCONVERTER BANK 7 CH 385 448 DEC 128 1024 M U X

CH 6 CH 7 CH 8

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

Sample Clock In PPS In TTL In LVPECL Bus Timing Bus

CH 4 I+Q
M U X

CH 8 FIFO 4 FIFO 8
M U X

CH 5 I+Q
DIGITAL DOWNCONVERTER BANK 8 CH 449 512 DEC 128 1024 M U X

CH 6 CH 7 CH 8 XTAL OSC

XIL NX XC5VSX95T
X linx XC5VLX30T PCI X INTERFACE Xilinx XC5VLX30T PCI X INTERFACE

X L NX XC5VSX95T

PCI TO PCIe BRIDGE

PCI X BUS 1

PCI X BUS 2

PCI TO PCIe BRIDGE

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

x4 PCIe

Model 7751D

x16 PCI Exp ess

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7751, 7751D

256/512-Channel DDC with 4/8 200 MHz, 16-bit A/Ds - x16 PCIe
Each of the output FIFOs operates at its

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T (one for 7751, two for 7751D) dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface (one for 7751, two for 7751D) PCI to PCIe Interface PCI-X Bus: 64-bits, 133 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: one x4 port per PCI-X bus one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe, 4.38 in. x 12.3 in.

own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

Clocking and Synchronization


The Model 7751 architecture includes a flexible timing and synchronization circuit for each bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. One or two front panel 26-pin LVPECL Clock/Sync connectors allow multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7751s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

PCI Express Interface


The 7751 includes a multiple port, 48-lane Gen 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x16 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with one x4 connection provided to each 64-bit PCI-X interface.

Ordering Information
Model 7751 Description 256-Channel DDC with four 200 MHz, 16-bit A/D - Full-Length x16 PCIe 512-Channel DDC with eight 200 MHz, 16-bit A/D - Full-Length x16 PCIe

7751D

Options: -731 Two-slot heat sink

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7752, 7752D

32/64-Channel DDC with 4/6 200 MHz, 16-bit A/Ds - x16 PCIe
General Information
Model 7752 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds (Model 7752) or eight A/Ds (Model 7752D). Each group of four A/Ds is supported by a high-performance 32-channel installed DDC IP Core, and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 7752 attaches to motherboards with full length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. Each of the DDCs has an independent 32-bit tuning frequency setting ranging from DC to s (s is the A/D sample rate).

Decimation and Filtering


All of the eight channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have a unique decimation setting supporting up to four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. Rejection of adjacent-band components within the 80% bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

Model 7752D

Features

A/D Converter Stage


The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.

PCI Express 2.0 (Gen. 2) Interface up to x16 wide 32 or 64 channels of DDC in banks of 8 channels Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multimodule synchronization

DDC Input Selection and Tuning


Each of the Model 7752 SX95T FPGAs employs an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four attached A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank.

Power Meters and Threshold Detectors


The 7752 features up to 64 power meters that continuously measure the individual average power output of each DDC channel. The time constant of the averaging interval for each meter is programmable up to 16K samples. In addition, threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.
200 MHz 16 bit A/D
8X4 CHANNEL SUMMATION

CH 1 RF In

RF XFORMR

200 MHz 16 bit A/D


8X4 CHANNEL SUMMATION M U X DDC BANK 1 CH 1 8 DEC 16 8192

CH 1 I+Q
M U X F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4 F I F 0 5 F I F 0 6 F I F 0 7 F I F 0 8 M U X

CH 1 I+Q

RF XFORMR

CH 5 RF In

CH 2 RF In

RF XFORMR

200 MHz 16 bit A/D

CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHOLD DETECTORS

CH 5 I+Q
POWER METER & THRESHOLD DETECTORS DDC BANK 5 CH 33 40 DEC 16 8192 M U X

CH 6 CH 7 CH 8

200 MHz 16 bit A/D

RF XFORMR

CH 6 RF In

CH 3 RF In

RF XFORMR

200 MHz 16 bit A/D CH 1 CH 2


M U X

CH 2
M U X

CH 2
M U X

200 MHz 16 bit A/D CH 5


M U X

RF XFORMR

CH 7 RF In

CH 4 RF In

RF XFORMR

200 MHz 16 bit A/D

CH 3 CH 4

DDC BANK 2 CH 9 16 DEC 16 8192

I+Q
POWER METER & THRESHOLD DETECTORS

I+Q
POWER METER & THRESHOLD DETECTORS

DDC BANK 6 CH 41 48 DEC 16 8192

CH 6 CH 7 CH 8 200 MHz 16 bit A/D RF XFORMR CH 8 RF In

Sample Clk In PPS n TTL In

CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4


M U X DDC BANK 4 CH 25 32 DEC 16 8192

CH 3
M U X

CH 3
M U X

CH 5 I+Q
DDC BANK 7 CH 49 56 DEC 16 8192 M U X

CH 2 CH 3 CH 4

M U X

DDC BANK 3 CH 17 24 DEC 16 8192

I+Q
POWER METER & THRESHOLD DETECTORS

CH 6 CH 7 CH 8

TIMING BUS GENERATOR Clock / Sync / Gate / PPS

Samp e C k In PPS In TTL In

CH 4
M U X

CH 4
M U X

POWER METER & THRESHOLD DETECTORS

CH 5 I+Q
DDC BANK 8 CH 57 64 DEC 16 8192 M U X

LVPECL Bus

I+Q
POWER METER & THRESHOLD DETECTORS

CH 6 CH 7 CH 8 XTAL OSC LVPECL Bus

XTAL OSC

Timing Bus

XILINX XC5VSX95T
Xilinx XC5VLX30T PCI X INTERFACE Xi inx XC5VLX30T PCI X INTERFACE

XILINX XC5VSX95T

POWER METER & THRESHOLD DETECTORS

Timing Bus

PCI TO PCIe BRIDGE

PCI X BUS 1

PCI X BUS 2

PCI TO PCIe BRIDGE

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

x4 PCIe

Model 7752D

x16 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7752, 7752D

32/64-Channel DDC with 4/6 200 MHz, 16-bit A/Ds - x16 PCIe
Output Multiplexers and FIFOs
Four output MUXs in each SX95T FPGA can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T (one for 7752, two for 7752D) dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface (one for 7752, two for 7752D) PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: one x4 port per PCI-X bus one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe , 4.38 in. x 12.3 in.

Clocking and Synchronization


The Model 7752 architecture includes a flexible timing and synchronization circuit for each group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. One or two front panel 26-pin LVPECL Clock/Sync connectors allow multiple modules to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7752s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. For larger systems, many more modules can be synchronized with an external clock and sync generator.

PCI Express Interface


The 7752 includes a multiple port, 48-lane Gen 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x16 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with one x4 connection provided to each 64-bit PCI-X interface.

Ordering Information
Model 7752 Description 32-Channel DDC with four 200 MHz, 16-bit A/D s - Full-Length x16 PCIe 64-Channel DDC with eight 200 MHz, 16-bit A/D s - Full-Length x16 PCIe

7752D

Options: -731 Two-slot heat sink

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7753, 7753D

4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - x16 PCIe
General Information
Model 7753 is a high-speed software radio board designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds (Model 7753) or eight A/Ds (Model 7753D). Each group of four A/Ds is supported by a high-performance 4-channel installed DDC and a complete set of beamforming functions. With built-in multiboard synchronization, it is ideally matched to the requirements of realtime software radio and radar systems. The 7753 attaches to motherboards with full length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sampling frequency.

Decimation and Filtering


Each of the four DDC channels can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. The DDC core can be configured in four-channel mode with each channel offering decimations between 2 and 256, or in two-channel mode with each channel having a decimation range of 2 to 65536, for applications that require a wider range of decimations. The decimating filter for each DDC channel accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N.

Model 7753D

Features

Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel PCI Express 2.0 (Gen. 2) Interface up to x16 wide 2 or 4 (Model 7753) and 4 or 8 (Model 7753D) channels of DDC Four or eight 200 MHz, 16-bit A/Ds Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization

A/D Converter Stage


The front end accepts four or eight fullscale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into Xilinx Virtex-5 FPGAs for routing, formatting and signal processing.

DDC Input Selection and Tuning


The Model 7753 employs an advanced FPGA-based digital downconverter engine consisting of two or four DDC channels. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC channel. In this way, many different configurations can be achieved including one A/D driving all four DDC channels and each of the four A/Ds driving its own DDC bank.

Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.

Block Diagram, Model 7753. Model 7753D doubles all resources except the PCIe switch.
CH 1 RF In
RF XFORMR 200 MHz 16-bit A/D

CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER

SUM N SUM OUT

AURORA GIGAB T SERIAL NTERFACE F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4

4X 4X P15 XMC

CH 2 RF In

RF XFORMR

200 MHz 16-bit A/D

I+Q CH 1
M U X

CH 3 RF In

RF XFORMR

200 MHz 16-bit A/D

D G TAL DOWNCONVERTER CH 1 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

CH 4 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 3 CH 4
M U X

CH 2
M U X

D G TAL DOWNCONVERTER CH 2 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

Xilinx XC5VLX30T PCI-X INTERFACE PCI-X BUS 1

Sample Clock In PPS In TTL In LVDS Bus Timing Bus

CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4


M U X D G TAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*

CH 3
M U X

CH 2 CH 3 CH 4

M U X

D G TAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHOLD DETECTORS

PCI TO PCIe BRIDGE

CH 4
M U X

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

I+Q
POWER METER & THRESHOLD DETECTORS

x16 PCI Exp ess

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

XILINX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7753, 7753D

4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - x16 PCIe
Beamformer
In addition to the A/Ds and DDCs, these Models include essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI-X bus. For larger systems, multiple Models can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.

Clocking and Synchronization


The Model 7753 architecture includes a flexible timing and synchronization circuit for each group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. One or two front panel 26-pin LVPECL Clock/Sync connectors allow multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7753s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. For larger systems, many more boards can be synchronized with an external clock and sync generator.

XMC Interface
For large systems, multiple 7753s or 7753Ds can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

Output Multiplexers and FIFOs


Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

PCI Express Interface


The 7753 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x16 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with one x4 connection provided to each 64-bit PCI-X interface.

PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

GAIN

I Q

I Q

I
Q

I
Q

DIG TAL DOWNCONVERTER A

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT A

AURORA PORT

SUMMAT ON EXPANS ON CHAIN IN 1 25 GByte/sec x4 Auro a Link

F om P evious Boa d

P15
GAIN

DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

I Q

I Q

I Q

I Q
SUMMATION CHA N B T GROWTH COMPENSAT ON

DIG TAL DOWNCONVERTER B

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT B

I Q

I Q

I Q

To FIFO 1 (Final Result or Intermediate Result

GAIN

(DECIMATION: 2-256)*

I Q

I Q

I
Q

I
Q

Summation Chain Gain POWER METER & THRESHO D DETECT C

SUMMATION POWER METER & THRESHOLD DETECT

DIG TAL DOWNCONVERTER C

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

AURORA PORT

SUMMAT ON EXPANS ON CHA N OUT 1 25 GByte/sec x4 Auro a Link

To Next Board

GAIN

P15 I
Q

I
Q

I
Q

(DECIMATION: 2-256)*

DIG TAL DOWNCONVERTER D

Weight Phase I Weight Phase Q Weight Gain

POWER METER & THRESHO D DETECT D

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

BEAMFORMER DATA FLOW DETAIL

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7753, 7753D

4/8-Ch. DDC, 4/8 200 MHz 16-bit A/Ds, Beamformer - x16 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 and 4 or 8 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, user-programmable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four or eight channels onboard; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four or eight FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI to PCIe Interface PCI-X Bus: 64 bits, 100 MHz and 64 or 32 bits at 33 or 66 MHz DMA: 4-channel demand-mode and chaining controller per PCI-X bus PCIe Interface: Gen. 2, x16 width PCIe Ports: one x4 port per PCI-X bus one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe , 4.38 in. x 12.3 in.

Ordering Information
Model 7753 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - Full-Length x16 PCIe 8-Channel DDC with eight 200 MHz, 16-bit A/Ds and Beamformers - Full-Length x16 PCIe

7753D

Options: -731 Two-slot heat sink

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7756, 7756D

Dual/Quad 400 MHz A/D, 800 MHz D/A,Virtex-5 FPGAs - x16 PCIe
General Information
Model 7756 is a high-speed data converter suitable for connection to HF or IF ports of a communication system. It is available with either two A/Ds, D/As and FPGAs (Model 7756), or four A/Ds, D/As and FPGAs (Model 7756D). It attaches to motherboards with full-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.

Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family
RF In
RF XFORMR

Model 7756D

A/D Converter Stage


The front end accepts two or four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing or routing to other board resources.

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x16 wide Two or four 400 MHz, 14-bit A/Ds One or two DUCs (Digital Upconverters) Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIM NG BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus D/A Clock Bus

400 MHz 14 B T A/D 14

400 MHz 14 B T A/D 14

800 MHz 16 BIT D/A

800 MHz 16 BIT D/A

TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS

DIGITAL UPCONVERTER 32

To All Sections VCXO

Timing Bus

Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T


GTP GTP GTP LVDS

8 FLASH 32 MB

4X

4X

4X
GTP

64

INTERFACE FPGA VIRTEX 5 LX30T or SX50T


PCI X LVDS

GTP

4X

64

32
32

PCI X BUS 1 (64 B ts 100 MHz)

Block Diagram, Model 7756. Model 7756D doubles all resources except the PCIe switch.

4X Gbit Serial

4X Gbit Serial 4X 4X

PCI TO PCIe BRIDGE

GP O 1 (68-Pin)

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

SER I/O A

SER I/O B

x16 PCI Exp ess

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7756, 7756D

Dual/Quad 400 MHz A/D, 800 MHz D/A,Virtex-5 FPGAs - x16 PCIe
part, providing not only interface
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to each processing FPGA, and 16 pairs of LVDS connections to each interface FPGA for custom I/O. Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks per processing FPGA (2 GB max.) PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: two x4 ports per FPGA; one x4 port per PCI bus; one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe, 4.38 in. x 12.3 in.

PCI Express Interface


The 7756 includes a multiple port, 48-lane Gen 2 PCIe switch with integrated SerDes. The switch provides x16 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports include buffer memory to minimize bottlenecks. Two x4 PCIe connections are provided to each FPGA, as well as one x4 connection to each 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to two slave 7756Ds and three slave 7756s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
Up to four independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

Ordering Information
Model 7756 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length x16 PCIe Quad 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length x16 PCIe

7756D

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688

Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit serial I/O: two fullduplex 4X paths (Model 7756) or four full duplex4X paths (Model 7756D)

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7758, 7758D

Dual/Quad 500 MHz A/D, 800 MHz D/A,Virtex-5 FPGAs - x16 PCIe
General Information
Model 7758 is a high-speed data converter suitable for connection to HF or IF ports of a communication system. It is available with either two A/Ds, D/As and FPGAs (Model 7758), or four A/Ds, D/As and FPGAs (Model 7758D). It attaches to motherboards with full-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.

Virtex-5 FPGAs
The architecture includes two or four Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family
RF In
RF XFORMR

Model 7758D

A/D Converter Stage


The front end accepts two or four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5463 12-bit 500 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the Virtex-5 processing FPGA for signal processing or routing to other board resources.

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x16 wide Two or four 500 MHz, 12-bit A/Ds One or two DUCs (Digital Upconverters) Two or four 800 MHz, 16-bit D/As Up to 2 GB of DDR2 SDRAM Two or four Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 or 64 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIM NG BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus D/A Clock Bus

500 MHz 12 B T A/D 14

500 MHz 12 B T A/D 14

800 MHz 16 BIT D/A

800 MHz 16 BIT D/A

TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS

DIGITAL UPCONVERTER 32

To All Sections VCXO

Timing Bus

Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 256 MB

PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T


GTP GTP GTP LVDS

8 FLASH 32 MB

4X

4X

4X
GTP

64

INTERFACE FPGA VIRTEX 5 LX30T or SX50T


PCI X LVDS

GTP

4X

64

32
32

PCI X BUS 1 (64 B ts 100 MHz)

Block Diagram, Model 7758. Model 7758D doubles all resources except the PCIe switch.

4X Gbit Serial

4X Gbit Serial 4X 4X

PCI TO PCIe BRIDGE

GP O 1 (68-Pin)

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

SER I/O A

SER I/O B

x16 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Models 7758, 7758D

Dual/Quad 500 MHz A/D, 800 MHz D/A,Virtex-5 FPGAs - x16 PCIe
part, providing not only interface
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to each processing FPGA, and 16 pairs of LVDS connections to each interface FPGA for custom I/O. Type: TI DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks per processing FPGA (2 GB max.) PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x16 width PCIe Ports: two x4 ports per FPGA; one x4 port per PCI bus; one x16 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Full-length PCIe, 4.38 in. x 12.3 in.

PCI Express Interface


The 7758 includes a multiple port, 48-lane Gen 2 PCIe switch with integrated SerDes. The switch provides x16 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports include buffer memory to minimize bottlenecks. Two x4 PCIe connections are provided to each FPGA, as well as one x4 connection to each 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to two slave 7758Ds and three slave 7758s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Ordering Information
Model 7758 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length x16 PCIe Quad 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Full-length x16 PCIe

Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

7758D

Options: -104 FPGA I/O through the GPIO connector(s) -140 1 GB DDR2 SDRAM, Model 7758; 2 GB DDR2 SDRAM, Model 7758D -5xx Gigabit serial I/O: two fullduplex 4X paths (Model 7758) or four full duplex4X paths (Model 7758D)

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

RAD AR & SDR I/O - x 8 PCI Express RADAR


MODEL
7850 7851 7852 7853 7856 7858 Cobalt 78620 Cobalt 78621 Cobalt 78630 Cobalt 78640 Cobalt 78641 Cobalt 78650 Cobalt 78651 Cobalt 78660 Cobalt 78661 Cobalt 78662 Cobalt 78670 Cobalt 78671 Cobalt 78690 Cobalt 7809 Onyx 78720 Onyx 78760

DESCRIPTION
Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x8 PCIe 256-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe 32-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe 4/2-Channel DDC, four 200 MHz 16-bit A/Ds, Beamformer - x8 PCIe Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 3-Channel 200 MHz A/D with DDC, DUC, 2-Channel 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIe 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Virtex-6 FPGA - x8 PCIe 1-Channel 3.6 GHz or 2-Channel 1.8 GHz 12-bit A/D, Wideband DDC, Virtex-6 FPGA - x8 PCIe Two 500 MHz A/Ds, DUC, 800 MHz D/As, Virtex-6 FPGA - x8 PCIe 2-Chan 500 MHz A/D with DDC, DUC with 2-Chan 800 MHz D/A, Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz, 16-bit A/D, Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe 4-Channel 200 MHz A/D with 32-Channel DDC and Virtex-6 FPGA - x8 PCIe 4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIe 4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe L-Band RF Tuner, 2-Channel 200 MHz A/D, Virtex-6 FPGA - x8 PCIe 4-Channel SFP Transceiver PCIe Module for Cobalt Boards 3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A, Virtex-7 FPGA - x8 PCIe 4-Channel 200 MHz, 16-bit A/D, Virtex-7 FPGA - x8 PCIe Customer Information

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& & & & &

SDR SDR SDR SDR SDR

I/O I/O I/O I/O I/O

PMC/XMC CompactPCI PCI x16 PCI Express 3U VPX

Last updated: February 2013


www.pentek.com

Model 7850

Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x8 PCIe


General Information
Model 7850 is a high-speed data converter suitable for connection as the HF or IF input of a communications system. It features four 200 MHz, 16-bit A/Ds. These are supported by an array of data processing and transport resources ideally matched to requirements of high-performance systems. The 7850 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. cessing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the A/D converters, DDR2 SDRAM memory, interface FPGA, programmable LVPECL I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T and FX100T. The SXT parts feature between 288 and 640 DSP48E Slices and are ideal for demodulation/modulation, decoding/ encoding, decryption/encryption, digital delay and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the Model 7150 can be optionally configured with an LX155T in the processing FPGA position for 155,648 logic cells. The interface FPGA provides board connections including PCI-X or PCI Express. Implementing the PCI interfaces in this FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT or an SXT family part, providing not only interface functionality, but processing resources up to an additional 640 DSP48E Slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
RF In
RF XFORMR Sample Clk In PPS In TIMING BUS GENERATOR Clock / Sync / Gate / PPS To All Sections

A/D Converter Stage


The front end accepts four full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-5 FPGA for signal processing or for routing to other module resources.

Virtex-5 FPGAs
The Model 7850 architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory- shipped functions. There are two FPGA types on the 7850: processing and interface. The pro-

Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Four 200 MHz 16-bit A/Ds Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Up to 2.56 seconds of data capture at 200 MHz LVPECL clock/sync bus for multimodule synchronization Up to 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF In
RF XFORMR

RF In
RF XFORMR

Clock/Sync Bus

TTL In

200 MHz 16 bit A/D

200 MHz 16 bit A/D

200 MHz 16 bit A D

200 MHz 16 bit A/D

LVPECL Bus
XTL OSC

Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX 5 LX50T SX50T SX95T LX155T or FX100T


GTP GTP GTP LVDS

Timing Bus

8
4X 4X

4X
GTP

64

FLASH 32 MB

INTERFACE FPGA VIRTEX 5 LX30T or SX50T


GTP PCI X LVDS

4X

64

32

PCI X BUS 1 (64 Bits, 100 MHz)

32

4X Gbit Serial

4X Gbit Ser al 4X 4X

PCI TO PCIe BRIDGE

GPIO 1 (68-Pin)

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

x8 PCI Express
SER I/O A SER I/O B

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7850

Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs - x8 PCIe


Clocking and Synchronization
The Model 7850 architecture includes a flexible timing and synchronization circuit for each bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. Each timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/ Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7850s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VLX155T and XC5VFX100T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to the processing FPGA and 16 pairs to the interface FPGA Memory DDR2 SDRAM: Up to 1 GB in two banks PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to processing FPGA; one can be alternately routed to interface FPGA one x4 port to PCI bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe , 4.38 in. x 6.6 in.

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGA. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering. Each memory bank can be easily accessed through the PCI interface using the on-board DMA controllers. Custom user-installed functions within the FPGA can take advantage of the SDRAM for many other purposes.

PCI Express Interface


The 7850 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with two x4 PCIe connections provided to the processing FPGA, as well as one x4 connection to the 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.

Ordering Information
Model 7850 Description Quad 200 MHz, 16-bit A/D with Virtex-5 FPGAs Half-length x8 PCIe

Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit Serial I/O - two full duplex 4X paths

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7851

256-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe


General Information
Model 7851 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds. The A/D converters are supported by a high-performance 256-channel installed DDC (digital down-converter) IP Core and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 7851 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. including one A/D driving all 256 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the DDCs has an independent 32-bit tuning frequency setting that ranges from DC to s where s is the A/D sample rate.

Decimation and Filtering


All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 156.25 kHz to 1.25 MHz. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 64. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

A/D Converter Stage


The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.

Features

DDC Input Selection and Tuning


The Model 7851 SX95T FPGA employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks. Four independently controllable input multiplexers select one of the attached four A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling 256 DDC channels Four 200 MHz 16-bit A/Ds Independent tuning for each channel DDC decimation from 128 to 1024 in steps of 64 Independent decimation for each bank Each bank independently selects one of four A/Ds User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multimodule synchronization

CH 1 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 2 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 3 CH 4
M U X D GITAL DOWNCONVERTER BANK 1: CH 1-64 DEC: 128 - 1024

CH 1 I+Q
M U X

FIFO 1

CH 3 RF In

RF XFORMR

200 MHz 16-bit A/D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16-bit A/D

CH 2
M U X D GITAL DOWNCONVERTER BANK 2: CH 65-128 DEC: 128 - 1024

CH 3 CH 4

I+Q

M U X

FIFO 2

Sample Clock In PPS In TTL In LVPECL Bus Timing Bus

CH 1 TIM NG BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4


M U X DIGITAL DOWNCONVERTER BANK 4: CH 193-256 DEC: 128 - 1024

CH 3
M U X DIGITAL DOWNCONVERTER BANK 3: CH 129-192 DEC: 128 - 1024

CH 2 CH 3 CH 4

I+Q

M U X

FIFO 3

CH 4 I+Q
M U X

FIFO 4

XILINX XC5VSX95T
Xilinx XC5VLX30T PCI-X NTERFACE

PCI TO PCIe BRIDGE

PCI-X BUS 1

x4 PCIe
PCI EXPRESS SW TCH PEX 8648

x8 PCI Exp ess

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7851

256-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe


Output Multiplexers and FIFOs
Four output MUXs in the SX95T FPGA can be independently switched to deliver either A/D or DDC data into each output FIFO. This allows users to view either wideband A/D data or narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 133 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI-X bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.

Clocking and Synchronization


The Model 7851 architecture includes a flexible timing and synchronization circuit for the bank of four A/D converters, allowing the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connectors allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple bords. Up to three slave 7851s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. More boards can be synchronized with an external clock and sync generator.

PCI Express Interface


The 7851 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with a x4 connection provided to the 64-bit PCI-X interface.

Ordering Information
Model 7851 Description 256-Channel DDC with four 200 MHz, 16-bit A/D - Half-length x8 PCIe

Options: -731 Two-slot heat sink

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7852

32-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe


General Information
Model 7852 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds. The A/Ds are supported by a high-performance 32-channel installed DDC (digital downconverter) IP Core, and interfaces ideally matched to the requirements of real-time software radio and radar systems. The 7852 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.

Decimation and Filtering


All of the eight channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have a unique decimation setting supporting up to four different output bandwidths for the board. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. Rejection of adjacent-band components within the 80% bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled with each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.

A/D Converter Stage


The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.

DDC Input Selection and Tuning


The Model 7852 SX95T FPGA employs an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four attached A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the DDCs has an independent 32-bit tuning frequency setting ranging from DC to s (s is the A/D sample rate).

Power Meters and Threshold Detectors


The 7852 features 32 power meters that continuously measure the individual average power output of each DDC channel. The time constant of the averaging interval for each meter is programmable up to 16 kilosamples. In addition, threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.

Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling 32 channels of DDC in banks of 8 channels Independent 32-bit DDC tuning for all channels DDC decimation from 16 to 8192 in steps of 8 Bandwidths from 20 kHz to 10 MHz Different decimation factors between banks User-programmable 18-bit FIR filter coefficients Default filters offer 0.2 dB ripple and 100 dB rejection Power meters and threshold detectors LVPECL clock/sync bus for multimodule synchronization

CH 1 RF In

RF XFORMR

200 MHz 16 bit A/D


8X4 CHANNEL SUMMATION M U X DDC BANK 1 CH 1 8 DEC 16 8192

CH 1 I+Q
M U X F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4

CH 2 RF In

RF XFORMR

200 MHz 16 bit A/D

CH 1 CH 2 CH 3 CH 4 I+Q
POWER METER & THRESHOLD DETECTORS

CH 3 RF In

RF XFORMR

200 MHz 16 bit A/D

CH 1 CH 2 CH 4 RF In
RF XFORMR 200 MHz 16 bit A/D

CH 2
M U X

CH 3 CH 4

M U X

DDC BANK 2 CH 9 16 DEC 16 8192

I+Q
POWER METER & THRESHOLD DETECTORS

Sample C k In PPS In

CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 CH 3 CH 4


M U X DDC BANK 4 CH 25 32 DEC 16 8192

CH 3
M U X

CH 2 CH 3 CH 4

M U X

TTL In

DDC BANK 3 CH 17 24 DEC 16 8192

I+Q
POWER METER & THRESHOLD DETECTORS

CH 4
M U X

LVPECL Bus

I+Q
POWER METER & THRESHOLD DETECTORS

XTAL OSC

Timing Bus

XILINX XC5VSX95T
Xilinx XC5VLX30T PCI X INTERFACE

PCI TO PCIe BRIDGE

PCI X BUS 1

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7852

32-Channel DDC with Four 200 MHz, 16-bit A/Ds - x8 PCIe


Output Multiplexers and FIFOs
Four output MUXs in the SX95T FPGA can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillators, external or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS input/output LVPECL bus; one gate/trigger and one sync/ PPS input TTL signal Field Programmable Gate Array Processing FPGA: Xilinx Virtex-5 XC5VSX95T dedicated to digital downcoverters and output Interface FPGA: Xilinx Virtex-5 XC5VLX30T dedicated to the PCI interface PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI-X bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe , 4.38 in. x 6.6 in.

Clocking and Synchronization


The Model 7852 architecture includes a flexible timing and synchronization circuit for the group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple modules to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7852s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules. For larger systems, many more modules can be synchronized with an external clock and sync generator.

PCI Express Interface


The 7852 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with one x4 connection provided to the 64-bit PCI-X interface.

Ordering Information
Model 7852 Description 32-Channel DDC with four 200 MHz, 16-bit A/D s Half-length x8 PCIe

Options: -731 Two-slot heat sink

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7853

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - x8 PCIe


General Information
Model 7853 is a high-speed software radio board designed for processing baseband RF or IF signals from a communications receiver. It features four 200 MHz 16-bit A/Ds supported by a high-performance 4-channel installed DDC (digital downconverter) and a complete set of beamforming functions. With buit-in multiboard synchronization, it is ideally matched to the requirements of real-time software radio and radar systems. The 7853 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems. Each of the DDC channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency.

Decimation and Filtering


Each of the four DDC channels can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. The DDC core can be configured in four-channel mode with each channel offering decimations between 2 and 256, or in two-channel mode with each channel having a decimation range of 2 to 65536, for applications that require a wider range of decimations. The decimating filter for each DDC channel accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N.

Features

A/D Converter Stage


The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.

Built-in Beamformer supports multiboard systems Programmable Power Meter and Threshold Detect per channel Four 200 MHz, 16-bit A/Ds 2 or 4 Channels of DDC PCI Express 2.0 (Gen. 2) interface up to x8 wide Independent 32-bit DDC tuning for all channels DDC decimation range from 2 to 256 or from 2 to 65536 Independent decimation factors for each channel Default filters offer 0.2 dB ripple and 100 dB rejection LVPECL clock/sync bus for multiboard synchronization

DDC Input Selection and Tuning


The Model 7853 employs an advanced FPGA-based digital downconverter engine consisting of two or four DDC channels. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC channel. In this way, many different configurations can be achieved including one A/D driving all four DDC channels and each of the four A/Ds driving its own DDC bank.

Power Meters
Each DDC includes a power meter that continuously measures the individual average power output. The power meters calculate and present average power measurements for each channel in easy-to-read registers. The time constant of the averaging interval for each meter is programmable up to 8 kilosamples. Threshold detectors can generate interrupts when the calculated power levels exceed or fall below user-programmable thresholds, ideal for scanning and monitoring applications.

CH 1 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4 CH 1 CH 2 CH 3 CH 4
M U X SUMMER

SUM IN SUM OUT

AURORA GIGAB T SERIAL INTERFACE F I F 0 1 F I F 0 2 F I F 0 3 F I F 0 4

4X 4X P15 XMC

CH 2 RF In

RF XFORMR

200 MHz 16-bit A D

I+Q CH 1
M U X

CH 3 RF In

RF XFORMR

200 MHz 16-bit A D

D G TAL DOWNCONVERTER CH 1 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHO D DETECTORS

CH 4 RF In

RF XFORMR

200 MHz 16-bit A D

CH 1 CH 2 CH 3 CH 4
M U X

CH 2
M U X

D G TAL DOWNCONVERTER CH 2 DEC: 2 - 65536 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHO D DETECTORS

Xilinx XC5VLX30T PCI-X INTERFACE PCI-X BUS 1

Sample Clock In PPS In TTL In LVDS Bus Timing Bus

CH 1 TIMING BUS GENERATOR Clock / Sync / Gate / PPS CH 1 CH 2 XTAL OSC CH 3 CH 4


M U X D G TAL DOWNCONVERTER CH 4 (DEC: 2 - 256)*

CH 3
M U X

CH 2 CH 3 CH 4

M U X

D G TAL DOWNCONVERTER CH 3 (DEC: 2 - 256)*

I+Q
POWER METER & THRESHO D DETECTORS

PCI TO PCIe BRIDGE


x4 PCIe PCI EXPRESS SWITCH PEX 8648 x8 PCI Express

CH 4
M U X

I+Q
POWER METER & THRESHO D DETECTORS

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

XILINX XC5VSX95T

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7853

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - x8 PCIe


Beamformer
In addition to the A/Ds and DDCs, these Models include essential resources of a complete beamforming subsystem. First, each DDC channel provides user-programmable I & Q phase and gain adjustments to apply beamforming weights. Then, a summation block adds the four DDC output channels. An additional programmable-gain stage compensates for summation bit growth. A power meter and threshold detect block is provided for the sum output. The sum output is then delivered to the Channel 1 FIFO for delivery through the PCI-X bus. For larger systems, multiple Models can be chained together using a built-in Xilinx Aurora engine. It accepts an x4 gigabit sum input stream from a previous board and propagates an x4 sum output stream to the next board through the P15 XMC connector.

Clocking and Synchronization


The Model 7853 architecture includes a flexible timing and synchronization circuit for the group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Up to three slave 7853s can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. For larger systems, many more boards can be synchronized with an external clock and sync generator.

XMC Interface
For large systems, multiple 7853s can be chained together via a built-in Xilinx Aurora interface through the P15 XMC connector. This link creates a board-toboard summation expansion chain for creating larger multichannel beamformer systems. Xilinxs Aurora protocol is used to provide an efficient x4, 1.25 GB/sec point-to-point data path between boards.

Output Multiplexers and FIFOs


Four output MUXs can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

PCI Express Interface


The 7853 includes a multiple port, 48-lane Gen. 2 PCI Express (PCIe) switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports each include buffer memory to minimize bottlenecks, with one x4 connection provided to the 64-bit PCI-X interface.

PHASE SHIFT
DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

GAIN

I Q

I Q

I
Q

I
Q

DIG TAL DOWNCONVERTER A

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT A

AURORA PORT

SUMMAT ON EXPANS ON CHAIN IN 1 25 GByte/sec x4 Auro a Link

F om P evious Boa d

P15
GAIN

DECIMAT ON: 2-65536 (DECIMATION: 2-256)*

I Q

I Q

I Q

I Q
SUMMATION CHA N B T GROWTH COMPENSAT ON

DIG TAL DOWNCONVERTER B

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

POWER METER & THRESHO D DETECT B

I Q

I Q

I Q

To FIFO 1 (Final Result or Intermediate Result

GAIN

(DECIMATION: 2-256)*

I Q

I Q

I
Q

I
Q

Summation Chain Gain POWER METER & THRESHO D DETECT C

SUMMATION POWER METER & THRESHOLD DETECT

DIG TAL DOWNCONVERTER C

Weight Phase I Weight Phase Q Weight Gain PHASE SHIFT

AURORA PORT

SUMMAT ON EXPANS ON CHA N OUT 1 25 GByte/sec x4 Auro a Link

To Next Board

GAIN

P15 I
Q

I
Q

I
Q

(DECIMATION: 2-256)*

DIG TAL DOWNCONVERTER D

Weight Phase I Weight Phase Q Weight Gain

POWER METER & THRESHO D DETECT D

*2 Channel Mode: Dec 2-65536, 4 Channel Mode: Dec 2-256

BEAMFORMER DATA FLOW DETAIL

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7853

4/2-Ch. DDC, four 200 MHz 16-bit A/Ds, Beamformer - x8 PCIe


Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Internal Clock: 200 MHz crystal osc. External Clock: 10 to 200 MHz Resolution: 16 bits A/D Data Reduction Mode: Data from the A/Ds can be decimated by any value between 1 and 4096 Clock Sources: Selectable from onboard crystal oscillator, external reference or LVPECL clocks External Clock Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC-coupled 50 ohms Sync/Gate Bus: 26-pin connector, clock/ sync/gate/PPS, input/output LVPECL bus; one gate/trigger and one sync/PPS input TTL signal Digital Downconverter Type: IP core for Xilinx Virtex-5 Qty of DDC Channels: 2 or 4 Center Frequency Tuning: 4 tuning words, one for each DDC channel Center Frequency Tuning Range: DC to s with 32 bit resolution NCO SFDR: 120 dBFS Channel Phase Offset Adjustment: 32-bit resolution Channel Gain Adjustment: 32-bit resolution Input Selection for DDC Banks: Any channel can select any of the four A/Ds Decimation Range (N): 2-Channel Mode: 2 to 65536 4-Channel Mode: 2 to 256 FIR Filter: Default passband 0.8*s/N with 0.2 dB passband ripple and 100 dB adjacent channel rejection FIR Filter Coefficients: 18 bits, user-programmable (default values provided) Qty FIR Filter Taps: 28*N/8 Output Format: 24 bits I + 24 bits Q Output Spectrum Modes: Normal or frequency-reversed Output Spectrum Offset: No offset or offset by one-half the output bandwidth Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Output Multiplexer and FIFO Qty Output FIFOs: Four FIFO Source Selection: Independent multiplexer selects DDC output or A/D PCI to PCIe Interface PCI-X Bus: 64 bits, 100 MHz and 64 or 32 bits at 33 or 66 MHz DMA: 4-channel demand-mode and chaining controller PCIe Interface: Gen. 2, x8 width PCIe Ports: one x4 port to PCI-X bus one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.

Ordering Information
Model 7853 Description 4-Channel DDC with four 200 MHz, 16-bit A/Ds and Beamformer - Half-length x8 PCIe

Options: -731 Two-slot heat sink

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7856

Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
General Information
Model 7856 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 400 MHz A/Ds, 800 MHz D/ As and Virtex-5 FPGAs. The 7856 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.

Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family

A/D Converter Stage


The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5474 14-bit 400 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the processing FPGA for signal processing, capture or routing to other board resources.

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Two 400 MHz, 14-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR Sample Clk / Reference Clk In PPS In TIM NG BUS GENERATOR Clock / Sync / Gate / PPS

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

A/D Clock Bus D/A Clock Bus

400 MHz 14 BIT A/D 14

400 MHz 14 BIT A D 14

800 MHz 16 BIT D A

800 MHz 16 BIT D/A

TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS

DIGITAL UPCONVERTER 32

To All Sections VCXO

T ming Bus

Control/ Status
32 DDR2 SDRAM 512 MB 32 DDR2 SDRAM 512 MB

PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T


GTP GTP GTP LVDS

8 FLASH 32 MB

4X

4X

4X
GTP

64

INTERFACE FPGA VIRTEX 5 LX30T or SX50T


PCI X LVDS

GTP

4X

64

32
32

PCI X BUS 1 (64 B ts 100 MHz)

4X Gbit Serial

4X Gbit Serial 4X 4X

PCI TO PCIe BRIDGE

GPIO 1 (68-Pin)

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

SER /O A

SER /O B

x8 PCI Exp ess

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7856

Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
part, providing not only interface
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O. Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 400 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to FPGA; one x4 port to PCI bus; one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.

PCI Express Interface


The 7856 includes a multiple port, 48-lane Gen. 2 PCIe switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports include buffer memory to minimize bottlenecks. Two x4 PCIe connections are provided to the FPGA, as well as one x4 connection to the 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7856s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
Up to two independent 512 MB banks of DDR2 SDRAM are available to the processing FPGAs. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

Ordering Information
Model 7856 Description Dual 400 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length x8 PCIe

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: TI DAC5688

Options: -104 FPGA I/O through the GPIO connector(s) -5xx Gigabit serial I/O: two fullduplex 4X paths

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7858

Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
General Information
Model 7858 is a dual-channel, high-speed data converter suitable for connection to HF or IF ports of a communication system. It includes two 500 MHz A/Ds, 800 MHz D/ As and Virtex-5 FPGAs. The 7858 attaches to motherboards with half-length PCI Express (PCIe) interface slots for installation in various PCs, blade servers and computer systems.

Virtex-5 FPGAs
The architecture includes two Virtex-5 FPGAs. All of the boards data and control paths are accessible by the FPGAs, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. In addition to the built-in functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. The processing FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters, DDR2 SDRAM memory, interface FPGA, programmable LVDS I/O and clock, gate and synchronization circuits. The processing FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: Virtex-5 SX50T, SX95T, LX50T, LX155T, and FX100T. The SXT parts feature between 288 and 640 DSP48E slices and are ideal for demodulation/modulation, decoding/encoding, decryption/encryption, digital delay, and channelization of the signals between reception and transmission. For applications requiring more FPGA logic cells, the board can be optionally configured with an LX155T in the processing FPGA position for 156,648 logic cells. A second Virtex-5 FPGA provides the boards PCI-X interface. Implementing the interface in this second FPGA keeps the processing FPGA resources free for signal processing. The interface FPGA can be configured as an LXT family or an SXT family part, providing not only interface
RF In
RF XFORMR

A/D Converter Stage


The front end accepts two full scale analog HF or IF inputs on front panel SMC connectors at +8 dBm into 50 ohms with transformer coupling into TI ADS5463 12-bit 500 MHz A/Ds. Designed with a 750 MHz input bandwidth, the A/Ds are excellent for undersampling applications. The digital outputs are delivered into the processing FPGA for signal processing, capture or routing to other board resources.

Digital Upconverter and D/A Stage


A TI DAC5688 digital upconverter (DUC) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as an upconverter, it interpolates and translates real or complex baseband input signals to any IF center frequency between DC and 300 MHz. It delivers real or quadrature (I+Q) outputs at up to 500 MHz to the 16-bit D/A converter. Analog output is through a pair of front panel SMC connectors at +4 dBm into 50 ohms. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC provides interpolation factors of 2x, 4x and 8x.

Features

Complete software radio interface solution PCI Express 2.0 (Gen. 2) Interface up to x8 wide Built-in fan for added cooling Two 500 MHz, 12-bit A/Ds One DUC (Digital Upconverter) Two 800 MHz, 16-bit D/As Up to 1 GB of DDR2 SDRAM Two Xilinx Virtex-5 FPGAs Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization 32 pairs of LVDS connections to the Virtex-5 FPGAs for custom I/O

RF In
RF XFORMR

RF Out
RF XFORMR

RF Out
RF XFORMR

Sample Clk / Reference Clk In PPS In

TIM NG BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock Bus D/A Clock Bus

500 MHz 12 BIT A/D 14

500 MHz 12 BIT A D 14

800 MHz 16 BIT D A

800 MHz 16 BIT D/A

TTL Gate / Trig TTL Sync / PPS Sample C k Sync C k Gate A Gate B Sync PPS

DIGITAL UPCONVERTER 32

To All Sections VCXO

T ming Bus

Control/ Status
32 DDR2 SDRAM 256 MB 32 DDR2 SDRAM 256 MB

PROCESSING FPGA VIRTEX 5 LX50T LX155T SX50T SX95T or FX100T


GTP GTP GTP LVDS

8 FLASH 32 MB

4X

4X

4X
GTP

64

INTERFACE FPGA VIRTEX 5 LX30T or SX50T


PCI X LVDS

GTP

4X

64

32
32

PCI X BUS 1 (64 B ts 100 MHz)

4X Gbit Serial

4X Gbit Serial 4X 4X

PCI TO PCIe BRIDGE

GPIO 1 (68-Pin)

x4 PCIe
PCI EXPRESS SWITCH PEX 8648

SER /O A

SER /O B

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 7858

Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - x8 PCIe
functionality, but processing resources up to an additional 640 DSP48E slices. Option -104 installs a GPIO connector with 16 pairs of LVDS connections to the processing FPGA, and 16 pairs of LVDS connections to the interface FPGA for custom I/O.
Input Data Rate: 250 MHz max. Output IF: DC to 300 MHz Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with intepolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SMC connectors Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer: Clocks Source: Selectable from on-board programmable VCXO, front panel external clock or LVPECL timing bus Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clocks Type: Front panel female SMC connector, sine wave, 0 to +10 dBm, AC- coupled, 50 ohms, accepts 20 to 500 MHz sample clock or 10 MHz system reference Timing Bus: 26-pin connector LVPECL bus includes clock/sync/gate/PPS input/ output; TTL signals for gate/trigger and sync/PPS inputs Field Programmable Gate Arrays Processing FPGA: Xilinx Virtex-5 XC5VSX50T; optional FPGAs include: XC5VLX50T, XC5VSX95T, XC5VFX100T, or XC5VLX155T Interface FPGA: Xilinx Virtex-5 XC5VLX30T; optional FPGA: XC5VSX50T or XC5VFX70T Custom I/O Available only with SX95T, LX155T and FX100T FPGAs Option -104: Provides GPIO with 16 LVDS pairs to each processing FPGA and 16 pairs to each interface FPGA Memory DDR2 SDRAM: Up to 1.0 GB in two banks to processing FPGA PCI to PCIe Interface PCI-X Bus: 64-bits, 100 MHz and 64- or 32-bits at 33 or 66 MHz DMA: 4 channel demand-mode and chaining controller per PCI bus PCIe Interface: Gen. 2, x8 width PCIe Ports: two x4 ports to FPGA; one x4 port to PCI bus; one x8 port to PCIe motherboard Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe, 4.38 in. x 6.6 in.

PCI Express Interface


The 7858 includes a multiple port, 48-lane Gen. 2 PCIe switch with integrated SerDes. The switch provides x8 wide connection to the PCIe interface, allowing high-speed data transfers to and from the motherboard. Switch ports include buffer memory to minimize bottlenecks. Two x4 PCIe connections are provided to the FPGA, as well as one x4 connection to the 64-bit PCI-X interface. Option -5xx adds two full duplex 4X gigabit serial paths on high-speed connectors, supporting PCIe or other gigabit protocols.

Clocking and Synchronization


Two internal timing buses can provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An internal clock generator receives an external sample clock from the front panel SMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage controlled crystal oscillator. In this mode, the front panel SMC connector can be used to provide a 10 MHz system reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Up to three slave 7858s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
Two independent 256 MB banks of DDR2 SDRAM are available to the processing FPGA. These can be upgraded to 512 MB banks with option -140. Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering and D/A waveform playback mode. All memory banks are supported with DMA engines for easily moving data through the PCI interface.

Ordering Information
Model 7858 Description Dual 500 MHz A/D, 800 MHz D/A, Virtex-5 FPGAs - Half-length x8 PCIe

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: TI ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits D/A Converters Type: TI DAC5688

Options: -104 FPGA I/O through the GPIO connector -140 1 GB DDR2 SDRAM -5xx Gigabit serial I/O: two fullduplex 4X paths

Contact Pentek for additional available options.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78620

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - x8 PCIe
General Information
Model 78620 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78620 includes optional general-purpose and gigabit serial card edge connectors for application-specific I/O . and a PCIe interface complete the factoryinstalled functions and enable the 78620 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78620 factory-installed functions include three A/D acquisition and a D/A waveform playback IP modules, ideally matched to the boards analog interfaces. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator,
RF In

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
RF In RF In RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

GTX

GTX

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

40

8X

4X

4X

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Optional FPGA GPIO 68-pin Header

x8 PCIe

Optional Serial I/O Dual 4X Serial Conn

Memory Banks 1 & 2

Memory Banks 3 & 4

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78620
A/D Acquisition IP Modules
The 78620 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - x8 PCIe
A/D Converter Stage
The front end accepts three full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78620s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Memory Resources
The 78620 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the
to D/A D/A loopback
TEST SIGNAL GENERATOR

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.
from A/D Ch 1 from A/D Ch 2 from A/D Ch 3

D/A Waveform Playback IP Module


The Model 78620 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either onboard memory or off-board host memory. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

MEMORY CONTROL

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78620

3-Ch. 200 MHz A/D, 2-Ch. 800 MHz D/A, Virtex-6 FPGA - x8 PCIe
boards DMA capabilities, providing
FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz sample clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks. 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.

PCI Express Interface


The Model 78620 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz

Ordering Information
Model 78620 Description 3-Channel 200 MHz A/D and 2-Channel 800 MHz D/A with Virtex-6 FPGA PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Options: -062 -064 -104

-105

-150

-160

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78621

3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
General Information
Model 78621 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes three A/Ds, two D/As and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78621 includes an optional general-purpose connector for applicationspecific I/O. sition modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 78621 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78621 factory installed functions include three A/D acquisition and a D/A waveform playback IP modules. Each of the three acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquiRF In

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O.
RF In RF In RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Three 200 MHz 16-bit A/Ds Three multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF XFORMR Sample Clk / Reference Clk In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


LVDS

GTX

GTX

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

40

8X

4X

4X

x8 PCIe Optional FPGA GPIO 68-pin Header x8 PCI Express Sum from previous board

Aurora Gigabit Serial I/O Sum to next board Dual 4X Serial Conn

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Memory Banks 1 & 2

Memory Banks 3 & 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78621
A/D Acquisition IP Modules
The 78621 features three A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from any of the three A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
frequency. Each DDC can have its own unique decimation setting, supporting as many as three different output bandwidths for the board. Decimations can be programmed from 2 to 65,536 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or 16-bit I + 16-bit Q samples at a rate of s/N. A programmable summation block provides summing of any of the three DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 78621s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.

Beamformer IP Core
In addition to the DDCs, the 78621 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold.

D/A Waveform Playback IP Module


The Model 78621 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or off- board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3 D/A loopback

to D/A

INPUT MULTIPLEXER

TEST SIGNAL GENERATOR

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all three DDCs or each of the three A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

MUX

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

8X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78621

3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
A/D Converter Stage
The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78621s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to crate a total range from 2x to 524,288x.

Memory Resources
The 78621 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the modules DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alter-

PCI Express Interface


The Model 78621 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78621

3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Three channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Three channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

Ordering Information
Model 78621 Description 3-Channel 200 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe

Options: -062 -064 -104 XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

-150

-160

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78630

1 GHz A/D and 1 GHz D/A with Virtex-6 FPGA - x8 PCIe


General Information
Model 78630 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes 1 GHz A/D and 1 GHz D/A converters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78630 includes optional general-purpose and gigabit serial card connectors for application specific I/O protocols. generator and a PCIe interface complete the factory-installed functions and enable the 78630 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory installed applications ideally matched to the boards analog interfaces. The 78630 factory-installed functions include an A/D acquisition and a D/A waveform playback IP module. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
RF In RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One 1 GHz 12-bit A/D One 1 GHz 16-bit D/A Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Sync In

1 GHz 12-BIT A/D

A/D Sync Bus


Gate In Sync In

D/A Clock/Sync Bus


12

1 GHz 16-BIT D/A 16

D/A Sync Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

GTX

GTX

GTX

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 DDR3 SDRAM 512 MB

16

16 Config FLASH 64 MB 40

8X

4X

4X

Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB

Memory Banks 3 & 4 DDR3 option 165

Optional FPGA GPIO 68-pin Header

x8 PCIe

Optional Serial I/O Dual 4X Serial Conn

QDRII+ option 150

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78630
A/D Acquisition IP Module
The 78630 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, a test signal generator, or from the D/A Waveform Playback IP Module in loopback mode. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

1 GHz A/D and 1 GHz D/A with Virtex-6 FPGA - x8 PCIe


A/D Converter Stage
The front end accepts an analog HF or IF input on a front panel SSMC connector with transformer coupling into a Texas Instruments ADS5400 1 GHz, 12-bit A/D converter. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. Two front panel 7-pin LVPECL Sync connectors allows multiple boards to be synchronized. One connector for the A/D and one for the D/A each provide sync and gate signals.

D/A Converter Stage


The 78630 features a TI DAC5681Z 1 GHz, 16-bit D/A. The converter has an input sample rate of 1 GSPS, allowing it to acept full rate data from the FPGA. Additionally, the D/A includes a 2x or 4x interpolation filter for applications that provide 1/2 or 1/4 rate input data. Analog output is through a front panel SSMC connector.

Memory Resources
The 78630 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to

from A/D D/A loopback


TEST SIGNAL GENERATOR

to D/A

D/A Waveform Playback IP Module


The Model 78630 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back waveforms stored in either on-board memory or off- board host memory to the D/A. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROLLER MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP) 8X PCIe Gigabit Serial I/O 4X 4X 40

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

FPGA GPIO

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78630

1 GHz A/D and 1 GHz D/A with Virtex-6 FPGA - x8 PCIe


PCI Express Interface
The Model 78630 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 100 MHz to 1 GHz divider input clock, or PLL system reference Timing Bus: 7-pin connectors, LVPECL bus for sync and gate, one A/D connector and one D/A connector External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2, or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8 Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADS5400 Sampling Rate: 100 MHz to 1 GHz Resolution: 12 bits D/A Converter Type: Texas Instruments DAC5681Z Input Data Rate: 1 GHz max. Interpolation Filter: bypass, 2x or 4x Output Sampling Rate: 1 GHz max. Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO or front panel external clock VCXO Frequency Ranges: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz Synchronization: VCXO can be locked to an external 4 to 200 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock

Ordering Information
Model 78630 Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T XC6VSX315T LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required Description 1 GHz A/D and D/A, Virtex-6 FPGA - x8 PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78640

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - x8 PCIe
General Information
Model 78640 is a member of the Cobalt family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. A highspeed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. The 78640 includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78640 includes optional general-purpose and gigabit serial connectors for application-specific I/O protocols. and a PCIe interface complete the factoryinstalled functions and enable the 78640 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
RF In RF In

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78640 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchronization functions, a test signal generator

Features

Ideal radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Reset In Ref Clk In Ref Clk Out

3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-Bit A/D


12 12

Sync Bus

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

GTX

GTX

GTX

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

40

8X

4X

4X

Memory Banks 1 & 2

Memory Banks 3 & 4

Optional FPGA GPIO 68-pin Header

x8 PCIe

Optional Serial I/O Dual 4X Serial Conn

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78640

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - x8 PCIe
A/D Converter Stage
The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 78640 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other module resources. synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 78640s can be synchronized using the Cobalt high speed sync board to drive the sync bus.

Memory Resources
The 78640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

A/D Acquisition IP Module


The 78640 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

PCI Express Interface


The Model 78640 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Clocking and Synchronization


The 78640 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple boards to be

from A/D

from A/D
TEST SIGNAL GENERATOR

VIRTEX-6 FPGA DATAFLOW DETAIL


(Two channel mode shown) INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE to MEM CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE

MEMORY CONTROLLER PCIe INTERFACE

MEMORY CONTROLLER

(supports user installed IP) to Mem Bank 1 to Mem Bank 2 8X PCIe Gigabit Serial I/O 4X 4X 40 to Mem Bank 3 to Mem Bank 4

FPGA GPIO

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78640

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, V-6 FPGA - x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.

Ordering Information
Model 78640 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, Virtex-6 FPGA - x8 PCIe

Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78641

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - x8 PCIe
General Information
Model 78641 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A highspeed data converter, with a programmable digital downconverter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes a 3.6 GHz, 12-bit A/D converter and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78641 includes an optional connection to the Virtex-6 FPGA for custom I/O. nization functions, a test signal generator and a PCIe interface complete the factoryinstalled functions and enable the 78640 to operate as a complete turnkey solution, without the need to develop any FPGA IP. For applications that require additional control and status signals, option -104 provides 20 pairs of LVDS connections from the FPGA on PMC P14 to a 68-pin DIL ribboncable header on the PCIe board for custom I/O.

A/D Converter Stage


The front end accepts analog HF or IF inputs on a pair of front panel SSMC connectors with transformer coupling into a Texas Instruments ADC12D1800 12-bit A/D. The converter operates in single-channel interleaved mode with a sampling rate of 3.6 GHz and an input bandwidth of 1.75 GHz; or, in dual-channel mode with a sampling rate of 1.8 GHz and input bandwidth of 2.8 GHz. The ADC12D1800 provides a programmable 15-bit gain adjustment allowing the 78641 to have a full scale input range of +2 dBm to +4 dBm. A built-in AutoSync feature supports A/D synchronization across multiple boards. The A/D digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78641 factory-installed functions include an A/D acquisition IP module. In addition, IP modules for DDR3 memories, a controller for all data clocking and synchro-

Features

Ideal radar and software radio interface solution One-channel mode with 3.6 GHz, 12-bit A/D Two-channel mode with 1.8 GHz, 12-bit A/Ds 2 GB of DDR3 SDRAM Programable one- or twochannel DDC (Digital Downconverter) 2 GB of DDR3 SDRAM Sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface, up to x8 Clock/sync bus for multiboard synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF In

Sample Clk TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

Gate In Reset In Ref Clk In Ref Clk Out

3.6 GHz (1 Channel) or 1.8 GHz (2 Channel) 12-Bit A/D


12 12

Sync Bus

VIRTEX-6 FPGA SX315T


GTX
LVDS

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

8X

40

Memory Banks 1 & 2

Memory Banks 3 & 4

x8 PCIe

Optional FPGA GPIO 68-pin Header

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78641
A/D Acquisition IP Module
The 78641 features an A/D Acquisition IP Module for easy capture and data moving. The IP module can receive data from the A/D, or a test signal generator. The IP module has associated memory banks for buffering data in FIFO mode or for storing data in transient capture mode. In single-channel mode, all four banks are used to store the single-channel of input data. In dual-channel mode, memory banks 1 and 2 store data from input channel 1 and memory banks 3 and 4 store data from input channel 2. In both modes, continuous, full-rate transient capture of 12-bit data is supported. The memory banks are supported with a DMA engine for moving A/D data through the PCIe interface. This powerful linked-list DMA engine is capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - x8 PCIe
DDC IP Cores
Within the FPGA is a powerful DDC IP core. The core supports a single-channel mode, accepting data samples from the A/D at the full 3.6 GHz rate. Additionally, a dual-channel mode supports the A/Ds 1.8 GHz two-channel operation . In dual-channel mode, each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. In single-channel mode, decimation can be programmed to 8x, 16x or 32x. In dual-channel mode, both channels share the same decimation rate, programmable to 4x, 8x or 16x. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 16-bit I + 16-bit Q samples at a rate of s/N.

Clocking and Synchronization


The 78641 accepts a 1.8 GHz dual-edge sample clock via a front panel SSMC connector. A second front panel SSMC accepts a TTL signal that can function as Gate, PPS or Sync. A front panel multi-pin sync bus connector allows multiple boards to be synchronized, ideal for larger multichanel systems. The sync bus includes gate, reset and in and out reference clock signals. Multiple 78641s can be synchronized using the Cobalt high speed sync board to drive the sync bus.

Memory Resources
The 78640 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and data capture capabilities. Built-in memory functions include an A/D data transient capture mode for taking snapshots of data for transfer to a host computer.

from A/D

from A/D

VIRTEX-6 FPGA DATAFLOW DETAIL


*Two channel mode shown. Programmable decimation of 8, 16 or 32 available in one channel mode.
INPUT MULTIPLEXER TEST SIGNAL GENERATOR DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT

DDC *DEC: 4, 8 or 16
POWER METER & THRESHOLD DETECT

DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE MEMORY CONTROLLER A/D ACQUISITION IP MODULE PCIe INTERFACE to MEM CONTROL

DDC CORE DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE MEMORY CONTROLLER

to Mem Bank 1

to Mem Bank 2

8X PCIe

FPGA GPIO

40

to Mem Bank 3

to Mem Bank 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78641

1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, w/ Wideband DDC, Virtex-6 FPGA - x8 PCIe
PCI Express Interface
The Model 78641 includes an industry standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links of x4 or x8, the interface includes multiple DMA controllers for efficient transfers to and from the board. Sample Clock Sources: Front panel SSMC connector Sync Bus: Multi-pin connectors, bus includes gate, reset and in and out ref clock External Trigger Input Type: Front panel female SSMC connector, TTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1or Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half-length PCIe card, 4.38 in. x 7.13 in.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors A/D Converter Type: Texas Instruments ADC12D1800 Sampling Rate: Single-channel mode: 500 MHz to 3.6 GHz; dual-channel mode: 150 MHz to 1.8 GHz Resolution: 12 bits Input Bandwidth: single-channel mode: 1.75 GHz; dual-channel mode: 2.8 GHz Full Scale Input: +2 dBm to +4 dBm, programmable Digital Downconverters Modes: One or two channels, programmable Supported Sample Rate: One-channel mode: 3.6 GHz, two-channel mode: 1.8 GHz Decimation Range: One-channel mode: 8x, 16x or 32x, two-channel mode: 4x, 8x, or 16x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: User-programmable 18-bit coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation

Ordering Information
Model 78641 Description 1-Ch. 3.6 GHz or 2-Ch. 1.8 GHz, 12-bit A/D, with Wideband DDC, Virtex-6 FPGA - x8 PCIe

Options: -002* -064* -104 -2 FPGA speed grade XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78650

Two 500 MHz A/Ds, DUC, 800 MHz D/As,Virtex-6 FPGA - x8 PCIe
General Information
Model 78650 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. It includes two A/Ds, one DUC (Digital Upconverter), two D/As, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78650 includes optional generalpurpose and gigabit serial card connectors for application specific I/O protocols. the factory-installed functions and enable the 78650 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow Design Kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory installed applications ideally matched to the boards analog interfaces. The 78650 factory-installed functions include two A/D acquisition and one D/A waveform playback IP modules. In addition, IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator and a PCIe interface complete
RF In

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
RF In RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds One digital upconverter Two 800 MHz 16-bit D/As Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

A/D Clock/Sync Bus

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

500 MHz 12-BIT A/D

500 MHz 12-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

Timing Bus
GTX
GTX

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB 40

8X

4X

4X

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Optional FPGA GPIO 68-pin Header

x8 PCIe

Optional Serial I/O Dual 4X Serial Conn

Memory Banks 1 & 2

Memory Banks 3 & 4

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78650

Two 500 MHz A/Ds, DUC, 800 MHz D/As,Virtex-6 FPGA - x8 PCIe
A/D Converter Stage
Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alternate mode, the sample clock can be sourced from an onboard programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78650s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

A/D Acquisition IP Modules


The 78650 features two A/D Acquisition IP Modules for easy capture and data moving. Each IP module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfers, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processors job of identifying and executing on the data.

The front end accepts two full scale analog HF or IF inputs on front panel SSMC connectors at +5 dBm into 50 ohms with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x.

Memory Resources
The 78650 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths.

from A/D Ch 1

from A/D Ch 2 D/A loopback TEST SIGNAL GENERATOR

to D/A

INPUT MULTIPLEXER

D/A Waveform Playback IP Module


The Model 78650 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back waveforms stored in either on-board memory or off- board host memory to the dual D/As. Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.
MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

DATA UNPACKING & FLOW CONTROL MUX

to Mem Bank 1

to Mem Bank 2

MEMORY CONTROL

to Mem Bank 3

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78650

Two 500 MHz A/Ds, DUC, 800 MHz D/As,Virtex-6 FPGA - x8 PCIe
boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.
Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen.1: x4 or x8 Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

PCI Express Interface


The Model 78650 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option 014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz, max. Output IF: DC to 400 MHz, max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz, max. with interpolation Resolution: 16 bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock

Ordering Information
Model 78650 Description Two 500 MHz A/Ds, one DUC, two 800 MHz D/As with Virtex-6 FPGA x8 PCIe

Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -160 Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78651

2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
General Information
Model 78651 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A twochannel, high-speed data converter with a programmable DDC, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution. The 78651 includes two A/Ds, two D/As and four banks of memory. It features native support for PCI Express Gen 2. memories, a controller for all data clocking and synchronization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory-installed functions and enable the 78651 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78651 factory-installed functions include two A/D acquisition and a D/A waveform playback IP modules. Each of the two acquisition IP modules contains a powerful, programmable DDC IP core. The waveform playback IP module contains an intrepolation IP core, ideal for matching playback rates to the data and decimation rates of the acquisition modules. IP modules for either DDR3 or QDRII+
RF In

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O.
RF In RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Two 500 MHz 12-bit A/Ds Two multiband DDCs (digital downconverters) Two 800 MHz 16-bit D/As One DUC (digital upconverter) Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM PCI Express (Gen. 2) interface up to x8 Sample clock synchronization to an external system reference LVPECL clock/sync bus for multimodule synchronization Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Sample Clk / Reference Clk In TTL PPS/Gate/Sync TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A/D Gate D/A Sync / PPS A/D Sync / PPS D/A

500 MHz 12-BIT A/D

500 MHz 12-BIT A/D

800 MHz 16-BIT D/A

D/A Clock/Sync Bus

800 MHz 16-BIT D/A DIGITAL UPCONVERTER 32

16

16

VCXO

VIRTEX-6 FPGA LX240T or SX315T


LVDS

Timing Bus
GTX
GTX

GTX

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB 40

8X

4X

4X

Memory Banks 1 & 2 DDR3 option 155 QDRII+ SRAM 8 MB QDRII+ SRAM 8 MB

Memory Banks 3 & 4 DDR3 option 165

Optional FPGA GPIO

x8 PCIe Sum from previous board

Aurora Gigabit Serial I/O Sum to next board Dual 4X Serial Conn

68-pin Header x8 PCI Express

QDRII+ option 150

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78651
A/D Acquisition IP Modules
The 78651 features two A/D Acquisition IP Modules for easily capturing and moving data. Each module can receive data from either of the two A/Ds, a test signal generator or from the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
frequency. Each DDC can have its own unique decimation setting, supporting as many as two different output bandwidths for the board. Decimations can be programmed from 2 to 131,072 providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 16-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the two DDC core outputs. An additional programmable gain stage compensates for summation change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 78651s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the dual 4X serial connector. This allows summation across channels on multiple boards.

Beamformer IP Core
In addition to the DDCs, the 78651 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average

D/A Waveform Playback IP Module


The Model 78651 factory-installed functions include a sophisticated D/A Waveform Playback IP module. A linkedlist controller allows users to easily play back to the dual D/As waveforms stored in either on-board memory or off- board host memory . Parameters including length of waveform, delay from playback trigger, waveform repetition, etc. can be programmed for each waveform. Up to 64 individual link entries can be chained together to create complex waveforms with a minimum of programming.

from A/D Ch 1

from A/D Ch 2 D/A loopback


INPUT MULTIPLEXER

to D/A

TEST SIGNAL GENERATOR

DDC DEC: 2 TO 131027

DDC DEC: 2 TO 131027


POWER METER & THRESHOLD DETECT

INTERPOLATOR 2 TO 65536 IP CORE DATA UNPACKING & FLOW CONTROL MUX

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving both DDCs or each of the two A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling
MEMORY CONTROL

MUX

POWER METER & THRESHOLD DETECT

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

VIRTEX-6 FPGA DATAFLOW DETAIL

8X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78651

2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
A/D Converter Stage
The front end accepts two analog HF or IF inputs on front panel SSMC connectors with transformer coupling into two Texas Instruments ADS5463 500 MHz, 12-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources. nate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78651s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Digital Upconverter and D/A Stage


A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and dual D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals to any IF center frequency up to 360 MHz. It delivers real or quadrature (I+Q) analog outputs to the dual 16-bit D/A converter. Analog output is through a pair of front panel SSMC connectors. If translation is disabled, the DAC5688 acts as a dual interpolating 16-bit D/A with output sampling rates up to 800 MHz. In both modes the DAC5688 provides interpolation factors of 2x, 4x and 8x. In addition to the DAC5688, an FPGA based interpolator core provides additional interpolation from 2x to 65,536x. The two interpolators can be combined to create a total range from 2x to 524,288x.

Memory Resources
The 78651 architecture supports up to three independent memory banks which can be configured with QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boardss DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


Two internal timing buses provide either a single clock or two different clock rates to the A/D and D/A signal paths. Each timing bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly for either the A/D or D/A sections or can be divided by a built-in clock synthesizer circuit to provide different A/D and D/A clocks. In an alter-

PCI Express Interface


The Model 78651 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78651

2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe
Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +5 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters (standard) Type: Texas Instruments ADS5463 Sampling Rate: 20 MHz to 500 MHz Resolution: 12 bits A/D Converters (option -014) Type: Texas Instruments ADS5474 Sampling Rate: 20 MHz to 400 MHz Resolution: 14 bits Digital Downconverters Quantity: Two channels Decimation Range: 2x to 131,072x in two programmable stages of 2x to 256x and one fixed 2x stage LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 16-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: 250 MHz max. Output IF: DC to 400 MHz max. Output Signal: 2-channel real or 1-channel with frequency translation Output Sampling Rate: 800 MHz max. with 2x, 4x or 8x interpolation Resolution: 16 bits Digital Interpolator Interpolation Range: 2x to 65,536x in two stages of 2x to 256x Beamformer Summation: Two channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via via a dual 4X connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Front Panel Analog Signal Outputs Output: Transformer-coupled, front panel female SSMC connectors Transformer: Coil Craft WBC4-6TLB Full Scale Output: +4 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: one A/D clock and one D/A clock Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16, independently for the A/D clock and D/A clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T-2 Optional: Xilinx Virtex-6 XC6VSX315T-2 Custom I/O Option -104: Provides 20 pairs of LVDS connections between the FPGA and the VPX P2 connector for custom I/O Memory Option -150: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option -155 or -165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 2: x4 or x8 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

Ordering Information
Model 78651 Description 2-Channel 500 MHz A/D with DDC, DUC with 2-Channel 800 MHz D/A, and a Virtex-6 FPGA - x8 PCIe

Options: -002* -014 -062 -064 -104 -2 FPGA speed grade 400 MHz, 14-bit A/Ds

XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through a 68-pin DIL connector -150 Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) -155 Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165 Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * This option is always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78660

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - x8 PCIe


General Information
Model 78660 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter, it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution. It includes four A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78660 includes optional general-purpose and gigabit serial connectors for applicationspecific I/O protocols. installed functions and enable the 78660 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory installed applications ideally matched to the boards analog interfaces. The 78660 factory-installed functions include four A/D acquisition IP modules. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchronization functions, a test signal generator, an Aurora gigabit serial interface, and a PCIe interface complete the factory-

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF In

RF In

RF In

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

GTX

GTX

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB 40

8X

4X

4X

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Optional FPGA GPIO 68-pin Header

x8 PCIe

Optional Serial I/O Dual 4X Serial Conn

Memory Banks 1 & 2

Memory Banks 3 & 4

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78660

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - x8 PCIe


A/D Converter Stage
The front end accepts four full-scale analog HF or IF inputs on front panel SSMC connectors at +8 dBm into 50 ohms with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture or for routing to other board resources. LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78660s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

Memory Resources
The 78660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deep memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include an A/D data transient capture mode and D/A waveform playback mode. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a built-in clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage-controlled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the

A/D Acquisition IP Modules


The 78660 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

PCI Express Interface


The Model 78660 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3

from A/D Ch 4

TEST SIGNAL GENERATOR DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL DATA PACKING & FLOW CONTROL

INPUT MULTIPLEXER

DATA PACKING & FLOW CONTROL MEMORY CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DATA PACKING & FLOW CONTROL MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

MUX METADATA GENERATOR LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

PCIe

8X

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78660

4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - x8 PCIe


Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T Optional: Xilinx Virtex-6 XC6VLX240T or XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

Ordering Information
Model 78660 Options: -062 -064 -104 XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) Description 4-Channel 200 MHz A/D with Virtex-6 FPGA - PCIe

-105

-150

-160

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78661

4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe
General Information
Model 78661 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. A multichannel, high-speed data converter with programmable DDCs (digital downconverters), it is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution. It includes four A/Ds, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78661 includes an optional general-purpose connector for application-specific I/O. nization functions, a test signal generator, a programmable beamforming IP core, an Aurora gigabit serial interface, and a PCIe interface complete the factory- installed functions and enable the 78661 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78661 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable DDC (Digital Downconverter) IP core. IP modules for either DDR3 or QDRII+ memories, a controller for all data clocking and synchro-

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O.

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Multiboard programmable beamformer Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF In

RF In

RF In

RF In

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


LVDS

GTX

GTX

GTX

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 QDRII+ SRAM 8 MB

16

16 Config FLASH 64 MB

40

8X

4X

4X

x8 PCIe Optional FPGA GPIO 68-pin Header Sum from previous board

Aurora Gigabit Serial I/O Sum to next board Dual 4X Serial Conn

QDRII+ option 150 DDR3 option 155 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

QDRII+ option 160 DDR3 option 165 DDR3 SDRAM 512 MB DDR3 SDRAM 512 MB

Memory Banks 1 & 2

Memory Banks 3 & 4

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78661
A/D Acquisition IP Modules
The 78661 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe
providing a wide range to satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or16-bit I + 16-bit Q samples at a rate of s/N. change bit growth. A power meter and threshold detect block is provided for the summed output. The output is then directed back into the A/D Acquisition IP Module 1 FIFO for reading over the PCIe. For larger systems, multiple 78661s can be chained together via a built-in Xilinx Aurora gigabit serial interface through the P16 XMC connector. This allows summation across channels on multiple boards.

A/D Converter Stage


The front end accepts three analog HF or IF inputs on front panel SSMC connectors with transformer coupling into three Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other board resources.

Beamformer IP Core
In addition to the DDCs, the 78661 features a complete beamforming subsystem. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up to 8K samples. The power meters present average power measurements for each DDC core output in easy-to-read registers. In addition, each DDC core includes a threshold detector to automatically send an interrupt to the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. A programmable summation block provides summing of any of the four DDC core outputs. An additional programmable gain stage compensates for summation

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltage

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3

from A/D Ch 4

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the A/D Acquistion IP Modules, many different configurations can be achieved including one A/D driving all four DDCs or each of the four A/Ds driving its own DDC. Each DDC has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed from 2 to 65,536

TEST SIGNAL GENERATOR

INPUT MULTIPLEXER

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

DDC DEC: 2 TO 65536


POWER METER & THRESHOLD DETECT

MUX

DDC CORE

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

AURORA GIGABIT SERIAL INTERFACE 4X 4X

sum out sum in

SUMMER

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

BEAMFORMER CORE

to next from previous board board

8X PCIe

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78661

4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe
controlled crystal oscillator. In this mode,
the front panel SSMC connector can be used to provide a 10 MHz reference clock for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78661s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. Beamformer Summation: Four channels on-board; multiple boards can be summed via Summation Expansion Chain Summation Expansion Chain: One chain in and one chain out link via XMC connector using Aurora protocol Phase Shift Coefficients: I & Q with 16-bit resolution Gain Coefficients: 16-bit resolution Channel Summation: 24-bit Multiboard Summation Expansion: 32-bit Sample Clock Sources: On-board clock synthesizer Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/ trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Memory Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

PCI Express Interface


The Model 78661 includes an industry-standard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe Links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Memory Resources
The 78661 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM, DDR3 SDRAM, or as combination of two banks of each type of memory. Each QDRII+ SRAM bank can be up to 8 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory space for creating DMA packets. For applications requiring deeper memory resources, DDR3 SDRAM banks can each be up to 512 MB deep. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Specifications Ordering Information


Model 78621 Description 4-Channel 200 MHz A/D with DDCs and Virtex-6 FPGA - x8 PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Two 8 MB QDRII+ SRAM Memory Banks (Banks 1 and 2) Two 8 MB QDRII+ SRAM Memory Banks (Banks 3 and 4) Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Options: -062 -064 -104

-150

-160

-155

-165

Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four channels Decimation Range: 2x to 65,536x in two stages of 2x to 256x LO Tuning Freq. Resolution: 32 bits, 0 to s LO SFDR: >120 dB Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, <0.3 dB passband ripple, >100 dB stopband attenuation

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78662

4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe
General Information
Model 78662 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This fourchannel, high-speed data converter with programmable DDCs (digital downconverters) is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes four A/Ds, and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78662 includes optional generalpurpose and gigabit serial connectors for application-specific I/O protocols. voltage and temperature monitoring, DDR3 SDRAM memory controllers, and a PCIe interface complete the factory-installed functions and enable the 78662 to operate as a complete turnkey solution without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized function, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factory installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, and triggering. The Cobalt architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78662 factory-installed functions include four A/D acquisition IP modules. Each of the four acquisition IP modules contains a powerful, programmable 8-channel DDC IP core. IP modules for control of all data clocking, synchronization, gate and trigger functions, a test signal generator,

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
RF In RF In RF In RF In

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 200 MHz 16-bit A/Ds Four multiband DDCs Up to 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference LVPECL clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable serial gigabit interfaces Optional LVDS connections to the Virtex-6 FPGA for custom I/O

Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

RF XFORMR

A/D Clock/Sync Bus

TTL Gate / Trig TTL Sync / PPS Sample Clk Reset Gate A Gate B Sync / PPS A Sync / PPS B

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

200 MHz 16-BIT A/D

16

16

16

16

Timing Bus

VCXO

VIRTEX-6 FPGA LX240T or SX315T


LVDS

GTX

GTX

GTX

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

32 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB 40

8X

4X

4X

Memory Banks 1 & 2 DDR3 option 155

Memory Banks 3 & 4 DDR3 option 165

Optional FPGA GPIO 68-pin Header

x8 PCIe

Optional Serial I/O Dual 4X Serial Conn

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78662
A/D Acquisition IP Modules
The 78662 features four A/D Acquisition IP Modules for easily capturing and moving data. Each IP module can receive data from any of the four A/Ds or a test signal generator Each IP module has an associated memory bank for buffering data in FIFO mode or for storing data in transient capture mode. All memory banks are supported with DMA engines for easily moving A/D data through the PCIe interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary. For each transfer, the DMA engine can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processors job of identifying and executing on the data.

4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe
available output bandwidths range from 19.53 kHz to 10.0 MHz. Each 8-channel bank can have its own unique decimation setting supporting a different bandwidth associated with each of the four acquisition modules. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*s/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of s/N. Any number of channels can be enabled within each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within a bank.

Clocking and Synchronization


An internal timing bus provides all timing and synchronization required by the A/D converters. It includes a clock, two sync and two gate or trigger signals. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly by the A/D or divided by a builtin clock synthesizer circuit. In an alternate mode, the sample clock can be sourced from an on-board programmable voltagecontrolled crystal oscillator. In this mode, the front panel SSMC connector can be used to provide a reference clock, typically 10 MHz, for synchronizing the internal oscillator. A front panel 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronized. In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple boards. Multiple 78662s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards.

A/D Converter Stage


The front end accepts four analog HF or IF inputs on front panel SSMC connectors with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into the Virtex-6 FPGA for signal processing, data capture and for routing to other module resources.

Memory Resources
The 78662 architecture supports up to four independent memory banks which can be configured with DDR3 SDRAM.

from A/D Ch 1

from A/D Ch 2

from A/D Ch 3

from A/D Ch 4

DDC IP Cores
Within each A/D Acquisition IP Module is a powerful 8-channel DDC bank. Because of the flexible input routing of the A/D Acquisition IP Modules, many different configurations can be achieved including one A/D driving all 32 DDC channels or each of the four A/Ds driving its own DDC bank. Each of the 32 channels has an independent 32-bit tuning frequency setting that ranges from DC to s, where s is the A/D sampling frequency. All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the

TEST SIGNAL GENERATOR

INPUT MULTIPLEXER

DIGITAL DOWNCONVERTER BANK 1: CH 1-8 DEC: 16 TO 8192


.

DIGITAL DOWNCONVERTER BANK 2: CH 9-16 DEC: 16 TO 8192


.

DIGITAL DOWNCONVERTER BANK 3: CH 17-24 DEC: 16 TO 8192


.

DIGITAL DOWNCONVERTER BANK 4: CH 18-32 DEC: 16 TO 8192


.

DDC CORE DATA PACKING & FLOW CONTROL MEMORY CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 1 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 2 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 3 MEMORY CONTROL

DDC CORE DATA PACKING & FLOW CONTROL METADATA GENERATOR MUX LINKED-LIST DMA ENGINE A/D ACQUISITION IP MODULE 4

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

32 Memory Bank 1

32 Memory Bank 2

32 Memory Bank 3

32 Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78662

4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe
Each DDR3 SDRAM bank can be up to
512 MB deep and is an integral part of the boards DMA capabilities, providing FIFO memory and capture space for creating DMA packets. Built-in memory functions include multichannel A/D data capture, tagging and streaming. In addition to the factory installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes. Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock, or PLL system reference Timing Bus: 26-pin connector LVPECL bus includes, clock/sync/gate/PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX240T Optional: Xilinx Virtex-6 XC6VSX315T Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4 Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

PCI Express Interface


The Model 78662 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. Supporting PCIe links up to x8, the interface includes multiple DMA controllers for efficient transfers to and from the board.

Specifications
Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel female SSMC connectors Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +8 dBm into 50 ohms 3 dB Passband: 300 kHz to 700 MHz A/D Converters Type: Texas Instruments ADS5485 Sampling Rate: 10 MHz to 200 MHz Resolution: 16 bits Digital Downconverters Quantity: Four 8-channel banks, one per acquisition module Decimation Range: 16x to 8192x in steps of 8x LO Tuning Freq. Resolution: 32 bits, 0 to s Phase Offset Resolution: 32 bits, 0 to 360 degrees FIR Filter: 18-bit coefficients, 24-bit output, with user programmable coefficients Default Filter Set: 80% bandwidth, >100 dB stopband attenuation Sample Clock Sources: On-board clock synthesizer

Ordering Information
Model 78662 Description 4-Ch 200 MHz A/D with 32-Ch DDC and Virtex-6 FPGA - PCIe XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector Gigabit serial FPGA I/O through two 4X top edge connectors Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4)

Options: -062 -064 -104

-105

-155

-165

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78670

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIe


General Information
Model 78670 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78670 includes optional general purpose and gigabit serial connectors for application-specific I/O. complete the factory-installed functions and enable the 78670 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78670 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions, a test signal generator, and a PCIe interface
RF Out

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with a variety of different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX130T, LX240T, or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, one of the lower-cost LXT FPGAs can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
RF Out RF Out RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

Clock/Sync Bus A Clock/Sync Bus B

Gate In Sync In

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

mSync Bus A
Gate In Sync In

mSync Bus B

VCXO

VIRTEX-6 FPGA LX130T, LX240T or SX315T


LVDS

GTX

GTX

GTX

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

40

8X

4X

4X

Memory Banks 1 & 2

Memory Banks 3 & 4

Optional FPGA GPIO 68-pin Header

x8 PCIe

Optional Serial I/O Dual 4X Serial Conn

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78670

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIe


Digital Upconverter and D/A Stage
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up to 1.25 GHz. In both modes, the D/A provides interpolation factors of 2x, 4x, 8x and 16x. Analog output is through four front panel SSMC connectors. provide a 10 MHz reference clock for synchronizing the internal oscillator. A pair of front panel Sync connectors allows multiple boards to be synchronized. In the slave mode, they accept CML inputs that drive the boards clock, sync and gate signals. In the master mode, the Sync connectors can drive the front panel timing signals for synchronizing a slave 78670 module. For larger systems, the Pentek Model 7891 Cobalt Synchronizer can drive multiple 78670s enabling large, multichannel synchronous configurations.

Memory Resources
The 78670 architecture supports four independent memory banks of DDR3 SDRAM. Each bank is 512 MB deep and is an integral part of the boards DMA and waveform playback capabilities. Waveform tables can be loaded into the memories with playback managed by the linked list controllers. In addition to the factory-installed functions, custom user-installed IP within the FPGA can take advantage of the memories for many other purposes.

Clocking and Synchronization


An internal timing bus provides all required D/A clocking. The bus includes a clock, sync and a gate or trigger signal. An on-board clock generator receives an external sample clock from the front panel SSMC connector. This clock can be used directly or can be divided by a built-in clock synthesizer circuit to provide different D/A clocks. In an alternate mode, the sample clock can be sourced from an on-board programmable VCXO (Voltage-Controlled Crystal Oscillator). In this mode, the front panel SSMC connector can be used to

PCI Express Interface


The Model 78670 includes an industrystandard interface fully compliant with PCI Express Gen. 1 & 2 bus specifications. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the board.
16 to D/A Ch 3 & 4

D/A Waveform Playback IP Module


The Model 78670 factoryinstalled functions include a sophisticated D/A Waveform Playback IP module. Four linked list controllers support waveform generation to the four D/As from tables stored in either on-board memory or offboard host memory. Data for Channel 1 and Channel 2 are interleaved for delivery to a dual channel D/A device. For this reason, they must share a common trigger/ gate, sample rate, interpolation factor, and other parameters. The same rules apply to Channel 3 and Channel 4. Parameters including length of waveform, waveform repetition, etc. can be programmed for each channel. Up to 64 individual link entries for each D/A channel can be chained together to create complex waveforms with a minimum of programming.

16
TEST SIGNAL GENERATOR

to D/A Ch 1 & 2

DATA INTERLEAVER

DATA INTERLEAVER

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

DATA UNPACKING & FLOW CONTROL MUX

MEMORY CONTROL

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 1

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 2

MEMORY CONTROL LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 3

to Mem Bank 1

to Mem Bank 2

to Mem Bank 3

to Mem Bank 4

LINKED-LIST DMA ENGINE D/A WAVEFORM PLAYBACK IP MODULE 4

VIRTEX-6 FPGA DATAFLOW DETAIL

PCIe INTERFACE

(supports user installed IP)

Memory Bank 1

Memory Bank 2

Memory Bank 3

Memory Bank 4

8X PCIe

Gigabit Serial I/O

4X

4X

FPGA GPIO

40

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78670

4-Channel 1.25 GHz D/A with DUC, Virtex-6 FPGA - x8 PCIe


Specifications
D/A Converters Type: TI DAC3484 Input Data Rate: 312.5 MHz max. Output Bandwidth: 250 MHz max. Output Sampling Rate: 1.25 GHz max. with interpolation Interpolation: 2x, 4x, 8x or 16x Resolution: 16 bits Front Panel Analog Signal Outputs Quantity: Four D/A outputs Output Type: Transformer-coupled, front panel female SSMC connectors Full Scale Output: Programmable from 20 dBm (0.063 Vp-p) to +4 dBm (1.0 Vp-p) in 16 steps Full Scale Output Programming: 1.0x(G+1)/16 Vp-p, where 4-bit integer G = 0 to 15 Clock Synthesizer Clock Source: Selectable from on-board programmable VCXO, front panel external clock or Sync timing buses Synchronization: Clocks can be locked to a front panel 5 or 10 MHz system reference External Clock Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 500 MHz sample clock or 5 or 10 MHz system reference External Trigger Input Type: Front panel female SSMC connector, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Timing Bus: 19-pin Sync bus connector includes, clock, reset and gate/trigger inputs and outputs, CML Field Programmable Gate Array Standard: Xilinx Virtex-6 XC6VLX130T-2 Optional: Xilinx Virtex-6 XC6VLX240T-2 or XC6VSX315T-2 Custom I/O Option -104: Connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105: Connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board Memory: Four 512 MB DDR3 SDRAM memory banks, 400 MHz DDR PCI-Express Interface PCI Express Bus: Gen. 1 or Gen 2: x4 or x8; Environmental Operating Temp: 0 to 50 C Storage Temp: 20 to 90 C Relative Humidity: 0 to 95%, non-cond. Size: Half length PCIe card, 4.38 in. x 7.13 in.

Ordering Information
Model 78670 Description 4-Channel 1.25 GHz D/A with Virtex-6 FPGA - x8 PCIe

Options: -002* -062 -064 -104 -2 FPGA speed grade XC6VLX240T FPGA XC6VSX315T FPGA LVDS FPGA I/O through 68-pin ribbon cable connector -105 Gigabit serial FPGA I/O through two 4X top edge connectors -155* Two 512 MB DDR3 SDRAM Memory Banks (Banks 1 and 2) -165* Two 512 MB DDR3 SDRAM Memory Banks (Banks 3 and 4) * These options are always required

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

! w e N

Model 78671

4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe
General Information
Model 78671 is a member of the Cobalt family of high performance PCIe boards based on the Xilinx Virtex-6 FPGA. This 4-channel, high-speed data converter is suitable for connection to transmit HF or IF ports of a communications or radar system. Its built-in data playback features offer an ideal turnkey solution for demanding transmit applications. It includes four D/As with a wide range of programmable interpolation factors, four digital upconverters and four banks of memory. In addition to supporting PCI Express Gen. 2 as a native interface, the Model 78671 includes optional generalpurpose and gigabit serial connectors for application-specific I/O. a test signal generator, and a PCIe interface complete the factory-installed functions and enable the 78671 to operate as a complete turnkey solution, without the need to develop any FPGA IP.

Extendable IP Design
For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include all of the factoryinstalled modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

Xilinx Virtex-6 FPGA


The Virtex-6 FPGA site can be populated with two different FPGAs to match the specific requirements of the processing task. Supported FPGAs include: LX240T or SX315T. The SXT part features 1344 DSP48E slices and is ideal for modulation/demodulation, encoding/decoding, encryption/ decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources, the lower-cost LXT FPGA can be installed. Option -104 connects 20 pairs of LVDS signals from the FPGA on PMC P14 to a 68-pin DIL ribbon-cable header on the PCIe board for custom I/O. Option -105 connects two 4X gigabit serial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board.
RF Out RF Out RF Out

The Cobalt Architecture


The Pentek Cobalt Architecture features a Virtex-6 FPGA. All of the boards data and control paths are accessible by the FPGA, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering and memory control. The Cobalt Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. Each member of the Cobalt family is delivered with factory-installed applications ideally matched to the boards analog interfaces. The 78671 factory-installed functions include four D/A waveform playback IP modules, to support waveform generation through the D/A converters. IP modules for DDR3 SDRAM memories, a controller for all data clocking and synchronization functions,
RF Out

Features

Complete radar and software radio interface solution Supports Xilinx Virtex-6 LXT and SXT FPGAs Four 1.25 GHz 16-bit D/As Four digital upconverters Extended interpolation range from 2x to 1,048,576x Programmable output levels 250 MHz max. output bandwidth 2 GB of DDR3 SDRAM Sample clock synchronization to an external system reference Dual-Sync clock/sync bus for multiboard synchronization PCI Express (Gen. 1 & 2) interface up to x8 Optional user-configurable gigabit serial interface Optional LVDS connections to the Virtex-6 FPGA for custom I/O

RF XFORMR Sample Clk / Reference Clk In Trigger In TIMING BUS GENERATOR Clock / Sync / Gate / PPS

RF XFORMR

RF XFORMR

RF XFORMR

Clock/Sync Bus A Clock/Sync Bus B

Gate In Sync In

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER

1.25 GHz 16-BIT D/A DIGITAL UPCONVERTER 16

mSync Bus A
Gate In Sync In

mSync Bus B

VCXO

VIRTEX-6 FPGA LX240T or SX315T


LVDS

GTX

GTX

GTX

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 DDR3 SDRAM 512 MB

16 Config FLASH 64 MB

40

8X

4X

4X

Memory Banks 1 & 2

Memory Banks 3 & 4

Optional FPGA GPIO 68-pin Header

x8 PCIe

Optional Serial I/O Dual 4X Serial Conn

x8 PCI Express

Pentek, Inc.

One Park Way Upper Saddle River New Jersey 07458 Tel: 201.818.5900 Fax: 201.818.5904 Email: info@pentek.com

www.pentek.com

Model 78671

4-Channel 1.25 GHz D/A with DUC, Extended Interpolation and Virtex-6 FPGA - x8 PCIe
Digital Upconverter and D/A Stage
Two Texas Instruments DAC3484s provide four DUC (digital upconverter) and D/A channels. Each channel accepts a baseband real or complex data stream from the FPGA and provides that input to the upconvert, interpolate and D/A stage. When operating as a DUC, it interpolates and translates real or complex baseband input signals to a user-selectable IF center frequency. It delivers real or quadrature (I+Q) analog outputs to a 16-bit D/A converter. If translation is disabled, each D/A acts as an interpolating 16-bit D/A with output sampling rates up t