CMOS Fundamentals and Fabrication Steps

CMOS LAYOUT DESIGN

C omplementary M etal O xide S emiconductor

CMOS Fundamentals
Gate Gate

Source n+ n+

Drain

Source p+ p+

Drain

p+ substrate

n+ substrate

• For Channel to be formed: VGS > 0 If this is not followed, channel will not be formed. • If Vsource = Logic HI and Gate is made logic HI above condition is not met and channel is not formed prominantly. It appears like this: Very high resistance Source Drain

• For Channel to be formed: VGS < 0 If this is not followed, channel will not be formed. • If Vsource = Logic LO and Gate is made logic LO above condition is not met and channel is not formed prominantly. It appears like this: Very high resistance Source Drain

CMOS Fundamentals Strong .'0' .

CMOS Fundamentals Weak .'1' .

CMOS Fundamentals Weak .'0' .

'1' .CMOS Fundamentals Strong .

junction transistors. • It is the job of the CMOS Layout Engineer to: minimize the effects of these devices in a circuit. capacitors and resistors. .CMOS Fundamentals • For a good Layout Engineer it is important to know the Principles of Electronic Circuits. Many microchips have failed because of a parasitic device. SCRs. • The parasitics can affect the response time of the circuit and even its reliability. • One has to realize that five types of parasitics could get created with every layout. These are: Diodes.

The wiring among “Interconnects”. The basic building block of an IC is a transistor. Passive elements.CMOS Fundamentals • An Integrated Circuit (IC) is an electronic network that has been fabricated on a single piece of semiconductor material such as Silicon. the devices is achieved using • • • . but arise as parasitic due to electrical properties of the materials. such as resistors and capacitors are not always included as elements in the circuits.

!The device structures are very simple.CMOS Fundamentals The primary switching devices in High Density Integrated Circuits are MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) for the following reasons: !They are extremely small. !The "drain" and "source" terminals are interchangeable. .

Preparing each pattern for physical transfer to the wafer. The lithographic sequence has the following major steps: ! ! ! ! Drawing the patterns using a Layout Editor.CMOS Fundamentals AN INTEGRATED CIRCUIT IS A SET OF PATTERNED LAYERS • The process used to transfer the pattern to the semiconductor is called LITHOGRAPHY . • . Transferring the pattern on the wafer (called printing). Using processing techniques to physically pattern each layer.

CMOS Fundamentals Basic Fabrication Steps Initial Layering Photo-resist Coating Exposure Development Etching Layer Specific Process eg. Ion Implantation. . PolySilicon formation etc. CVD formation.

p type Epitaxial Layer p+ type Substrate . • Provides protection against Latchup condition by decreasing the transistor betas.CMOS Fabrication Steps • A p-type Epitaxial layer is grown on the starting material which is p+ type substrate. • It is used as the base layer on which the devices will be formed.

• Resists are of two types: Positive Photoresists and Negative Photoresists • When polymerized photoresist becomes susceptible to removal.CMOS Fabrication Steps • Resists are acid-resistant coatings of a photosensitive organic material. • When non-polymerized photoresist becomes susceptible to removal. • This material gets polymerized by UV rays. it is called "positive photoresist". Resist p type Epitaxial Layer p+ type Substrate . it is called "negative photoresist".

CMOS Fabrication Steps
UV Rays are made incident on the wafer through a "mask".

UV Rays

Polymerization takes place here.

This area remains non-polymerized.

p type Epitaxial Layer

p+ type Substrate

CMOS Fabrication Steps

Since this area is non-polymerized it gets dissolved in an organic solvent.

p type Epitaxial Layer

p+ type Substrate

CMOS Fabrication Steps
Doping (Diffusion)
Arsenic Ions for forming the n well. This process is called ion implantation.

Resist

The depth is governed by the temperature of wafer at the time of diffusion and impinging energy of the ions.

n-well

p type Epitaxial Layer

p+ type Substrate

the material under it is not exposed to UV rays. • After this. the photo-resist becomes susceptible to removal and is removed using an organic solvent. • Wherever exposed. the photo-resist elsewhere is also removed. • Subsequently.CMOS Fabrication Steps • Wherever the mask is opaque. the material under it is exposed to UV rays. Location of n-MOS device Location of p-MOS device n-well p type Epitaxial Layer p+ type Substrate . all the material under it is etched away chemically. • Wherever the mask is transparent.

CMOS Fabrication Steps • A thin layer of oxide is grown on the wafer. • It also acts as a "stress relieving" layer. • This layer is to provide isolation for the next process of growing thick oxide. Thin Oxide n-well p type Epitaxial Layer p+ type Substrate .

Thin Oxide Silicon Nitride n-well p type Epitaxial Layer p+ type Substrate .CMOS Fabrication Steps • Silicon Nitride layer is used to prevent oxidation from happening in the region being defined as "active region" (where the active devices would be formed). • The "thin oxide" layer under the Silicon Nitride is called "stress relief" oxide layer and is used as a mechanical buffer between the nitride and substrate.

CMOS Fabrication Steps • Preparation of one more step of Photolithography by way of depositing one more layer of photoresist. Thin Oxide Silicon Nitride Photoresist n-well p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps UV Rays are made incident on the wafer through a "mask". UV Rays n-well p type Epitaxial Layer p+ type Substrate .

• Wherever exposed. the material under it is not exposed to UV rays. • Wherever the mask is transparent. • After this. n-well p type Epitaxial Layer p+ type Substrate . all the material under it is etched away chemically. the photo-resist becomes susceptible to removal and is removed using an organic solvent. the photo-resist elsewhere is also removed. the material under it is exposed to UV rays.CMOS Fabrication Steps • Wherever the mask is opaque. • Subsequently.

n-well p type Epitaxial Layer p+ type Substrate . Area where thick oxide will be formed.CMOS Fabrication Steps • The nitride and the thin oxide layers are selectively etched away (chemically) and wafer is prepared for deposition of thick oxide layer.

This is because of its chemical properties. Thick Oxide layer Vertical and Lateral Growth of Oxide n-well p type Epitaxial Layer p+ type Substrate . it grows vertically and horizontally in both the directions.CMOS Fabrication Steps • The thick oxide layer prevents the lateral diffusion of active devices as well as prevents unnecessary device currents from flowing. • When the oxide is formed on the wafer.

CMOS Fabrication Steps • The nitride and the stress relief oxide layers are removed and the substrate is now exposed. n-well p type Epitaxial Layer p+ type Substrate .

Gate Oxide n-well p type Epitaxial Layer p+ type Substrate .CMOS Fabrication Steps • A thin layer of oxide. which would be used as the "gate oxide" is formed.

This forms the gate of the transistor.CMOS Fabrication Steps • Preparation for depositing the Poly-Silicon. n-well p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps • UV rays are made incident on the wafer through the mask. n-well p type Epitaxial Layer p+ type Substrate . Areas of photoresist that are exposed to UV rays get polymerized and can be removed.

CMOS Fabrication Steps • Polymerized resist areas are removed and this is where the polysilicon would be deposited. Gate Oxide n-well p type Epitaxial Layer p+ type Substrate .

However. The thickness of the gate is controlled. Gate Oxide Poly-Silicon n-well p type Epitaxial Layer p+ type Substrate . the length of polysilicon is what matters.CMOS Fabrication Steps • Polysilicon is deposited wherever resist is not present.

CMOS Fabrication Steps • The photoresist layer is removed by dissolving it in organic solvents. • Extra thin oxide layer has to be removed so that the die is ready for forming the diffusion areas. n-well p type Epitaxial Layer p+ type Substrate .

n-well p type Epitaxial Layer p+ type Substrate .CMOS Fabrication Steps • Now die is ready for forming the diffusion areas.

CMOS Fabrication Steps • Areas except where the Arsenic ions are to be diffused are covered by photoresist. Resist n-well p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps Doping (Diffusion) Arsenic Ions for forming the n+ diffusion layer n+ n+ n-well p type Epitaxial Layer p+ type Substrate .

Resist n+ n+ n-well p type Epitaxial Layer p+ type Substrate .CMOS Fabrication Steps • Areas except where the Boron ions are to be diffused are covered by photoresist.

CMOS Fabrication Steps Doping (Diffusion) Boron Ions for forming the p+ diffusion layer n+ n+ p+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

Contacts that are provided for active devices are called "active contacts" while those provided for gate are called "gate contacts". n+ n+ p+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .CMOS Fabrication Steps • The formation of active devices is completed and now the steps are to be taken to build contacts for the active regions and the gate.

CMOS Fabrication Steps CVD Oxide/ LTO is used so that underlying doped regions do not undergo any diffusion spreading.Chemical Vapour Deposition Oxide/ Low Temperature Oxide n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate . CVD/ LTO Oxide .

CMOS Fabrication Steps • Preparation for building contacts. n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps Metal1 n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps VIA Cut n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

CMOS Fabrication Steps Via12 Metal2 n+ n+ p+ n-well p+ p type Epitaxial Layer p+ type Substrate .

Stick Plan and Layout .CMOS Schematic.

CMOS Layout Design THREE BASIC LOGIC FUNCTIONS: "INVERTER "NAND "NOR INVERTER NAND NOR .

CMOS Layout Design Symbols Used in the Design POWER +V INPUT SYMBOLS OUTPUT SYMBOLS CONNECTION A A A SOURCE (GROUND) “SHORT” A -V B A MOSFET N TYPE P TYPE .

CMOS Layout Design Logic Gates and their Boolean Equivalents .

CMOS Layout Design Logic Gates and their Boolean Equivalents AND-OR-INVERT OR-AND-INVERT .

Specification of gate dimensions Specified as W(width)/L(length) ratio W/L = 10/0.2 Size for NMOS Sizes can also be different for PMOS and NMOS .2 Size for PMOS W/L = 10/0.

Illustration of gate dimensions Polysilicon Diffusion Width(W) Length(L) .

Layout and Stick Plan • Stick Plan : Representation of device layout using lines(sticks) • Layout : Physical structure of the device Stick Plan Symbol Poly x x x Contact Diffusion Transistor is formed here Layout Poly Contact Diffusion .

Transistors in series Layout X Y Diffusion sharing A X B Y C A B C Stick plan Y X A B C .

Transistors in parallel Layout X A A X Y A B Diffusion sharing X B Y Y A A B Stick plan Y X A B A .

CMOS Layout Design Logic Functions Logic Symbol AND Operation C A OR Operation C A B I/P Schematic A B Schematic B=A A B 0 1 1 0 Truth Table B I/P Schematic B A +V I/P Layout C I/P I/P A C B +V I/P Layout A B -V Layout -V .

CMOS Layout Design Logic Functions A C B Logic Symbol A C B Logic Symbol A Schematic A C B Schematic C B B ___ C = A •B A B C 0 0 1 0 1 1 1 0 1 1 1 0 Truth Table -V +V C A +V +V A B +V C ___ C = A+B A B C 0 0 1 0 1 0 1 0 0 1 1 0 -V Truth Table C -V Layout -V C Layout .

Euler's Method +V 1 +V A 2 Can be swapped A B C B 1 2 3 A 3 B A 0 -V Schematic +V C B 0 -V Schematic 1 A X X 2 B X 1 P+ 1 A X X 2 B X 3 C C 0 X A X 3 B X 2 N+ -V 0 X A X 3 B X 0 Stick Plan Stick Plan .CMOS Layout Design Logic Functions to Schematic .

4: Put the parallel equivalents of the series structure of step3 and put Pmos transistors in the top arm bubbles Y Step .CMOS Layout Design Logic Functions with Complex Gates .INVERT Logic Function Step .1: Identify the Simple Device A B C D VDD A Y B C D Simple Device NOR: 2 Nmos in parallel 2 Pmos in series Step .3: Put down the basic AND gate series structure with Nmos transistors in the bottom arm bubbles .Steps for Construction of Schematic Example: AND .OR .2: Draw the schematic of the simple device as shown Step .

should be connected in parallel in the top arm and the Nmos should be replaced by Pmos VDD 1 Y B C 1 D 3 X A 2 B X X 1 2 X C X 3 D X 2 Y C Basic AND Gate Structure A 4 0 5 X A 4 B 3 X X C 5 D Stick Plan X X 0 B 0 D .Schematic Diagram A B C D A Diffusion has to be cut to prevent shorting 2 Whatever is in series in the bottom arm.CMOS Layout Design Logic Functions with Complex Gates .

CMOS Layout Design Logic Functions with Complex Gates Example: OR . should be connected in series in the top arm and the Nmos should be replaced by Pmos 1 A B C D B 1 Y A 2 VDD C 4 3 D Y B X A 2 B 3 X X C 4 D X X A 5 Basic OR Gate Structure C 0 D X A 5 B X X 0 5 X X 3 X C 0 D 5 Stick Plan Diffusion has to be cut to prevent shorting .INVERT Logic Function Whatever is in parallel in the bottom arm.AND .

CMOS Layout Design Logic Functions with Complex Gates +V A B C D E Logic Diagram A D E 1 A 2 B C B C 4 D 1 A 2 B 3 C 4 D 5 E 1 A B -V C A B E D E 3 D E 5 +V Y 6 C 0 -V Schematic X X X X X X 0 X A 6 B X X 0 C6 X D X 4 E X 6 Stick Plan .

CMOS Layout Design Logic Functions with Complex Gates +V A B C D E F Logic Diagram D F' 1 A 2 B 3 C 4 D 5 E 4 5 F' 1 F F' E 7 A B -V F C A +V 1 F' Schematic 0 -V B C A Y B C Y E D 6 4 F' Y F' D E A B C 2 D 3 E +V 1 F' 5 X X X X X X X X X X X 0 A 7 B0 X X C7 X D X 6 E X 4 F' 7 0 X X 0 F X -V Stick Plan .

CMOS Layout Design Transmission Gates Symbols: P • Transmission Gates are also called Pass Gates. • PMOS and NMOS transistors are arranged so that gate passes both Good-0 and Good-1 .

CMOS Layout Design Transmission Gates G1 A B A G1 X X B G2 Logic Diagram A X G2 X B Stick Plan .

CMOS: Design Rules .

CMOS: Design Rules What is the logic circuit/ device whose layout is shown below? .

CMOS: General Design Rules N Well Taps N Well P+ Active Contact N-Well Enclosure of P type diffusion Poly N-Well Spacing to N type active Metal Enclosure of contact N+ Active Contact Polysilicon Endcap length Metal width Substrate Taps .

15 0.01 .3 0.36 0.CMOS: General Design Rules Sr.36 0.14 0.4 0.3 0.4 0.24 0.22 0.14 0. No.6 0.4 0.28 0.15 0.6 1.32 0.4 0. 1 a) b) c) d) e) f) 2 a) b) c) 3 a) b) c) 4 a) b) c) d) e) 5 a) b) c) d) e) f) g) 6 a) b) c) Description Minimum N-Well enclosure of P type active Minimum N-Well enclosure of N type active Minimum N-Well space to P type active Minimum N-Well space to N type active Minimum N-Well width Minimum N-Well space to N-Well Minimum P+ width Minimum P+ space to same type active Minimum P+ space to opposite type active Minimum N+ width Minimum N+ space to same type active Minimum N+ space to opposite type active Minimum polysilicon width Minimum polysilicon space to polysilicon Minimum polysilicon space to active Minimum gate space to gate Minimum polysilicon endcap length Minimum contact width Maximum contact width Minimum contact space to contact Minimum active enclosure of contact Minimum polysilicon enclosure of contact Minimum polysilicon contact space to active Minimum active contact space to polysilicon Minimum metal1 width Minimum metal1 space to metal1 Minimum metal1 enclosure of contact Dimensions in microns 0.6 0.4 0.2 0.32 0.3 0.4 0.4 0.4 0.

CMOS: Design Rules 2 Input NAND Gate 1b 1 e) 2 c) 2 a) 1a 1a 1 f) 1 d) 4 a) 5 a) 5 c) 4 c) 4 b) 4 d) 5 d) 3 a) 4 e) 3 c) 6 b) 6 a) 5 c) .

CMOS: Parasitic Components .

CMOS: Parasitic Components • DIODES (P-N JUNCTIONS) • RESISTORS • CAPACITORS • TRANSISTORS • THYRISTORS .

CMOS: Parasitic Components Via12 Metal2 n+ n+ p+ n-well p+ p type Epitaxial Layer p-n junctions p+ type Substrate .

CMOS: Parasitic Components . both Q1 and Q2 would saturate causing a heavy current to flow between VDD and VSS. its collector current causes a drop in Rwell and this pushes Q2 towards active . Can be prevented by: • Reducing Rwell and Rsubstrate.Latchup Condition OUT VSS IN VDD p+ n+ n+ p+ p+ n+ Q1 Q2 Rwell n-well Rsubstrate p type Substrate • Slight noise or surge could cause Q1 or Q2 to get active. • IT’S A SHORT CIRCUIT!!! This is called "latch-up".saturation. • Reducing the Betas (gains) of the transistors. • If Q1 goes active. • Ultimately. VDD Rwell Q2 Q1 Rsubstrate VSS . • This in turn would push Q1 towards saturation.

CMOS: Process Related Effects .

CMOS: Process Related Effect • Process Antenna Effect • Hot Carrier Effect • Electromigration .

CMOS: Finger Gates and Bent Gates .

FINGERGATES IN SERIES 2 . EXAMPLES ❁ BENT GATES .FINGER GATES AND BENT GATES MAIN OBJECTIVES ❁IMPORTANCE ❁ FINGER GATES APPROACH 1 . FINGER GATES IN PARALLEL 3 .

THE SIZE OF THE GATE IS RESTRICTED.IMPORTANCE IN FABRICATION FOUNDRY. FOR EXAMPLE .THEN HOW TO ACHIEVE A GATE SIZE OF 100µm/ 150 µm/ 200 µm etc .e. IF THE FABRICATION SUPPORTS MAXIMUM OF 50µm OF GATE SIZE . TO SOLVE THE ABOVE PROBLEM THE FOLLOWING TWO APPROACHES ARE USED 1. BENT GATES APPROACH . i. FINGER GATES APPROACH 2.

the diffusion width is divided into three portions (10 µm /2 µm) as shown in figure.FINGER GATES APPROACH Suppose the required GATE SIZE =W/L = 30 µm/ 2 µm Maximum Gate Size restriction from foundry = 10 µm / 2 µm To obtain a gate size of 30 µm /2 µm with the existing 10 µm /2 µm gate size facility. .

EXAMPLE
Required gate size = 30 µm/2 µm Actual gate size = 10 µm/2 µm (each leg)
G B A 30 µm/2 µm

A A A G

B B B

10µ/2µ

10µ/2µ

A

B

B

A

A

B

10µ/2µ

RESULTANT VIEW

LAYOUT

A

B

B

A

A

B G G G

B

G

G

G A

SCHEMATIC A

G

B

By sharing the diffusion, the three gates of size 10 µm /2 µm in parallel, are controlled by same signal.The structure looks like finger structure, hence it is called finger gates.

LIKE WISE , A GATE WIDTH OF 15 µm /2 µm CAN BE OBTAINED BY 10 µm /2 µm PLUS 5 µm /2 µm . 15 µm /2 µm = 10 µm /2 µm + 5 µm /2 µm 5 µm /2 µm

BEFORE SHARING G

15 µm /2 µm

A G B 15 µm/2 µm

10 µm /2 µm

A

B

G A B A B

G

10 µm /2 µm

5 µm /2 µm

AFTER SHARING LAYOUT SCHEMATIC A G A B A B G .

FINGER GATES IN SERIES EXAMPLE : CONSTRUCT ION OF GIVEN CIRCUIT USING FINGER GATES WITH EACH FINGER HAVING THE SIZE OF 10 µm /2 µm A Y Z 30 µm /2 µm X 20 µm /2 µm Y B STICK PLAN Y X A A X B B Z X Z 10µ/2µ 10µ/2µ 10µ/2µ 10µ/2µ 10µ/2µ X SCHEMATIC A .

FINGER GATES IN PARALLEL EXAMPLE : CONSTRUCT ION OF GIVEN CIRCUIT USING FINGER GATES WITH EACH FINGER HAVING THE SIZE OF 10 µm /2 µm A X 20µ/2µ B SCHEMATIC Y 20µ/2µ X Z 10µ/2µ . Y B A . Y 10µ/2µ A X B A . A STICK PLAN . B .

EXAMPLE : CONSTRUCT ION OF AN INVERTER USING FINGER GATES WITH EACH FINGER HAVING THE SIZE OF 15 µm /2 µm VCC 30 µm /2 µm A 15 µm /2 µm A A X 30 µm /2 µm A 15 µm /2 µm VSS .

SCHEMATIC VCC VCC A STICK PLAN A A . VSS A A VSS .

BENT GATES IN THIS METHOD . EXAMPLE A A G B G B A B . THE GATE IS BENT INSIDE THE DIFFUSION AREA TO ACHIEVE THE REQUIRED GATE SIZE. THIS METHOD IS NOT PREFERED BECAUSE DURING THE FABRICATION PROCESS .HENCE FINGER GATES APPROACH IS PREFERED. TO MAINTAIN THE SAME WIDTH AND LENGTH OF GATE IS NOT POSSIBLE DUE TO THE BENDING .

CMOS: Reverse Engineering .

Reverse Engineering Main objectives : • • • • What is reverse engineering Why it is required Steps required for layout to schematic conversion Examples .

WHAT IS REVERSE ENGINEERING Layout Reverse Engineering Schematic/ Logic circuit Reverse Engineering is the process of converting layout into schematic /logic circuit. .

WHY REVERSE ENGINEERING Netlist P&R Tool Layout Verify the compliance of netlist with layout .

STEPS FOR REVERSE ENGINEERING A GIVEN PIECE OF LAYOUT • • • • • • Identify VCC and VSS lines Identify sharing of diffusion Identify finger gates Identify OR and AND structures Conversion of layout to schematic Conversion of schematic to logic .

INVERTER STICK PLAN VCC SCHEMATIC VCC LOGIC A A VSS A A A A VSS .

INVERTER USING FINGER GATES STICK PLAN VCC SCHEMATIC VCC LOGIC B A B A B VSS A VSS .

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