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256K SPI™ Bus Serial EEPROM
Device Selection Table
Part Number 25LC256 25AA256 VCC Range 2.5-5.5V 1.8-5.5V Page Size 64 Byte 64 Byte Temp. Ranges I, E I Packages P, SN, SM, ST, MF P, SN, SM, ST, MF
• Max. clock 10 MHz • Low-power CMOS technology: - Max. Write Current: 5 mA at 5.5V, 10 MHz - Read Current: 6 mA at 5.5V, 10 MHz - Standby Current: 1 μA at 5.5V • 32,768 x 8-bit organization • 64 byte page • Self-timed erase and write cycles (5 ms max.) • Block write protection: - Protect none, 1/4, 1/2 or all of array • Built-in write protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • Sequential read • High reliability: - Endurance: 1,000,000 erase/write cycles - Data retention: > 200 years - ESD protection: > 4000V • Temperature ranges supported: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C • Pb-free packages available
The Microchip Technology Inc. 25AA256/25LC256 (25XX256*) are 256 Kbit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface™ (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25XX256 is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead DFN and 8-lead TSSOP. Pb-free (Pure Sn) finish is available.
Package Types (not to scale)
CS 1 SO 2 WP 3 VSS 4 8 7 6 5 VCC HOLD SCK SI CS SO WP VSS
(P, SN, SM)
1 2 3 4 8 7 6 5 VCC HOLD SCK SI
Pin Function Table
Name CS SO WP VSS SI SCK HOLD VCC Function Chip Select Input Serial Data Output Write-Protect Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage
CS SO WP VSS
Rotated TSSOP (ST)
HOLD VCC CS SO 1 2 3 4 8 7 6 5 SCK SI VSS WP
1 2 3 4 8 7 6 5 VCC HOLD SCK SI
SPI is a registered trademark of Motorola Corporation.
* 25XX256 is used in this document as a generic part number for the 25AA256, 25LC256 devices.
© 2005 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................................................................-65°C to 150°C Ambient temperature under bias ...............................................................................................................-40°C to 125°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.
Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Min. .7 VCC -0.3 -0.3 — — VCC -0.5 — — — Typ.(2) — — — — — — — — — Max. VCC +1 0.3 VCC 0.2 VCC 0.4 0.2 — ±1 ±1 7 Units V V V V V V μA μA pF VCC ≥ 2.5V VCC < 2.5V IOL = 2.1 mA, VCC = 4.5V IOL = 1.0 mA, VCC = 2.5V IOH = -400 μA CS = VCC, VIN = VSS OR VCC CS = VCC, VOUT = VSS OR VCC TA = 25°C, FCLK = 1.0 MHz, VCC = 5.0V (Note 1) VCC = 5.5V; FCLK = 10.0 MHz; SO = Open VCC = 2.5V; FCLK = 5.0 MHz; SO = Open VCC = 5.5V VCC = 2.5V CS = VCC = 5.5V, Inputs tied to VCC or VSS, 125°C CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Test Conditions
DC CHARACTERISTICS Param. No. D001 D002 D003 D004 D005 D006 D007 D008 D009 Sym. VIH VIL VIL VOL VOL VOH ILI ILO CINT Characteristic High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current Internal Capacitance (all inputs and outputs)
ICC Read Operating Current
— — — — — Standby Current —
2.5 0.5 0.6 0.15 0.1
6 2.5 5 3 5 1
mA mA mA mA μA μA
ICC Write ICCS
Note 1: 2:
This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature (25°C).
© 2005 Microchip Technology Inc.
5V 2.5V 1.5V 1.8V ≤ Vcc < 2.8V ≤ Vcc < 2.5V ≤ Vcc < 4.5V ≤ Vcc < 4.5V 1.5V 1. please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www. 1 FCLK Characteristic Clock Frequency 2 TCSS CS Setup Time 3 TCSH CS Hold Time 4 5 TCSD Tsu CS Disable Time Data Setup Time 6 THD Data Hold Time 7 8 9 TR TF THI CLK Rise Time CLK Fall Time Clock High Time 10 TLO Clock Low Time 11 12 13 TCLD TCLE TV Clock Delay Time Clock Enable Time Output Valid from Clock Low Output Hold Time Output Disable Time 14 15 THO TDIS 16 THS HOLD Setup Time 17 THH HOLD Hold Time Note 1: This parameter is periodically sampled and not 100% tested.5V 2.8V ≤ Vcc < 2.5V 2.8V ≤ Vcc < 2.5V 4.5V (Note 1) 1.5V 1.5V ≤ Vcc < 4.5V ≤ Vcc ≤ 5.5V 1. 10 5 3 — — — — — — — — — — — — — 100 100 — — — — — — — — 50 100 160 — 40 80 160 — — — — — — Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC = 1. No.5V ≤ Vcc ≤ 5.5V ≤ Vcc ≤ 5.5V — 4.8V to 5.5V ≤ Vcc < 4.8V ≤ Vcc < 2.5V ≤ Vcc < 4.5V (Note 1) 4.5V 2.8V ≤ Vcc ≤ 2.5V 4.5V 1.5V ≤ Vcc ≤ 5.5V ≤ Vcc < 4.5V 2.5V 4.5V 4.5V (Note 1) (Note 1) 4.5V ≤ Vcc ≤ 5.5V — — 4.5V VCC = 2.8V ≤ Vcc < 2. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.5V 2.5V Test Conditions 4. DS21822E-page 3 .5V ≤ Vcc < 4.5V 2.5V (Note 1) 2.microchip.5V 4.5V 2.5V ≤ Vcc ≤ 5.5V 1.5V ≤ Vcc < 4.8V ≤ Vcc < 2.5V 1.5V (Note 1) 4.5V ≤ Vcc < 4. 3: This parameter is not tested but ensured by characterization. — — — 50 100 150 100 200 250 50 10 20 30 20 40 50 — — 50 100 150 50 100 150 50 50 — — — 0 — — — 20 40 80 20 40 80 Max.5V to 5.5V ≤ Vcc ≤ 4.5V ≤ Vcc ≤ 5.5V ≤ Vcc ≤ 5.5V 1. For endurance estimates in a specific application.8V ≤ Vcc < 2.5V ≤ Vcc ≤ 5.5V ≤ Vcc < 4.5V ≤ Vcc ≤ 5. Sym.5V 2.5V ≤ Vcc ≤ 5.25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Min.5V AC CHARACTERISTICS Param.com.5V 2. © 2005 Microchip Technology Inc.8V ≤ Vcc < 2.8V ≤ Vcc < 2.
5V ≤ Vcc ≤ 5.0V CL = 50 pF Timing Measurement Reference Level Input Output Note 1: For VCC ≤ 4.5 VCC 0.0V DS21822E-page 4 © 2005 Microchip Technology Inc. TABLE 1-3: AC Waveform: VLO = 0.5V (Note 1) 2.2V AC TEST CONDITIONS — (Note 1) (Note 2) — 0.0V 2: For VCC > 4.5V to 5.8V to 5. please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.5V VCC = 2. 3: This parameter is not tested but ensured by characterization. 30 60 160 30 60 160 — 1M Max.8V ≤ Vcc < 2.8V ≤ Vcc < 2.5V 2.5V (Note 1) 4.5 VCC VHI = VCC – 0.5V (Note 1) 1.5V ≤ Vcc < 4.5V (NOTE 2) AC CHARACTERISTICS Param.25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Min.5V ≤ Vcc ≤ 5. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.com.2V VHI = 4.5V ≤ Vcc < 4. Sym.5V 1. — — — — — — 5 — Units ns ns ns ns ns ns ms VCC = 1. 18 THZ Characteristic HOLD Low to Output High-Z HOLD High to Output Valid Internal Write Cycle Time Endurance 19 THV 20 21 TWC — E/W (NOTE 3) Cycles Note 1: This parameter is periodically sampled and not 100% tested. For endurance estimates in a specific application. No.5V Test Conditions 4. .
1 Mode 0.1 SCK Mode 0.0 5 SI 6 LSB in 7 8 3 12 11 MSB in SO high-impedance FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 SCK 13 14 SO MSB out 15 ISB out 10 3 Mode 1.0 SI don’t care © 2005 Microchip Technology Inc. DS21822E-page 5 .25AA256/25LC256 FIGURE 1-1: CS 16 SCK 18 SO n+2 n+1 n high-impedance 19 n 5 n n-1 n-1 17 16 17 HOLD TIMING don’t care SI HOLD n+2 n+1 n FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 Mode 1.
the user can assert the HOLD input and place the 25XX256 in ‘HOLD’ mode. the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. All instructions.2 Read Sequence The device is selected by pulling CS low. regardless of the number of bytes actually being written. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. If the write operation is initiated immediately after the WREN instruction without CS being brought high. end at addresses that are integer multiples of page size – 1. including Microchip’s PICmicro® microcontrollers. The 8-bit READ instruction is transmitted to the 25XX256 followed by the 16-bit address. While the write is in progress. the user may proceed by setting the CS low. the data will not be written to the array because the write enable latch will not have been properly set. the STATUS register may be read to check the status of the WPEN. Note: Page write operations are limited to writing bytes within a single physical page.25AA256/25LC256 2. with the first MSB of the address being a “don’t care” bit. Table 2-1 contains a list of the possible instruction bytes and format for device operation. WIP. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. After all eight bits of the instruction are transmitted. When the write cycle is completed. Data (SI) is sampled on the first rising edge of SCK after CS goes low. Up to 64 bytes of data can be sent to the device before a write cycle is necessary. the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. 2. the write enable latch is reset. If CS is brought high at any other time. LSB last.768-byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families. The read operation is terminated by raising the CS pin (Figure 2-1). Prior to any attempt to write data to the 25XX256. If the clock line is shared with other peripheral devices on the SPI bus.0 2. For the data to be actually written to the array. The only restriction is that all of the bytes must reside in the same page. and data are transferred MSB first. WEL. with data being clocked in on the rising edge of SCK. After the correct READ instruction and address are sent. the write enable latch must be set by issuing the WREN instruction (Figure 2-4). The device is accessed via the SI pin. The 25XX256 contains an 8-bit instruction register. This is done by setting CS low and then clocking out the proper instruction into the 25XX256. .3 Write Sequence The 25XX256 is a 32. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. issuing a WRITE instruction. When the highest address is reached (7FFFh). followed by the 16-bit address. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and. with the first MSB of the address being a “don’t care” bit. A read attempt of a memory array location will not be possible during a write cycle. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. If a Page Write command attempts to write across a physical page boundary. the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence. The CS pin must be low and the HOLD pin must be high for the entire operation. After releasing the HOLD pin. the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there). instead of being written to the next page as might be expected. Once the write enable latch is set. the data stored in the memory at the selected address is shifted out on the SO pin. BP1 and BP0 bits (Figure 2-6). the CS must be brought high to set the write enable latch.1 FUNCTIONAL DESCRIPTION Principles of Operation 2. DS21822E-page 6 © 2005 Microchip Technology Inc. addresses. respectively. operation will resume from the point when the HOLD was asserted. and then the data to be written.
DS21822E-page 7 .25AA256/25LC256 BLOCK DIAGRAM STATUS Register HV Generator I/O Control Logic Memory Control Logic X Dec EEPROM Array Page Latches SI SO CS SCK HOLD WP VCC VSS Y Decoder Sense Amp. R/W Control TABLE 2-1: INSTRUCTION SET Instruction Format Description Read data from memory array beginning at selected address Write data to memory array beginning at selected address Reset the write enable latch (disable write operations) Set the write enable latch (enable write operations) Read STATUS register Write STATUS register Instruction Name READ WRITE WRDI WREN RDSR WRSR 0000 0011 0000 0010 0000 0100 0000 0110 0000 0101 0000 0001 READ SEQUENCE FIGURE 2-1: CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 instruction SI 0 0 0 0 0 0 1 16-bit address 1 15 14 13 12 2 1 0 data out 7 6 5 4 3 2 1 0 high-impedance SO © 2005 Microchip Technology Inc.
.25AA256/25LC256 FIGURE 2-2: CS Twc 0 SCK instruction SI 0 0 0 0 0 0 1 16-bit address 0 15 14 13 12 2 1 0 7 6 data byte 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 BYTE WRITE SEQUENCE high-impedance SO FIGURE 2-3: CS 0 SCK 1 PAGE WRITE SEQUENCE 2 3 4 5 6 7 8 9 10 11 16-bit address 21 22 23 24 25 26 27 28 29 30 31 data byte 1 2 1 0 7 6 5 4 3 2 1 0 instruction SI 0 0 0 0 0 0 1 0 15 14 13 12 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK data byte 2 SI 7 6 5 4 3 2 1 0 7 6 data byte 3 5 4 3 2 1 0 7 data byte n (64 max) 6 5 4 3 2 1 0 DS21822E-page 8 © 2005 Microchip Technology Inc.
This latch must be set before any write operation will be completed internally. See Table 2-4 for the Write-Protect Functionality Matrix. The WREN instruction will set the latch.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed The 25XX256 contains a write enable latch.25AA256/25LC256 2. DS21822E-page 9 . and the WRDI will reset the latch. FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 SCK 1 2 3 4 5 6 7 SI 0 0 0 0 0 1 1 0 high-impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 SCK 1 2 3 4 5 6 7 SI 0 0 0 0 0 1 0 1 0 high-impedance SO © 2005 Microchip Technology Inc.
When set to a ‘1’. FIGURE 2-6: CS READ STATUS REGISTER TIMING SEQUENCE (RDSR) 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction SI 0 0 0 0 0 1 0 1 high-impedance SO 7 data from STATUS register 6 5 4 3 2 1 0 DS21822E-page 10 © 2005 Microchip Technology Inc. The state of this bit can always be updated via the WREN or WRDI commands. and are shown in Table 2-3. even during a write cycle. regardless of the state of write protection on the STATUS register. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These commands are shown in Figure 2-4 and Figure 2-5. The Read Status Register instruction (RDSR) provides access to the STATUS register. These bits are nonvolatile.25AA256/25LC256 2. When set to a ‘1’. the latch allows writes to the array. These bits are set by the user issuing the WRSR instruction. The Write-In-Process (WIP) bit indicates whether the 25XX256 is busy with a write operation. This bit is read-only. when set to a ‘0’. when set to a ‘0’. a write is in progress. .5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. no write is in progress. See Figure 2-6 for the RDSR timing sequence. The STATUS register may be read at any time. The STATUS register is formatted as follows: TABLE 2-2: 7 W/R WPEN 6 x 5 x STATUS REGISTER 4 x 3 W/R BP1 2 W/R BP0 1 R WEL 0 R WIP W/R = writable/readable. the latch prohibits writes to the array. R = read-only.
only writes to nonvolatile bits in the STATUS register are disabled. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. See Table 2-4 for a matrix of functionality on the WPEN bit. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. © 2005 Microchip Technology Inc. The partitioning is controlled as shown in Table 2-3. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. DS21822E-page 11 .25AA256/25LC256 2. two. The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 2-2.6 Write Status Register Instruction (WRSR) See Figure 2-7 for the WRSR timing sequence. When the chip is hardware write-protected. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. one. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. The array is divided up into four segments. or all four of the segments of the array. TABLE 2-3: BP1 ARRAY PROTECTION BP0 Array Addresses Write-Protected none upper 1/4 (6000h-7FFFh) upper 1/2 (4000h-7FFFh) all (0000h-7FFFh) 0 0 1 1 0 1 0 1 FIGURE 2-7: CS WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction SI 0 0 0 0 0 0 0 1 7 6 data to STATUS register 5 4 3 2 1 0 high-impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register sequence. The user has the ability to write-protect none.
25AA256/25LC256 2.7 Data Protection 2. the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued The 25XX256 powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on CS is required to enter active state TABLE 2-4: WEL (SR bit 1) 0 1 1 1 x = don’t care WRITE-PROTECT FUNCTIONALITY MATRIX WPEN (SR bit 7) x 0 1 1 WP pin x x 0 (low) 1 (high) Protected Blocks Protected Protected Protected Protected Unprotected Blocks Protected Writable Writable Writable STATUS Register Protected Writable Protected Writable DS21822E-page 12 © 2005 Microchip Technology Inc. . page write or STATUS register write.8 Power-On State The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write.
When the device is deselected. regardless of the CS input signal. a programming cycle which is already initiated or in progress will be completed. A high level deselects the device and forces it into Standby mode. HOLD must be brought high while the SCK pin is low. 3.1 Chip Select (CS) 3. The HOLD pin must be brought low while SCK is low. However. If CS is brought high during a program cycle. The WP pin functions will be enabled when the WPEN bit is set high. After powerup. the device will go into Standby mode as soon as the programming cycle is complete. TABLE 3-1: Name CS SO WP VSS SI SCK HOLD VCC PIN FUNCTION TABLE Function Chip Select Input Serial Data Output Write-Protect Pin Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage PDIP/SOIC Rotated TSSOP/DFN TSSOP 1 2 3 4 5 6 7 8 3 4 5 6 7 8 1 2 3. During a read cycle. while data on the SO pin is updated after the falling edge of the clock input. To resume serial communication.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25XX256. Data is latched on the rising edge of the serial clock. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. 3. data is shifted out on this pin after the falling edge of the serial clock.6 Hold (HOLD) A low level on this pin selects the device. When WP is low and WPEN is high. all functions. If an internal write cycle has already begun. WP going low will have no effect on the write. WP low during a STATUS register write sequence will disable writing to the STATUS register.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. a low level on CS is required prior to any sequence being initiated.4 Serial Input (SI) The SI pin is used to transfer data into the device.25AA256/25LC256 3. addresses and data. If the WPEN bit is set.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX256. Lowering the HOLD line at any time will tri-state the SO line. 3. The HOLD pin is used to suspend transmission to the 25XX256 while in the middle of a serial sequence without having to retransmit the entire sequence again. 3. DS21822E-page 13 . Instructions. SO goes to the high-impedance state. © 2005 Microchip Technology Inc. It must be held high any time this function is not being used. All other operations function normally. the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The 25XX256 must remain selected during this sequence. This allows the user to install the 25XX256 in a system with WP pin grounded and still be able to write to the STATUS register. When WP is high. The WP pin function is blocked when the WPEN bit in the STATUS register is low.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. including writes to the nonvolatile bits in the STATUS register. otherwise serial communication will not resume. Once the device is selected and a serial sequence is underway. It receives instructions. operate normally. otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. allowing multiple parts to share the same SPI bus. addresses or data present on the SI pin are latched on the rising edge of the clock input. writing to the nonvolatile bits in the STATUS register is disabled. The SI.
In the event the full Microchip part number cannot be marked on one line.X T Y YY WW NNN e3 Note: Part number or part number code Temperature (I.1 PACKAGING INFORMATION Package Marking Information 8-Lead DFN XXXXXXX T/XXXXX YYWW NNN Example: 25LC256 I/MF e3 0528 1L7 8-Lead PDIP XXXXXXXX T/XXXNNN YYWW Example: 25LC256 I/P e3 1L7 0528 8-Lead SOIC (150 mil) Example: 8-Lead SOIC (208 mil) Example: XXXXXXXT XXXXYYWW NNN 25LC256I SN e3 0528 1L7 XXXXXXXX XXXXXXXX YYWWNNN 25LC256 I/SM e3 05281L7 8-Lead TSSOP XXXX TYWW NNN Example: 5LE I528 1L7 TSSOP 1st Line Marking Codes Device 25AA256 25LC256 Standard 5AE 5LE Rotated 5AEX 5LEX Legend: XX.. E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) For very small packages with no room for the Pb-free JEDEC designator e3 . thus limiting the number of available characters for customer-specific information. . Note: DS21822E-page 14 © 2005 Microchip Technology Inc. the marking will only appear on the outer carton or reel label.25AA256/25LC256 4.0 4. it will be carried over to the next line..
01 0.00 5.00 0.47 0.254mm) per side.014 .85 0.184 BSC .80 0.236 BSC .85 4.27 BSC 0.50 . 4.60 0.152 .010" (0.039 .0004 . .085 .163 .019 .65 0.050 BSC .008 REF.05 4.67 BSC 3.356 MAX 1.99 BSC 5.16 2.25AA256/25LC256 8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) E E1 n B p L R D1 D D2 1 2 EXPOSED METAL PADS PIN 1 INDEX E2 TOP VIEW α A2 A3 BOTTOM VIEW A A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Length Molded Package Length Exposed Pad Length Overall Width Molded Package Width Exposed Pad Width Lead Width Lead Length Tie Bar Width Mold Draft Angle Top Units Dimension Limits n p A A2 A1 A3 E E1 E2 D D1 D2 B L R α MIN .74 BSC 2.014 MAX MIN .097 .030 12° MILLIMETERS* NOM 8 1.016 .35 0.75 12° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions.033 .226 BSC . DS21822E-page 15 . JEDEC equivalent: Pending Drawing No. Mold flash or protrusions shall not exceed .024 .020 INCHES NOM 8 .92 BSC 4.20 REF.031 .091 .15 2.46 0.000 .194 BSC .31 0. C04-113 © 2005 Microchip Technology Inc.158 .40 0.002 .026 .00 0.
130 .115 .94 2.012 .022 .78 0.38 7.35 9. JEDEC Equivalent: MS-001 Drawing No.62 7.385 .430 15 15 MILLIMETERS NOM 8 2.94 6.370 10 10 MAX MIN .310 5 5 INCHES* NOM 8 .68 8.260 . .325 .92 3.10 6.46 0.145 .60 9.015 .43 0.87 9.070 .54 3.46 3. C04-018 DS21822E-page 16 © 2005 Microchip Technology Inc.135 .26 6.100 .14 9.29 1.78 3.045 .32 3.008 .373 .240 .130 .56 3.25AA256/25LC256 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β eB B1 p B Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB α β MIN § .010” (0.125 .015 .46 7.30 0.40 5 10 5 10 MAX 4.56 10.058 .30 0.254mm) per side.170 .36 0.300 . Mold flash or protrusions shall not exceed .014 .38 1.018 .140 .313 .360 .20 0.155 .14 1.250 .18 3.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions.
020 15 15 MILLIMETERS NOM 8 1.80 4.025 4 .79 6.254mm) per side.189 .02 3.157 .51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions.25 6.244 .052 .010 .013 0 0 INCHES* NOM 8 .25 0.197 .056 .76 8 0.48 0.053 .55 0.55 1.42 0 12 0 12 MAX 1.154 .00 0.42 0.90 0.71 3.030 8 .20 0.009 . 150 mil (SOIC) E E1 p D 2 B n 1 45° h α c A A2 φ β L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L φ c B α β MIN .010” (0.061 . C04-057 © 2005 Microchip Technology Inc.010 .75 1. JEDEC Equivalent: MS-012 Drawing No.017 12 12 MAX MIN .18 5.193 .10 0.004 .32 1.008 .35 1.020 .20 3.228 .061 .050 .146 .25 0.23 0.51 0.237 .38 0.019 0 . DS21822E-page 17 .91 4.33 0.069 .015 .62 0 4 0.27 1.010 .99 5.25AA256/25LC256 8-Lead Plastic Small Outline (SN) – Narrow.007 . Mold flash or protrusions shall not exceed .
03 1.51 15 15 DS21822E-page 18 © 2005 Microchip Technology Inc.20 0.13 5.017 12 12 MAX MIN MILLIMETERS NOM 8 1.75 1. Drawing No.76 8 0. C04-056 Units Dimension Limits n p MIN INCHES* NOM 8 .005 .51 0.43 0 12 0 12 MAX 2.014 .020 α Mold Draft Angle Top 0 15 β Mold Draft Angle Bottom 0 15 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions.020 .313 .33 0.64 0 4 0.050 .62 7.010 Overall Width E . Formerly called SOIC) E E1 p D 2 n B 1 α c A A2 φ β L A1 Number of Pins Pitch Overall Height A .025 4 .210 Foot Length L .36 0.205 .075 .010" (0.26 5.11 5.88 0. 208 mil Body (SOIJ) (JEITA/EIAJ Standard.38 5.208 .009 .030 φ Foot Angle 0 8 c Lead Thickness .325 Molded Package Width E1 .080 .05 0.21 0.202 .98 0. . Mold flash or protrusions shall not exceed .002 .23 0.300 .95 5.212 Overall Length D .27 1.078 .78 1.008 .074 .201 .070 Molded Package Thickness A2 .25 8.069 Standoff A1 .13 7.28 5.25 0.254mm) per side.25AA256/25LC256 8-Lead Plastic Small Outline (SM) – Medium.97 1.010 Lead Width B .
60 0. Mold flash or protrusions shall not exceed .19 0.30 0 5 10 0 5 10 Notes: Dimensions D and E1 do not include mold flash or protrusions.169 .05 0.004 .026 .007 0 0 .50 2.65 1. C04-086 © 2005 Microchip Technology Inc.85 0.127mm) per side.95 0.25 6.043 .15 6.028 8 .50 4.10 0.004 .00 3.020 0 .002 .70 0 4 8 0.037 .20 0.10 0.114 .033 .40 4.30 4.25 0.012 10 10 MILLIMETERS* NOM MAX 8 0.006 .38 6.173 .008 . DS21822E-page 19 .25AA256/25LC256 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.006 .90 3.10 0.177 .122 .50 0.005” (0.246 .024 4 .118 .035 .256 .09 0.15 0.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β L A1 A2 Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L φ c B α β MIN INCHES NOM 8 .251 . JEDEC Equivalent: MO-153 Drawing No.010 5 5 MAX MIN .90 0.
Revise Table 1-1. REVISION HISTORY DS21822E-page 20 © 2005 Microchip Technology Inc. Params. .0.25AA256/25LC256 APPENDIX A: Revision C (11/03) Corrections to Section 1. Revision D (06/05) Update package information Revision E (08/05) Remove Preliminary status. D011 and D012. Electrical Characteristics.
listings of Microchip sales offices.com.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. A listing of sales offices and locations is included in the back of this document. design resources. latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ). DS21822E-page 21 . application notes and sample programs. This web site is used as a means to make files and information easily available to customers.microchip.com. distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor. the web site contains the following information: • Product Support – Data sheets and errata. Local sales offices are also available to help customers. access the Microchip web site at www. Accessible by using your favorite Internet browser. updates. listing of seminars and events.microchip. online discussion groups. © 2005 Microchip Technology Inc. Subscribers will receive e-mail notification whenever there are changes. Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides. To register. latest Microchip press releases. revisions or errata related to a specified product family or development tool of interest.25AA256/25LC256 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip. representative or field application engineer (FAE) for support. Technical support is available through the web site at: http://support. user’s guides and hardware support documents. click on Customer Change Notification and follow the registration instructions. technical support requests.
Do you find the organization of this document easy to follow? If not. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. and ways in which our documentation can better serve you. ._________ Application (optional): Would you like a reply? Y N Literature Number: DS21822E FAX: (______) _________ ._________ Device: 25AA256/25LC256 Questions: 1. clarity. What are the best features of this document? 2. If you wish to provide your comments on organization. subject matter. How would you improve this document? DS21822E-page 22 © 2005 Microchip Technology Inc. please FAX your comments to the Technical Publications Manager at (480) 792-4150.25AA256/25LC256 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. Please list the following information. why? 4. and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ . How does this document meet your hardware and software development needs? 3.
SOIC package 25AA256T-I/ST = 256k-bit.. SPI Serial EEPROM. Tape and Reel.com) Please specify which device. Extended temp. FAX: (480) 792-7277 The Microchip Worldwide Site (www. refer to the factory or the listed sales office.8V Serial EEPROM.com/cn) to receive the most current information on our products. TSSOP package 25LC256XT-I/ST = 256k-bit. Industrial temp.8V Serial EEPROM. PART NO. 1. Your local Microchip sales office The Microchip Corporate Literature Center U.25AA256/25LC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information. 64-Byte Page. 8-lead TSSOP. rotated pinout (ST only) Standard packaging (tube) Tape & Reel -40°C to+85°C -40°C to+125°C Micro Lead Frame (6 x 5 mm body). TSSOP package 25LC256-I/P = 256k-bit. 8-lead Plastic SOIC (208 mil body).5V Serial EEPROM.5V.5V Serial EEPROM.microchip. 8-lead Plastic DIP (300 mil body). Industrial temp. Tape & Reel. 8-lead c) d) e) Package: MF P SN ST SM = = = = = Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds.microchip.8V. 1. 2. please contact one of the following: 1. 64-Byte Page.. 64-Byte Page. © 2005 Microchip Technology Inc. DS21822E-page 23 . SPI Serial EEPROM. e. 2. 2.8V. 64-Byte Page. revision of silicon and Data Sheet (include Literature #) you are using. Tape & Reel. New Customer Notification System Register on our web site (www. 2.. Tape & Reel. rotated pinout (ST only) 256k-bit.5V Serial EEPROM. To determine if an errata sheet exists for a particular device. SPI Serial EEPROM 256k-bit.S. SPI Serial EEPROM 256k-bit. 1. P-DIP package 25LC256T-E/ST = 256k-bit. Industrial temp. on pricing or delivery. Device X Tape & Reel – X Temp Range /XX Package Examples: a) 25AA256T-I/SN = 256k-bit.g.. Industrial temp. 1. 2. 3.. 2. 8-lead Plastic SOIC (150 mil body). Rotated TSSOP package b) Device: 25AA256 25LC256 25AA256X 25LC256X Tape & Reel: Temperature Range: Blank T I E = = = = 256k-bit.5V..
25AA256/25LC256 NOTES: DS21822E-page 24 © 2005 Microchip Technology Inc. .
dsPICDEM. nonvolatile memory and analog products. the Microchip logo. DS21822E-page 25 . SEEVAL. ECAN. Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U. Microchip is willing to work with the customer who is concerned about the integrity of their code. and other countries. Printed on recycled paper.S. There are dishonest and possibly illegal methods used to breach the code protection feature.net. MPLIB. Migratable Memory. Trademarks The Microchip name and logo. MPASM. FilterLab. PICDEM.S. rfLAB.net. MPSIM. you may have a right to sue for relief under that Act. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. PowerSmart. microID. It is your responsibility to ensure that your application meets with your specifications. Analog-for-the-Digital Age. MERCHANTABILITY OR FITNESS FOR PURPOSE. All other trademarks mentioned herein are property of their respective companies. dsPIC.A. PICDEM. when used in the intended manner and under normal conditions. Most likely. FanSense. the person doing so is engaged in theft of intellectual property. INCLUDING BUT NOT LIMITED TO ITS CONDITION. rfPICDEM. SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U. Microchip believes that its family of products is one of the most secure families of its kind on the market today. California in October 2003. PowerTool. © 2005 Microchip Technology Inc.S. PowerInfo. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs. MXLAB. PICSTART. QUALITY. If such acts allow unauthorized access to your software or other copyrighted work. MPLINK. PowerMate. Serial EEPROMs. RELATED TO THE INFORMATION. and other countries.” • • • Code protection is constantly evolving. MPLAB. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters. In addition. Code protection does not mean that we are guaranteeing the product as “unbreakable. AmpLab. All of these methods. PRO MATE. STATUTORY OR OTHERWISE. All Rights Reserved.Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Arizona and Mountain View. Select Mode. SQTP is a service mark of Microchip Technology Incorporated in the U. We at Microchip are committed to continuously improving the code protection features of our products. PICMASTER. to our knowledge. Accuron. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. Smart Serial. Microchip disclaims all liability arising from this information and its use..S. PICtail. In-Circuit Serial Programming.A. Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.A.A. dsPICworks. ICSP. Application Maestro. and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U. implicitly or otherwise. PERFORMANCE. ICEPIC. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED. dsPICDEM. require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Microchip Technology Incorporated. KEELOQ® code hopping devices. under any Microchip intellectual property rights. ECONOMONITOR. microperipherals. rfPIC. No licenses are conveyed. MXDEV.A. PowerCal. PICmicro. FlexROM. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Linear Active Thermistor. © 2005. WRITTEN OR ORAL. PICLAB. PICkit. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. PIC. Printed in the U. KEELOQ. design and wafer fabrication facilities in Chandler and Tempe. fuzzyLAB.S. SmartTel.
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