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Textbook chapter 12

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12.1 Consider 3 Y = Y + Y + Y, that is, we need to add Y to itself 3 times. First, clear the accumulator before the first rising clock edge so that the X-register is 000000. Let the Ad pulse be 1 for 3 rising clock edges and let the Y register contain the desired number ( y5 y4 y3 y2 y1 y0 ) which is to be added three times. The timing diagram is on FLD p. 650. Note: ClrN should go to 0 and back to 1 before the first rising clock edge. Ad should be 1 before the same clock edge. However, it does not matter in what order, that is, Ad could go to 1 before ClrN returns to 1, or even before it goes to 0. Serial input connected to D0 for left shift. Sh = 0, L = 1 causes a left shift. Sh = 1, L = 1 or 0 causes a right shift Serial Out SI SH Ld Clock 12.3 See FLD p. 650 for solution.

12.2

Q3

Q2 Q1 Q0

12.4 (a)

DC B A 00 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 10 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1

Present State

D+C+B+A+ 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0

Next State

TDTCTBTA 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 1 1

Flip-Flop Inputs

D'

D TD

C'

C TC

B'

B TB

A'

A TA

1

Clock As explained in Section 12.3, it can be seen that A changes on every pulse: TA = 1 B changes only when A = 1: TB = A C changes only when both B and A = 1: TC = AB D changes only when A, B, and C = 1: TD = ABC

12.4 (b) The binary counter using D flip-flops is obtained by converting each T flip-flop to a D flip-flop by adding an XOR gate. See FLD p. 650 and Figure 12-15 on FLD p. 335.

12.5

Equations for C, B, and A are from Equations (122) on FLD p. 335. Beginning with (b) of Problem 12.4 solutions, D+ = D CBA = D'CBA + D(CBA)' = D'CBA + D(C' + B' + A') = D'CBA + DC' + DB' + DA'

81

12.6

In the following state graph, the first flip-flop (C) A+ takes on the required sequence 0, 0, 1, 0, 1, 1, (repeat). B A

000 110 101 010 001 100

C 00 01 11 10

B 0 1 0 X 1

+

1 0 0 X 0

B A

C 00 01 11 10

C+ 0 0 0 X 0 1 1 1 X 0 B A

C 00 01 11 10

0 0 1 X 1

1 0 1 X 0

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

C+.B+ A+ 0 0 1 1 0 0 1 0 1 X 0 1 0 X 1 1 0 X 0 0 0

A = C'A'

B+ = C B'

C + = A + C'B

X X X

12.7 (a)

CB A 00 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1

C+B+A+ XXX 01 1 11 0 01 0 00 1 10 0 11 1 10 1

C+ B A

C 00 01 11 10

B+ 0 X 0 0 1 1 0 1 1 1 B A

C 00 01 11 10

+

A+ 0 X 1 1 1 1 0 0 0 1 B A

C 00 01 11 10

+ +

0 X 1 0 0

1 1 0 1 1

C + = C A + B A'

B = C' + B A'

12.7 (b)

TC

B A

C 00 01 11 10

TB

0 X 0 0 1

1 1 0 0 0

B A

C 00 01 11 10

TA

0 X 1 0 0

1 0 0 1 0

B A

C 00 01 11 10

0 X 0 1 0

1 1 1 0 1

TC = C'A' + B'A'

TB = C'B' + C B A

82

12.8 (a)

CB A 00 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1

C+B+A+ XXX 01 1 11 0 01 0 00 1 10 0 11 1 10 1

KC C 00 01 11 10

C+ B A

C 00 01 11 10

B+ 0 X 0 0 1 1 0 1 1 1 B A

C 00 01 11 10

A+ 0 X 1 1 1 1 0 0 0 1 B A

C 00 01 11 10

0 X 1 0 0

1 1 0 1 1

JC B A

C 00 01 11 10

JB

0 X 0 0 1

1 X X X X

B A

0 X X X X

1 1 0 0 0

B A

C 00 01 11 10

KB 0 X 1 X X 1 0 0 X X B A

C 00 01 11 10

JA

0 X X 0 0

1 X X 1 0

B A

C 00 01 11 10

KA 0 X X X 0 JA = C 1 1 X X 1 B A

C 00 01 11 10

0 X 0 1 X

1 X 1 0 X

JC = A'

KC = B'A'

JB = C'

KB = C A

K A = C'B + C B'

In state 000, JC = A' = 1, KC = B'A' = 1, C+ = C' = 1 JB = C' = 1, KB = CA = 0, B+ = 1 JA = C = 0, KA = CB' + C'B = 0, A+ = A = 0 So the next state is C+B+A+ = 110 12.8 (b)

SC B A C 00 01 11 10

RC

0 X 0 0 1

1 0 X X X

B A

C 00 01 11 10

SB 0 X X X 0 1 1 0 0 0 B A

C 00 01 11 10

RB 0 X 1 X X 1 0 0 0 X B A

C 00 01 11 10

SA 0 X 0 0 0 1 X X 1 0 B A

C 00 01 11 10

RA 0 X X 0 0 1 B A 1 0 X 1

C 00 01 11 10

0 X 0 1 X

1 0 1 0 0

S C = B A' S C = C'A'

R C = B'A'

S B = C'

RB = C A

S A = C A'

R A = C'B + C B'A

In state 000, SC = BA' = 0, RC = B'A' = 1, C+ = 0 SB = C' = 1, RB = CA = 0, B+ = 1 SA = CA' = 0, RA = C'B + C'BA = 0, A+ = A = 0 So the next state is C+B+A+ = 010

83

12.9 (a)

Q Q+ M N 00 01 10 11

C+ B A C 00 01 11 10

12.9 (b)

} 10 1X 1 1} 10 }X0 00 01 X1 1 1}

00 0X 01

MC

CB A 00 0 0 0 1 1 1 0 1 1 0 0 1 1 1 1 0

C+B+A+ 00 1 0 1 1 1 0 1 1 0 0 0 1 1 1 0 0

0 0 0 1 X

1 0 1 1 X

B A

C 00 01 11 10

NC 0 0 0 1 X 1 X X X X B A

C 00 01 11 10

0 X X X X

1 0 1 1 X

C+

B+ MB

MC = B C 00 01 11 10 NB 0 0 1 X X 1 0 0 X X B A

NC = A

B A

C 00 01 11 10

0 0 1 1 X

1 0 0 0 X

B A

C 00 01 11 10

0 X X 1 X

1 X X 0 X

B+

A+ B A C 00 01 11 10

MA

MB = C'A NA

0

NB = C'

0 1 1 1 X

1 0 0 1 X

B A

C 00 01 11 10

1 0 X X X

1 X X X

B A

C 00 01 11 10

0 X 1 1 X

1 X 0 1 X

A+ 12.10 12.11

MA = C'

NA = C' + B

The flip-flops change state only when Ld or Sh = 1. So CE = Sh + Ld. Now only a 2-to-1 MUX is required to select the input to the D flip-flop.

SI

1 0

D3

D Q3

CE D2

1 0

D Q2

CE D1

1 0

D Q1

CE D0

1 0

D Q0

CE

Sh Ld

84

12.12 (a) When ShLd = 00, the MUX for flip-flop i selects Qi to hold its state When ShLd = 01, the MUX for flip-flop i selects Di to load. When ShLd = 10 or 11, the MUX for flip-flop i selects Qi to shift left.

Q3 D

D3

Q2 D

D2

Q1 D

D1

Q0 D

SI D0 Sh Ld

+ + + 12.12 (b) Q3 = Ld'Sh'Q3 + LdSh'D3 + ShQ2; Q2 = Ld'Sh'Q2 + LdSh'D2 + ShQ1; Q1 = Ld'Sh'Q1 + LdSh'D1 + ShQ0 + Q0 = Ld'Sh'Q0 + LdSh'D0 + ShSI

12.13

Clock Sh Ld QA SI = QC QD QB

12.14 (b) Similar to problem 12.4 (b), DE = E DBCA. DD, DC, DB, and DA, remain unchanged.

E'

12.14 (a) Similar to problem 12.4 (a), TE = ABCD. TD, TC, TB, and TA, remain unchanged.

E DE

E'

E TE

Clk

E

Clk

A BCD

12.15 4-bit Johnson counter using J-K flip-flops:

J4 K4 Q4 Q' 4 J3 K3 Q3 Q' 3 J2 K2 Q2 Q' 2 J1 K1 Q1 Q' 1

A BCD

CLK

Starting in 0000: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, (repeat) 0000, ... Starting in 0110: 0110, 1011, 0101, 0010, 1001, 0100, 1010, 1101, (repeat) 0110, ...

85

12.16

When U = 1, D = 0, add 001. When U = 0, D = 1, subtract 1: add 111. When U = 0, D = 0, no change: add 000. U = 1, D = 1, can never occur. So add the contents of the register to X2 X1 X0, where X2 = X1 = D and X0 = D + U. (Note: to save the OR gate, let X0 = D and Cin = U.)

Q2 Q1 Q0 D2 D1 D0

Clk 0

D D

S2 S 1 S0

12.17 (a)

DA C D

A B 00 00 01 11 10

DB 01 11 X X 1 X X X X 10 1 C D

D U

A B 00 00 01 11 10 1 1 01 1 1 11 X X X X X X 10

DA = B C D + A D' DC C D A B 00 00 01 11 10 1 1 1 1 DD 01 11 X X X X X X 10 C D

01 1

11 X X X X

10 1

X X

DC = A'C'D + C D'

DD = D'

C D A B 00 00 01 11 10 0 0 0 0 01 0 0 1 0 11 X X X X 10 X X X X C D A B 00 00 01 11 10 0 0 1 0 01 X X X X 11 X X X X 10 0 0 X X C D A B 00 00 01 11 10 0 1 X X 01 0 1 X X 11 X X X X 10 0 0 X X C D A B 00 00 01 11 10 1 X X 1 01 1 X X 1 11 X X X X 10 1 X X X

JA = B C D C D A B 00 00 01 11 10 X X X X 01 X X X X 11 X X X X 10 0 1 X X C D A B 00 00 01 11 10 X X X X

JB = C D 01 0 0 1 0 11 X X X X 10 X X X X C D A B 00 00 01 11 10 X X 1 0

JC = A'D 01 X X 1 0 11 X X X X 10 X X X X C D A B 00 00 01 11 10 X 1 1 X

JD = 1 01 X 1 1 X 11 X X X X 10 X 1 X X

KA = D

KB = C D

86

KC = D

KD = 1

SA C D A B 00 00 01 11 10 1 SB 01 11 X X X X SA = B C D RA C D RB 01 X X 11 X X X X X 1 X X 10 C D X X 10 X C D A B 00 00 01 11 10 1 X SC 01 X X 11 X X X X X X 10 C D A B 00 00 01 11 10 X X 1 1 SD 01 11 X X X X X X 10 C D A B 00 00 01 11 10 1 1 1

01 1

11 X X X X

10 1

X X

SB = B'C D RC 01 11 X X 1 X X X RB = B C D 10 X X X X C D

SC = A'C'D RD 01 X 11 X X 1 1 X X RC = C D 10 X X X X C D

SD = D'

A B 00 00 01 11 10 X X X X

A B 00

00

X X

A B 00 00 01 11 10 X

A B 00 00 01 11 10 1 1

01 1 1

11 X X X X

10 1 X X

01 11 10

RA = C'D RA = A D RA = B'D

RD = D

TA C D A B 00 00 01 11 10 1 TB 01 11 X X X X 1 X X 10 C D A B 00 00 01 11 10 1 1 TC 01 11 X X X X TB = C D X X 10 C D A B 00 00 01 11 10 1 1 1 1 TD 01 11 X X X X TC = A'D X X 10 C D A B 00 00 01 11 10 1 1 1 1 01 1 1 1 1 11 X X X X 10 1 1 X X

TA = B C D + A D

TD = 1

12.17 (e) Use equations to find next states for unused states. State 1101: JA = BCD = 0, KA = D = 1, A+ = 0 JB = CD = 0, KB = CD = 0, B+ = B = 1 JC = A'D = 0, KC = D = 1, C+ = 0 JD = 1, KD = 1, D+ = D' = 0 So the next state is 0100. Other next states can be found in a similar way.

1110

1000 0111

0010 0011

0110 1010

0101 1011

0100

1101

1100

87

12.18

12.18 (a) DA = A'B'C'D' + AD; DB= BD + BC + AD'; DC = CD + BC'D' + AD'; DD = D' 12.18 (b) JA = B'C'D', KA = D'; JB = AD', KB = C'D'; JC = BD' + AD', KC = D'; JD = 1, KD = 1 12.18 (c) SA = A'B'C'D', RA = AD'; SB = AC'D', RB = BC'D' or A'C'D'; SC = BD'C' + AD', RC = CD', SD = D', RD = D 12.18 (d) TA = B'C'D'; TB = BC'D' + AC'D'; TC = CD' + BD' + AD'; TD = 1 12.18 (e) 0010 1101 1100 1011 1111 0011 1010 1110 0001 0000 1001

1000 0111

0100

0101

0110

12.19

A B C A+B+C+ 00 0 X XX 00 1 1 0 0 01 0 0 1 1 01 1 0 0 1 10 0 1 0 1 10 1 1 1 1 11 0 0 1 0 11 1 1 1 0 LM

12.19 (a) DA = B' + AC; DB = AC + BC'; DC = A'B + AB' 12.19 (b) JA = B', KA = BC'; JB = AC, KB = A'C; JC = A' + B', KC = A'B' + AB 12.19 (c) TA = A'B' + ABC'; TB = A'BC + AB'C; TC = A'B' + A'C' + B'C' + ABC 12.19 (d) SA = B', RA = BC'; SB = AC, RB = A'C; SC = A'B + AB', RC = A'B' + AB 12.19 (e) State 000 goes to 100, because DADBDC = 100. 12.20 (b) A B C A+B+C+ 00 0 1 0 0 00 1 0 0 0 01 0 X XX 01 1 0 0 1 10 0 1 0 1 10 1 1 1 1 11 0 X XX 11 1 0 1 1

A+ B C

12.20 (a) Q Q+ 00 01 10 11

A 00 01 11 10

B+ 0 1 0 0 X 1 1 1 0 X B C

A 00 01 11 10

} 00 X0 1 0} 10 }1X 11 00 0X 0 1}

01 X1 11

0 0 0 0 X

1 0 1 1 X

C+ B C

A 00 01 11 10

0 0 0 1 X

1 1 1 1 X

88

B C A 00 01 11 10 0 X X X X 1 0 0 1 X B C A 00 01 11 10 0 0 1 1 X 1 X X X X B C A 00 01 11 10 0 X X 1 X 1 X X 0 X B C A 00 01 11 10 0 1 1 X X 1 1 0 X X B C A 00 01 11 10 0 X 1 0 X 1 X 0 0 X B C A 00 01 11 10 0 1 X X X 1 0 X X X

LA = B

MA = C

LB = A'

MB = A' + C'

LC = A'B'

MC = A'

12.21

ABCD 00 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 10 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1

JA KA JB KB JC KC JD KD 0 X 0 X 1 X 1 X 0 X 1 X 0 X X 1 0 X 1 X X 1 1 X 0 X 1 X X 0 X 1 0 X X 0 1 X 1 X 1 X X 1 0 X X 1 1 X X 1 X 1 1 X 1 X X 1 X 0 X 1 X 0 0 X 1 X 1 X X 0 1 X 0 X X 1 X 0 1 X X 1 1 X X 0 1 X X 0 X 1 X 0 X 0 1 X 1 X X X X X X X X X X X X X X X X X X X X X X X X X

12.22

Clock Cycle 0 1 2 3 4 5 6

Input Accumulator Data EnIn EnAd LdAc LdAd Register 18 1 0 1 0 0 13 1 0 0 1 18 15 0 1 1 0 18 93 1 0 0 1 31 47 0 1 1 0 31 22 1 0 0 1 124 0 0 1 0 0 124

Addend Register 0 0 13 13 93 93 22

Description Input to accumulator Input to addend Sum to accumulator Input to addend Sum to accumulator Input to addend Sum on bus

Note: Register values change after the clock edge. So a value loaded from the bus appears in the register on the next clock cycle after the load signal and bus value are present.

89

12.23 (a, b)

8 8

X

8

8 NAND gates

Y

8

8 8 CE En 8

E0

Ck CE En

E1 E2

8

' E0

Ck

CE En

Ck

CE En

Ck

G0 G1

' E1 ' E2

2-to-4 decoder

' E1 E2

12.23 (c) Call the values beginning in the A & D registers X and Y, respectively. We want C = X + Y = (X'Y')'. Invert using M' = 1 NAND M. To invert a value on the right side, in register C or D, we will need a 1 on the left side, in register A or B. This can be accomplished using 1 = 0 NAND (anything.) There are several solutions using different registers. Here is an example: Clock Cycle G0G1 1 00 2 3 4 01 11 10

E0 0 1 1 0

E1E2 Description 1 1 1 NAND A = A' = X' A 10 01 01 0 NAND B = 1 B B NAND D = 1 NAND Y = Y' D A NAND D = X' NAND Y' = X + Y C

Alternate three-cycle solution: Use X + Y = X + X'Y = (X' (X'Y)')' Clock Cycle G0G1 1 00 2 3 11 10 E0 0 0 0 E1E2 Description 1 1 1 NAND A = A' = X' A 01 01 A NAND D = (X'Y)' D A NAND D = (X' (X'Y)')' = X + Y C

12.24 (a) For bit reversal using the D inputs of the shift register: Sh = 0, Ld = 1

Ld Sh SI Clk

Q3 D3

Q2 D2

Q1 D1

Q0 D0

12.24 (b) Same as Figure 12-10 (b) on FLD p. 331, except that for the "11" input of each MUX, instead of SI, Q3, Q2, or Q1, use Q0, Q1, Q2, or Q3, respectively. Also, replace Sh with A and Ld with B.

90

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