EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 121
OpAmp Circuits:
CMOS
OpAmp
Reference: Neamen, Chapter 13
(12)
I
Learning Outcome
Able to:
Describe and analyze the dc
and ac characteristics of CMOS
opamp circuits.
Z
3
Most CMOS opamps:
are designed for specific onchip applications
only required to drive capacitive loads of few pF
do not need lowresistance output stage
do not need electrostatic input protection
devices if the opamp inputs are not connected
directly to IC external terminals
Two designs will be considered:
1) MC14573 CMOS opamp circuit
2) Foldedcascode opamp
DC and smallsignal analysis will be performed.
12.0) CMOS OpAmp Circuits
4
12.1) MC14573 CMOS OpAmp Circuit
Figure 13.14: MC14573 CMOS
opamp equivalent circuit.
Input Stage:
M
1
and M
2
: PMOS
input differential pair.
M
3
and M
4
: NMOS
active load.
M
5
and M
6
: current
mirror for input stage
biasing, reference
current I
set
can be
determined by R
set
b
12.1) MC14573 CMOS OpAmp Circuit (Cont)
Figure 13.14: MC14573 CMOS
opamp equivalent circuit.
Second Stage (also
Output Stage):
M
7
: commonsource
connected transistor.
M
8
: provides bias
current for M
7
, also
acts as active load.
Capacitor C
1
:
internal feedback
compensation (Miller
compensation) to
provide stability.
o
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.1) DC Analysis
Assuming M
5
and M
6
are matched, the reference
and inputstage bias currents are given by:
(13.36)
The reference current and sourcetogate voltage
V
SG5
are also related by:
(13.37)
set
SG
Q set
R
V V V
I I
5
= =
+
2
5 5
) (
TP SG p set
V V K I + =
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 122
7
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.1) DC Analysis (Cont)
The quiescent bias currents can be changed by
changing resistor R
set
.
If transistors M
6
and M
8
are identical to M
5
, then
their currents:
since V
SG6
= V
SG8
= V
SG5
.
set D D D
I I I I = = =
5 8 6
8
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.1) DC Analysis (Cont)
Example 13.8
Objective: Determine the dc bias currents in the
MC14573 opamp.
Assume transistor parameters of V
T
 = 0.5 V
(all transistors), k
n
= 100 A/V
2
, k
p
= 40 A/V
2
,
and the circuit parameters of V
+
= 5 V, V

= 5 V,
and R
set
= 225 k.
Assume transistor widthtolength ratios of
6.25 for M
3
and M
4
, and 12.5 for all other
transistors.
9
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.1) DC Analysis (Cont)
Example 13.8 (Cont)
Solution: For M
5
and M
6
, the conduction
parameters are:
K
p
= (k
p
/2)(W/L)
5
= (40/2)(12.5) = 0.25 mA/V
2
Combining Equations (13.36) and (13.37) yields
the sourcetogate voltage of M
5
:
K
p
(V
SG5
+ V
TP
)
2
= (V
+
 V

 V
SG5
) / R
set
I0
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.1) DC Analysis (Cont)
Example 13.8 (Cont)
or (0.25m)(V
SG5
 0.5 )
2
= (5  (5)  V
SG5
) / 225k
which yields V
SG5
= 0.9022 V
From Equation (13.36),
I
REF
= I
Q
= (10 0.9022)/225k = 40.4 A
The quiescent drain currents in M
7
and M
8
are then
also 40.4 A, and the currents in M
1
through M
4
are 20.2 A.
II
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.1) DC Analysis (Cont)
Do Ex 13.8
IZ
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.2) SmallSignal Analysis
The smallsignal differential voltage gain of input
stage:
(13.38)
where r
o2
and r
o4
are output resistances of M
2
and
M
4
respectively.
Input impedance to the 2
nd
stage is essentially
infinite. Hence, no loading effect due to 2
nd
stage.
Assuming is identical for all transistors,
(13.39)
( )
4 2 1
2
o o Q p d
r r I K A =
) 2 / (
1 1
4 2
Q D
o o
I I
r r
= = =
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 123
I3
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.2) SmallSignal Analysis (Cont)
The magnitude of the gain of the second stage:
(13.40)
where
and
Equation (13.40) implies that there is no loading
effect due to an external load connected at output.
Note: The openloop gain of a CMOS opamp is generally less than that of
a bipolar opamp, but the use of active loads provides acceptable results.
( )
7 8 7
7 7 7
8 7 7 2
/ 1
2
D o o
D n m
o o m v
I r r
I K g
r r g A
= =
=
=
I4
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.2) SmallSignal Analysis (Cont)
Example 13.9
Objective: Determine the smallsignal voltage
gains of the input and second stages, and the
overall voltage gain, of the MC14573 opamp.
Assume the same transistor and circuit
parameters as in Example 13.8. Let = 0.02 V
1
for all transistors.
Ib
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.2) SmallSignal Analysis (Cont)
Example 13.9 (Cont)
Solution: The conduction parameters of M
1
and
M
2
are
K
p1
= K
p2
= (k
p
/2)(W/L)
1
K
p1
= K
p2
= (40/2)(12.5) = 0.25 mA/V
2
and the output resistances are
r
o2
= r
04
= 1 / ( I
D
)
r
o2
= r
04
= 1 / ((0.02)(20.2)) = 2.475 M
Io
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.2) SmallSignal Analysis (Cont)
Example 13.9 (Cont)
From Equation (13.38), the gain of the input stage
is then
The transconductance of M
7
is
( )
( ) 176 2475 2475 ) 4 . 40 )( m 25 . 0 ( 2
2
4 2 1
= =
=
d
o o Q p d
A
r r I K A
mA/V 3178 . 0 ) 4 . 40 )( 5 . 12 )( /2 100 ( 2
) / )( 2 / ( 2
7
7 7
'
7
= =
=
m
D n m
g
I L W k g
I7
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.2) SmallSignal Analysis (Cont)
Example 13.9 (Cont)
and the output resistances of M
7
and M
8
are
r
o7
= r
08
= 1 / ( I
D7
)
r
o7
= r
08
= 1 / ((0.02)(40.4)) = 1.238 M
From Equation (13.40), the gain of the second
stage is then
A
v2
= g
m7
(r
o7
 r
08
)
A
v2
= (0.3178m)(1.238M1.238M) = 197
Finally, the overall voltage gain of the opamp is
A
v
= A
d
A
v2
= (176)(197) = 34,672
I8
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.2) SmallSignal Analysis (Cont)
Problem 13.29
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 124
I9
12.1) MC14573 CMOS OpAmp Circuit (Cont)
12.1.2) SmallSignal Analysis (Cont)
Do Ex 13.9
Z0
12.2) Cascode CMOS OpAmp Circuits
Figure 13.16: (a) Classical cascode stage
(b) Foldedcascode stage
The voltage gain of an amplifier can be increased by using
a cascode configuration.
ZI
12.2) Cascode CMOS OpAmp Circuits (Cont)
Figure 13.16 (a) Conventional
cascode configuration
Consists of 2 transistors in series.
M
1
= commonsource amplifying
device, dc current I
D1
is determined
by input voltage v
i
M
2
= commongate configuration.
I
D1
is input signal to M
2
Output is taken off the drain of
cascode transistor.
AC current is through both
transistors and dc power supply.
ZZ
12.2) Cascode CMOS OpAmp Circuits (Cont)
Figure 13.16 (b) Folded
cascode configuration
DC current I
1
in M
1
determined by input voltage v
i
DC current in M
2
= I
2
I
2
= I
Q
I
1
AC current is through both
transistors and ground.
AC currents in M
2
& M
1
,
equal in magnitude but
opposite in directions
current is folded back
folded cascode circuit
Z3
12.3) CMOS FoldedCascode OpAmp
Figure 13.17:
CMOS folded
cascode amplifier.
Z4
12.3) CMOS FoldedCascode OpAmp (Cont)
Foldedcascode configuration can be applied to
the diffamp as shown in Figure 13.17
M
1
and M
2
: PMOS input differential pair.
M
5
and M
6
: cascode transistors.
M
7
to M
10
: form a modified Wilson current
mirror acting as active load.
The biasing V
B1
and V
B2
must be provided by
a separate network.
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 125
Zb
12.3) CMOS FoldedCascode OpAmp (Cont)
Assuming that transistors M
3
, M
4
and M
11
 M
13
are
all matched, then:
dc currents in M
1
and M
2
are I
REF
/ 2
dc currents in M
3
and M
4
are I
REF
dc currents in M
5
and M
6
are I
REF
/ 2
If a differentialmode input voltage v
d
is applied,
then ac currents are induced in the differential pair
as shown in Figure 13.17
AC current in M
1
flows through M
6
to output.
AC current in M
2
flows through M
5
and is
induced in M
8
by currentmirror action of the
active load.
Zo
12.3) CMOS FoldedCascode OpAmp (Cont)
Hence, from previous work on diffamps, the
differentialmode voltage gain is:
(13.41)
where
and
Note: Body effect is neglected. Normally the
substrates of all NMOS devices are tied to V and
the substrates of all PMOS devices are tied to V+
( )
( )( )
( )
1 8 8 8
1 4 6 6 6
8 6 1
o o m o
o o o m o
o o m d
r r g R
r r r g R
R R g A
=
=
=
Z7
12.3) CMOS FoldedCascode OpAmp (Cont)
Study Example 13.11
Comments from the example:
Very high differentialmode voltage gains can
be achieved in a foldedcascode CMOS circuit
compared to simple diffamp circuits.
Output resistance may be limited by leakage
currents in actual circuits, so actual gain is less
than ideal gain.
Do Ex 13.11
Z8
Larger circuits
Z9
12.1) MC14573 CMOS OpAmp Circuit
Figure 13.14: MC14573 CMOS opamp equivalent circuit
30
12.1) MC14573 CMOS OpAmp Circuit (Cont)
Problem 13.29 (Cont)
A simple CMOS opamp circuit as shown in Figure
P13.29 is biased with I
Q
= 200 A. The transistor
parameters are k
n
= 100 A/V
2
, k
p
= 40 A/V
2
,
V
TN
= 0.4 V, V
TP
= 0.4 V, and
n
=
p
= 0. The
transistor widthtolength ratios are (W/L)
1
= (W/L)
2
= 20, (W/L)
3
= 50, and (W/L)
4
= 40.
i) Design the circuit (i.e. find the values of R
D1
, R
D2
,
and R
S
) such that I
D3
= 150 A, I
D4
= 200 A, and
v
o
= 0 for v
1
= v
2
= 0.
ii) Find the overall smallsignal voltage gain if the
gain of the gain stage is 19.21.
EEEB273 Electronics Analysis & Design II
Lecturer: Dr Jamaludin Bin Omar 126
3I
12.1) MC14573 CMOS OpAmp Circuit (Cont)
Problem 13.29 (Cont)
3Z
12.1) MC14573 CMOS OpAmp Circuit (Cont)
Problem 13.29 (Cont)
(i)
I
D3
= (k
p
/2)(W/L)
3
(V
SG3
+ V
TP
)
2
150 = (40/2)(50)(V
SG3
0.4)
2
V
SG3
= 0.7873 V
R
D1
= V
SG3
/ I
D1
= V
SG3
/ (I
Q
/2)
= 0.7873 / (200/2)
= 7.87 k
33
12.1) MC14573 CMOS OpAmp Circuit (Cont)
Problem 13.29 (Cont)
(i)
I
D4
= (k
n
/2)(W/L)
4
(V
GS4
 V
TN
)
2
200 = (100/2)(40)(V
GS4
0.4)
2
V
GS4
= 0.7162 V
V
G4
= V
O
+ V
GS4
= 0 + 0.7162 = 0.7162 V
R
D2
= (V
G4
 (V

)) / I
D3
= (0.7162 (3))/(150) = 24.8 k
R
S
= (V
O
 (V

)) / I
D4
= (0 (3))/(200) = 15 k
34
12.1) MC14573 CMOS OpAmp Circuit (Cont)
Problem 13.29 (Cont)
(ii)
A
d1
= (g
m1
R
D1
)/2
g
m1
= 2 SQRT[(k
n
/2)(W/L)
1
(I
Q
/2)]
= 2 SQRT[(100/2)(20)( 200/2)]
= 0.6325 mA/V
A
d1
= ((0.6325m)(7.87k))/2 = 2.49
A
2
= 19.21 (given)
A
3
= 1 (assume)
A = A
d1
x A
2
x A
3
= (2.49) x (19.21) x (1) = 47.8