# Worcester Polytechnic Institute

Electrical and Computer Engineering Department

EE3801 – Lab 2 (4-bit ALU)

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Make sure everyone also has the components available individually from previous labs. 2 . It is a good idea to backup your data on another media apart from the network space you have available.Please have all individual components created in this lab available to all parties working together to complete the lab.

AND. Big Picture Arithmetic Logic Unit (ALU) is an important part of every computer and calculator. D river clk O P (2:0) X(3:0): The first 4-bit operand Y(3:0): The second 4-bit operand OP(2:0): Three bits of control input which identifies the operation to be performed. and XOR operations. The ALU has the following structure. You will design a four bit ALU which can performs: Addition. Subtraction. As an 3 . If the signed input signal is high and the result of the operation is a negative number.Objective In this lab you will design a 4-bit ALU. OR. however sometimes it is convenient to see the final result of an operation as a signed number on the display. otherwise the unchanged result appears on the display. Table 1 defines the existing opcodes. the display unit shows the appropriate negative result. hierarchical structures to design a relatively complex digital system. In this process you will learn how to use MSI circuits. one of several arithmetic or logical operations is performed on the input operands. An ALU usually have two input operands for data and several inputs for control. and their associated operations. Your ALU must be able to display the result as a signed or unsigned number. X (3:0) Y (3:0) 4 4 3 signed Figure 1 5 4-bit A LU overflow S igned S even S eg. Depending upon the value of the control inputs. Signed: All the operations in your ALU is performed on a two’s complement bases. Usually we refer to that as opcodes.

As an example.N = (2n . i. to represent the number -6. over. Also.1 .e. When doing arithmetic. The two’s complement of an n-bit number N is defined as. negative numbers are represented in two’s complement. +5 +4 +9 0 1 0 + 0 0 1 0 1 1 0 0 0 1 0 0 0 1 (=carry Ci) = -7! also. we take two’s complement of 6 (0110) as follows. For a 4-bit number this means that the number is in the range -8 to +7. As is commonly done in digital systems.N) + 1 The last representation gives us an easy way to find two’s complement: take the bit wise complement of the number and add 1 to it. This has a number of advantages over the sign and magnitude representation such as easy addition or subtraction of mixed positive and negative numbers. you need to decide how to represent negative numbers.and underflow as is illustrated in the example below. -7 -2 -9 1 0 1 + 1 1 0 0 0 1 1 0 0 1 1 0 1 1 (=carry Ci) = +7! 5 . There is a potential problem we still need to be aware of when working with two's complement.Figure 2 Adder Unit There are five operations in your design which can be implemented with a four bit adder. 6 0 1 1 0 --> 1 0 0 1 + 1 1 0 1 0 (bit wise complement) (two’s complement) Numbers represented in two’s complement lie within the range: -(2n-1) to (2n-1 -1). 2n . the number zero has a unique representation in two’s complement.

Create a new schematic file to your project and name it consts. first it will reduce the amount of wiring in your design. Verify your design. you only need to modify a single component not the whole system. and save it. 13. 19. Figure 5 Signed Numbers In this part you will design a circuit capable of representing a number as signed or unsigned. Design a circuit for this component. Create a symbol for this component and name it consts. It will be more convenient if you design a component which provides these signals. and secondly if you decide to change the values of these constants in your design. 12. Figure 5 shows the symbol for this component. Create a test bench waveform to verify the behavior of system. 14. Make sure that your design works properly. Figure 6 shows the symbol for this design. 16.11. 7 . Check your schematic and save the file. Figure 4 Constant signals There are times when you want to apply a register level signal with a constant value (in this design 0 and 1) in your design. 15. Design a circuit which provides this function. Create a symbol for this component and name it inv4ctrl. and Table 2 shows the function of this component. There are two outputs in this system (ones = 1111. zeros = 0000). 17. This approach has two benefits. 18.

22. which represent whether you want to consider X and Y inputs as signed number or not. two single bit inputs (sign_x. 21. a clk and Reset. and Y(3:0)). 8 .Figure 6 signed 0 1 1 A(3:0) A3A2A1A0 A3A2A1A0 A3A2A1A0 A3 X 0 1 Q(3:0) A3A2A1A0 A3A2A1A0 Two’s complement of A3A2A1A0 Table 2 sign 0 0 1 20. Your design will have two 4-bit inputs (X(3:0). Seven Segment Display for Signed Numbers You have designed a seven segment driver unit in your first lab which is capable of displaying four hexadecimal numbers simultaneously on the Spartan3 board. 24. and sign_y). Create a test bench waveform to generate all the combinations of input and verify the outputs of your design. Now you will design a new component that displays two signed numbers on the seven segment displays. 23. Design a circuit which provides the function described in Table 2. Check your schematic and save your design. Create a symbol for your design and name it as signeddigit. The outputs of the system are the familiar signals that you have used to drive the seven segments as before. Create a new schematic file in your project and name it as signeddigit.

Your main task is to design the black box in a way to generate the appropriate controls for S1. and op0 representing the operation to be performed on the operands). (Control-path). Some notes about this template: • • • • • • There are two 4-bit inputs (A(3:0). and Cin signals. and B(3:0) representing two operands) on the data path. Using the two multiplexers you can decide which operand should go through the inversion and which should not. S2. the first five instructions of your ALU can be accomplished using an adder with some control logic.Figure 8 Adder Revisited As mentioned before. In fact 10 . Create this decode in VHDL. Create this black box in VHDL. The three-to-eight decoder activates one of its outputs based on the selected operation. op1. Here we have provided a template for your design that you can use (Figure 9). If you are using multiplexers with enable inputs pass them as an additional input of the component. Ctrl. There are three single bit inputs (op2.