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AIN SHAMS UNIVERSITY

FACULTY OF ENGINEERING
Electronics and Communications Engineering Department
Low Phase Noise VCO Design
A Thesis

Submitted in partial fulfillment for the requirements of Master of Science
degree in Electrical Engineering

Submitted by:

Ahmed Kamal Abd Elhamid Mahmoud
B.Sc. of Electrical Engineering
(Electronics and Communications Engineering)
Ain Shams University, 1996.

Supervised by:

Prof. Dr. Hani Fikry Ragaie
Dr. Khaled Sharaf
Cairo-2003
STATEMENT

This dissertation is submitted to Ain Shams University for the degree of
Master of Science in Electrical Engineering, Electronics and
Communications Engineering.

The work in this thesis was carried out by the author at the Electronics and
Communications Engineering Department, Faculty of Engineering, Ain
Shams University.

No part of this thesis was submitted for a degree or a qualification at any
other university or institution.

Date :
Signature :
Name : Ahmed Kamal Abd Elhamid.

Acknowledgment
I would like first to thank my supervisors, prof. Hany Fikry Ragai and Dr.
Khaled Sharaf for their very helpful technical support.
I would like also to thank Mentor Graphics Corporation for support by tools
and time and I thank specially Dr. Mohamed Tawfik, Egypt Mentor
Consulting Manager for his technical and time support. I would like also to
thank Mohamed Hassan from Device Modeling team in Mentor Graphics
who helped me in the circuit functionality verification.


2
M.Sc. Thesis

Name : Ahmed Kamal Abd Elhamid.
Thesis Title : Low Phase Noise VCO Design.
Degree Title : Masters of Science.
Department : Electronics & Communications Department- Ain Shams
University.


Referee Committee
Name and Position

• Prof Dr. AbdelHalim Mahmoud Shousha
Electronics & Communications Dept.
Cairo University.

• Prof Dr. Abdel Halim Zekry
Electronics & Communications Dept.
Ain Shams University.

• Prof Dr. Hani Fikry Ragaie
Electronics & Communications Dept.
Ain Shams University.

• Dr. Khaled Sharaf
Electronics & Communications Dept.
Ain Shams University.
3
ABSTRACT

The oscillator phase noise is one of the most difficult issues in the design of
modern RF telecommunication systems. One of the most problematic issues
in the low phase noise oscillator design is the upconversion of the low
frequency noise (flicker noise) from the baseband to the oscillation
frequency. The severity of the flicker noise is coming from its large
amplitude compared of other types of noise.
A new LC voltage-controlled oscillator circuit topology is proposed, in
which the phase noise generated by the tail transistor is noticeably reduced
by utilizing the phenomenon of flicker noise intrinsic reduction due to
switched biasing. A macro model of MOSFET under switched biasing is
used to prove the phase noise improvement in the new technique. Circuit
simulations were done on two oscillators with the same tail current value;
one with fixed biasing and the other with the proposed switching.
About 4.5 dB phase noise improvement is achieved at 1kHz frequency offset
in the switched biasing scheme with the same oscillation frequency and
tuning range.



4
SUMMARY

RF VOLTAGE-CONTROLLED oscillators (VCOs) are a vital part of the
RF transceivers, phase-locked loops, clock recovery circuits and frequency
synthesizers and are an important integral part of phase-locked loops, clock
recovery circuits, and frequency synthesizers. The timing accuracy of the
clock recovery circuits and the signal-to-noise ratio where frequency
translation is performed are affected dramatically by the oscillator phase
noise. In particular, it is a must for the RF oscillators employed in wireless
transceivers to be very low phase noise, mandating special attention and
effort in reducing the phase noise.

In the last decade a great effort was paid to the phase noise nature and
modeling. This because the general convince that when designer understand
the nature and the sources of the phase noise, he will be able to avoid it. The
Linear time invariant theory is the theory that most designers rely on in the
past. But it was in need of a lot of modifications and empirical data to be
valid (Leeson’s model). After that the linear time variant model has been
proposed in the research area. It succeeded to explain the behavior of the
phase noise including the cyclostationary behavior of the noise sources in
qualitative and quantitative approaches.
Applying these different theories, lot of researchers was able to minimize the
oscillator phase noise through either inventing new architectures or
optimization of the current architectures. One can say that great efforts were
5
done in the last decade to reduce the oscillator phase noise. These efforts
were in both the architecture-based work and the optimization-based work.
A remaining problem that has not been solved with satisfactory solutions is
the flicker noise upconversion to the oscillation frequency.
Although a great effort was done in the field of Flicker noise modeling, there
is still some lack in the large signal and RF flicker noise issues. One of these
effects is the flicker noise modeling under switched biasing.
This work has proposed a new oscillator circuit that overcomes the problem
of flicker noise upconversion from the tail current source baseband noise to
the oscillation frequency.










6
List of Symbols

µ Carrier mobility (cm
2
/V.s)
W MOS transistor width (µm)
L MOS transistor length (µm)
C
OX
Capacitance of oxide per unit area (F/µm
2
)
ε
o
Permitivity of oxide (F/µm)
N
A
Doping concentration of acceptors (1/µm
3
)
d
OX
Oxide thickness in a MOS (µm)
V
TH
Threshold voltage of a MOS (V)
φ
F
Work function between fermi level and the intrinsic Fermi level
n
i
Intrinsic doping concentration (1/µm
3
)
k Boltzmann constant
g
DS
Conductance between drain to source (mho)
AF Flicker noise exponent
EF Flicker noise frequency exponent
KF Flicker noise coefficient
Q Quality factor
f
o
Oscillator carrier frequency (Hz)
g
m
Trans-conductance of the amplifier (mho)
i
n
noise current
L(∆ω) Phase noise value at frequency offset ∆ω from the carrier
Γ(x)

Impulse sensitivity function (ISF)
α(x) The noise modulation function (NMF)
7
List of Figures
Figure page number

Fig. 1.1 The ideal and non-ideal oscillator harmonic 13
Fig. 1.2 The random fluctuations in real oscillator periodic time 14
Fig. 1.3 A typical Heterodyne transceiver 15
Fig. 1.4 The bad effect of phase noise in presence of adjacent strong channel
15
Fig. 1.5 Typical plot of phase noise versus frequency offset 17
Fig. 1.6 An ideal impulse parallel to ideal tank 18
Fig. 1.7 Injected impulse impact at different instances 19
Fig. 1.8 The impulse sensitivity function of a sine wave 20
Fig. 1.9 Phase impulse response of the oscillator system 21
Fig. 1.10 Output voltage relationship with injected current 22
Fig. 1.11 Equivalent system of current voltage transformation 22
Fig. 1.12 Thermal and flicker noise contribution 23
Fig. 1.13 Colpitts Oscillator 26
Fig. 1.14 (a) Output voltage (b) Collector current (c) bipolar shot noise in
Colpitts oscillator 27
Fig. 2.1 The tradeoff between power saving, tuning range and phase stability
of the oscillator under the same architecture 31
Fig. 2.2 Innovation in architecture can increase all tradeoffs together 32
Fig. 2.3 The voltage-biased negative resistance oscillator 33
Fig. 2.4.The current-biased negative resistance oscillator 34
Fig. 2.5 The oscillator with filtering capacitor 35
Fig. 2.6 The same oscillator with added inductor 36
Fig. 2.7 Adding off-chip inductor and capacitor 37
Fig. 2.8 Complementary versus only-NMOS structures comparison 38
Fig. 2.9 (a) The equivalent circuit of the VCO in Fig. 2.8-b (b) The bias
current I(t) versus time 39
Fig. 2.10 The dominant noise sources in oscillator 41
Fig. 2.11 (a) Simplified model for transistor noise sources (b) Differential
equivalent circuit 42
Fig. 2.12 The tail current noise transportation 43
Fig. 2.13 Three-dimensional diagram for the on-chip square inductor type
44
Fig. 2.14 The relationship between
2 2
L
g L
and L 51
8
Fig. 3.1 Drain current noise spectral density of an n-channel MOSFET
53
Fig. 3.2 Gate oxide thickness dependence of flicker noise in n-channel
MOSFETs with 0. 15µm and 0.2µm gate channel lengths 59
Fig. 3.3 Gate length dependence of flicker noise in n-channel MOSFETs
with various gate oxide thickness 60

Fig. 3.4 Noise reduction as a function of the "off' voltage for an nMOS,
V
GS_ON
=2.5V, V
th
, =1.9 V, f
SWITCH
=10 kHz, duty cycle =50% 61
Fig. 3.5 Two transistors (a) with fixed bias and the (b) with switched bias
62
Fig. 3.6 Noise reduction while switching at different frequencies for an
nMOS, V
GS
=2.5 V, V
GS.off
=0 V, duty cycle =50%. Also shown is the
noise floor under the same conditions 63
Fig. 4.1. N-type negative differential resistance VCO 65
Fig. 4.2. Complementary negative differential resistance VCO 66
Fig. 4.3. An oscillator with reduced tail current flicker noise effect due to
filtering 67
Fig. 4.2 The proposed macro-model schematic 69
Fig. 4.3 Comparison of fixed bias case (curve a), switched case with
classical model (curve b) and switched case with new macro-model (curves
c, d and e) 70
Fig. 4.4 Proposed complementary biased architecture 71
Fig. 4.5 The practical implementation of the proposed complementary
biasing (VCO-I) 72
Fig. 4.6 Tail current transistors gate voltages 73
Fig. 4.7 Proposed circuit layout 74
Fig. 4.8 Reference architecture (VCO-II) 75
Fig. 4.9 Waveform comparison of switched and fixed bias schemes 76
Fig. 4.10 Tuning behavior of both oscillators 77
Fig. 4.11 Phase noise comparison at 1kHz offset of three cases 78
Fig. B.1 An ideal LC oscillator, with the maximum voltage amplitude of V0
124



9
Table of Contents
Chapter 1......................................................................................12
Phase Noise Models...................................................................12
1.1 Introduction. 12
1.2 Phase Noise Description 12
1.3 Bad Effect of the phase noise: timing jitter 15
1.4 Linear Time Invariant (LTI) Model 16
1.5 Linear Time Variant (LTV) theory [3] 18
Chapter 2......................................................................................31
Low Phase Noise Design Techniques in LC
VCOs..........................................................................................31
2.1 Introduction 31
2.2 Architecture Based Improvements 33
2.3 Optimization-based phase noise improvement 39
Chapter 3......................................................................................52
Flicker Noise Modeling of MOSFET.....................................52
3.1 Introduction..........................................................................................................52
3.2 The Physical Mechanisms of Flicker Noise. 53
3.3 Flicker Noise existing Models. ............................................................................56
3.4 Future Work in Flicker Noise Modeling. 58
3.5 Flicker Noise Modeling of MOSFET under Switching Biasing 61
Chapter 4......................................................................................64
A New Circuit to Reduce Flicker Noise Effect in VCOs....64
4.1 Introduction. 64
4.2 A new macro-model for transistor noise under switched biasing.........................67
4.3 Complementary Biasing Technique 70
4.4 Design Considerations 72
4.5 Switched biasing versus constant biasing; a comparison 75
Conclusion and Future Work...................................................79
APPENDIX A: Test Benches and Macro-models.................80
A.1 Main test bench: 80
A.2 Simulation models: 86
APPENDIX B: Calculation of ISF for Ideal LC Oscillator.
......................................................................................................124




10

Introduction
During the last five decades, there has been tremendous growth in wireless
mobile systems [2]. The implementation of these systems has been made
feasible by scientific and technological advances in the field of integrated
circuits (ICs) [2], allowing a high level of integration at low cost because of
low power dissipation and small integration area. This resulted in a new
oscillator design challenge due to the known tradeoff between the oscillator
power saving and its phase stability [8].

On the other hand, there is a great value for the efficiency of using the
frequency spectrum in wireless communication. One of the most important
factors that affect the efficiency of utilizing the frequency spectrum is the
local oscillators characteristic. This is because local oscillators are used
heavily in both transmitters and receivers. And because of dependence of
signal upconversion and downconversion quality on the local oscillator
timing accuracy, the most important characteristic of the oscillator is the
phase noise. Phase noise dramatically worsens the RF transceivers
performance. For that reason, a deeper understanding of the fundamental
issues limiting the oscillator timing accuracy, and development of design
guidelines to improve it, are necessary.
High speed digital applications performance is also badly impacted by the
oscillator phase noise. The maximum clock rate and hence the maximum
number of operations per unit time is determined by the timing accuracy of
the clock signal [2]. In the huge synchronous digital system such as
microprocessors, the clock is generated through a phase locked loop (PLL).
I ntroduction
11
This PLL synchronizes the clock to a very accurate external oscillator. The
timing accuracy of the oscillator as a vital part of the PLL impacts the total
timing accuracy.
The known design techniques used for LC oscillator phase noise reduction
are studied in this work and a new oscillator circuit that has low tail current
flicker noise is suggested reducing the total oscillator phase noise.

In Chapter 1, the different basic theories that try to explain the nature and
sources of the phase noise are presented. A special care is given to the linear
time variant model presented in [5].

In Chapter 2, different efforts and design techniques to enhance the phase
noise are shown. The design techniques are divided in this chapter into two
parts. The first is the architecture based design techniques and the other is
optimization based design techniques. In the first part, various architectures
built to improve the phase noise are presented and the short comings of some
of them are shown. In the second part, the methodology of how to enhance
the phase noise given a certain pre-determined architecture is presented.

In Chapter 3, a special care is given to the flicker noise modeling, as it is one
the hardest obstacles in the way of phase noise improvement. The shortage
in the present MOSFET devices models regarding the physical phenomenon
used in the new oscillator circuit is shown.

In Chapter 4, a new LC voltage controlled oscillator is proposed utilizing a
newly discovered physical phenomenon in which the MOSFET flicker noise
is reduced substantially by switched biasing. A new macro model is built to
I ntroduction
12
overcome the current shortage in MOSFET flicker noise. This macro model
has helped in illustrating how this reduction in flicker noise due to switching
can reduce the total phase noise of the oscillator.
The spurious signals emerged due to switching are easily overcome by
making the switching frequency much larger than the oscillator tank
bandwidth. Finally, the thesis ends by drawing conclusions and suggesting
possible directions for future work.

Chapter1: Phase Noise Models
12
Chapter 1

Phase Noise Models.

1.1 Introduction.

As all types of electronic circuits, the oscillator is greatly affected by both
noise and interferer sources. Thermal, shot and flicker noise of the different
devices are examples for the former sources, while supply and substrate
noise are examples for the latter sources. Those sources affect both
amplitude and phase of the real oscillator, but due to the amplitude limitation
mechanisms in practical oscillators the amplitude noise is suppressed such
that the dominant noise is the phase noise [4].

1.2 Phase Noise Description

1.2.1 Frequency Domain.

The ideal oscillator output oscillating by frequency ω
o
is perfect periodic
time function
( )
o o out
t f V ψ ω + = ; ( ) ( )
o o o o
T t f t f ψ ω ψ ω + + = + ) ( and T =periodic time (1-1)
Chapter1: Phase Noise Models
13
accordingly, the Fourier expansion of such function is a series of Dirac
Deltas at nω
o
since the general expression of ideal periodic waveform is
1
( . [ ] . [ ])
2
o
out n n
o o
a
V a Cos n t b Sinn t
ω ω

= + +


(1-2)

Both the amplitude and frequency of the ideal oscillator are constant, while
the real oscillator amplitude and frequency have statistical nature around
certain average. The non-ideal waveform can be expressed as:
)] ( [ )]. ( 1 .[ t t f t A V Vout
o
o
ψ
ω
+ + = (1-3)
So the difference between the ideal oscillator harmonics and real oscillator
harmonics is shown in Fig. 1.1.


Fig. 1.1 The ideal and non-ideal oscillator harmonic [3]

The fluctuations in both amplitude and frequency generate the sidebands
shown in the figure. These sidebands are expressing the phase noise
sidebands to a far extent[1]. To be accurate, the phase noise is expressed
only by the sidebands resulted from the phase perturbation frequency
modulation as shown in [4]. To quantify the phase noise, we consider a unit
Chapter1: Phase Noise Models
14
bandwidth at an offset ω ∆ from the carrier, calculate the noise power in this
bandwidth, and divide the result by the carrier power, so phase noise can be
written as shown in [1] as:






= ∆
power Carrier
bandwidth Hz in Power
L
_
_ 1 _ _
log . 10 } { ω (1-4)
1.2.2 Time Domain
The equivalent picture of the phase noise in the time domain is known as
Timing J itter . In the ideal oscillator, the periodic time is constant with time,
while the real oscillator periodic time has random fluctuations shown in Fig.
(1.2).The above sine wave is an ideal one and the bottom sine wave is the
actual waveform.

Fig. 1.2 The random fluctuations in real oscillator periodic time [3]

Defining the waveform phase as φ(t), then the cycle to cycle phase noise is
proportional to its statistical variance E[φ(t)] [3].
Chapter1: Phase Noise Models
15
1.3 Bad Effect of the phase noise: timing jitter
There is a lot of harm that phase noise can cause to different applications.
One of the most important applications that are badly affected by the phase
noise is the heterodyne transceiver Fig. 1.3.

Fig. 1.3 A typical Heterodyne transceiver [1]

Fig. 1.4 demonstrates the bad effect of the noisy local oscillator in the
mentioned transceiver.

Fig. 1.4 The bad effect of phase noise in presence of adjacent strong channel
[1]

Chapter1: Phase Noise Models
16
If strong channel is located near the desired channel, the local oscillator will
transfer both of them in frequency domain. The transferred channels will be
affected by the oscillator noise, hence the noise level of the transferred
adjacent channel may be comparable with the level of the desired channel
resulting in very boor signal to noise ratio [1].
On the other side the timing jitter can badly affect the data handling in the
digital circuits and sampling levels accuracy in the sample and hold circuits.

1.4 Linear Time Invariant (LTI) Model
The linear time invariant model of phase noise in oscillators is widely
known as Leeson model and is the most well-known model. The phase noise
according to this model can be written as:
3
2
1
2
{ } 10.log . 1 . 1
2
o
s
L
FkT f
L
Q
P
ω
ω ω
ω
ω
1 | |
1
| |
1 |
1
|
∆ = + + 1 |
1
| ∆ ∆
1 |
\ ¹ | 1
¸ ]
1
\ ¹
¸ ]
(1-5)
Where F is the oscillator excess noise factor [4]. This number is obtained
empirically, k is Boltzmann’s constant, T is the absolute temperature, P
s
is
the tank average power dissipation, and QL is the loaded quality factor of
the tank. Fig. 1.5 is a plot of eqn.(1-4).
Chapter1: Phase Noise Models
17

Fig. 1.5 Typical plot of phase noise versus frequency offset [5]

This graph can be divided to three regions, Region I which is low frequency
offsets region, in which the phase noise slope is -30dB/decade,
-20dB/decade of them is due to noise filtering by the tank and the other
-10dB/decade is due to the upconversion of low frequency noise to the
oscillation frequency. Region II in which the phase noise slope is just
-20dB/decade due to the tank circuit noise filtering, and region III that has
flat noise level. This flattening can be a result of buffer noise, test
instrumentation noise or series resistances of both inductor and capacitor
that put a limit of tank circuit noise filtering [4].
1.4.1 LTI Model Limitations
Although the Leeson’s model is directly deduced from experimentation, the
existence of parameter F has led to a serious problem. There is no precise
picture on how F depends on the circuit parameters. One of the most
deceiving results from this model is that the blind application of it leads to
using additional circuits to boost Q of the tank to reduce the phase noise, but
Chapter1: Phase Noise Models
18
sadly, adding these circuits raises the value of F, wasting the phase noise
reduction by Q boosting [4].
1.5 Linear Time Variant (LTV) theory [3]
One of the most important steps in the phase noise-modeling trip is the
theory introduced by Thomas Lee and Ali Hajimiri [4], [5]. This new theory
has introduced a robust quantitative model for the phase noise based on new
linear time-variant model to build the relationship between noise and phase
perturbation. There is an important point here that although the oscillator is
mainly non-linear circuit, the relationship between the noise and the
corresponding zero-crossing deviations can be considered linear to a far
extent[5].
1.5.1 Tank voltage Phase change with parallel current Impulse
Assume we have an ideal tank circuit in parallel with an impulse current
source Fig. 1.6. The current impulse is located at time τ and has charge ∆q.

Fig. 1.6 An ideal impulse parallel to ideal tank [5]

As the current impulse spectrum is white, the energy of the pulse will be
absorbed almost completely by the capacitor resulting in abrupt change in
tank voltage expressed by:
total
C
q
V

= ∆ (1-6)
This abrupt change is illustrated in Fig. 1.7. Top part shows the impulse
effect on the phase when injected at the sine wave peak, it causes no phase
Chapter1: Phase Noise Models
19
difference from the reference sine wave. Down part shows the impulse effect
on the phase when injected at the zero crossings, it causes maximum phase
difference from the reference sine wave.

Fig. 1.7 Injected impulse impact at different instances [5]

It is clear that the waveform is sensitive to current impulse at zero crossings
much more than at peaks, so the sensitivity is dependent on the instance of
injection with respect to the zero crossings. Based on that notice an impulse
sensitivity function (ISF) can be defined as Γ(ω
o
τ), this function is periodic
function with the same period of the original waveform and dependent on
the time of impulse injection (τ) Fig. 1.8.
Chapter1: Phase Noise Models
20

Fig. 1.8 The impulse sensitivity function of a sine wave [5]

An important approximation can be applied here for the small values of ∆q
is that:
max
V
V ∆
∝ ∆φ (1-7)
For a certain time instance τ. To apply (1-6) on all time instances we have to
utilize the ISF resulting in:
) ( .. ). ( ). (
max max
τ τ ω τ ω φ −

Γ =

Γ = ∆ t u
q
q
V
V
o o
(1-8)
Where
total
C V q .
max max
=
(1-9)

The unity step function u (t-τ) is multiplied here because the effect of the
impulse does not occur before the instant τ.
Chapter1: Phase Noise Models
21
1.5.2 Phase Impulse Response
According to the previous analysis, since it was proved that the relationship
between ∆q and ∆φ is linear time-variant, and substituting in (1-8) by ∆q=1,
the oscillator system can be expressed as its impulse response h
φ
(t,τ).
) ( .
) (
) , (
max
τ
τ ω
τ
φ

Γ
= t u
q
t h
o
(1-10)
Fig. 1.9 illustrates this meaning clearly.

Fig. 1.9 Phase impulse response of the oscillator system [6]

1.5.3 Phase Response for an arbitrary current source
According to the linearity, the superposition principle can be applied to
obtain the phase response to an arbitrary current source i(t) using eqn (1-10)
we obtain:
τ τ
τ ω
τ τ τ φ
φ
d i
q
d i t h t
t
o
). ( .
) (
). ( ). , ( ) (
max
∫ ∫
∞ −

∞ −
Γ
= = (1-11)
1.5.4 Oscillator Output Response for an arbitrary current source
The relationship between current and phase is mainly linear time-variant as
seen in (1-8), while the output voltage relationship with the excess phase φ(t)
is non-linear relationship expressed as:
)] ( cos[ ) ( t t t V
o
φ ω + = (1-12)
The complete process is shown by Fig. 1.10

Chapter1: Phase Noise Models
22

Fig. 1.10 Output voltage relationship with injected current [6]

To have more insight in such process Γ(ω
o
τ) is analyzed to its Fourier
components:



+ + = Γ
1
) . cos( .
2
) (
o o n
o
o
n c
c
θ τ ω τ ω (1-13)
Substituting in (1-11):






+ =



∞ −

∞ −
t t
o n
o
d n i c d i
c
q
t
1 max
) cos( ) ( ) (
2
1
) ( τ τ ω τ τ τ φ (1-14)
Combining (1-13) with information in Fig. 1.10 we can obtain Fig. 1.11,
which is another version of Fig. 1.10 in which the effect of each Γ(ω
o
τ)
harmonic in the total transformation process appears.

Fig. 1.11 Equivalent system of current voltage transformation
Chapter1: Phase Noise Models
23
1.5.5 Single tone current injection
It can be shown according to (1-14) that injecting a single tone sine wave
current ( ) [ ] t n I t i
o n
ω ω ∆ + = cos ) ( into the ideal tank output node at offset ∆ω
from oscillation frequency multiples nω
o
creates time varying φ(t) given by:
ω
ω
φ


=
max
2
) sin(
) (
q
t c I
t
n n
(1-15)
Substituting eqn. (1-15) into (1-12) assuming that ) (t φ <<1, the sidebands
power relative to carrier power is:
ω ω
ω
2 2
max
2 2
2
max
16
2
4
) (

=









= ∆
q
c I
q
c I
P
n n
n n
dBc
RMS
(1-16)
1.5.6 Phase noise due to thermal and flicker noise
According to the last section, the noise sources beside nω
o
are the main
contributor in the oscillator phase noise. Two types of noise build the phase
noise sidebands, thermal noise and 1/f flicker noise. Thermal noise around
all nω
o
frequencies affect phase noise, while only low frequency flicker
noise affect phase noise. Fig. 1.12 illustrates this contribution of both
thermal and flicker noise in oscillator phase noise.

Fig. 1.12 Thermal and flicker noise contribution [5]
Chapter1: Phase Noise Models
24
To calculate the noise contribution we have to divide the problem into two
parts thermal noise contribution and flicker noise contribution.
The expressions of device thermal and flicker noise are given respectively
by equations (1-15) and (1-16).


K
f
i thermal n
=


2
_
(1-17)

ω
ω
f flic n
K
f
i
/ 1
2
ker _
=


(1-18)
where K is independent on frequency and ω
1/f
is the flicker noise corner (the
frequency at which the device flicker noise equals device thermal noise).
In the following two sections a detailed description of how both thermal and
flicker noise contribute in the oscillator phase noise is presented.

I -Thermal noise contribution
To calculate the effect of 1Hz bandwidth of thermal noise at offset ∆ω from
the n
th
harmonic nω
o
, Equation (1-17) is substituted in equation (1-16), we
have:
ω
ω
2 2
max
2
_ _ _
8
) (

= ∆
q
Kc
P
n
harmonic n thermal dBc
(1-19)
Summing all contributions from all harmonics:


ω
ω
2 2
max
0
2
_
8
) (

= ∆


q
c K
P
n
thermal dBc
(1-20)
Chapter1: Phase Noise Models
25
Using Parseval’s relation:
2 2
2
RMS
o
n
c Γ =


(1-21)
}
4
.
log{ . 10 ) (
2 2
max
2
_
ω
ω

Γ
= ∆
q
K
P
RMS
thermal dBc
(1-22)
I I -Flicker noise contribution
To calculate the effect of 1Hz bandwidth of flicker noise at frequency ∆ω
o
,
Equation (1-18) is substituted in equation (1-16), we have:
}
8
log{ . 10 ) (
2 2
max
2
/ 1
ker ; _
ω
ω
ω
ω


= ∆
q
c K
P
o
f
ic f dBc
(1-23)
Now
3
/ 1 f
ω can be calculated as the frequency offset at which phase noise due
to flicker noise equals phase noise due to thermal noise. Equating (1-22) and
(1-23) we get:
2
/ 1
2
/ 1
2
3
RMS
f o
f
c
Γ
= ∆
ω
ω (1-24)
This equation is one of the most important keys in the VCO design, because
it tells that it is possible to eliminate the flicker noise effect through making
c
o
=0. This can be made simply by keeping the oscillator waveform
symmetric as possible as we can. This is because when the oscillator
waveforms are symmetric the ISF waveform is symmetric w.r.t. zero
accordingly. This leads to having c
o
=0.
I I I -Total phase noise
From (1-22) and (1-23) we have:








+










+

Γ
= ∆ floor noise
q
K
L
f
RMS
... 1 .
4
.
log 10 } {
3
/ 1
2 2
max
2
ω
ω
ω
ω (1-25)
Chapter1: Phase Noise Models
26
1.5.7 Cyclostationary Noise Sources
In practical oscillators, the statistical properties of some of the random noise
sources may change with time in a periodic manner. These sources are
referred to as cyclostationary. For instance, the channel noise of a MOS
transistor in an oscillator is cyclostationary because the gate-source
overdrive, which varies with time periodically, modulates the noise power.
There may be other noise sources in the circuit whose statistical properties
do not depend on time and the operating point of the circuit. And are
therefore called stationary. Thermal noise of a resistor is an example of a
stationary noise source.

Fig. 1.13 Colpitts Oscillator [3]

These concepts can be understood best in the context of an example.
Consider the Colpitts oscillator of Fig. 1.13. The simulated collector voltage
and current of the transistor are shown in Fig. 1.14 [2]. Note that the
collector current consists of a short period of large current followed a quiet
interval. The power of collector shot noise is proportional to the
instantaneous collector current of the transistor; therefore it has the
maximum power during the peak of collector current.



Chapter1: Phase Noise Models
27



Fig. 1.14 (a) Output voltage (b) Collector current (c) bipolar shot noise in
Colpitts oscillator [3]

Fig. 1.14c shows one sample of collector shot noise of the bipolar transistor.
A white Cyclostationary noise current i
n
(t) can always be decomposed as
) ( ). ( ) (
0 0
t t i t i
n n
ω α = (1-26)

Where ) (
0
t i
n
is a white stationary process and ) (
0
t ω α is a deterministic
periodic function describing the noise amplitude modulation and therefore is
referred to as the noise modulating function (NMF). The NMF ) (
0
t ω α is
normalized to a maximum value of 1. This way f i
n
∆ /
2
0
is equal to maximum
of the periodically varying noise power density f t i
n
∆ / ) (
2
. Applying (1-26) to
(1-11), ) (t φ may be rewritten as:
Chapter1: Phase Noise Models
28
∫ ∫
∞ − ∞ −
Γ
=
Γ
=
t
n
t
n
d
q
i d
q
i t τ
τ ω τ ω α
τ τ
τ ω
τ φ
max
0 0
0
max
0
) ( ). (
) (
) (
) ( ) ( (1-27)


As can be seen, Cyclostationary noise can be treated as a stationary noise
applied to a system with a new Impulse sensitivity function (ISF) given by


) ( ). ( ) ( x x x
NMF
α Γ = Γ (1-28)



, where ) (
0
τ ω α can be derived easily from device noise characteristics and
the noiseless steady–state waveform. There is a strong correlation between
the Cyclostationary noise source and the waveform of the oscillator. The
maximum of the noise power always recurs at a certain point of the
oscillatory waveform, thus the average of the noise may not be a good
representation of the noise power.

Also note that as the waveform deviates in time from the noiseless
waveform due to phase noise ) (
0
τ ω α shifts by exactly the same amount
because the oscillator voltages and currents modulate the noise sources.
Therefore, they will always have a constant phase relationship and (1-25)
will be valid at all times. The relative timing of the cyclostationary noise
sources with respect to the impulse sensitivity function can dramatically
change the effect of those noise sources.

Chapter1: Phase Noise Models
29
The Colpitts oscillator example is considered to provide some design insight
into the effect of cyclostationary noise sources .As a first example consider
the Colpitts oscillator of Fig. 1.13. As can be seen in Fig. 1.14, the surge of
collector current occurs at the minimum of the voltage across the tank,
where the ISF is small. The collector shot noise has its maximum power
when the collector current is maximal, as shown in Fig. 1.14. This fortunate
coincidence lowers the phase noise deterioration due to the bipolar transistor
shot noise, because the maximum noise power always coincides with the
minimum phase noise sensitivity.
Another example is the single ended ring oscillator example, which has the
opposite phenomenon. In ring oscillator the maximum of the ISF function is
at the time of the maximum noise power so the phase noise is deteriorated a
lot.












Chapter2 Low Phase Noise Design Techniques in LC VCOs
31
Chapter 2

Low Phase Noise Design Techniques in LC VCOs
2.1 Introduction
It is well known that there is a tradeoff between power saving, tuning range
and phase noise of the voltage controlled oscillators for the same technology
and architecture [7]. This is shown in Fig. 2.1. The gray plane represents
certain architecture under certain technology. The phase noise enhancement
task can be achieved through one of two ways. First is the optimization of
the circuit parameters under fixed architecture. Second, is playing with









Fig. 2.1 The tradeoff between power saving, tuning range and phase stability
of the oscillator under the same architecture
Chapter2 Low Phase Noise Design Techniques in LC VCOs
32

architecture innovation to reduce the phase noise. The first approach is in
fact to have the tuning range and power saving above certain values
(determined by the standards/applications) with minimizing the phase noise.
Optimization techniques through computer-aided methods such as
geometrical programming were successfully used [13] for that purpose. The
second way is through moving the tradeoff plane far from the origin as
shown in Fig. 2.2. This enables the designer to obtain improvement in tuning
range, phase stability and power consumption at the same time.










Fig. 2.2 Innovation in architecture can increase all tradeoffs together

Such kind of movement cannot be achieved without changing in the
oscillator architecture. It is shown in Fig. 2.1 that architecture A may have
better phase noise without badly impacting either tuning rage or power
dissipation.



Chapter2 Low Phase Noise Design Techniques in LC VCOs
33
2.2 Architecture Based Improvements
It has been shown in a lot of researches that phase noise can be improved by
changing the architecture itself. The N-type negative resistance LC
oscillators different architectures are taken here as an example of how
architecture can play a major role in phase noise enhancement.

2.2.1 Voltage-biased negative resistance oscillators
One of the simplest architectures of the negative resistance oscillators is
shown in Fig. 2.3. This architecture has some advantages and some
disadvantages.








Fig. 2.3 The voltage-biased negative resistance oscillator

The advantage of this oscillator is that having low transistor count realizing
potential decrease in phase noise. On other hand, the oscillation amplitude of
this oscillator depends on both voltage supply level and temperature because
the current passing the tank depends on supply voltage and switching
transistors impedance (which depend on temperature variation). Another
drawback is that the current passing to ground has all frequency components
including ω
o
component. This loads the tank with the switching transistors

Chapter2 Low Phase Noise Design Techniques in LC VCOs
34
while they are in triode regime, subsequently reducing the loaded quality
factor. This reduction increases the phase noise substantially.

2.2.2 Current-biased negative resistance oscillator
Adding a biasing current source to the oscillator shown in Fig. 2.3 realizes
number of benefits. First is making the oscillation amplitude nearly
independent of both voltage supply level and temperature. Second and more
important is that it prevents the switching transistors from loading the tank
while being in triode region. This keeps the quality factor of the tank from
reduction.








Fig. 2.4.The current-biased negative resistance oscillator

While this current bias scheme solves some problems it does create other
problems. The practical implementation of this current source is done by
noisy transistors. This leads to contribution of current source noise in
oscillator phase noise. The thermal noise of the tail current will be mixed
through M1 and M2 to reach the tank. According to LTV phase noise theory
introduced in [5], only the thermal noise beside the multiples of oscillation
frequency ω
o
will affect the tank phase noise. This effect will be weighted
Chapter2 Low Phase Noise Design Techniques in LC VCOs
35
by the ISF coefficients (c
0
, c
1
… c
n
…). On other hand low frequency noise
(mainly flicker noise) of the tail current also undergoes transfer to the tank.
There are two mechanisms of upconverting the flicker noise of the tail
current to tank nodes. The first is through conveying the noise power
directly to the oscillation frequency f
o
by the mixing effect made by
switching transistors M
1
and M
2
. The second mechanism is through
upconverting some of the flicker noise power to 2f
o
by channel length
modulation of the tail current transistor. Then, translating such upconverted
noise back to f
o
through mixing effect by the negative G
m
transistors M
1
and
M
2
.

2.2.3 Negative resistance oscillators with noise filtering techniques
It was shown that adding a large capacitor between the tail current drain and
ground (see Fig. 2.5) short-circuits the noise upconverted at 2ω
o
. This
protects the oscillator core from that part of tail current flicker noise.









Fig. 2.5 The oscillator with filtering capacitor [9]


Chapter2 Low Phase Noise Design Techniques in LC VCOs
36
It was shown in [11] that the major drawback of this capacitor is passing the
high frequency current (2ω
0
). This loads the tank (at ω
0
) by the –ve G
m

while they are in triode. This reduces the effective quality factor of the tank,
losing some of the current source benefits[11].
A modification of the circuit in Fig. 2.5 was made in [11] to overcome its
drawback as shown in Fig. 2.6.
The inductor L
f
is added here to resonate with the parasitic capacitance C
p
at
frequency 2ω
o
to solve the quality factor degradation by –ve G
m
transistors.
Actually there are two notes on this circuit. The first is that the noise

Fig. 2.6 The same oscillator with added inductor [11]

component that was suppressed is the upconverted part to 2ω
o
while there is
a part of noise left at low frequency. This part is still harmful to the circuit
since it is upconverted directly to ω
o
deteriorating the phase noise of the
oscillator. The second note is that the filter does not cover the whole tuning
Chapter2 Low Phase Noise Design Techniques in LC VCOs
37
range since this filter is fixed while the oscillator frequency is tuned. Hence,
the tank circuit immunity of quality factor degradation is not covering all the
tuning range.
A solution for the first note was introduced in [12] by adding off-chip
inductor and capacitor to eliminate most of low frequency noise component
as shown in Fig. 2.7.


Fig. 2.7 Adding off-chip inductor and capacitor [12]

The problem here is that the on-chip solution trend has been violated.
Another solution is suggested in [40] and is fully described in chapter 3.

Chapter2 Low Phase Noise Design Techniques in LC VCOs
38
2.2.4 Complementary NMOS and PMOS Structure
It was shown in [9] that the phase noise of complementary MOS structure
(see Fig. 2.8) shows a better phase noise about 6dB lower than the only-
NMOS architecture. This can be explained by two reasons. First is that the
oscillation amplitude can be approximated by (2/π)*I for architecture (a)
while (4/π)*I for architecture (b).


Fig. 2.8 Complementary versus only-NMOS structures comparison

This means that the oscillation amplitude can be doubled by using
complementary structure, under the same bias current I. Second reason
behind this improvement is that; with the complementary architecture, the
designer can obtain a better waveform symmetry. This symmetry leads to a
symmetry in the I SF as well, hence making c
0
= 0. The minimization of c
0

minimizes the upconverted low flicker noise. This minimization improves
the total oscillator phase noise [4].

Chapter2 Low Phase Noise Design Techniques in LC VCOs
39
2.3 Optimization-based phase noise improvement
Given certain architecture, optimization techniques should be followed to
get the minimum phase noise under certain power dissipation and tuning
range. To do this optimization process, two pieces of information are
required. The first is the noise sources in the circuit and the second is their
share in the total phase noise of the oscillator. The share of this noise sources
in the total oscillator phase noise is significantly affected by oscillation
amplitude.
2.3.1 Tank circuit amplitude calculation and its effect on VCO phase
noise
Tank voltage amplitude has an important effect on the phase noise [2], as
emphasized by the presence of q
max
in the (1-14). A simple expression for
the tank amplitude can be obtained by assuming that the differential stage
switches quickly from one side to another. For that, the differential pair
oscillator shown in Fig. (2.8-b) can be modeled as current source switching
between I
tail
and –I
tail
in parallel with an RLC tank, as shown in Fig. 2.9. R
eq

is the equivalent parallel resistance of the tank.


Fig. 2.9 (a) The equivalent circuit of the VCO in Fig. 2.8-b (b) The bias
current I(t) versus time [2]

Chapter2 Low Phase Noise Design Techniques in LC VCOs
40
At the frequency of resonance, the admittances of L and C cancel, leaving
R
eq
. Harmonics of I(t) is strongly attenuated by the LC tank. The only
component that remains un-attenuated is the fundamental component. The
waveform in Fig. 2.9 can be approximated as rectangular waveform. It can
be shown that the fundamental frequency current amplitude is given by the
equation:
tail
I fund I *
4
_ 





=
π
(2-1)


This fundamental component will be simply multiplied by R
eq
to give the
oscillation voltage amplitude:
q I osc V
tail
Re * *
4
_ 





=
π
(2-2)
At high frequencies, the current waveform may be approximated as
sinusoidal wave due to finite switching time and limited gain. In this case,
the tank amplitude may be approximated as:
q I osc V
tail
Re * *
4
_ 





=
π
(2-3)
This mode of operation is referred as current-limited regime of operation
since in this regime, the tank voltage amplitude is determined mainly by bias
current I and equivalent tank parallel resistance R
eq
.
Equations (2-2) and (2-3) are no longer valid when tank amplitude reaches
supply voltage since the –ve Gm transistors enter triode regime at the peaks
of the voltage. Also the tail NMOS transistor may spend most or even all its
time in the linear region. The tank voltage in this case will be clipped at
VDD by PMOS transistor and at Ground by NMOS transistors. The tail
Chapter2 Low Phase Noise Design Techniques in LC VCOs
41
NMOS transistor helps tank voltage to reach 0V since it will be at triode
region in that case [2].

2.3.2 Noise sources in negative resistance oscillator
As shown in Fig. 2.10 the major noise sources affecting the oscillator phase
noise are transistors noise.

Fig. 2.10 The dominant noise sources in oscillator [2]

The noise power densities of these noise sources are required to calculate the
phase noise. In general, these noise sources are cyclostationary because of
the periodic change in current and voltages of the active devices. A
simplified stationary model for the noise sources is discussed then the true
cyclostationary behavior is considered.
In a simplified stationary approach, the power densities of the noise sources
can be evaluated at most sensitive time (zero crossings of the differential
voltage waveform). To estimate the stationary effect of all sources except
the tail current noise source, Fig. 2.11 is a simple model for the tank circuit
exposed to the differential couple stationary noise sources.
Chapter2 Low Phase Noise Design Techniques in LC VCOs
42

Fig. 2.11 (a) Simplified model for transistor noise sources (b) Differential
equivalent circuit [2]

Fig. 2.11a shows a simplified model of the sources in this balance case.
Fig. 2.11b is the effective noise sources seen by the tank circuit. The total
differential noise power due to the four cross-coupled transistors is:








+ =








+ + + =
___
2
___
2
___
2
2
___
2
1
___
2
2
___
2
1
___
2
2
1
4
1
p n p p n n eq
i i i i i i i
Where (2-4)








= =








= =
___
2
2
___
2
1
___
2
___
2
2
___
2
1
___
2
p p p n n n
i i i and i i i
And the following expression is valid for both
___
2
n
i /∆f and
___
2
p
i /∆f thermal
noise components of both short-channel and long-channel approximation
[2]:
( )
___
2
/ 4
n GS T
ox
W
i f kT V V
L
c
γµ ∆ = − (2-5)
Where µ is the carrier mobility at the channel, C
ox
is the oxide capacitance
per unit area, W and L are the width and length of the transistor gate,
respectively, V
GS
is the dc gate source voltage difference and V
T
is the
transistor threshold voltage. Note that:
3 / 2 ≈ γ for long channel transistors
Chapter2 Low Phase Noise Design Techniques in LC VCOs
43
And 3 ~ 2 ≈ γ for short channel region
2.3.3 Tail current noise source
Tail current noise source impulse sensitivity function (ISF) can be shown [2]
to have 2ω
0
oscillation frequency. This is expected, since the tail current
drain is oscillation with this frequency. This is expected because the tail
node is pulled up every time each one of the differential NMOS transistors
turns on and thus the tail node moves at twice the frequency of the
differential voltage. Because of this frequency doubling, only the even ISF
Fourier coefficients (c
0
c
2
c
4 ………
) have a value. All the odd coefficients are
0. This makes the noise spectrum beside the odd harmonics has no effect on
the oscillator. The noise spectrum beside 2ω
0
, 4ω
0
….. has been removed by
filtering techniques introduced by [18] and [18]. But the solution introduced
to eliminate the low frequency noise in [10] has contradicted the on-chip
solution trend nowadays.

Fig. 2.12 The tail current noise transportation [1]

Chapter2 Low Phase Noise Design Techniques in LC VCOs
44
A new technique will be introduced in chapter 4 reducing the tail current
flicker noise without off-chip components.

2.3.4 High Q on-chip inductor design as a key factor of low phase noise
oscillator
It can be shown that the noise source associated with the inductor:
L Q
kT
f i
L
ω
4
/
___
2
= ∆ (2-6)
So, as one leverages the quality factor of the inductor, the associated noise
decreases for the same oscillation frequency and the same inductance value.
And it is well known that as Q increases the effective filter bandwidth
associated with the tank decreases. This filters the noise around the oscillator
carrier decreasing the phase noise.










Fig. 2.13 Three-dimensional diagram for the on-chip square inductor type



Chapter2 Low Phase Noise Design Techniques in LC VCOs
45
2.3.4.1 High Q inductor design tips
I -Circular geometry
When the inductor lay-out is done as circular as possible it gives good
results. That is because circular geometry has larger perimeter than other
geometries with the same radius. However, increasing the number of sides of
a spiral (Number of sides =∞ represents circular geometry) increases the
inductor resistance. But, the inductance increases also, because of the
increase in wire length. However, the Q rises because the inductance
increases faster than the resistance. Several simulations were carried out [19]
to verify this rule (Fig. 2.13) at 1.5 GHz with ASITIC [26], considering the
characteristics of a CMOS standard process. The Q is found to rise with the
number of sides.
I I - Multi-metal spiral inductors
Reducing the resistance per length can increase the inductor quality factor Q.
The task can be accomplished using a thicker track. In conventional CMOS
processes, inductor metal lines can be thickened by shunting metal layers.
As the number of layers shunted becomes higher, the inductor resistance
becomes smaller and the quality factor rises. The number of metal layers
used to make the spiral depends on the CMOS process. Some designers
recommend not using the closest metal layer to the substrate, due to the
increase of the parasitic capacitance to the substrate [27], which reduces the
inductor self-resonant frequency. For example, a spiral of value 3 nH
fabricated using the closest metal layer has a self-resonant frequency of 4.5
GHz [24].For designers working less than 2.4 GHz, it is recommended to
use the metal layer closest to the substrate, because resistance reduction is
more important than resonant frequency reduction [19].

Chapter2 Low Phase Noise Design Techniques in LC VCOs
46

I I I - Hollow coil
Due to the generation of eddy currents at high frequencies, the innermost
turns of the coil suffer from an enormously high resistance and their
contribution to the inductance value is minimal [19]. By including these
turns into the inductor layout, the overall Q is reduced. Therefore, it is
essential to use a hollow coil. A rough percentage of a good inner radius is
approximately equal to the 25 to 40 percent of the outer radius [19].


I V- Metal width and spacing
The spiral traces should be as wide as possible until the skin effect becomes
significant. The increase of the metal width results in a rise of Q because the
resistance of the inductor decreases and the inductance remains the same.
However, due to the skin effect, increasing the metal width much greater
than twice of the skin depth leads to no more decrease in the series
resistance. Thus the increase in metal width is just waste of area and
decreases the self-resonant frequency. The good inductor design fixes the
width between 9 to 14 µm, depending on the design criteria [21]. These
values have been adopted as one of the rules to avoid FEM simulation [21].
The spacing between the metal lines should be as small as possible (just if
this does not increase the inter-winding capacitance significantly).
Increasing the spacing decreases the total inductance because of the
decreasing mutual inductance. It also increases the series resistance and the
total area [21]. If the metal spacing is increased, having the same inductor
area, the Q will increase slightly and the inductance will decrease. Several
simulations were done in [21] to conclude the following rule of thumb; the
Chapter2 Low Phase Noise Design Techniques in LC VCOs
47
quality improves with a minimum spacing and a high width (8 to 12 µm)
[21].

V- Spiral radius
The spiral radius is a very complex parameter to select. As the radius
increases [21], so does the Q. This assumption is valid for small radius. For
values greater than 90 to 100 µm the losses induced by the eddy currents are
heavy, which degrade the quality factor. Another point should be taken into
account when selecting the spiral radius. As the radius increases, the metal
area shared between the spiral and the substrate grows and increases the
parasitic capacitance between the substrate and the spiral. This reduces the
self-resonant frequency of the spiral inductor. Therefore, the radius should
be selected so that the frequency of operation of the spiral is not close to the
resonance. A good design should have a radius under 100 µm [21]. Over 100
µm the parasitic capacitance between the spiral and the substrate and the
induced currents become very high, degrading the Q.

2.3.4.2 Simple Quick Design Rules

1- Do not over increase the line width.
a-This limits the inductance value, assuming constant inductor area.
b-Due to the skin effect, the center of the conductor will not be used.
2- Use the minimum spacing between the adjacent conductors.
a-To enlarge the value of L (increase the turns number without
increasing the inductor area).
b-To allow for largest center hole.
c-The inter-winding fringing capacitance will be negligible in most
cases.
Chapter2 Low Phase Noise Design Techniques in LC VCOs
48

3- Do not fill the inductor up to the center.
a-To avoid the reduction in quality factor due to the eddy currents
effect in inner turns.
b-To avoid the reduction in inductance value due to the reverse
magnetic field produced by eddy currents effect in inner turns.

4- Limit the inductor area.
a-To limit the substrate losses.
b-To Limit the decrease in the inductance value.

2.3.5 Low Phase-Noise Oscillator Design Strategy
It was shown in [14] that a robust design strategy can be followed for
negative resistance LC oscillator (Fig. 2.8b).
2.3.5.1 Design Constraints
Assume that the following constrains are imposed on the design:
1- Power dissipation:
The maximum power consumption constraint is expressed through the
maximum bias current, given certain supply voltage V
supply

max _ bias bias
I I ≤ (2-7)

2- Tank voltage amplitude:
The tank amplitude should be larger than a certain value. This value is
determined by the system specifications

min _ tan tan k k
V V ≥ (2-8)
And assuming that the oscillator in the current-limited regime, we have:
max _ tan
tan
k
bias
k
g
I
V = (2-9)

From (2-8) and (2-9) we have:
min _ tan
max _ tan
k
k
bias
V
g
I
≥ (2-10)
Chapter2 Low Phase Noise Design Techniques in LC VCOs
49

3- Frequency tuning range:
The oscillator is required to have certain tuning range determined by the
relationship:
max _ 0 0 min _ 0
ω ω ω ≤ ≤ (2-11)
Or
2
max _ 0
2
0
2
_ 0
1 1 1
ω ω ω
≥ ≥
mn
(2-12)
And we have:
k k
C L
tan tan
2
0
.
1
=
ω
(2-13)
Then we have the constraint:
2
max _ 0
tan tan
2
_ 0
1
.
1
ω ω
≥ ≥
k k
mn
C L (2-14)

4- startup condition:
To guarantee safe startup, the following constraint should be taken on the
minimum g
active

max _ tan min
.
k active
g g α ≥ (2-15)
Where α
min
is the safety factor (a proper value is 3)

5- Diameter of spiral inductors.

According to the total chip area, the inductors should not exceed certain
area. This leads to a maximum diameter d
max
:
max
d d < (2-16)
2.3.5.2 Design Equations
It can be shown that [13]:
2
tan
2
} {
k
bias
V
I L
L ∝ ∆ω (2-17)
Then, if the oscillator is current limited region we have:
k
bias
k
g
I
V
tan
tan
= (2-18)
And for voltage-limited region we have
Chapter2 Low Phase Noise Design Techniques in LC VCOs
50
ply k
V V
sup tan
= (2-19)
So the design equations will be
bias
L
I
g L
L
2 2
} { ∝ ∆ω For current-limited region (2-20)
2
sup
2
} {
ply
bias
V
I L
L ∝ ∆ω For voltage-limited region (2-21)
2.3.5.3 Design Strategy
Examining equations (2-20) and (2-21) we find the following observations:
a- Phase noise decrease with I
bias
in the current-limited regime while –
surprisingly – increases with I
bias
in the voltage-limited region.
b- Phase noise increases with
2 2
L
g L in the current-limited regime while
increases with
2
L in the voltage-limited region.
From the first observation we can say that we increase I
bias
until one of the
following constraints is met; maximum power dissipation or entering the
voltage-limited regime.
The second observation mandates a piece of information to be complete.
How does
2 2
L
g L vary with the inductance L?
According to [13],
2 2
L
g L has the relationship shown in Fig. 2.13 with L
provided that the g
L
of the inductor is optimized and the diameter is
constrained by a maximum value.







Chapter2 Low Phase Noise Design Techniques in LC VCOs
51











Fig. 2.14 The relationship between
2 2
L
g L
and L [13]

Hence, the phase noise is proportional to inductance value L. So it is
recommended to decrease L. But L cannot be decreased without limit.
Decreasing L will decrease the oscillation amplitude. This may violate either
the start-up condition or the amplitude value constraint.
According to the last two observations and their interpretation, the
conclusion is the following design strategy:

Find the minimum inductance that satisfies both the tank amplitude and
startup constraints for the maximum bias current allowed by the design
specifications [13].





Chapter3 Flicker Noise Modeling in MOSFET
52
Chapter 3

Flicker Noise Modeling of MOSFET
3.1 Introduction.
Among all noise sources, the flicker noise is the dominant source for phase
noise in silicon MOSFET circuits, especially in the low-frequency-range
[28]. It sets a - lower limit on the level of signal detection and spectral
purity and is one of the factors limiting, the achievable dynamic range of
MOS ICs, so it is important for device and circuit designers to minimize this
effect in order to improve the circuit performance. As designers begin to
explore circuits with low-power and low-voltage MOSFETS, the impact of
low-frequency flicker noise becomes more and more crucial for providing
enough dynamic rang and better circuit performance.
In principle, flicker noise is a low-frequency noise and it mainly affects the
low-frequency performance of the device, so it can be ignored at very high
frequency. However, the contribution of flicker noise should be considered
in designing some radio frequency (RF) circuits such as mixers, oscillators,
or frequency dividers that up-convert the low-frequency noise to higher
frequency and deteriorate the phase noise or the signal to-noise ratio.
Channel resistance and all terminal resistances contribute to the thermal
noise at high frequency (HF), but typically channel resistance dominates in
Chapter3 Flicker Noise Modeling in MOSFET
53
the contributions of the thermal noise from the resistances in the device.
Induced gate noise is generated by the capacitive coupling of local noise
sources within the channel to the gate, and usually it plays a more important
role as the operation frequency goes much higher than the frequency at
which channel thermal noise dominates [28].
3.2 The Physical Mechanisms of Flicker Noise.
Noise at low frequencies in a MOSFET is dominated by flicker noise. The
current noise spectral density is roughly inversely proportional to frequency,
as shown in Fig. 3.1. Therefore, flicker noise is also called 1/f noise. Much
effort has been made in understanding the physical origin of flicker noise.
However, the physical mechanism is still not very clear so far. A lot of
discussions and investigations are continuing to find a universal model to
explain the experimental results reported by different research groups that
use devices from different manufacturers [28].

Fig. 3.1 Drain current noise spectral density of an n-channel MOSFET [29].

Chapter3 Flicker Noise Modeling in MOSFET
54
Although there are probably several different physical mechanisms resulting
in noise in MOSFETS, there is a strong indication that traps at the Si-SiO2
interface play the most important role, as discussed in [31]. Electron
trapping and de-trapping can lead to conductance variations. The exact
mechanism is still under discussions however basically; there are three
different theories on the mechanism of flicker noise as follows:

1. Carrier-density fluctuation models (number fluctuations), predicting
an input referred noise density independent of the gate bias voltage
and proportional to the square of the oxide thickness.

2. Mobility fluctuation models, predicting an input referred noise
voltage increasing with gate bias voltage and proportional to oxide
thickness.

3. Correlated carrier and mobility fluctuation models, a unified model
proposed in [29] with a functional form resembling the number
fluctuation model at low bias and the mobility fluctuation model at
high bias.

In the carrier density fluctuation model, the noise is explained by the
fluctuation of channel-free carriers due to the random capture and emission
of carriers by interface traps at the Si-SiO2 interface. According to this
model, the input noise is independent of the gate bias; and-the magnitude of
the noise spectrum is proportional to the density of the interface traps. A 1/f
noise spectrum is predicted if the trap density is uniform in the oxide.
Measurements of devices from many different CMOS processes with oxide
Chapter3 Flicker Noise Modeling in MOSFET
55
thickness between 10 and 80 nm suggest that NMOS transistors behave as
predicted by the carrier number fluctuation model [32]. However, noise
measurement of newer deep submicron transistors presents a much less
consistent picture [28]. For instance NMOS transistors also may show bias
dependence, while PMOS transistors may have noise corner frequency
comparable to NMOS transistors. Also, the experimental result shows a 1/fn
spectrum and n is not always 1 but in the range of 0.7 to 1.2. Some
experimental results even show that n decreases with increasing gate bias in
p-channel MOSFETs [28]. Modified charge density fluctuation theories
have been proposed to explain these experimental results. The spatial
distribution of the active traps in the oxide is assumed to be non-uniform to
explain the technology and the gate-bias dependence of n. The mobility
fluctuation model considers flicker noise to be the result of fluctuations in
carrier mobility based on Hooge's empirical relation for the spectral density
of the flicker noise in a homogeneous device. It has been proposed that the
fluctuations of the bulk mobility in MOSFETs are introduced by changes in
the phonon population. The mobility fluctuation models predict a gate bias-
dependent noise. However, they cannot always account for the magnitude of
the noise.
The unified theory for the origin of the 1/f noise suggests that the capture
and emission of carriers by the interface traps cause fluctuation in both the
carrier number and the mobility. All unified noise models assume implicitly
that the mobility, limited by Coulomb scattering at trapped interface charges,
does not depend on the inversion carrier density. However, recent
experimental results indicate that the mobility, limited by Coulomb
scattering, is proportional to the square root of the inversion carrier density
[32], [33]. Recently, some arguments even claim that the correlated mobility
Chapter3 Flicker Noise Modeling in MOSFET
56
fluctuations can be neglected compared to the noise contribution from
carrier number fluctuations, if the correct dependence of the Coulomb
scattering-limited mobility on inversion carrier density is taken into account.
As a result, the unified noise models cannot predict the experimentally
observed noise as a function of gate bias in p-type MOSFETs unless
nonphysical fitting parameters are used [33]. Nevertheless, even though this
unified theory cannot explain all the details of the experimental data, it
seems to be the most attractive model available today in circuit simulators.
3.3 Flicker Noise existing Models.
It is for historic reasons that different flicker noise models have been
developed on basis of the three different approaches discussed in the
preceding text. They are implemented in different simulators such as
HSPICE, SPECTRE, ELDO, PSPICE, and so on. Almost all of the
commercial simulators provide different options for users to select different
noise models in noise simulation together with a specific compact model,
such as MOS 9, EKV, and BSIM3v3, for simulations such as DC, AC, small
signal, or transient analysis. For example, HSPICE includes three different
models for the drain current flicker noise that are distinguished with
different model levels (0-3).
For NLEV =0:


f L C
I K
eff OX
AF
DS F
id S 2
=
(3-1)


Chapter3 Flicker Noise Modeling in MOSFET
57
where Sid is the drain current noise power spectral density, IDS is the drain
current, Cox is the unit-area gate oxide capacitance, L
eff
is the effective
channel length, f is the frequency, KF and AF are the fitting parameters.
For NLEV =1:
f W L C
I K
eff eff OX
AF
DS F
id S
=
(3-2)


Where, W
eff
is the effective channel width.
For NLEV =2 and 3:

2
F m
AF id
OX eff eff
K g
C L W f
S
=
(3-3)
Where gm is the transconductance of the device and AF is a fitting
parameter. In fact, some compact models have their own flicker noise
models. For example, BSIM3v3 introduces two flicker noise models [34].
One is the SPICE2 flicker noise model [35], while the other is the unified
flicker noise model. The latter is a newer model developed recently and has
been considered a more accurate model than the SPICE2 flicker noise
model. The reason that the SPICE2 flicker noise model is included in
BSIM3v3 is to provide the convenience to some BSIM3v3 users who were
familiar with the SPICE2 flicker noise model before the unified BSIM3
noise model was developed and who want to continue using it in noise
simulation [37].
The SPICE2 flicker noise model is


EF
eff OX
AF
DS F
id
f L C
I K
S 2
=
(3-4)

Chapter3 Flicker Noise Modeling in MOSFET
58
Where, EF is a fitting parameter.

The unified flicker noise model in BSIM3v3 is more complex. Basically, it
includes a portion equivalent to the SPICE2 flicker noise model given by Eq.
(3-4), but contains another portion to give a more accurate description of the
flicker noise characteristics in the saturation region[37].
Currently, it is a fact that many different noise models are included in circuit
simulators. However, it has to be pointed out that these models in
commercial simulators are not fully compatible with each other. For
example, the geometry dependence between Eqs. (3-1) and (3-3) are
different, and the bias dependence between them is also different.
Furthermore, those flicker noise models contain different oxide thickness
dependencies. Modeling engineers and circuit designers need to be aware of
this when performing noise simulation. A lot of work has been done to
verify the accuracy of the flicker noise models over various bias conditions
(see, for example,[33]), but further work is still needed to develop a better
flicker noise model that can explain most (if not all) of the experiments. So
a careful selection of the flicker noise model is required to make sure that
the model win predict reasonable noise performance according to the circuit
applications[28].


3.4 Future Work in Flicker Noise Modeling.
The above physical mechanisms of flicker noise are the ones we have
frequently encountered in literature. However, as the technology enters
more advanced stages, new noise mechanisms may appear and play an
important role [28]. For example, it has been reported that the influence of a
Chapter3 Flicker Noise Modeling in MOSFET
59
new mechanism on flicker noise performance should be accounted for in
ultra thin oxide MOS transistors (e.g., 1.5 nm or less) owing to direct
tunneling currents that will alter the characteristics of the 1/f noise,
depending on the length of the channel and the thickness of the gate oxide,
as shown in Figures 3.3 and 3.4.

Fig. 3.2 Gate oxide thickness dependence of flicker noise in n-channel
MOSFETs with 0. 15µm and 0.2µm gate channel lengths [30].

Chapter3 Flicker Noise Modeling in MOSFET
60

Fig. 3.3 Gate length dependence of flicker noise in n-channel MOSFETs
with various gate oxide thickness [30].

In Figures 3.2 and 3.3, the gate length and the oxide thickness dependence of
gate referred voltage noise are shown at 1-kHz. Fig. 3.2 shows the gate
oxide thickness dependence of the gate referred voltage noise in devices
with 0.15-µm and 0.2-µm channel lengths. For the devices with gate lengths
less than 0.2µm, the flicker noise in a device with 1.5-nm gate oxide
thickness is lower than that in devices with thicker gate oxides. It means
that the noise characteristics of devices have been improved with decreasing
gate oxide thickness for the devices with such short channel lengths,
although the gate leakage current becomes larger in the former. A possible
mechanism for the lowering of flicker noise in the devices with thinner
oxides is the appearance of band-to-band tunneling. However, as also
shown in Fig. 3.3, for devices with channel length longer than 0.2 µm, the
flicker noise in the device with 1.5-nm gate oxide is higher than that in the
device with thicker oxide (2.2 nm)[28]. An understanding of this result has
Chapter3 Flicker Noise Modeling in MOSFET
61
led to the theory that the higher flicker noise in such devices with longer
(than 0.2 µm) channel length and thinner (1.5 nm) gate oxide was caused by
the much larger gate leakage current as the devices with longer channel
lengths have larger gate area. Further theoretical and experimental
investigations on this issue are needed to fully understand the contribution of
the band-to-band tunneling and gate leakage to the flicker noise
characteristic in today's devices. A compact flicker noise model with the
consideration of band-to-band tunneling and gate leakage has not been
reported so far.


3.5 Flicker Noise Modeling of MOSFET under Switching
Biasing
It has been reported that devices under switched bias conditions show
lower flicker noise than those measured at DC bias conditions[38],[39].

Fig. 3.4 Noise reduction as a function of the "off' voltage for an nMOS,
V
GS_ON
=2.5V, V
th
, =1.9 V, f
SWITCH
=10 kHz, duty cycle =50% [39].

Chapter3 Flicker Noise Modeling in MOSFET
62
Fig. 3.4 shows a typical measurement result. The noise spectrum between
10 Hz and 100 kHz is shown for constant biasing (no switching) together
with noise spectra resulting from a 10-kHz switched bias signal with 50%
duty cycle. For 50% duty cycle, low frequency noise power that is reduced
by 6 dB compared to the constant-bias situation is expected. Further noise
reduction is observed when the gate-source voltage in the off' state is
decreased, indicating an increasing noise reduction closer to accumulation as
shown in Fig. 3.5.






Fig. 3.5 Two transistors (a) with fixed bias and the (b) with switched bias
[40].

Fig. 3.6 shows the results at various switching frequencies. All noise spectra
appear to merge at low frequencies, with about 7 dB of intrinsic noise
reduction (apart from the 6 dB related to 50% duty cycle). Even at
megahertz frequencies, where the settling of the output voltages becomes
incomplete, this noise reduction is found. As switched biasing has been
proposed as a technique for reducing the flicker noise in MOSFET with
reduced power consumption to benefit HF circuits [39], it becomes essential
for RF MOSFET models to give a reasonable prediction of flicker noise
performance of the device under such conditions. In order to do that, the
flicker noise model contained in the RF model must be continuous and



Chapter3 Flicker Noise Modeling in MOSFET
63
accurate over a wide bias range from strong inversion to accumulation and
from linear to saturation regimes. Further work is needed to validate the
flicker noise models with measured noise data in devices under switch-
biasing conditions and to develop more advanced noise models for RF
applications.




Fig. 3.6 Noise reduction while switching at different frequencies for an
nMOS, V
GS
=2.5 V, V
GS.off
=0 V, duty cycle =50%. Also shown is the
noise floor under the same conditions [39]











Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

64
Chapter 4

A New Circuit to Reduce Flicker Noise
Effect in VCOs
4.1 Introduction.
Low frequency noise can be harmful not only on the low frequency circuits
but also on RF circuits. This fact appears strange from the first glance, but
knowing that most of RF circuits have high nonlinearity and/or time
variation nature clarifies the flicker noise effect mechanism. Those effects
upconvert the flicker noise to higher frequencies impacting the circuit
operation. One of the circuits that are greatly affected by the flicker noise
upconversion is the voltage-controlled oscillator (VCO). The low frequency
noise of the MOSFET transistors is upconverted to the oscillation frequency
deteriorating the phase noise at offsets that are important for communication
systems. Because of that upconversion of the flicker noise, the phase noise
profile is divided mainly to three regions: -30dB/decade, -20dB/decade and
flat region due to noise floor. The flicker noise is the main contributor in the
first region while the thermal noise is the main contributor in the other
region. A lot of research effort was made in the last decade to avoid the
harmful effect of the flicker noise on the oscillator phase noise [2], [6], [8],

Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

65
[9]-[10], [40]. Referring to the cross-coupled negative-resistance VCO with
tail current I shown in Fig. 4.1, it was illustrated in [9] that the main
contributor in the -30dB/decade region is the tail current transistor flicker
noise.

Fig. 4.1. N-type negative differential resistance VCO.
There are two mechanisms of upconverting the flicker noise of the tail
current to tank nodes. The first is through upconverting the noise power
directly to the oscillation frequency f
o
by the mixing effect made by
switching transistors. The second mechanism is through upconverting some
of the flicker noise power to 2f
o
by channel length modulation of the tail
current transistor. Then, translating such upconverted noise back to f
o

through mixing effect by the negative G
m
transistors. For the first
mechanism, it was shown in [5] that minimizing the dc component of the
impulse sensitivity function (ISF) leads to minimizing the upconversion of
flicker noise to f
o
. This can be done by using complementary negative
resistance architecture, as shown in Fig. 4.2, and adjusting the N and P
device geometries such that g
mp
=g
mn
.
Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

66

Fig. 4.2. Complementary negative differential resistance VCO.
However equalizing the device transconductances of N and P transistors
based on simulation does not guarantee matching in reality. Another way has
been introduced in [10] to suppress low frequency noise. The idea was to put
off-chip inductor with a large value on the way of the tail current or off-chip
capacitor on tail current drain node. Although this solution can be efficient
but it contradicts the on-chip solution and this is not the trend of RF design
nowadays. The second mechanism of noise upconversion through the
channel length modulation of the tail current has a number of prevention
plans. The symmetry of the circuit with respect to the vertical axis including
the inductor layout was suggested in [9] to lower the amplitude of the drain
node voltage oscillation and hence, minimizing the upconversion to 2f
o
. In
the same paper [9] it was suggested to use cascode current source and/or
large capacitor from tail current drain to ground. This capacitor stabilizes the
tail drain voltage and short circuits the upconverted noise preventing it from
reaching the tank and contributing to phase noise. It has been shown in [9]
that using this capacitor results in reducing the loaded quality factor of the
Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

67
tank through loading by the negative G
m
transistors. The solution suggested
in [9] is to add a coil to resonate parasitic capacitance associated with the
common source of the two negative G
m
transistors as shown in Fig. .4.3.










Fig. 4.3. An oscillator with reduced tail current flicker noise effect due to
filtering .
In this work a new LC voltage-controlled oscillator circuit topology is
proposed. In this topology, the flicker noise generated by the tail transistor is
noticeably reduced by utilizing the phenomenon of flicker noise intrinsic
reduction due to switched biasing.
4.2 A new macro-model for transistor noise under switched
biasing.
The following tasks is performed by the macro-model:
1- Canceling the flicker noise of our transistor [transistor (a)] by putting
flicker noise multipliers =0 in the model card.
2- Transferring the terminal voltages of the original transistor [transistor
(a)] to both transistors (b) and (c) terminals through voltage controlled

Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

68
voltage sources. Transistor (b) is a mirror replica of transistor (a) but
without any noise (neither thermal noise nor flicker noise).And
Transistor (c) is a mirror replica of transistor (a) but without thermal
noise (flicker noise only). We have now i
1
=I
ds
flowing in transistor (b)
drain and i
2
=I
ds
+I
flicker noise
in transistor (c).
3- Subtracting i
1
-i
2
results in I
flicker noise
without any large signal bias
effect.
4- As shown in chapter (3), the flicker noise of the transistor under
switching can be divided into two regions. First region at frequencies
lower than switching frequency (f
s
) and the second region at
frequencies higher than f
s
. In the first region I
flicker_noise
is reduced by a
factor β so a low pass current mode filter (of corner frequency f
s
) is
applied to a reduced version of the de-embedded noise current (1/β
)*I
flicker_noise
to represent what happens in the first region. In the
second region I
flicker_noise
is not reduced, so a high pass current mode
filter (of corner frequency f
s
) is applied to the de-embedded noise
current I
flicker_noise
to represent what happens in the second region.

Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

69

Fig. 4.2 The proposed macro-model schematic.

Fig. 4.3 shows the noise power behavior for the fixed bias transistor (curve
a), the switched bias transistor with classical model (curve b) and switched
bias transistor using the proposed macro model (curves c, d and e for
switching frequencies 100Hz, 1kHz and 10kHz respectively). Bias
modulation leads to 6dB reduction in flicker noise [28] as shown in curve b.
Another extra 6dB reduction in flicker noise region [28] is pronounced in
curves c, d and e to match the experimental flicker noise measurements of
switched-bias MOSFETs [39].

Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

70
















Fig. 4.3 Comparison of fixed bias case (curve a), switched case with
classical model (curve b) and switched case with new macro-model (curves
c, d and e)
An important notice here is that curves c; d and e are drawn only to 0.9f
s
. At
fs, the spurious noise appears. This spurious noise can be very harmful to the
circuit if there is no filter that removes it. So it is essential to use the proper
filter in the circuit design.
4.3 Complementary Biasing Technique
The key point of the switched biasing technique is that it reduces tail current
intrinsic flicker noise, relaxing the design task that was mainly concentrating
on minimizing flicker noise upconversion. In [12], the same technique has
Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

71
been utilized to reduce the flicker noise of a coupled sawtooth ring
oscillator. Fig. 4.4 illustrates the basic proposed complementary biases
architecture. The oscillator designer does not have to match the
transconductances of the P-MOS and the N-MOS to reduce the
upconversion of the flicker noise. Therefore the two device dimensions can
be selected independently.


Fig. 4.4 Proposed complementary biased architecture

The oscillator with switched biasing shown in Fig. 4.4 can be implemented
by several schemes. The selected scheme is illustrated in Fig. 4.5.




Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

72

Fig. 4.5 The practical implementation of the proposed complementary
biasing (VCO-I)

4.4 Design Considerations
1-Biasing oscillator frequency:
The frequency of the biasing oscillator (2.24GHz) is selected such that
is far from the oscillating frequency fundamental and harmonics of the
main oscillator. This is due to two reasons. First is to guarantee no
mutual interaction of both oscillators phase noise. Of course, the
tuning behavior of the main oscillator must be taken into
consideration in this case. And second is to guarantee elimination of
any modulation effect due to the biasing oscillator.


Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

73
2-Biasing oscillator waveform:
The biasing oscillator waveform must be adjusted such that the tail
current transistors of the main oscillator switch from the strong
inversion regime to depletion regime. Both active transistor dimension
of the biasing oscillator and V
bias
can be adjusted to achieve this goal.
As shown in Fig 4.6, the tail current transistors gate voltages are
driven to negative values to guarantees depletion regime entrance.

Fig. 4.6 Tail current transistors gate voltages


3-Layout precautions:
It is essential to layout the switched tail current near the biasing
oscillator as shown in Fig.4.7. This helps in two ways. One is to avoid
have parasitic inductance series with the switched tail transistors gates
Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

74
due to routing large distance. The second ways is to avoid collecting
noise on the routes going to the gates.


Fig. 4.7 Proposed circuit layout

Filter resonance capacitor
MOS varactor
Filter noise shorting capacitor
Filter resonance inductor
Switched tail current
Core current path
Main inductor
Biasing oscillator inductor
Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

75
4.5 Switched biasing versus constant biasing; a comparison
The proposed oscillator shown in Fig. 4.5 (VCO-I) is compared with a
reference oscillator (VCO-II) as shown in Fig 4.8. This reference oscillator
has the same core of the switched bias oscillator but takes its bias from
traditional current mirror. Following are some comparison aspects:

1-Power dissipation:
The current supply of the traditional oscillator, VCO-II, is chosen to
be equal to the core current of VCO-I (I [in both Figs 4.5 and 4.8]
=3mA). This is to obtain the same oscillation frequency and tuning
range for both VCO-I and VCO-II. This power dissipation can by
calculated from the equation:
Power dissipation switched scheme =3.3V*(3mA +2mA)=16.5mW
(4-1)
Power dissipation constant bias scheme=3.3V*(3mA )=9.9mW


Fig. 4.8 Reference architecture (VCO-II)
Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

76
2-Output waveform:
Fig. 4.9 illustrates a time domain picture of VCO-I and VCO-II output
waveforms respectively.

Fig. 4.9 Waveform comparison of switched and fixed bias schemes
3-Tuning behavior:
Since we have the core of VCO-I and VCO-II the same including I
core

value, the tuning range is expected to be the same. The tuning
characteristics of both oscillators are shown in Fig 4.10.
Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

77

Fig. 4.10 Tuning behavior of both oscillators
4-Phase noise:
Finally the phase noise at a low frequency offset (1kHz) is simulated
for three cases. The first is for VCO-II and the second is for VCO-I
and the third is for ideally switched bias oscillator shown in Fig. 4.4.
The result of mentioned simulations is shown in Fig 4.11.
An improvement 4.9dB is noticed between the constant bias phase
noise and ideally switched scheme. This improvement is deteriorated
a little (decreased to 4.6dB) in the practical implementation due to
Chapter4 A New Circuit to Overcome Flicker Noise Effect in VCOs

78
biasing oscillator noise.

Fig. 4.11 Phase noise comparison at 1kHz offset of three cases.

4-Design area:
As shown in Fig 4.7 the switched bias layout is considerably larger
than the classical oscillator with the same core. This is because the
switched scheme has an extra area due to the existence of biasing
oscillator inductors. Moreover these inductors should be separated by
a minimum spacing to reduce coupling between the two oscillators.
Switched design layout area=0.77mm
2

Classical design layout area=0.36mm
2

Conclusion and Future Work

79
Conclusion and Future Work
A complementary switched biasing technique of an LC CMOS VCO tail
current has been proposed. The main idea was to convert the current source
from static current source to two complementary switched current sources.
The total phase noise of such scheme has been improved by a factor up to
4.5dB compared to the classical reported schemes with the same oscillation
frequency and tuning range. The design area of the switched scheme is
nearly double of classical scheme area due to use of two extra inductors. The
switched scheme dissipates extra 6.6mW compared to classical scheme.
Because of the current lack of switched MOSFET flicker noise modeling, a
macro model for switched MOSFET flicker noise has been used in the
oscillator circuit simulation. The macro model has been found to be in
qualitative agreement with the published results on this phenomenon. The
simulation was done using Eldo-RF simulator. The technology used in
simulation is a standard CMOS 0.35µm technology, the total power
dissipation of the new oscillator is 16.5mW, the center frequency is
3.35GHz, the tuning range is 300MHz and its design area =0.77mm
2
.
Based on the experience gained in this thesis, several useful future work
trends can be introduced.
• The first is to concentrate on the innovation in oscillator architecture.
Special care can be paid to cyclostationary behavior of noise sources.
• The second is to pay more attention and research to the RF device
modeling.
• The third potential future work is to elaborate more deeply the phase noise
simulation based on zero crossings statistics.

APPENDI X A: Test Benches and Macro-models
80
APPENDIX A: Test Benches and Macro-
models.
A.1 Main test bench:

***######### INCLUDES #########################
.include ../custom.mod

****############# OPTIONS ######################
.option eps=1e-6
.option acm


****############ GENERAL PARAMETERS #######
.paramtheta=0

.paramAFo =x*1.3600e00
.paramKFo =x*5.1e-2outp
.paramEFo =x*1.000e00
.paramNOIAo =x*1.outp3e19
.paramNOIBo =x*7.000e04
.paramNOICo =x*-5.64e-13

.paramx=0

****************
****************
.paramwpmain=15u
.paramwnmain=7.5u
.parammnmain=4
.parammpmain=4
.paramwvar=7.5u
.parammvar=20
.paramfmain=3.25geg
.paramvc=0.5v
.paramwcs=20u
.paramlcs=0.5u
.parammcs=10
.paramibias=2m


****############ GENERAL BIAS #####################
vsupply vdd 0 dc 3.3

***############### SUBCIRCUITS DEFINITIONS #######

APPENDI X A: Test Benches and Macro-models
81
.subckt core o1 o2 n t vdd gnd wn=10u mn=1 wp=20u mp=1 wv=100u mv=3 fm=1geg bb=2

xp1 o1 o2 vdd vdd spmos wo=wp lo=0.35u mo=mp fs=fmbeta=bb
xp2 o2 o1 vdd vdd spmos wo=wp lo=0.35u mo=mp fs=fmbeta=bb

xn1 o1 o2 n gnd snmos wo=wn lo=0.35u mo=mn fs=fmbeta=bb
xn2 o2 o1 n gnd snmos wo=wn lo=0.35u mo=mn fs=fmbeta=bb


mv1 o1 t o1 vdd modp w=wv l=0.35u m=mv
mv2 o2 t o2 vdd modp w=wv l=0.35u m=mv

xl1 o1 mid gnd SP020S180D !! 2.006e-09

xl2 o2 mid gnd SP020S180D !! 2.006e-09

.ends
*****************
*****************
.subckt cs d g1 g2 s b ws=10u ls=0.35u ms=1 fm=1geg bb=2

xs1 d g1 s b snmos wo=ws lo=ls mo=ms fs=fmbeta=bb
xs2 d g2 s b snmos wo=ws lo=ls mo=ms fs=fmbeta=bb

.ends





***############## CLASSICAL CONFIGURATION#######
*#####################################################
*#####################################################

*#com
*********************************************************
********************* classical parameters *******************
.paramcp=0.7p
.paramwsb=13.3u
.parammsb=10


************************** NETLIST *********************

******************* main oscillator ********************
x1 outp outn comtt vdd 0 core wn=wnmain mn=mnmain wp=wpmain mp=mpmain wv=wvar mv=mvar fm=fmain
bb=2
vt tt 0 dc vc
vtestcore comcommdc 0
cparasitic comm0 cp
xlf1 commsd 0 SP014S300D !! 1.245e-09
APPENDI X A: Test Benches and Macro-models
82
cfilter sd 0 10p
mx2 sd in2 0 0 modn w=wcs l=lcs m=mcs

********** Bias Cell *******************************
***************************************************

Ibias vdd in2 dc ibias

msb in2 in2 0 0 modn w=wsb l=0.5u m=msb


**********TRANSIENT ANALYSIS ************************
#com
.tran 1p 30n 0 1p
.ic v(outp)=1
.ic v(outn)=1.1


******* plots ************
.plot tran v(outp,outn)
.plot tran v(in2,sd)
#endcom
*********** SST ANALYSIS *****************************
*#com
.SST OSCIL FUND_OSC_GUESS1=fmain NHARM_OSC1=10
.SSTPROBE outp outn FUND_OSC1

*.sstnoise v(outp,outn) harm(1) dec 10 1 1e8

*.sstnoise v(outp,outn) harm(1) list 10
*.sstnoise v(outp,outn) harm(1) list 1e7

*.step paramwsb 1u 100u 1u
*.step paramcp 0.1p 1.5p 0.1p
.step paramvc 0 3.3 0.1

******* plots ************

.plot SSTNOISE DB(PHNOISE)
.plot tsst v(outp,outn)
.plot tsst v(outp) v(outn)
********* exctracts *********
.extract fsst label=fosc fund_osc
.extract tsst label=I average(i(vtestcore))
.extract tsst label=max_vgd_mmax(v(in2,sd))
.extract sstnoise label=phn_10 yval(db(phnoise),10)
.extract sstnoise label=phn_100meg yval(db(phnoise),1e7)
*#endcom
*********************************************************
*********************************************************
*#endcom



APPENDI X A: Test Benches and Macro-models
83




***########IDEAL SWITCHED CONFIGURATION######
*#####################################################
*#####################################################

*#com

*********************************************************
**************** Switched parameters ***********************
.paramfbias=2.24geg
.paramT=1/fbias
.paramrft=T/100
.paramwpulse=(T/2)-rft
.paramdbias=T/2
.paramvbias=0.907v
.paramcp=0.9p



********************* NETLIST **************************
******************* main oscillator ************************
x1 outp outn comtt vdd 0 core wn=wnmain mn=mnmain wp=wpmain mp=mpmain wv=wvar mv=mvar fm=fmain
bb=2
vt tt 0 dc vc
vtestcore comcommdc 0
cparasitic com0 cp
xlf1 commsd 0 SP014S300D !! 1.245e-09
cfilter sd 0 10p
x2 sd in1 in2 0 0 cs ws=wcs ls=lcs ms=mcs fm=fmain bb=2

********** Bias Oscillator *******************************
***************************************************

vs1 in1 0 pulse( 0 vbias 0 rft rft wpulse T )
vs2 in2 0 pulse( 0 vbias dbias rft rft wpulse T )





**********TRANSIENT ANALYSIS ************************
********************************************************

#com
APPENDI X A: Test Benches and Macro-models
84
.tran 1p 30n 0 1p
.ic v(outp)=1
.ic v(outn)=3
.ic v(in1)=3
.ic v(in2)=0

******* plots ************
.plot tran v(outp,outn)
.plot tran v(outp) v(outn)
.plot tran v(in2,in1)
.plot tran v(in2) v(in1)
.plot tran v(sd)
.plot tran v(in2,sd)
.plot tran i(vtestcore)
#endcom
*********** SST ANALYSIS *****************************
********************************************************
*#com
.SST OSCIL FUND_OSC_GUESS1=fmain NHARM_OSC1=10 fund1=fbias nharm1=10
.SSTPROBE outp outn FUND_OSC1


.sstnoise v(outp,outn) harm(1,0) dec 10 1 1e8

*.sstnoise v(outp,outn) harm(1,0) list 10
*.sstnoise v(outp,outn) harm(1,0) list 1e7

*.step paramcp 0.5p 1p 0.1p
*.step paramvc 0 3.3 0.1
*.step paramvbias 0.85v 0.95v 0.01v

******* plots ************

.plot SSTNOISE DB(PHNOISE)
.plot tsst v(outp,outn)
.plot tsst v(in1,in2)
.plot tsst v(in2) v(in1)
.plot tsst v(outp) v(outn)
.plot tsst v(sd)
.plot tsst v(in2,sd)
.plot tsst i(vtestcore)


********* extracts *********

.extract fsst label=fosc1 fund_osc1
.extract fsst label=fosc2 fund_osc2
.extract tsst label=I average(i(vtestcore))
.extract tsst label=max_vgd_mmax(v(in2,sd))
.extract sstnoise label=phn_10 yval(db(phnoise),10)
.extract sstnoise label=phn_100meg yval(db(phnoise),1e7)
*#endcom
*********************************************************
*********************************************************
*#endcom
APPENDI X A: Test Benches and Macro-models
85

***##############SWITCHED CONFIGRATION ########
*#####################################################
*#####################################################
#com
*************************************************************
********************Switched parameters ***********************
.paramcp=0.9p
.paramwb=25u
.parammb=2
.paramfbias=2.24geg


****************** NETLIST **********************
**************** main oscillator ********************

x1 outp outn comtt vdd 0 core wn=wnmain mn=mnmain wp=wpmain mp=mpmain wv=wvar mv=mvar fm=fmain
bb=2
vt tt 0 dc vc
vtestcore comcommdc 0
cparasitic com0 cp
xlf1 commsd 0 SP014S300D !! 1.245e-09
cfilter sd 0 10p
x2 sd in1 in2 0 0 cs ws=wcs ls=lcs ms=mcs fm=fmain bb=2

********** Bias Oscillator *******************************
***************************************************

Ibias vdd k dc ibias

xb1 in1 in2 k k spmos wo=wb lo=0.35u mo=mb fs=fbias beta=2
xb2 in2 in1 k k spmos wo=wb lo=0.35u mo=mb fs=fbias beta=2

xlb1 in1 vbb 0 SP090S155D !! 9.175e-09
xlb2 in2 vbb 0 SP090S155D !! 9.175e-09

vbias vbb 0 dc 0.5

**********TRANSIENT ANALYSIS ************************
********************************************************

*#com
.tran 1p 30n 0 1p
.ic v(outp)=1
.ic v(outn)=3
.ic v(in1)=3
.ic v(in2)=0

******* plots ************
.plot tran v(outp,outn)
.plot tran v(outp) v(outn)
APPENDI X A: Test Benches and Macro-models
86
.plot tran v(in2,in1)
.plot tran v(in2) v(in1)
.plot tran v(sd)
.plot tran v(in2,sd)
.plot tran i(vtestcore)
*#endcom


*********** SST ANALYSIS *****************************
********************************************************
*#com
.SST OSCIL FUND_OSC_GUESS1=fmain NHARM_OSC1=10 FUND_OSC_GUESS2=fbias NHARM_OSC2=10
.SSTPROBE outp outn FUND_OSC1
.SSTPROBE in1 in2 FUND_OSC2

*.sstnoise v(outp,outn) harm(1,0) dec 10 1 1e8

*.sstnoise v(outp,outn) harm(1,0) list 10
*.sstnoise v(outp,outn) harm(1,0) list 1e7

*.step paramcp 0.5p 1p 0.1p
*.step paramvc 0 3.3 0.1

******* plots ************

.plot SSTNOISE DB(PHNOISE)
.plot tsst v(outp,outn)
.plot tsst v(in1,in2)
.plot tsst v(in2) v(in1)
.plot tsst v(outp) v(outn)
.plot tsst v(sd)
.plot tsst v(in2,sd)
.plot tsst i(vtestcore)
********* exctracts *********
.extract fsst label=fosc1 fund_osc1
.extract fsst label=fosc2 fund_osc2
.extract tsst label=I average(i(vtestcore))
.extract tsst label=max_vgd_mmax(v(in2,sd))
.extract sstnoise label=phn_10 yval(db(phnoise),10)
.extract sstnoise label=phn_100meg yval(db(phnoise),1e7)
*#endcom
*********************************************************
*********************************************************
#endcom
A.2 Simulation models:

. MODEL MODN NMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
APPENDI X A: Test Benches and Macro-models
87
* ext r act ed : B10866 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =0
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 0296e-01
+K2 =3. 3985e-02 K3 =-1. 136e+00 K3B =-4. 399e-01
+NPEAK =2. 611e+17 VTH0 =4. 979e-01
+VOFF =-8. 925e-02 DVT0 =5. 000e+01 DVT1 =1. 039e+00
+DVT2 =-8. 375e-03 KETA =2. 032e-02
+PSCBE1 =3. 518e+08 PSCBE2 =7. 491e-05
+DVT0W =1. 089e-01 DVT1W =6. 671e+04 DVT2W =-1. 352e-02
* *** Mobility related model parameters ***
+UA =4. 705e-12 UB =2. 137e-18 UC =1. 000e-20
+U0 =4. 758e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =1. 415e-02 ETAB =-1. 221e-01
+NFACTOR=4. 136e-01
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =6. 948e-01
+PDI BLC1=3. 571e-01 PDI BLC2=2. 065e-03 DROUT =5. 000e-01
+A0 =2. 541e+00 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 338e+05 AGS =2. 408e-01
+B0 =4. 301e-09 B1 =0. 000e+00 DELTA =1. 442e-02
+PDI BLCB=3. 222e-01
* *** Geometry modulation related parameters ***
+W0 =2. 673e-07 DLC =3. 0000e-08
+DWC =9. 403e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =-1. 297e-14 WWL =-9. 411e-21 WLN =1. 000e+00
+WWN =1. 000e+00
* *** Temperature effect parameters ***
+AT =3. 300e+04 UTE =-1. 800e+00
+KT1 =-3. 302e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =1. 300e-10 CGSO =1. 200e-10 CGBO =1. 100e-10
+CGDL =1. 310e-10 CGSL =1. 310e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =3. 449e+02
+CDSC =0. 000e+00 CDSCB =1. 500e-03 CDSCD =1. 000e-03
+PRWB =-2. 416e-01 PRWG =0. 000e+00 CI T =4. 441e-04
* *** Process and parameters extraction related model parameters ***
+TOX =7. 575e-09 NGATE =0. 000e+00
+NLX =1. 888e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =1. 3600e+00 KF =5. 1e-27 EF =1. 000e+00
+NOI A =1. 73e+19 NOI B =7. 000e+04 NOI C =-5. 64e-13
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
APPENDI X A: Test Benches and Macro-models
88
+RD =0. 000e+00 RS =0. 000e+00 RSH =7. 000e+01
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-5. 005e-08
+WD =9. 403e-08
+LDIF =0. 000e+00 HDI F =8. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =1. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =9. 400e-04 CJ SW =2. 500e-10 FC =0. 000e+00
+MJ =3. 400e-01 MJ SW =2. 300e-01 TT =0. 000e+00
+PB =6. 900e-01 PBSW =6. 900e-01
. MODEL MODN_not h NMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : B10866 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =1 gdsnoi =t het a
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 0296e-01
+K2 =3. 3985e-02 K3 =-1. 136e+00 K3B =-4. 399e-01
+NPEAK =2. 611e+17 VTH0 =4. 979e-01
+VOFF =-8. 925e-02 DVT0 =5. 000e+01 DVT1 =1. 039e+00
+DVT2 =-8. 375e-03 KETA =2. 032e-02
+PSCBE1 =3. 518e+08 PSCBE2 =7. 491e-05
+DVT0W =1. 089e-01 DVT1W =6. 671e+04 DVT2W =-1. 352e-02
* *** Mobility related model parameters ***
+UA =4. 705e-12 UB =2. 137e-18 UC =1. 000e-20
+U0 =4. 758e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =1. 415e-02 ETAB =-1. 221e-01
+NFACTOR=4. 136e-01
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =6. 948e-01
+PDI BLC1=3. 571e-01 PDI BLC2=2. 065e-03 DROUT =5. 000e-01
+A0 =2. 541e+00 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 338e+05 AGS =2. 408e-01
+B0 =4. 301e-09 B1 =0. 000e+00 DELTA =1. 442e-02
+PDI BLCB=3. 222e-01
* *** Geometry modulation related parameters ***
+W0 =2. 673e-07 DLC =3. 0000e-08
+DWC =9. 403e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =-1. 297e-14 WWL =-9. 411e-21 WLN =1. 000e+00
+WWN =1. 000e+00
* *** Temperature effect parameters ***
+AT =3. 300e+04 UTE =-1. 800e+00
+KT1 =-3. 302e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
APPENDI X A: Test Benches and Macro-models
89
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =1. 300e-10 CGSO =1. 200e-10 CGBO =1. 100e-10
+CGDL =1. 310e-10 CGSL =1. 310e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =3. 449e+02
+CDSC =0. 000e+00 CDSCB =1. 500e-03 CDSCD =1. 000e-03
+PRWB =-2. 416e-01 PRWG =0. 000e+00 CI T =4. 441e-04
* *** Process and parameters extraction related model parameters ***
+TOX =7. 575e-09 NGATE =0. 000e+00
+NLX =1. 888e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =1. 3600e+00 KF =5. 1e-27 EF =1. 000e+00
+NOI A =1. 73e+19 NOI B =7. 000e+04 NOI C =-5. 64e-13
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =7. 000e+01
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-5. 005e-08
+WD =9. 403e-08
+LDI F =0. 000e+00 HDI F =8. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =1. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =9. 400e-04 CJ SW =2. 500e-10 FC =0. 000e+00
+MJ =3. 400e-01 MJ SW =2. 300e-01 TT =0. 000e+00
+PB =6. 900e-01 PBSW =6. 900e-01
. MODEL MODN_nof l NMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : B10866 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =0
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 0296e-01
+K2 =3. 3985e-02 K3 =-1. 136e+00 K3B =-4. 399e-01
+NPEAK =2. 611e+17 VTH0 =4. 979e-01
+VOFF =-8. 925e-02 DVT0 =5. 000e+01 DVT1 =1. 039e+00
+DVT2 =-8. 375e-03 KETA =2. 032e-02
+PSCBE1 =3. 518e+08 PSCBE2 =7. 491e-05
+DVT0W =1. 089e-01 DVT1W =6. 671e+04 DVT2W =-1. 352e-02
* *** Mobility related model parameters ***
+UA =4. 705e-12 UB =2. 137e-18 UC =1. 000e-20
+U0 =4. 758e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =1. 415e-02 ETAB =-1. 221e-01
APPENDI X A: Test Benches and Macro-models
90
+NFACTOR=4. 136e-01
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =6. 948e-01
+PDI BLC1=3. 571e-01 PDI BLC2=2. 065e-03 DROUT =5. 000e-01
+A0 =2. 541e+00 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 338e+05 AGS =2. 408e-01
+B0 =4. 301e-09 B1 =0. 000e+00 DELTA =1. 442e-02
+PDI BLCB=3. 222e-01
* *** Geometry modulation related parameters ***
+W0 =2. 673e-07 DLC =3. 0000e-08
+DWC =9. 403e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =-1. 297e-14 WWL =-9. 411e-21 WLN =1. 000e+00
+WWN =1. 000e+00
* *** Temperature effect parameters ***
+AT =3. 300e+04 UTE =-1. 800e+00
+KT1 =-3. 302e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =1. 300e-10 CGSO =1. 200e-10 CGBO =1. 100e-10
+CGDL =1. 310e-10 CGSL =1. 310e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =3. 449e+02
+CDSC =0. 000e+00 CDSCB =1. 500e-03 CDSCD =1. 000e-03
+PRWB =-2. 416e-01 PRWG =0. 000e+00 CI T =4. 441e-04
* *** Process and parameters extraction related model parameters ***
+TOX =7. 575e-09 NGATE =0. 000e+00
+NLX =1. 888e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =AFo KF =KFo EF =EFo
+NOIA =NOIAo NOIB =NOIBo NOIC =NOICo
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =7. 000e+01
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-5. 005e-08
+WD =9. 403e-08
+LDI F =0. 000e+00 HDI F =8. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =1. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =9. 400e-04 CJ SW =2. 500e-10 FC =0. 000e+00
+MJ =3. 400e-01 MJ SW =2. 300e-01 TT =0. 000e+00
+PB =6. 900e-01 PBSW =6. 900e-01
. MODEL MODN_nof l _not h NMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* extr act ed : B10866 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
APPENDI X A: Test Benches and Macro-models
91
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =1 gdsnoi =t het a
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 0296e-01
+K2 =3. 3985e-02 K3 =-1. 136e+00 K3B =-4. 399e-01
+NPEAK =2. 611e+17 VTH0 =4. 979e-01
+VOFF =-8. 925e-02 DVT0 =5. 000e+01 DVT1 =1. 039e+00
+DVT2 =-8. 375e-03 KETA =2. 032e-02
+PSCBE1 =3. 518e+08 PSCBE2 =7. 491e-05
+DVT0W =1. 089e-01 DVT1W =6. 671e+04 DVT2W =-1. 352e-02
* *** Mobility related model parameters ***
+UA =4. 705e-12 UB =2. 137e-18 UC =1. 000e-20
+U0 =4. 758e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =1. 415e-02 ETAB =-1. 221e-01
+NFACTOR=4. 136e-01
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =6. 948e-01
+PDI BLC1=3. 571e-01 PDI BLC2=2. 065e-03 DROUT =5. 000e-01
+A0 =2. 541e+00 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 338e+05 AGS =2. 408e-01
+B0 =4. 301e-09 B1 =0. 000e+00 DELTA =1. 442e-02
+PDI BLCB=3. 222e-01
* *** Geometry modulation related parameters ***
+W0 =2. 673e-07 DLC =3. 0000e-08
+DWC =9. 403e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =-1. 297e-14 WWL =-9. 411e-21 WLN =1. 000e+00
+WWN =1. 000e+00
* *** Temperature effect parameters ***
+AT =3. 300e+04 UTE =-1. 800e+00
+KT1 =-3. 302e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =1. 300e-10 CGSO =1. 200e-10 CGBO =1. 100e-10
+CGDL =1. 310e-10 CGSL =1. 310e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =3. 449e+02
+CDSC =0. 000e+00 CDSCB =1. 500e-03 CDSCD =1. 000e-03
+PRWB =-2. 416e-01 PRWG =0. 000e+00 CI T =4. 441e-04
* *** Process and parameters extraction related model parameters ***
+TOX =7. 575e-09 NGATE =0. 000e+00
+NLX =1. 888e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =AFo KF =KFo EF =EFo
+NOIA =NOIAo NOIB =NOIBo NOIC =NOICo
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =7. 000e+01
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-5. 005e-08
+WD =9. 403e-08
APPENDI X A: Test Benches and Macro-models
92
+LDI F =0. 000e+00 HDI F =8. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =1. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =9. 400e-04 CJ SW =2. 500e-10 FC =0. 000e+00
+MJ =3. 400e-01 MJ SW =2. 300e-01 TT =0. 000e+00
+PB =6. 900e-01 PBSW =6. 900e-01
* ----------------------------------------------------------------------
. SUBCKT ND A C PARAM: AREA=1e-12 PERI =4e-6
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : DIODE
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : B10866 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
* TERMINALS: A=anode=P-region C=cathode=N-region
* VARI ABLES: M ( mul i t i pl i er ) , AREA [ m^2] , PERI [ m] .
* NOTE: The role of a protection DIODE is to conduct ESD current to VDD
* (or from VSS). This forward bias is NOT modelled, only leakage current
* and capacitance during normal operation. Any inductive load etc that
* will give forward bias, must be limited by other components to within
* Operating Conditions, otherwise parasitic bipolar action can occur.
*
D1 A C NDI NSUB AREA=AREA PERI =PERI
.ENDS ND
*
. MODEL NDI NSUB D LEVEL=1 MODTYPE=ELDO
+I S =1. 000e-05 I SW =0. 000e+00 N =1. 000e+00
+CJ =9. 400e-04 M =3. 400e-01 VJ =6. 900e-01 TT =0. 000e+00
+CJ SW =2. 500e-10 MJ SW =2. 300e-01 FC =0. 500e+00
+EG =1. 110e+00 XTI =3. 000e+00 AF =1. 000e+00 KF =0. 000e+00
* ----------------------------------------------------------------------
. MODEL MODNM NMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : B11004 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =0
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =7. 4922e-01
+K2 =1. 1026e-01 K3 =-3. 776e+00 K3B =-7. 691e-02
+NPEAK =2. 265e+17 VTH0 =7. 525e-01
+VOFF =-8. 295e-02 DVT0 =3. 000e+01 DVT1 =1. 528e+00
+DVT2 =2. 529e-02 KETA =3. 585e-02
APPENDI X A: Test Benches and Macro-models
93
+PSCBE1 =4. 309e+08 PSCBE2 =1. 000e-10
+DVT0W =-5. 000e+00 DVT1W =2. 578e+06 DVT2W =5. 105e-02
* *** Mobility related model parameters ***
+UA =4. 708e-10 UB =1. 470e-18 UC =-4. 342e-11
+U0 =5. 643e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =3. 795e-02 ETAB =-7. 653e-04
+NFACTOR=8. 573e-01
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =2. 125e-01
+PDI BLC1=1. 000e-04 PDI BLC2=5. 458e-04 DROUT =5. 000e-01
+A0 =2. 064e+00 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 078e+05 AGS =1. 079e-01
+B0 =-1. 493e-07 B1 =0. 000e+00 DELTA =1. 000e-02
+PDI BLCB=5. 186e-01
* *** Geometry modulation related parameters ***
+W0 =1. 617e-07 DLC =1. 0000e-07
+DWC =1. 623e-07 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =-5. 117e-14 WWL =-5. 704e-21 WLN =1. 000e+00
+WWN =1. 000e+00
* *** Temperature effect parameters ***
+AT =3. 300e+04 UTE =-1. 760e+00
+KT1 =-4. 502e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =1. 080e-10 CGSO =1. 080e-10 CGBO =1. 100e-10
+CGDL =2. 270e-10 CGSL =2. 270e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =1. 390e+03
+CDSC =0. 000e+00 CDSCB =-1. 500e-03 CDSCD =0. 000e+00
+PRWB =-6. 740e-02 PRWG =0. 000e+00 CI T =0. 000e+00
* *** Process and parameters extraction related model parameters ***
+TOX =1. 516e-08 NGATE =0. 000e+00
+NLX =2. 283e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =1. 270e+00 KF =3. 50e-27 EF =1. 000e+00
+NOI A =6. 64e+19 NOI B =1. 090e+05 NOI C =-1. 4e-13
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =7. 900e+01
+RDC =0. 000e+00 RSC =0. 000e+00 LD =1. 225e-07
+WD =1. 623e-07
+LDI F =0. 000e+00 HDI F =6. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =1. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =9. 400e-04 CJ SW =2. 500e-10 FC =0. 000e+00
+MJ =3. 400e-01 MJ SW =2. 300e-01 TT =0. 000e+00
+PB =6. 900e-01 PBSW =6. 900e-01
* ----------------------------------------------------------------------
.MODEL MODPM PMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
APPENDI X A: Test Benches and Macro-models
94
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : C64685 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =0
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 4907e-01
+K2 =4. 6395e-02 K3 =8. 317e+00 K3B =-1. 479e+00
+NPEAK =8. 479e+16 VTH0 =-1. 011e+00
+VOFF =-1. 148e-01 DVT0 =5. 399e-01 DVT1 =4. 112e-01
+DVT2 =-9. 479e-02 KETA =3. 010e-02
+PSCBE1 =5. 000e+09 PSCBE2 =1. 000e-10
+DVT0W =8. 099e-01 DVT1W =1. 480e+05 DVT2W =4. 404e-02
* *** Mobility related model parameters ***
+UA =1. 800e-12 UB =2. 218e-18 UC =-7. 278e-11
+U0 =1. 373e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =9. 736e-02 ETAB =-2. 948e-02
+NFACTOR=7. 046e-01
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =4. 395e+00
+PDI BLC1=2. 037e-02 PDI BLC2=1. 000e-20 DROUT =5. 000e-01
+A0 =1. 386e+00 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 436e+05 AGS =1. 364e-01
+B0 =1. 991e-08 B1 =0. 000e+00 DELTA =1. 000e-02
+PDI BLCB=1. 000e+00
* *** Geometry modulation related parameters ***
+W0 =1. 000e-10 DLC =2. 5000e-08
+DWC =6. 203e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =-9. 750e-16 WWL =-1. 787e-21 WLN =1. 000e+00
+WWN =1. 040e+00
* *** Temperature effect parameters ***
+AT =3. 300e+04 UTE =-1. 300e+00
+KT1 =-6. 003e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =9. 100e-11 CGSO =9. 100e-11 CGBO =1. 100e-10
+CGDL =0. 600e-10 CGSL =0. 600e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =1. 623e+03
+CDSC =1. 214e-03 CDSCB =2. 945e-04 CDSCD =0. 000e+00
+PRWB =-4. 521e-01 PRWG =0. 000e+00 CI T =5. 259e-05
* *** Process and parameters extraction related model parameters ***
+TOX =1. 450e-08 NGATE =0. 000e+00
+NLX =2. 231e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
APPENDI X A: Test Benches and Macro-models
95
+AF =1. 5e+00 KF =9. 4e-27 EF =1. 000e+00
+NOI A =1. 09e+18 NOI B =6. 01e+03 NOI C =1. 19e-12
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =1. 300e+02
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-8. 504e-08
+WD =6. 203e-08
+LDI F =0. 000e+00 HDI F =6. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =9. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =1. 360e-03 CJ SW =3. 200e-10 FC =0. 000e+00
+MJ =5. 600e-01 MJ SW =4. 300e-01 TT =0. 000e+00
+PB =1. 020e+00 PBSW =1. 020e+00
* ----------------------------------------------------------------------
. MODEL MODP PMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : C64685 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =0
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 9959e-01
+K2 =-6. 038e-02 K3 =1. 103e+01 K3B =-7. 580e-01
+NPEAK =9. 240e+16 VTH0 =-6. 915e-01
+VOFF =-1. 170e-01 DVT0 =1. 650e+00 DVT1 =3. 868e-01
+DVT2 =1. 659e-02 KETA =-1. 440e-02
+PSCBE1 =5. 000e+09 PSCBE2 =1. 000e-04
+DVT0W =1. 879e-01 DVT1W =7. 335e+04 DVT2W =-6. 312e-03
* *** Mobility related model parameters ***
+UA =5. 394e-10 UB =1. 053e-18 UC =1. 000e-20
+U0 =1. 482e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =2. 480e-01 ETAB =-3. 917e-03
+NFACTOR=1. 214e+00
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =3. 184e+00
+PDI BLC1=1. 000e-04 PDI BLC2=1. 000e-20 DROUT =5. 000e-01
+A0 =5. 850e-01 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 158e+05 AGS =2. 468e-01
+B0 =8. 832e-08 B1 =0. 000e+00 DELTA =1. 000e-02
+PDI BLCB=1. 000e+00
* *** Geometry modulation related parameters ***
+W0 =1. 000e-10 DLC =2. 4500e-08
+DWC =3. 449e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =1. 894e-16 WWL =-1. 981e-21 WLN =1. 000e+00
+WWN =1. 040e+00
* *** Temperature effect parameters ***
APPENDI X A: Test Benches and Macro-models
96
+AT =3. 300e+04 UTE =-1. 300e+00
+KT1 =-5. 403e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =8. 600e-11 CGSO =8. 600e-11 CGBO =1. 100e-10
+CGDL =1. 080e-10 CGSL =1. 080e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =1. 033e+03
+CDSC =2. 589e-03 CDSCB =2. 943e-04 CDSCD =4. 370e-04
+PRWB =-9. 731e-02 PRWG =1. 477e-01 CI T =0. 000e+00
* *** Process and parameters extraction related model parameters ***
+TOX =7. 754e-09 NGATE =0. 000e+00
+NLX =1. 770e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =1. 48e+00 KF =8. 5e-27 EF =1. 000e+00
+NOI A =1. 52e+18 NOI B =7. 75e+03 NOI C =5. 0e-13
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =1. 290e+02
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-7. 130e-08
+WD =3. 449e-08
+LDI F =0. 000e+00 HDI F =8. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =9. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =1. 360e-03 CJ SW =3. 200e-10 FC =0. 000e+00
+MJ =5. 600e-01 MJ SW =4. 300e-01 TT =0. 000e+00
+PB =1. 020e+00 PBSW =1. 020e+00
* ----------------------------------------------------------------------
. MODEL MODP_not h PMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : C64685 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =1 gdsnoi =t het a
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 9959e-01
+K2 =-6. 038e-02 K3 =1. 103e+01 K3B =-7. 580e-01
+NPEAK =9. 240e+16 VTH0 =-6. 915e-01
+VOFF =-1. 170e-01 DVT0 =1. 650e+00 DVT1 =3. 868e-01
+DVT2 =1. 659e-02 KETA =-1. 440e-02
+PSCBE1 =5. 000e+09 PSCBE2 =1. 000e-04
+DVT0W =1. 879e-01 DVT1W =7. 335e+04 DVT2W =-6. 312e-03
APPENDI X A: Test Benches and Macro-models
97
* *** Mobility related model parameters ***
+UA =5. 394e-10 UB =1. 053e-18 UC =1. 000e-20
+U0 =1. 482e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =2. 480e-01 ETAB =-3. 917e-03
+NFACTOR=1. 214e+00
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =3. 184e+00
+PDI BLC1=1. 000e-04 PDI BLC2=1. 000e-20 DROUT =5. 000e-01
+A0 =5. 850e-01 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 158e+05 AGS =2. 468e-01
+B0 =8. 832e-08 B1 =0. 000e+00 DELTA =1. 000e-02
+PDI BLCB=1. 000e+00
* *** Geometry modulation related parameters ***
+W0 =1. 000e-10 DLC =2. 4500e-08
+DWC =3. 449e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =1. 894e-16 WWL =-1. 981e-21 WLN =1. 000e+00
+WWN =1. 040e+00
* *** Temperature effect parameters ***
+AT =3. 300e+04 UTE =-1. 300e+00
+KT1 =-5. 403e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =8. 600e-11 CGSO =8. 600e-11 CGBO =1. 100e-10
+CGDL =1. 080e-10 CGSL =1. 080e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =1. 033e+03
+CDSC =2. 589e-03 CDSCB =2. 943e-04 CDSCD =4. 370e-04
+PRWB =-9. 731e-02 PRWG =1. 477e-01 CI T =0. 000e+00
* *** Process and parameters extraction related model parameters ***
+TOX =7. 754e-09 NGATE =0. 000e+00
+NLX =1. 770e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =1. 48e+00 KF =8. 5e-27 EF =1. 000e+00
+NOI A =1. 52e+18 NOI B =7. 75e+03 NOI C =5. 0e-13
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =1. 290e+02
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-7. 130e-08
+WD =3. 449e-08
+LDI F =0. 000e+00 HDI F =8. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =9. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =1. 360e-03 CJ SW =3. 200e-10 FC =0. 000e+00
+MJ =5. 600e-01 MJ SW =4. 300e-01 TT =0. 000e+00
+PB =1. 020e+00 PBSW =1. 020e+00
* ----------------------------------------------------------------------
. MODEL MODP_nof l PMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
APPENDI X A: Test Benches and Macro-models
98
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : C64685 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =0
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 9959e-01
+K2 =-6. 038e-02 K3 =1. 103e+01 K3B =-7. 580e-01
+NPEAK =9. 240e+16 VTH0 =-6. 915e-01
+VOFF =-1. 170e-01 DVT0 =1. 650e+00 DVT1 =3. 868e-01
+DVT2 =1. 659e-02 KETA =-1. 440e-02
+PSCBE1 =5. 000e+09 PSCBE2 =1. 000e-04
+DVT0W =1. 879e-01 DVT1W =7. 335e+04 DVT2W =-6. 312e-03
* *** Mobility related model parameters ***
+UA =5. 394e-10 UB =1. 053e-18 UC =1. 000e-20
+U0 =1. 482e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =2. 480e-01 ETAB =-3. 917e-03
+NFACTOR=1. 214e+00
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =3. 184e+00
+PDI BLC1=1. 000e-04 PDI BLC2=1. 000e-20 DROUT =5. 000e-01
+A0 =5. 850e-01 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 158e+05 AGS =2. 468e-01
+B0 =8. 832e-08 B1 =0. 000e+00 DELTA =1. 000e-02
+PDI BLCB=1. 000e+00
* *** Geometry modulation related parameters ***
+W0 =1. 000e-10 DLC =2. 4500e-08
+DWC =3. 449e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =1. 894e-16 WWL =-1. 981e-21 WLN =1. 000e+00
+WWN =1. 040e+00
* *** Temperature effect parameters ***
+AT =3. 300e+04 UTE =-1. 300e+00
+KT1 =-5. 403e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =8. 600e-11 CGSO =8. 600e-11 CGBO =1. 100e-10
+CGDL =1. 080e-10 CGSL =1. 080e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =1. 033e+03
+CDSC =2. 589e-03 CDSCB =2. 943e-04 CDSCD =4. 370e-04
+PRWB =-9. 731e-02 PRWG =1. 477e-01 CI T =0. 000e+00
* *** Process and parameters extraction related model parameters ***
+TOX =7. 754e-09 NGATE =0. 000e+00
+NLX =1. 770e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =AFo KF =KFo EF =EFo
APPENDI X A: Test Benches and Macro-models
99
+NOIA =NOIAo NOIB =NOIBo NOIC =NOICo
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =1. 290e+02
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-7. 130e-08
+WD =3. 449e-08
+LDI F =0. 000e+00 HDI F =8. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =9. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =1. 360e-03 CJ SW =3. 200e-10 FC =0. 000e+00
+MJ =5. 600e-01 MJ SW =4. 300e-01 TT =0. 000e+00
+PB =1. 020e+00 PBSW =1. 020e+00
* ----------------------------------------------------------------------
. MODEL MODP_nof l _not h PMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : C64685 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =1 gdsnoi=theta
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =3. 000e+00 DERI V =1
* *** Threshold voltage related model parameters ***
+K1 =5. 9959e-01
+K2 =-6. 038e-02 K3 =1. 103e+01 K3B =-7. 580e-01
+NPEAK =9. 240e+16 VTH0 =-6. 915e-01
+VOFF =-1. 170e-01 DVT0 =1. 650e+00 DVT1 =3. 868e-01
+DVT2 =1. 659e-02 KETA =-1. 440e-02
+PSCBE1 =5. 000e+09 PSCBE2 =1. 000e-04
+DVT0W =1. 879e-01 DVT1W =7. 335e+04 DVT2W =-6. 312e-03
* *** Mobility related model parameters ***
+UA =5. 394e-10 UB =1. 053e-18 UC =1. 000e-20
+U0 =1. 482e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =2. 480e-01 ETAB =-3. 917e-03
+NFACTOR=1. 214e+00
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =3. 184e+00
+PDI BLC1=1. 000e-04 PDI BLC2=1. 000e-20 DROUT =5. 000e-01
+A0 =5. 850e-01 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =1. 158e+05 AGS =2. 468e-01
+B0 =8. 832e-08 B1 =0. 000e+00 DELTA =1. 000e-02
+PDI BLCB=1. 000e+00
* *** Geometry modulation related parameters ***
+W0 =1. 000e-10 DLC =2. 4500e-08
+DWC =3. 449e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =1. 894e-16 WWL =-1. 981e-21 WLN =1. 000e+00
+WWN =1. 040e+00
* *** Temperature effect parameters ***
APPENDI X A: Test Benches and Macro-models
100
+AT =3. 300e+04 UTE =-1. 300e+00
+KT1 =-5. 403e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =8. 600e-11 CGSO =8. 600e-11 CGBO =1. 100e-10
+CGDL =1. 080e-10 CGSL =1. 080e-10 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =1. 033e+03
+CDSC =2. 589e-03 CDSCB =2. 943e-04 CDSCD =4. 370e-04
+PRWB =-9. 731e-02 PRWG =1. 477e-01 CI T =0. 000e+00
* *** Process and parameters extraction related model parameters ***
+TOX =7. 754e-09 NGATE =0. 000e+00
+NLX =1. 770e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =AFo KF =KFo EF =EFo
+NOIA =NOIAo NOIB =NOIBo NOIC =NOICo
* *** Common extrinsic model parameters ***
+ALEV =2 RLEV =2
+RD =0. 000e+00 RS =0. 000e+00 RSH =1. 290e+02
+RDC =0. 000e+00 RSC =0. 000e+00 LD =-7. 130e-08
+WD =3. 449e-08
+LDI F =0. 000e+00 HDI F =8. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4 J S =9. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =1. 360e-03 CJ SW =3. 200e-10 FC =0. 000e+00
+MJ =5. 600e-01 MJ SW =4. 300e-01 TT =0. 000e+00
+PB =1. 020e+00 PBSW =1. 020e+00
* ----------------------------------------------------------------------
. SUBCKT PD A C PARAM: AREA=1e-12 PERI =4e-6
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : DIODE
* pr ocess : C35
* r evi si on : 2;
* ext r act ed : C64685 ; 2002-12; ese( 487)
* doc# : ENG-182 REV_2
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
* TERMINALS: A=anode=P-region C=cathode=N-region
* VARIABLES: M (muliti pl i er ) , AREA [ m^2] , PERI [ m] .
* NOTE: The role of a protection DIODE is to conduct ESD current to VDD
* (or from VSS). This forward bias is NOT modelled, only leakage current
* and capacitance during normal operation. Any inductive load etc that
* will give forward bias, must be limited by other components to within
* Operating Conditions, otherwise parasitic bipolar action can occur.
*
D1 A C PDI NSUB AREA=AREA PERI =PERI
.ENDS PD
*
. MODEL PDI NSUB D LEVEL=1 MODTYPE=ELDO
+I S =9. 000e-05 I SW =0. 000e+00 N =1. 000e+00
+CJ =1. 360e-03 M =5. 600e-01 VJ =1. 020e+00 TT =0. 000e+00
APPENDI X A: Test Benches and Macro-models
101
+CJ SW =3. 200e-10 MJ SW =4. 300e-01 FC =0. 500e+00
+EG =1. 110e+00 XTI =3. 000e+00 AF =1. 000e+00 KF =0. 000e+00
* ----------------------------------------------------------------------
. SUBCKT MODNH D G S B PARAM: W=1e-6 L=1e-6 AD=0 AS=0 PD=0 PS=0 NRD=0 NRS=0
* VARIABLES: W,L,AD,AS,PD,PS,NRD,NRS = standard MOSFET parameters
*
M1 D1 G S B MODNHI NSUB W=WL=L AD=AD AS=AS PD=PD PS=PS NRD=NRD NRS=NRS
RD D1 D {1. 328e+03*4. 000e-06/ ( W) } TC=6. 200e-03
.ENDS MODNH
. MODEL MODNHI NSUB NMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* pr ocess : C35
* revision : ;
* ext r act ed : C35 B11004. L2; 2002-11; hhl ( 5481)
* doc# : REV_2. 0
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =0. 000e+00
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =1. 000e+00 DERI V =1. 000e+00
* *** Threshold voltage related model parameters ***
+K1 =6. 2697e-01
+K2 =-4. 966e-03 K3 =-2. 240e+00 K3B =6. 954e-01
+NPEAK =2. 236e+17 VTH0 =4. 460e-01
+VOFF =-5. 090e-02 DVT0 =4. 985e+01 DVT1 =1. 296e+00
+DVT2 =1. 311e-02 KETA =-4. 553e-02
+PSCBE1 =1. 000e+10 PSCBE2 =1. 024e-05
+DVT0W =0. 000e+00 DVT1W =0. 000e+00 DVT2W =0. 000e+00
* *** Mobility related model parameters ***
+UA =1. 000e-30 UB =1. 949e-18 UC =1. 217e-10
+U0 =3. 427e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =3. 075e-02 ETAB =-5. 261e-02
+NFACTOR=2. 034e-01
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =2. 940e-01
+PDI BLC1=3. 090e-02 PDI BLC2=6. 375e-04 DROUT =5. 000e-01
+A0 =1. 893e-01 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =2. 402e+05 AGS =1. 245e-01
+B0 =6. 790e-08 B1 =0. 000e+00 DELTA =1. 729e-02
+PDI BLCB=2. 067e-01
* *** Geometry modulation related parameters ***
+W0 =1. 145e-07 DLC =6. 000e-07
+DWC =2. 605e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =0. 000e+00 WWL =0. 000e+00 WLN =1. 000e+00
+WWN =1. 000e+00
* *** Temperature effect parameters ***
+TNOM =2. 700e+01 AT =3. 300e+04 UTE =-1. 800e+00
+KT1 =-3. 302e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =1. 200e-10 CGSO =1. 200e-10 CGBO =1. 100e-10
APPENDI X A: Test Benches and Macro-models
102
+CGDL =0. 000e+00 CGSL =0. 000e+00 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =1. 092e+03
+CDSC =7. 944e-03 CDSCB =0. 000e+00 CDSCD =8. 448e-05
+PRWB =0. 000e+00 PRWG =0. 000e+00 CI T =1. 000e-03
* *** Process and parameters extraction related model parameters ***
+TOX =7. 700e-09 NGATE =0. 000e+00
+NLX =1. 132e-07
+XL =0. 000e+00 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =1. 400e+00 KF =2. 810e-27 EF =1. 000e+00
+NOI A =1. 000e+20 NOI B =5. 000e+04 NOI C =-1. 400e-12
* *** Common extrinsic model parameters ***
+ALEV =2. 000e+00 RLEV =2. 000e+00
+RD =0. 000e+00 RS =0. 000e+00 RSH =8. 200e+01
+RDC =0. 000e+00 RSC =0. 000e+00 LD =6. 000e-07
+WD =2. 605e-08
+LDI F =0. 000e+00 HDI F =6. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4. 000e+00 J S =6. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2. 000e+00 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =8. 000e-05 CJ SW =5. 100e-10 FC =0. 000e+00
+MJ =3. 900e-01 MJ SW =2. 700e-01 TT =0. 000e+00
+PB =5. 300e-01 PBSW =6. 900e-01
* ----------------------------------------------------------------------
. SUBCKT MODNMH D G S B PARAM: W=1e-6 L=1e-6 AD=0 AS=0 PD=0 PS=0 NRD=0 NRS=0
* VARIABLES: W,L,AD,AS,PD,PS,NRD,NRS = standard MOSFET parameters
*
M1 D1 G S B MODNMHI NSUB W=WL=L AD=AD AS=AS PD=PD PS=PS NRD=NRD NRS=NRS
RD D1 D {1. 547e+03*4. 000e-06/ ( W) } TC=6. 200e-03
.ENDS MODNMH
. MODEL MODNMHI NSUB NMOS LEVEL=53 MODTYPE=ELDO
* ----------------------------------------------------------------------
************************* SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO, AccusimII, Continuum
* model : MOS BSI M3v3
* process : C35
* revision : ;
* ext r act ed : C35 B11004. L2; 2002-11; hhl ( 5481)
* doc# : REV_2. 0
* ----------------------------------------------------------------------
* TYPICAL MEAN CONDITION
* ----------------------------------------------------------------------
*
+THMLEV =0. 000e+00
* *** Flags ***
+MOBMOD =1. 000e+00 CAPMOD =2. 000e+00 NQSMOD =0. 000e+00
+NOI MOD =1. 000e+00 DERI V =1. 000e+00
* *** Threshold voltage related model parameters ***
+K1 =9. 5409e-01
+K2 =4. 9101e-02 K3 =-2. 439e+00 K3B =4. 077e-01
+NPEAK =2. 092e+17 VTH0 =6. 449e-01
+VOFF =-4. 948e-02 DVT0 =4. 985e+01 DVT1 =1. 683e+00
+DVT2 =4. 126e-02 KETA =-7. 397e-02
+PSCBE1 =4. 000e+10 PSCBE2 =1. 000e-10
+DVT0W =0. 000e+00 DVT1W =0. 000e+00 DVT2W =0. 000e+00
APPENDI X A: Test Benches and Macro-models
103
* *** Mobility related model parameters ***
+UA =1. 000e-12 UB =3. 768e-19 UC =6. 391e-12
+U0 =4. 394e+02
* *** Subthreshold related parameters ***
+DSUB =5. 000e-01 ETA0 =1. 616e-03 ETAB =-1. 373e-02
+NFACTOR=3. 455e-01
* *** Saturation related parameters ***
+EM =4. 100e+07 PCLM =1. 055e-01
+PDI BLC1=1. 000e-10 PDI BLC2=1. 000e-10 DROUT =5. 000e-01
+A0 =2. 190e-01 A1 =0. 000e+00 A2 =1. 000e+00
+PVAG =0. 000e+00 VSAT =5. 129e+04 AGS =9. 448e-02
+B0 =-3. 629e-08 B1 =0. 000e+00 DELTA =3. 370e-03
+PDI BLCB=3. 872e-01
* *** Geometry modulation related parameters ***
+W0 =6. 289e-08 DLC =8. 917e-08
+DWC =4. 938e-08 DWB =0. 000e+00 DWG =0. 000e+00
+LL =0. 000e+00 LW =0. 000e+00 LWL =0. 000e+00
+LLN =1. 000e+00 LWN =1. 000e+00 WL =0. 000e+00
+WW =0. 000e+00 WWL =0. 000e+00 WLN =1. 000e+00
+WWN =1. 000e+00
* *** Temperature effect parameters ***
+TNOM =2. 700e+01 AT =3. 300e+04 UTE =-1. 760e+00
+KT1 =-4. 502e-01 KT2 =2. 200e-02 KT1L =0. 000e+00
+UA1 =0. 000e+00 UB1 =0. 000e+00 UC1 =0. 000e+00
+PRT =0. 000e+00
* *** Overlap capacitance related and dynamic model parameters ***
+CGDO =1. 080e-10 CGSO =1. 080e-10 CGBO =1. 100e-10
+CGDL =0. 000e+00 CGSL =0. 000e+00 CKAPPA =6. 000e-01
+CF =0. 000e+00 ELM =5. 000e+00
+XPART =1. 000e+00 CLC =1. 000e-15 CLE =6. 000e-01
* *** Parasitic resistance and capacitance related model parameters ***
+RDSW =5. 304e+02
+CDSC =1. 000e-02 CDSCB =0. 000e+00 CDSCD =8. 448e-05
+PRWB =0. 000e+00 PRWG =0. 000e+00 CI T =8. 122e-04
* *** Process and parameters extraction related model parameters ***
+TOX =1. 514e-08 NGATE =0. 000e+00
+NLX =1. 593e-07
+XL =-1. 050e-06 XW =0. 000e+00
* *** Substrate current related model parameters ***
+ALPHA0 =0. 000e+00 BETA0 =3. 000e+01
* *** Noise effect related model parameters ***
+AF =1. 400e+00 KF =2. 810e-27 EF =1. 000e+00
+NOI A =1. 000e+20 NOI B =5. 000e+04 NOI C =-1. 400e-12
* *** Common extrinsic model parameters ***
+ALEV =2. 000e+00 RLEV =2. 000e+00
+RD =0. 000e+00 RS =0. 000e+00 RSH =7. 946e+01
+RDC =0. 000e+00 RSC =0. 000e+00 LD =8. 917e-08
+WD =4. 938e-08
+LDI F =0. 000e+00 HDI F =6. 000e-07 WMLT =1. 000e+00
+LMLT =1. 000e+00 DEL =0. 000e+00 XJ =3. 000e-07
+DI OLEV =4. 000e+00 J S =6. 000e-05 J SW =0. 000e+00
+I S =0. 000e+00 N =1. 000e+00
+DCAPLEV=2. 000e+00 CBD =0. 000e+00 CBS =0. 000e+00
+CJ =8. 000e-05 CJ SW =5. 100e-10 FC =0. 000e+00
+MJ =3. 900e-01 MJ SW =2. 700e-01 TT =0. 000e+00
+PB =5. 300e-01 PBSW =6. 900e-01
* ----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
*-----------------------------------------------------------------------
APPENDI X A: Test Benches and Macro-models
104
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP014S300C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP014S300C N1 N2 N3
LS N1 N1X 1. 245e-09
RS N1X N2 1. 966e+00
CP N1 N2 1. 315e-16
COX1 N1 N3X 2. 992e-13
CSUB1 N3X N3 3. 946e-14
RSUB1 N3X N3 1. 704e+02
COX2 N2 N3Y 3. 240e-13
CSUB2 N3Y N3 2. 561e-16
RSUB2 N3Y N3 1. 810e+02
. ENDS SP014S300C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP018S300C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP018S300C N1 N2 N3
LS N1 N1X 1. 717e-09
RS N1X N2 2. 294e+00
CP N1 N2 2. 782e-15
COX1 N1 N3X 3. 389e-13
CSUB1 N3X N3 2. 590e-14
RSUB1 N3X N3 1. 828e+02
COX2 N2 N3Y 3. 498e-13
CSUB2 N3Y N3 6. 645e-15
RSUB2 N3Y N3 1. 791e+02
. ENDS SP018S300C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
APPENDI X A: Test Benches and Macro-models
105
* model : RF I NDUCTOR SP020S180C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP020S180C N1 N2 N3
LS N1 N1X 1. 936e-09
RS N1X N2 4. 852e+00
CP N1 N2 3. 244e-16
COX1 N1 N3X 1. 392e-13
CSUB1 N3X N3 2. 433e-14
RSUB1 N3X N3 3. 041e+02
COX2 N2 N3Y 1. 463e-13
CSUB2 N3Y N3 1. 000e-16
RSUB2 N3Y N3 3. 223e+02
. ENDS SP020S180C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF INDUCTOR SP023S200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP023S200C N1 N2 N3
LS N1 N1X 2. 037e-09
RS N1X N2 3. 995e+00
CP N1 N2 1. 000e-16
COX1 N1 N3X 2. 472e-13
CSUB1 N3X N3 3. 499e-14
RSUB1 N3X N3 2. 133e+02
COX2 N2 N3Y 2. 526e-13
CSUB2 N3Y N3 1. 001e-16
RSUB2 N3Y N3 2. 714e+02
.ENDS SP023S200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP025C200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
APPENDI X A: Test Benches and Macro-models
106
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP025C200C N1 N2 N3
LS N1 N1X 2. 190e-09
RS N1X N2 4. 117e+00
CP N1 N2 2. 207e-13
COX1 N1 N3X 9. 345e-14
CSUB1 N3X N3 4. 949e-14
RSUB1 N3X N3 5. 214e+02
COX2 N2 N3Y 2. 931e-13
CSUB2 N3Y N3 5. 973e-14
RSUB2 N3Y N3 1. 269e+02
. ENDS SP025C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP026S200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP026S200C N1 N2 N3
LS N1 N1X 2. 536e-09
RS N1X N2 5. 572e+00
CP N1 N2 5. 377e-16
COX1 N1 N3X 1. 618e-13
CSUB1 N3X N3 4. 254e-14
RSUB1 N3X N3 3. 043e+02
COX2 N2 N3Y 1. 603e-13
CSUB2 N3Y N3 1. 159e-14
RSUB2 N3Y N3 3. 447e+02
. ENDS SP026S200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP028C200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
APPENDI X A: Test Benches and Macro-models
107
. SUBCKT SP028C200C N1 N2 N3
LS N1 N1X 2. 791e-09
RS N1X N2 7. 609e+00
CP N1 N2 4. 746e-14
COX1 N1 N3X 1. 505e-13
CSUB1 N3X N3 4. 819e-14
RSUB1 N3X N3 3. 789e+02
COX2 N2 N3Y 1. 850e-13
CSUB2 N3Y N3 4. 382e-14
RSUB2 N3Y N3 2. 077e+02
. ENDS SP028C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP028S300C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP028S300C N1 N2 N3
LS N1 N1X 2. 541e-09
RS N1X N2 2. 983e+00
CP N1 N2 1. 000e-16
COX1 N1 N3X 5. 093e-13
CSUB1 N3X N3 5. 972e-14
RSUB1 N3X N3 1. 554e+02
COX2 N2 N3Y 4. 837e-13
CSUB2 N3Y N3 1. 000e-16
RSUB2 N3Y N3 2. 073e+02
. ENDS SP028S300C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP030C200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP030C200C N1 N2 N3
LS N1 N1X 2. 991e-09
RS N1X N2 1. 041e+01
CP N1 N2 1. 989e-16
COX1 N1 N3X 1. 409e-13
APPENDI X A: Test Benches and Macro-models
108
CSUB1 N3X N3 7. 975e-14
RSUB1 N3X N3 3. 214e+02
COX2 N2 N3Y 1. 466e-13
CSUB2 N3Y N3 5. 584e-14
RSUB2 N3Y N3 1. 916e+02
. ENDS SP030C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP037S180C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP037S180C N1 N2 N3
LS N1 N1X 3. 681e-09
RS N1X N2 1. 018e+01
CP N1 N2 8. 527e-16
COX1 N1 N3X 1. 030e-13
CSUB1 N3X N3 6. 752e-14
RSUB1 N3X N3 3. 287e+02
COX2 N2 N3Y 9. 526e-14
CSUB2 N3Y N3 3. 717e-14
RSUB2 N3Y N3 3. 447e+02
. ENDS SP037S180C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP038S300C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP038S300C N1 N2 N3
LS N1 N1X 3. 670e-09
RS N1X N2 4. 388e+00
CP N1 N2 3. 098e-14
COX1 N1 N3X 5. 788e-13
CSUB1 N3X N3 7. 587e-14
RSUB1 N3X N3 1. 531e+02
COX2 N2 N3Y 5. 451e-13
CSUB2 N3Y N3 2. 057e-16
RSUB2 N3Y N3 1. 952e+02
APPENDI X A: Test Benches and Macro-models
109
. ENDS SP038S300C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP040C200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP040C200C N1 N2 N3
LS N1 N1X 3. 612e-09
RS N1X N2 7. 711e+00
CP N1 N2 1. 010e-13
COX1 N1 N3X 2. 004e-13
CSUB1 N3X N3 3. 818e-14
RSUB1 N3X N3 3. 205e+02
COX2 N2 N3Y 2. 532e-13
CSUB2 N3Y N3 2. 871e-14
RSUB2 N3Y N3 1. 865e+02
. ENDS SP040C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP040C300C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP040C300C N1 N2 N3
LS N1 N1X 3. 557e-09
RS N1X N2 4. 508e+00
CP N1 N2 4. 614e-13
COX1 N1 N3X 1. 818e-13
CSUB1 N3X N3 7. 188e-14
RSUB1 N3X N3 4. 740e+02
COX2 N2 N3Y 5. 108e-13
CSUB2 N3Y N3 1. 847e-14
RSUB2 N3Y N3 9. 825e+01
. ENDS SP040C300C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
APPENDI X A: Test Benches and Macro-models
110
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP045C200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP045C200C N1 N2 N3
LS N1 N1X 4. 337e-09
RS N1X N2 7. 017e+00
CP N1 N2 3. 506e-13
COX1 N1 N3X 1. 796e-13
CSUB1 N3X N3 3. 213e-14
RSUB1 N3X N3 5. 880e+02
COX2 N2 N3Y 3. 692e-13
CSUB2 N3Y N3 4. 011e-14
RSUB2 N3Y N3 1. 445e+02
. ENDS SP045C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP047S180C
* pr ocess : C/ B/ S 35
* revision : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP047S180C N1 N2 N3
LS N1 N1X 4. 672e-09
RS N1X N2 1. 196e+01
CP N1 N2 9. 935e-16
COX1 N1 N3X 1. 117e-13
CSUB1 N3X N3 7. 429e-14
RSUB1 N3X N3 2. 685e+02
COX2 N2 N3Y 1. 004e-13
CSUB2 N3Y N3 3. 081e-14
RSUB2 N3Y N3 3. 368e+02
. ENDS SP047S180C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP050S155C
APPENDI X A: Test Benches and Macro-models
111
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP050S155C N1 N2 N3
LS N1 N1X 5. 296e-09
RS N1X N2 1. 603e+01
CP N1 N2 1. 162e-15
COX1 N1 N3X 8. 263e-14
CSUB1 N3X N3 4. 827e-14
RSUB1 N3X N3 3. 489e+02
COX2 N2 N3Y 8. 589e-14
CSUB2 N3Y N3 2. 731e-14
RSUB2 N3Y N3 4. 155e+02
. ENDS SP050S155C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP051C300C
* process : C/B/S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
.SUBCKT SP051C300C N1 N2 N3
LS N1 N1X 4. 895e-09
RS N1X N2 5. 945e+00
CP N1 N2 5. 619e-13
COX1 N1 N3X 3. 272e-13
CSUB1 N3X N3 6. 843e-14
RSUB1 N3X N3 2. 925e+02
COX2 N2 N3Y 6. 784e-13
CSUB2 N3Y N3 3. 851e-14
RSUB2 N3Y N3 1. 002e+02
. ENDS SP051C300C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP068C300C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
APPENDI X A: Test Benches and Macro-models
112
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP068C300C N1 N2 N3
LS N1 N1X 6. 433e-09
RS N1X N2 6. 803e+00
CP N1 N2 7. 733e-13
COX1 N1 N3X 3. 100e-13
CSUB1 N3X N3 5. 860e-14
RSUB1 N3X N3 3. 875e+02
COX2 N2 N3Y 7. 909e-13
CSUB2 N3Y N3 5. 427e-14
RSUB2 N3Y N3 1. 053e+02
. ENDS SP068C300C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP090C200C
* process : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP090C200C N1 N2 N3
LS N1 N1X 8. 769e-09
RS N1X N2 1. 275e+01
CP N1 N2 3. 645e-13
COX1 N1 N3X 1. 523e-13
CSUB1 N3X N3 5. 968e-14
RSUB1 N3X N3 5. 178e+02
COX2 N2 N3Y 3. 605e-13
CSUB2 N3Y N3 6. 564e-14
RSUB2 N3Y N3 1. 471e+02
. ENDS SP090C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP090S155C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP090S155C N1 N2 N3
APPENDI X A: Test Benches and Macro-models
113
LS N1 N1X 9. 088e-09
RS N1X N2 3. 041e+01
CP N1 N2 1. 093e-15
COX1 N1 N3X 7. 481e-14
CSUB1 N3X N3 4. 402e-14
RSUB1 N3X N3 2. 830e+02
COX2 N2 N3Y 8. 410e-14
CSUB2 N3Y N3 3. 604e-14
RSUB2 N3Y N3 3. 926e+02
. ENDS SP090S155C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF INDUCTOR SP112C300C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP112C300C N1 N2 N3
LS N1 N1X 1. 122e-08
RS N1X N2 1. 113e+01
CP N1 N2 6. 914e-13
COX1 N1 N3X 3. 096e-13
CSUB1 N3X N3 1. 461e-13
RSUB1 N3X N3 3. 394e+02
COX2 N2 N3Y 7. 005e-13
CSUB2 N3Y N3 4. 202e-14
RSUB2 N3Y N3 1. 045e+02
. ENDS SP112C300C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP140C200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP140C200C N1 N2 N3
LS N1 N1X 1. 403e-08
RS N1X N2 2. 035e+01
CP N1 N2 3. 788e-13
COX1 N1 N3X 1. 229e-13
CSUB1 N3X N3 7. 911e-14
APPENDI X A: Test Benches and Macro-models
114
RSUB1 N3X N3 3. 914e+02
COX2 N2 N3Y 3. 549e-13
CSUB2 N3Y N3 7. 239e-14
RSUB2 N3Y N3 1. 382e+02
. ENDS SP140C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP200C200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP200C200C N1 N2 N3
LS N1 N1X 2. 020e-08
RS N1X N2 2. 894e+01
CP N1 N2 3. 916e-13
COX1 N1 N3X 4. 121e-13
CSUB1 N3X N3 1. 056e-13
RSUB1 N3X N3 2. 238e+03
COX2 N2 N3Y 3. 313e-13
CSUB2 N3Y N3 5. 000e-16
RSUB2 N3Y N3 1. 556e+02
. ENDS SP200C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SY014C165C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SY014C165C N1 N2 N3
LS N1 N1X 1. 396e-09
RS N1X N2 3. 185e+00
CP N1 N2 5. 056e-15
COX1 N1 N3X 1. 433e-13
CSUB1 N3X N3 7. 393e-15
RSUB1 N3X N3 3. 312e+02
COX2 N2 N3Y 1. 410e-13
CSUB2 N3Y N3 4. 530e-15
RSUB2 N3Y N3 3. 097e+02
. ENDS SY014C165C
APPENDI X A: Test Benches and Macro-models
115
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SY015C200C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SY015C200C N1 N2 N3
LS N1 N1X 1. 419e-09
RS N1X N2 3. 327e+00
CP N1 N2 2. 640e-16
COX1 N1 N3X 2. 167e-13
CSUB1 N3X N3 1. 531e-14
RSUB1 N3X N3 2. 570e+02
COX2 N2 N3Y 2. 168e-13
CSUB2 N3Y N3 2. 631e-15
RSUB2 N3Y N3 2. 328e+02
. ENDS SY015C200C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SY016C180C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SY016C180C N1 N2 N3
LS N1 N1X 1. 524e-09
RS N1X N2 3. 324e+00
CP N1 N2 1. 000e-16
COX1 N1 N3X 1. 796e-13
CSUB1 N3X N3 3. 165e-14
RSUB1 N3X N3 2. 961e+02
COX2 N2 N3Y 1. 734e-13
CSUB2 N3Y N3 2. 573e-14
RSUB2 N3Y N3 2. 843e+02
. ENDS SY016C180C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
APPENDI X A: Test Benches and Macro-models
116
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SY017C165C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SY017C165C N1 N2 N3
LS N1 N1X 1. 692e-09
RS N1X N2 4. 170e+00
CP N1 N2 1. 000e-16
COX1 N1 N3X 1. 696e-13
CSUB1 N3X N3 1. 106e-14
RSUB1 N3X N3 3. 263e+02
COX2 N2 N3Y 1. 681e-13
CSUB2 N3Y N3 2. 775e-15
RSUB2 N3Y N3 3. 010e+02
. ENDS SY017C165C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SY019C180C
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SY019C180C N1 N2 N3
LS N1 N1X 1. 889e-09
RS N1X N2 4. 250e+00
CP N1 N2 1. 000e-16
COX1 N1 N3X 1. 989e-13
CSUB1 N3X N3 1. 609e-14
RSUB1 N3X N3 3. 043e+02
COX2 N2 N3Y 1. 954e-13
CSUB2 N3Y N3 1. 150e-14
RSUB2 N3Y N3 2. 821e+02
. ENDS SY019C180C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SY028C160C
* pr ocess : C/ B/ S 35
APPENDI X A: Test Benches and Macro-models
117
* r evi si on : 3. 0;
* ext r act ed : C35; 2002-06; mer ( 5617)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SY028C160C N1 N2 N3
LS N1 N1X 2. 823e-09
RS N1X N2 6. 581e+00
CP N1 N2 2. 760e-15
COX1 N1 N3X 1. 545e-13
CSUB1 N3X N3 3. 957e-14
RSUB1 N3X N3 4. 039e+02
COX2 N2 N3Y 1. 230e-13
CSUB2 N3Y N3 2. 642e-14
RSUB2 N3Y N3 3. 668e+02
. ENDS SY028C160C
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP014S300D
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* extracted : C35B4 B11404 022PD2; 2003-02; kmo( 5966)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP014S300D N1 N2 N3
LS N1 N1X 1. 334e-09
RS N1X N2 2. 146e+00
CP N1 N2 1. 448e-14
COX1 N1 N3X 8. 332e-13
CSUB1 N3X N3 1. 699e-14
RSUB1 N3X N3 3. 868e+02
COX2 N2 N3Y 9. 089e-13
CSUB2 N3Y N3 5. 473e-17
RSUB2 N3Y N3 3. 855e+02
. ENDS SP014S300D
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP020S180D
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35B4 B11404 022PD2; 2003-02; kmo( 5966)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
APPENDI X A: Test Benches and Macro-models
118
*
* ----------------------------------------------------------------------
*
. SUBCKT SP020S180D N1 N2 N3
LS N1 N1X 2. 006e-09
RS N1X N2 5. 116e+00
CP N1 N2 1. 094e-16
COX1 N1 N3X 4. 962e-13
CSUB1 N3X N3 1. 404e-14
RSUB1 N3X N3 6. 657e+02
COX2 N2 N3Y 5. 224e-13
CSUB2 N3Y N3 3. 794e-15
RSUB2 N3Y N3 6. 229e+02
. ENDS SP020S180D
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP026S200D
* process : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35B4 B11404 022PD2; 2003-02; kmo( 5966)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP026S200D N1 N2 N3
LS N1 N1X 2. 606e-09
RS N1X N2 6. 107e+00
CP N1 N2 1. 000e-18
COX1 N1 N3X 4. 360e-13
CSUB1 N3X N3 4. 009e-14
RSUB1 N3X N3 7. 196e+02
COX2 N2 N3Y 3. 409e-13
CSUB2 N3Y N3 2. 566e-14
RSUB2 N3Y N3 6. 595e+02
. ENDS SP026S200D
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP037S180D
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35B4 B11404 022PD2; 2003-02; kmo( 5966)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP037S180D N1 N2 N3
LS N1 N1X 3. 744e-09
APPENDI X A: Test Benches and Macro-models
119
RS N1X N2 1. 244e+01
CP N1 N2 1. 000e-18
COX1 N1 N3X 7. 453e-14
CSUB1 N3X N3 5. 421e-14
RSUB1 N3X N3 4. 634e+02
COX2 N2 N3Y 6. 469e-14
CSUB2 N3Y N3 4. 133e-14
RSUB2 N3Y N3 4. 573e+02
. ENDS SP037S180D
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP047S180D
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35B4 B11404 022PD2; 2003-02; kmo( 5966)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP047S180D N1 N2 N3
LS N1 N1X 4. 753e-09
RS N1X N2 1. 426e+01
CP N1 N2 1. 000e-18
COX1 N1 N3X 7. 813e-14
CSUB1 N3X N3 6. 025e-14
RSUB1 N3X N3 3. 728e+02
COX2 N2 N3Y 6. 934e-14
CSUB2 N3Y N3 3. 945e-14
RSUB2 N3Y N3 4. 206e+02
. ENDS SP047S180D
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP050S155D
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35B4 B11404 022PD2; 2003-02; kmo( 5966)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP050S155D N1 N2 N3
LS N1 N1X 5. 367e-09
RS N1X N2 2. 179e+01
CP N1 N2 9. 593e-16
COX1 N1 N3X 4. 422e-14
CSUB1 N3X N3 2. 801e-14
RSUB1 N3X N3 2. 752e+02
APPENDI X A: Test Benches and Macro-models
120
COX2 N2 N3Y 5. 982e-14
CSUB2 N3Y N3 2. 994e-14
RSUB2 N3Y N3 6. 127e+02
. ENDS SP050S155D
*----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
* *********************** SIMULATION PARAMETERS ************************
* ----------------------------------------------------------------------
* format : ELDO
* model : RF I NDUCTOR SP090S155D
* pr ocess : C/ B/ S 35
* r evi si on : 3. 0;
* ext r act ed : C35B4 B11404 022PD2; 2003-02; kmo( 5966)
* doc# : ENG-188 REV_3
* ----------------------------------------------------------------------
*
*
* ----------------------------------------------------------------------
*
. SUBCKT SP090S155D N1 N2 N3
LS N1 N1X 9. 175e-09
RS N1X N2 3. 327e+01
CP N1 N2 4. 034e-15
COX1 N1 N3X 5. 104e-14
CSUB1 N3X N3 3. 771e-14
RSUB1 N3X N3 3. 746e+02
COX2 N2 N3Y 4. 851e-14
CSUB2 N3Y N3 2. 498e-14
RSUB2 N3Y N3 5. 606e+02
. ENDS SP090S155D
*----------------------------------------------------------------------
* Owner: austriamicrosystems
* HIT-Kit: Digital
A.2.1 Transistor under switched biasing macro-model:

. subckt snmos d g s b par am: wo=10u l o=0. 35u mo=1 f s=1k bet a=3
**********
**********
. subckt zzl i n out par am: f c=1k
r i n i n 0 1 nonoi se
E1 1 0 i n 0 1
r 1 1 2 r 1 nonoi se
c2 2 0 c2
g1 0 out 2 0 1
. par amr 1=1
. par amomga_c=2*3. 14*f c
.param c2=1/ ( r 1*omga_c)
.ends
APPENDI X A: Test Benches and Macro-models
121
*********
**********
. subckt zzh i n out par am: f c=1k
r i n i n 0 1 nonoi se
E1 1 0 i n 0 1
c1 1 2 c1
r 2 2 0 r 2 nonoi se
g1 0 out 2 0 1
. par amr 2=1
. par amomga_c=2*3. 14*f c
. par amc1=1/ ( r 2*omga_c)
.ends
*********
mo d g s b modn_nofl w=wo l=lo m=mo
. par amf z=0. 1*f s
. par amf p=0. 1*f s
g1 s uu vn 0 o_over _bet a !! flicker
x1 uu d zzl f c=f z !! flicker
. par amo_over _bet a=1/ bet a
g2 s 2uu vn 0 1 !! flicker
x2 2uu d zzh f c=f p !! flicker
mf l i cker 3 6 7 5 modn_not h w=wo l =l o m=mo
vsen1 3 4 dc 0
ed1 4 0 d 0 1
eg1 6 0 g 0 1
es1 7 0 s 0 1
eb1 5 0 b 0 1
mno_noi se 9 11 12 10 modn w=wo l =l o m=mo nonoi se
vsen2 9 8 dc 0
ed2 8 0 d 0 1
eg2 11 0 g 0 1
es2 12 0 s 0 1
eb2 10 0 b 0 1
f f l i cker 0 vn vsen1 1
f nonoi se vn 0 vsen2 1
r con vn 0 1 nonoise
APPENDI X A: Test Benches and Macro-models
122
.ends
. subckt spmos d g s b par am: wo=10u l o=0. 35u mo=1 f s=1k bet a=3
**********
**********
. subckt zzl i n out par am: f c=1k
r i n i n 0 1 nonoi se
E1 1 0 i n 0 1
r 1 1 2 r 1 nonoi se
c2 2 0 c2
g1 0 out 2 0 1
. par amr 1=1
. par amomga_c=2*3. 14*fc
. par amc2=1/ ( r 1*omga_c)
.ends
*********
**********
. subckt zzh i n out par am: f c=1k
r i n i n 0 1 nonoi se
E1 1 0 i n 0 1
c1 1 2 c1
r 2 2 0 r 2 nonoi se
g1 0 out 2 0 1
. par amr 2=1
. par amomga_c=2*3. 14*f c
. par amc1=1/ ( r 2*omga_c)
.ends
*********
mo d g s b modp_nofl w=wo l=lo m=mo
. par amf z=0. 1*f s
. par amf p=0. 1*f s
g1 s uu vn 0 o_over _bet a !! flicker
x1 uu d zzl f c=f z !! flicker
. par amo_over _bet a=1/ bet a
APPENDI X A: Test Benches and Macro-models
123
g2 s 2uu vn 0 1 !! flicker
x2 2uu d zzh f c=f p !! flicker
mf l i cker 3 6 7 5 modp_not h w=wo l =lo m=mo
vsen1 3 4 dc 0
ed1 4 0 d 0 1
eg1 6 0 g 0 1
es1 7 0 s 0 1
eb1 5 0 b 0 1
mno_noi se 9 11 12 10 modp w=wo l =l o m=mo nonoi se
vsen2 9 8 dc 0
ed2 8 0 d 0 1
eg2 11 0 g 0 1
es2 12 0 s 0 1
eb2 10 0 b 0 1
f f l i cker 0 vn vsen1 1
f nonoi se vn 0 vsen2 1
rcon vn 0 1 nonoi se
.ends























Appendix B: Calculation of I SF for Sinusoidal Wave
124
APPENDIX B: Calculation of ISF for
Ideal LC Oscillator.
Consider the LC oscillator of Fig. B.1.Assuming that the tank has maximum
voltage amplitude of V
0
, the voltage across the capacitor and the current
through the inductor can be written as:





Fig. B.1 An ideal LC oscillator, with the maximum voltage amplitude of V0
[2]

) cos( ) (
0
t t V
V
ω =
(B-1)
) sin( ) (
0
t
L
C
t i
V
ω =

Where L and C are the values of inductor and capacitor, respectively and
LC / 1 = ω is the angular frequency of oscillation.








Fig. B.2. Induced phase and amplitude changes due to a change in the
voltage [2]
Appendix B: Calculation of I SF for Sinusoidal Wave
125



If a current impulse with an area of ∆q is injected into the tank at t=t
0
, it will
induce a voltage change of ∆q/C in the capacitor voltage, as shown in Fig.
B.2.Therefore, the capacitor voltage at t
0
+
is C q
t
/ ) cos(
0 0
∆ + ω
ν
and the
inductor current does not change and is ) sin( /
0 0 t
L C ω
ν
the capacitor
voltage and inductor current after
t0
will be sinusoid with a phase shift, φ ∆ ,
and amplitude change, ν ∆ , with respect to the initial sinusoid, i.e.…

) cos( ) ( ) (
0
φ ω ν ν ∆ + ∆ + = t t
v

(B-2)
) sin( ) ( ) (
0
φ ω ν
ν
∆ + ∆ + = t
L
C
t i



The voltage and current given by (B-2) should be equal to the initial
condition at t
0
+


C
q
t t v

+ = ∆ + ∆ + ) cos( ) cos( ) (
0 0 0 0
ω φ ω ν
ν

(B-3)
) sin( ) sin( ) (
0 0 0 0 t t
ω φ ω ν
ν ν
= ∆ + ∆ +


Expanding the cosine and sine functions (B-3) can be written as

C
q
t t t

+ = ∆ − ∆ ∆ + ) cos( )] sin( ) sin( ) cos( ) )[cos( (
0 0 0 0 0
ω φ ω φ ω ν
ν ν


(B-5)
) sin( )] sin( ) cos( ) cos( ) )[sin( (
0 0 0 0 0 t t t
ω φ ω φ ω ν
ν ν
= ∆ + ∆ ∆ +



Appendix B: Calculation of I SF for Sinusoidal Wave
126
Since φ ∆ and ν ∆ are small, cos 1 ) ( ≈ ∆φ , sin φ φ ∆ ≈ ∆ ) ( and
ν
ν
0 0
≈ ∆ +
v

, are valid approximation. Using these approximations, (B-4) can be written
as

C
q
t t

= ∆ − ∆ ) sin( ) cos(
0 0 0
ω φ ω ν
ν


(B-6)
0 ) cos( ) sin(
0 0 0
= ∆ + ∆
t t
ω φ ω ν
ν



Multiply the first and second equations in (B-5) by sin ) (
0 t
ω and cos ) (
0 t
ω
respectively, and subtracting the first from the second, the following is
obtained
) sin(
0
0
t
c
q
ω φ
ν

− = ∆ (B-7)



And, therefore, the phase impulse response is
) (
) sin(
) , ( τ
χ
ωτ
τ
φ


= t u
qma
t
h
(B-8)

Comparing (B-7) with (4.3), the phase ISF for an ideal oscillator is


) sin( ) ( χ χ − = Γ (B-10)
1

Bibliography
127
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[1] Behzad Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE
J ournal Of Solid-State Circuits, vol. 31, no. 3, pp. 331-343, Mar. 1996.
[2] Ali Hajimiri and Thomas H. Lee, The Design of Low Noise
Oscillators. 1999 Kluwer Academic Publishers.
[3] Asad A. Abidi, Analog Circuit Design-RF Analog-to-Digital Con-
verters; Sensor and Actuator Interfaces; Low-Noise Oscillators, PLLs
and Synthesizers. 1997 Kluwer Academic Publishers.
[4] Thomas H. Lee, and Ali Hajimiri, “Oscillator Phase Noise: A
Tutorial,” IEEE J ournal Of Solid-State Circuits, vol. 35, no. 3, Mar
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[5] Thomas H. Lee, and Ali Hajimiri, “A General Theory of Phase Noise
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33, no. 2, Feb 1998.
[6] Ali Hajimiri and Thomas H. Lee, “Phase Noise in CMOS Differential
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[7] Asaad Abidi and A. Kral, “RF-CMOS Oscillators with Switched
Tuning,” in CustomIC Conf. 1998.
[8] J ae J oon Kim and Beomsup Kim, “ A Low Phase Noise CMOS LC
Oscillator with ring structure,” in Solid-State Circuits Conference,
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[9] HongMo Wang, “A Solution for Minimizing Phase Noise in Low-
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[10] Bram De Muer, M. Borremans, M. Steyaert, and G. Li Puma, “A 2-
GHz Low-Phase-Noise Integrated LC-VCO Set with Flicker-Noise
Upconversion Minimization,” IEEE J ournal of Solid-State Circuits,
vol. 35 no. 7, pp. 1034 – 1038, J uly 2000.
[11] Hegazi E., Sjoland. H. and Abidi A., “A filtering technique to lower
oscillator phase noise,” IEEE J ournal of Solid-State Circuits, vol. 36
no. 12, pp. 1921-1930, Dec 2001.
[12] Pietro Andreani, and Henrik Sjِland, “Tail Current Noise Suppression
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3, pp. 342 –348, Mar 2002.
[13] Eric A. M. Klumperink, Sander L. J . Gierkink, Arnoud P. van der Wel
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Consumption by Switched Biasing,” IEEE J ournal of Solid-State
Circuits, vol. 35 no. 7, pp. 994 –1001, J uly 2000.
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[15] C. Samori, A. L. Lacaita, A. Zanchi, S. Levantino and G. Cali, “Phase
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[16] Maria del Mar Hershenson, Ali Hajimiri, Sunderarajan S. Mohan,
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CEIT;Frank Oehler, Heiko Hein and J osef Sauerer, “A Guide for On-
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[19] Y. Hong and M. Frei, “An Approach for Fabricating High-
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[21] P. Yue, “On-chip Spiral Inductors with Patterned Ground Shields for
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[22] K. Khong, G. Kenneth, “Characteristics of an Integrated Spiral
Inductor with an Underlying N-well,” IEEE Transactions on Electron
Devices, vol. 44, no. 9, Sep 1997.
[23] A. Niknejad and R. Meyer, “Analysis, Design and Optimization of
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Solid State Circuits, vol. 33, Oct 1998.
[24] A. Kral, “A 2.4 GHz CMOS Frequency Synthesizer,” UCLA, Mar
1998.
[25] N. Nguyen, R. Meyer, “Si IC-Compatible Inductor and LC Passive
Filters,” IEEE J ournal of Solid State Circuits, vol. 25, Aug 1990.
[26] J . Burghartz, D.C. Edelstein and M. Soyuer, “RF Circuit Design
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CMOS Measurements,” Proceedings of IEEE International
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