FiniteStateMachines

Slidesbasedonchapter8ofBrownand
VranesicText

SachinB.Patkar

Combinational
circuit

Flipflops

Combinational
circuit

Clock

Figure8.1Thegeneralformofasequentialcircuit

ASequenceRecognizer
Assumeonenonglitchyinput,w,andoneoutput,
z.
Assumechangesinwoccur,ifatall,immediately
aftertheactiveclockedge(thatis,wisstablefor
almostwholeclockcycleandthereforewecan
considerthisstablevalueasthatofwfortheclock
cycle
zis1ifwis1duringlasttwoclockcycles.
Clockcycle: t0

t1

t2

t3

t4

t5

t6

t7

t8

t9

t10

w:

z:

Figure8.2Sequencesofinputandoutputsignals

Reset
w =1
w =0

A z =0

B z =0
w =0
w =1

w =0

C z =1

w =1

Figure8.3Statediagramofasimplesequentialcircuit

Next state Output

Present
state w= 0 w= 1
z
A
B
C

A
A
A

B
C
C

0
0
1

Figure8.4Statetable

Y1

y1

Combinational
circuit

Combinational
circuit

Y2

y2

Clock

Figure8.5Ageneralsequentialcircuit

Present
state

Nextstate
w = 0

w = 1

Output
z

y y
2 1

Y Y
2 1

Y Y
2 1

00

00

01

01

00

10

10

00

10

11

dd

dd

Figure8.6AStateassignedtable

y y
2 1
w
0
1

11

10

00

01

11

10

= wy y
1 2

= wy y + wy y
1 2
1 2

= wy y
1 2

= wy

+ wy
1
2
= w(y + y )
1
2

y
1

0
1

01

Usingdon'tcares

y y
2 1

y
2

00

Ignoringdon'tcares

z = y y
1 2

z = y
2

Figure8.7Derivationoflogicexpressions

Y2

y2

Y1

y1

Clock
Resetn

Figure8.8Sequentialcircuit

t0
Clock

y1
y2

t1

t2

t3

t4

t5

t6

t7

t8

t9

t10

1
0
1
0
1
0
1
0
1
0

Figure8.9Timingdiagram

FSMbasedDesign:Mechanical
Procedure

Verbosespecificationofthedesiredcircuit.
Astatediagramfromspecs.
Astatetablefromstatediagram.
Stateminimization(optional).
Stateassignment.
Logicexpressionsfornextstateandoutput.
Realizationofthelogicexpression

MealyFSM
Themachinethatwesaw,hadtheoutput
dependentonlyonthepresentstate.Thatisa
Mooremachine
Ontheotherhand,inMealyFSMmachines
outputdependsonbothpresentstateandcurrent
inputs.

Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0
1
z: 0 0 0 0 1 0 0 1 1 0
0

Figure8.22Sequencesofinputandoutput
signals

Reset
w=1 z =0
w =0 z =0

w =1 z =1

B
w=0 z =0

Nextstate
Output z
Present
state w = 0 w = 1 w = 0 w = 1
A
B

A
A

B
B

0
0

0
1

Figure8.23Statediagram

Nextstate
Output z
Present
state w = 0 w = 1 w = 0 w = 1
A
B

A
A

B
B

0
0

0
1

Nextstate
Output
Present
state w = 0 w = 1 w= 0 w = 1
A
B

0
1

0
0

1
1

0
0

0
1

Figure8.24Statetable

z
w

Clock

Resetn
(a)Circuit

Clock

1
0

1
0

1
0

1
0

t0

t1

t2

t3

t4

t5

t6

t7

t8

t9

(b)Timingdiagram

Figure8.26FSMimplementation

t10

Q
Clock
Resetn
(a)Circuit

t0
Clock
w
y
z
Z

t1

t2

t3

t4

t5

t6

t7

1
0
1
0
1
0
1
0
1
0

(b)Timingdiagram

Figure8.27FSMimplementation

t8

t9

t10

a
Shiftregister
Adder
FSM

s
Shiftregister

Shiftregister
b
Sum = A+ B
B
Clock

Figure8.39Blockdiagramofaserial
adder

Reset

ab s

11 0
00 0
01 1
10 1

01 0
10 0
11 1

00 1
G: carry-in = 0
H: carry-in = 1

Figure8.40Statediagramfortheserial

adder

Nextstate
Present
state ab =00 01 10
G
H

G
G

G
H

G
H

Output s
11

00

01

10

11

H
H

0
1

1
0

1
0

0
1

Nextstate

Present
state ab =00
y
0
1

01

10

Output
11

00

01

Y
0
0

0
1

10

11

1
0

0
1

s
0
1

1
1

0
1

1
0

Figure8.41Statetablefortheserialadder

a
b

Full
adder

s
Y

D
carry-out

Clock

Reset

Figure8.43CircuitfortheadderFSM

Reset

00

01
10

01
10

11

G0 s = 0

H0 s = 0

00
00

G1 s = 1

11

00

11

01
10

01
10

H1 s = 1

11

Figure8.44StatediagramfortheMoore

typeserialadderFSM

Nextstate
Present
state
ab =00 01 10
G0
G1
H0
H1

G0
G0
G1
G1

Present
state ab =00
y2y1
00
01
10
11

G1
G1
H0
H0

G1
G1
H0
H0

11

Output
s

H0
H0
H1
H1

0
1
0
1

11

Output

Nextstate

00
00
01
01

01

10

Y2Y1
01
01
10
10

01
01
10
10

10
10
11
11

0
1
0
1

Figure8.45StatetablefortheMooretypeserialadder

FSM

a
b

Sum bit
Full
adder

Y1

Carry-out

Y2

Clock

y1

y2

Reset

Figure8.47CircuitfortheMooretypeserialadder

FSM

w =0

A/0

w =0

w =1

B/1

w =0

w =1

C/2

w =0

w =1

w =1

H/7

w =0

D/3

w =1

w =1

G/6

w =1

w =0

F/5

w =0

w =1

E/4

w =0

Figure8.60Statediagramforacounter

Nextstate
Present
Output
state w = 0 w = 1
A
B
C
D
E
F
G
H

A
B
C
D
E
F
G
H

B
C
D
E
F
G
H
A

0
1
2
3
4
5
6
7

Figure8.61Statetableforthecounter

Present
state
y2y1y0
A
B
C
D
E
F
G
H

000
001
010
011
100
101
110
111

Nextstate
w = 0

w = 1

Y2Y1Y0

Y2Y1Y0

000
001
010
011
100
101
110
111

001
010
011
100
101
110
111
000

Count
z2z1z0
000
001
010
011
100
101
110
111

Figure8.62Stateassignedtableforthe

counter

wy2

y1y0

wy2

00 01 11 10

y1y0
00 01 11 10

00

00

01

01

11

11

10

10

Y0 = wy0 +wy0

Y1 = wy1 +y1y0 +wy0y1

wy2

y1y0
00 01 11 10
00

01

11

10

Y 2 = wy2 +y0y2 +y1y2 +wy0y1y2

Figure8.63KarnaughmapsforDflipflopsforthe

counter

Y0

y0

Y1

y1

Y2

y2

Clock
Resetn

Figure8.64Circuitdiagramforthecounter