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ACADEMIC YEAR: 2012 – 2013 OBECTIVE QUESTIONS Subject: VLSI Design (R 09) ,Common to ECE &EIE Class : I11B.TECH. II SEM Faculty : K.Murali/ B. Gopichandra kumar/ R.Gunasekhar
UNIT - 1
Multiple choice 1. The speed – power product of any MOS technology is measured in [ C ] a)KJ b) MW-sec c) PJ d) Joules 2. For depletion mode MOSFET, threshold voltage [ D ] a) 0.2 V DD b) -0.2 V DD c) 0.8 V DD d) -0.8 V DD 3. The technology which is characterized by high speed [ D ] a)CMOS b) BICMOS c) GaAs d)ECL 4. Latch up in CMOS device can be avoided by [ B ] A) Increasing temp b) doping control c) increasing the substrate resistance d)decreasing substrate doping level 5. Material used for metallization is [ A ] a)Aluminum b) copper c)silver d)tungsten 6. Material used for gate oxide in MOS technology. [ C ] a) Si b) Ge c) Sio2 d) AlO2 7. Poly silicon is a _________ material [ C ] a) Crystalline b) Amorphous c) Poly crystalline d) None 8. Silicide is combination of [ A ] a) Metal –poly b) Metal-Silicon c) Metal-Ge d) Metal-SiO2 9. In modern CMOS fabrication, the pattern on each layer is created by a) Ion implantation b) Oxidation c) Photo lithography d) Encapsulation 10. The advantage of twin- tub process [ C ] a) Low complexity b) Low cost depletion c) Latch up immunity d) high mask count Fill in the blanks: 11. Expansion of CVD is ___chemical vapour deposition___________ 12.______Electron_______________ lithography is preferred in submicron device dimension 13. The kinetics of thermal oxidation is modeled by ___deal and groover___________________model. 14. The static power dissipation in CMOS technology is _____zero__________ 15. In normal mode of operation in CMOS, substrate terminal of NMOS is connected to ____vss_______ and substrate terminal of PMOS is connected to ___vdd________ 16. CMOS technology is high delay than ____bipolar_______________ Technology 17. The deficiency of MOS technology is ___limited load driving capacity_____________________ 18. Under DEPLETION mode NMOS is ____ON____________state. 19. NMOS FET’s are ___faster_________than PMOS FET’s 20. Power dissipation in NMOS technology is ____high_______compared to CMOS technology.
UNIT - 2
Multiple choice 1. MOSFET operated in saturation when [ C ] (a) Vds = vgs-vt (b) vds < vgs-vt (c) Vds > vgs-vt (d) Vds < vt 2. For faster NMOS circuits, one would choose the following type of substrate [ B ] (a) 110 Oriented n - type substrate (c) 111 Oriented p - type substrate (b) 100 oriented p - type substrate (d) 111 oriented n- type substrate 3. Pull up to pull down ratio for n MOS inverter driven by another n MOS inverter is [ D ] (a) 4:4 (b) 4:1 (c) 1:4 (d) 8:1
Bi-CMOS inverter has high driving capability than ___cmos____technology . 19. An inverter driven through one or more pass transistor should have Zpu/Zpd ratio of_ _____8 : 1_______ 12.sec b) 240 cm2/V. The color encoding for polysilicon is [ A (a) Red (b) Green (c) Blue (d) Orange 2. The threshold voltage is increased due to ___body effect_________________ 13.sec 8.4. For high performance CMOS inverter βn βp should be__low______ UNIT – 3 Multiple choices 1. The following device is less likely to suffer latch up [ C ] (a)n MOS (b) CMOS (c) BICMOS (d) PMOS 5. Pickup the ‘true’ statement with respect to Bi-CMOS Inverter [ C ] a) Low input impedance b) High output impedance c) high noise margin d) Low driving capability 9. More lightly doped substrate ___________less___________ will be the body effect 14.1 VIN (b VIN = 0. Zpu/Zpd ratio should be a) Zero b) One c) As low as possible d) As high as possible [ C ] 10.5 VDD (d) VIN = Vout = VDD 6. The power dissipation is ___low______in CMOS technology. In CMOS inverter if βn=βp & if Vtn =Vtp. Number of transistors to implement three-input AND gate using pass transistor logic is a) 6 b) 3 c) 5 d) 9 [B ] Fill in the blanks: 11. then the logic levels are disposed about at a point where [ C ] (a)VIN = Vout = 0.5 VDD (c) VIN = Vout =0. The color encoding of ‘VIA’ in double metal CMOS p-well process [ B a) Red b) Black c) Brown d) Yellow 3. The buried contact is made between [ B (a) Poly to metal (b) poly to diff (c) poly to diff using metal (d) Metal to metal 5. Transconductance of MOS transistor (gm) is expressed as__________ 16.sec L µ 2 d) 480 cm2/V. To achieve best performance NMOS inverter transfer characteristics. The drain. Metal 1 to metal 1 spacing in layout design is [ C (a) 4 (b) 2 (c) 3 ( d) 1 4. 20. Typical mobility of holes (Bulk) is a) 650cm2/V. For devices of similar dimension n-channel is ___faster________ than the p – channel 17. A simple BICMOS inverter has ___high____input impedance and__low____ output impedance 18. the colour of contact cut [ A ] a) Black b) Green c) Blue d) Red ] ] ] ] .source current (IDS) for NMOS under saturation can be expressed as___________ 15. The figure of merit of MOS transistor can be expressed as [ C ] a) g m Cg b) cg gm c) gm cg d) [ D ] c) 1250 cm2/V.In NMOS layout design style.sec 7.
The minimum width of metal 1 layer is _________3λ _____________ 16. Metal 1 for_____LOCAL DISTRIBUTION_______ and metal 2 for __GLOBAL DISTRIBUTION_______of power lines in stick notation 18.0x10 – 4 pF/µm2 b) 1. A __MOS TRANSISTOR_________is formed wherever polysilicon crosses Diffusion 17. The typical value of load capacitance is [ D ] a) CL < 10 4 cg (b) CL 10 4 cg (c) CL = 10 14 cg (d) CL 10 14 cg 5. the heat sink size___REDUCES__________ 20. What is color of metal 1 (CMOS encoding) [ B a) Black b) Blue c) Red d) Yellow 7. The rise time of CMOS inverters is a) = (b) = (c) = b) = [ C ] 4. The p-type transistors are placed above the [ C a) Poly silicon b) diffusion c) Demarcation line d) metal 8. According to 2µm CMOS technology. The layer preferred for global distribution of power buses is __METAL 2________________ 12. Power dissipation per unit area is scaled by (a) (b) (c) (d) [ A] d) 0. The size of a transistor is usually designed in terms of [ D a) Drain b) source c) metal d) channel length 10. For CMOS circuits stick encodings for demarcation line is ___BROWN________________in color. moderate C d) moderate R. The overall delay Td for n sections is given by [ B ] a) Td= nrc ( τ ) b) Td= n2 rc( τ ) c) Td = n2r2 c( τ ) d) Td= n r2 c( τ ) 8. 14.1x10 – 4 pF/µm2 3.6. The characteristics of a metal layer are [A ] a) Low R._____STICK DIAGRAM___________________ is used to convey layer information. Typical value of Diffusion capacitor(C area ) in 5 µm technology a) 1. Demarcation line is shown by__DOTTED LINE__________ UNIT – 4 Multiple choice 1. high C 6. What is the formula for Rise-time estimation [ A ] a) Tr= 3C β p V DD L b) Tr = 3C β v p 2 L c) Tr = 3C DD β p V DD 2 L d) Tr = C β V DD L p . low C b) low R.1x10 – 2 pF/µm2 [ C ] 2. the minimum separation between contact cuts a) 2 µm b) 4 µm c) 6 µm d) 5 µm [ B ] ] ] ] ] Fill in the blanks 11. Deposition of the metal/silicon alloy prior to sintering may be done with [ A ] a) Sputtering b) diffusion c) Implantation d) Metallization 9. The power and ground lines often called _______POWER RANGE__________ 15. In CMOS design style.0X10 – 2 pF/µm2= c) 0. The minimum gap between diffusion and diffusion is [ A a) 2 λ b) 5 λ c) 7 λ d) 10 λ 9. As fabrication technology improves. 13. The typical sheet resistance of polysilicon for 5µm is [ D ] a) 0-10 Ω b) 10-14 Ω c) 120 to 140Ω d) 15 to 100 Ω 7. moderate C c) Low R. The minimum polysilicon width is______2λ __________19.
The propagation delay of n sections is given by ________________________________ 12. The layer in which metal is deposited on poly silicon is called _____SILICIDE________________ 13. 14. ___METAL 1_____ layer is suitable for routing Vdd or Vss 18. 19. 17. .10. The sheet resistance of p–diff is _____2 : 5_________ times that of n-diffusion. The formula for fall-time estimation in CMOS inverter is 2 2 3C 3C L L 3 C L a) Tf = b) Tf = c) Tf = p v DD p V DD n V DD [ C d) ] β β β 3C β V DD 2 L n 2 Fill in the blanks 11. The Delay for Bi-CMOS inverter is _______REDUCED____________by a factor of h f e compared with a CMOS Inverter. The values for N-diffusion region are___0.4_______ times the P-diffusion regions. 15. Power consumption in CMOS circuits depends on __FREQUENCY_____________at which they operate. In Bi-Polar transistor collector current depends ____EXPONENTIALY____________on Vbe. 20. The ___LARGE CAPACITIVE__________________load can’t be driven by a single inverter. Bi-CMOS technology is reasonably good for__HIGH LOW DRIVING CAPABILITY____________ 16.
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