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Lab Workbook

Vivado HLS Design Flow Lab

Vivado HLS Design Flow Lab
Introduction
This lab provides a basic introduction to high-level synthesis using the Vivado HLS tool flow. You will use Vivado HLS in GUI mode to create a project. You will simulate, synthesize, and implement the provided design.

Objectives
After completing this lab, you will be able to: • • • • • • Create a new project using Vivado HLS GUI Simulate a design Synthesize a design Implement a design Analyze a design using Design Viewer capability Simulate in Project Navigator

Procedure
This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab. This lab comprises 9 primary steps: You will create a new project in Vivado HLS, run simulation, run debugger, synthesize the design, open a design viewer, run SystemC simulation, create a project in Project Navigator, run simulation using ISIM, and implement the design in Vivado HLS. Note: If you are unable to complete the lab at this time, you can download the original lab files for this lab by visiting www.xilinx.com/university/workshops/high-level-synthesis-flow/index.htm and selecting labsource for the appropriate board and tools version.

General Flow for this Lab
Step 1: Creating a New Project
Step 2:

Run Simulation

Step 3: Run Debugger

Step 4:

Synthesize the design

Step 5: Open a Design Viewer

Step 6: Run SystemC Simulation

Step 7: Create Project in ProjNav

Step 8: Run ISIM Simulation

Step 9: Implement the Design in Vivado HLS

© Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com

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Vivado HLS Design Flow Lab

Lab Workbook

Create a New Project
1-1.

Step 1

Create a new project in Vivado HLS targeting Spartan6 XC6SLX45CSG324-2.

1-1-1. Launch Vivado HLS: Select Start > All Programs > Xilinx Design Tools > Vivado 2012.2 > Vivado HLS. A Getting Started GUI will appear.

Figure 1. Getting Started View of Vivaldo-HLS 1-1-2. In the Getting Started GUI, click on Create New Project. The New Vivado HLS Project wizard opens. 1-1-3. Click the Browse… button of the Location field and browse to c:\xup\hls\labs\lab1 and then click OK. 1-1-4. For Project Name, type matrixmul.prj

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© Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com

called matrixmul1).Lab Workbook Vivado HLS Design Flow Lab Figure 2. Click the Add Files… button. to be synthesized. 1-1-10. In the Add/Remove Files for the testbench. type –DHW_COSIM. 1-1-7. click the Add Files… button. Select the matrixmul1_test.cpp in the files list window and click the Edit CFLAG… button. New Vivado HLS Project Wizard 1-1-5.com/university xup@xilinx. 1-1-9. Click Next.cpp file from the c:\xup\hls\labs\lab1 folder and click Open. select matrixmul1.cpp file from the c:\xup\hls\labs\lab1 folder. type matrixmul1 as the function name (the provided source file contains the function. select matrixmul1_test. In the Add/Remove Files for the source files. © Copyright 2012 Xilinx www. 1-1-6.xilinx. Click Next.com Atlys 1-3 . and click OK. 1-1-8. and then click Open.

Leave Uncertainty field blank as it will take 1. 1-1-13. Lab Workbook 1-1-12. Expand various sub-folders to see the entries under each sub-folder. Click Finish.com/university xup@xilinx.xilinx. and click OK: Family: Spartan6 Sub-Family: Spartan6 Package: csg324 Speed Grade: –2 Figure 3. and select the following filters to select the XC6SLX45CSG324-2 part. Click Next.25 as the default value.com . In the Solution Configuration page. Atlys 1-4 © Copyright 2012 Xilinx www. You will see the created project in Explorer view. Click on Part’s Browse button.Vivado HLS Design Flow Lab 1-1-11. leave Solution Name field as solution1 and clock period as 10. Part Selection Dialog 1-1-14.

com Atlys 1-5 . Run C/C++ project to observe the expected output. Row is the outer-most loop. The Product loop is the inner most loop performing the actual elements product. The files will be compiled and you will see the output in the Console window. from the tools bar buttons. Finally. Run C/C++ Project 2-1. The res[i][j]=0 (line 79) resets the result every time a new row element is passed and new column element is used. Step 2 2-1-1. The Design under Consideration It can be seen that the design consists of three nested loops.xilinx. Explorer Window 1-1-15.com/university xup@xilinx. © Copyright 2012 Xilinx www. Figure 5.Lab Workbook Vivado HLS Design Flow Lab Figure 4. Select Project > Run C/C++ Project or click on 2-1-2.cpp under the source folder to open its content in the information pane. Double-click on the matrixmul1. The Col loop is the outer-loop which feeds next column element data with the passed row element data to the Product loop.

In case of invoking using the button. The Debug perspective will open. argc and argv variables defined in the Variables view. a dialog box will appear. If HW_COSIM is defined then it calls matrixmul1 function and the compares the output of the computed result with the one returned from the called function and prints Test passed if the results match. the application will be compiled for debugging purpose with debugging related information embedded into the executable. You should see two input matrix initialized with some values and then the code executes the algorithm.xilinx. Run Debugger 3-1. Click Yes to switch to the Debugger perspective. Select Project > Debug C/C++ Project or click on In case of pull-down menu.cpp under testbench folder in the Explorer to see the content. Note that the execution is suspended at the main() entry point. You can also switch to this perspective by clicking on on the top right bar.cpp in the source view. showing the matrixmul1_test. A Confirm Perspective Switch dialog box will appear. and then click on Debug button.Debug in the left pane as an application type. thread created and the program suspended in the Debug view. 3-1-3. Program Output 2-1-3. from the tools bar buttons. Step 3 Run the application in debugger mode and understand the behavior of the program. 3-1-1. Double-click on matrixmul1_test.com/university xup@xilinx. Outline view showing the objects which are in the current scope.Vivado HLS Design Flow Lab Lab Workbook Figure 6. 3-1-2. Atlys 1-6 © Copyright 2012 Xilinx www. If HW_COSIM had not been defined then it will simply output the computed result and not call the matrixmul1 function. Select matrixmul1.com .

Debugger’s Intermediate Output View © Copyright 2012 Xilinx www. observe the execution progress. Similarly. 3-1-5.com Atlys 1-7 . Figure 8. set a breakpoint at line 101. This will set a break-point at line 105.xilinx. Scroll-down in the source view.com/university xup@xilinx. and double-click on line 105 where it is about to output “{“ in the output console window. Using the Step Over (F6) button ( ) several times. Do it for about 19 times and observe the variable values as well as computed software result. A Debugger Perspective 3-1-4.Lab Workbook Vivado HLS Design Flow Lab Figure 7.

Using the Step Over (F6) several times.com/university xup@xilinx. 3-1-10. Figure 10. Observe the following computed software result in the variables view. Figure 9. Observe the software and hardware (function) computed results in Variables view. observe the computed results.xilinx. and observe that the execution is paused on line 75 of the module.com .Vivado HLS Design Flow Lab 3-1-6. 3-1-9. you can use the Step Return (F7) button ( ) to return from the function. Computed Results Atlys 1-8 © Copyright 2012 Xilinx www. Software Computed Result 3-1-8. Once satisfied. Now click the Resume ( Lab Workbook ) button to complete the software computation and stop at line 101. Click on the Step Into (F5) button ( ) to traverse into the matrixmul1 module. the one that we will synthesize. 3-1-7. The program execution will suspend at line 105 as we had set a breakpoint.

on the tools bar.com Atlys 1-9 . Step 4 Switch to Synthesis view and synthesize the design with the defaults. 3-1-12. If you expand solution1 in Explorer. Figure 11. and click on the Resume button. Press the Resume button or Terminate button to finish the debugging session. Switch to the Synthesis view by clicking 4-1-2.Lab Workbook 3-1-11.com/university xup@xilinx. Set a breakpoint on line 134. Select Solution > Synthesis > Active Solution or click on the process. View the synthesis results and answer the question listed in the detailed section of this step. 4-1-3.xilinx. Synthesize the Design 4-1. the Synthesis Results will be displayed along with the Outline pane. When synthesis is completed. Report View after Synthesis is completed 4-1-4. © Copyright 2012 Xilinx www. The console window will show the results as seen earlier (Figure 6). several generated files including report files will become accessible and the Synthesis Results will be displayed in the information pane. one can navigate to any part of the report with a simple click. Vivado HLS Design Flow Lab The execution will continue until the breakpoint is encountered. button to start the synthesis 4-1-1. Using the Outline pane.

Also note that if the target design has hierarchical functions. and cpp) files. header. it will show report. verilog. The Synthesis Report shows the performance and resource estimates as well as estimated latency in the design.com/university xup@xilinx.com . By double-clicking any of these entries will open the corresponding file in the information pane. Question 1 Estimated clock period: Worst case latency: Number of DSP48A used: Number of FFs used: Number of LUTs used: Atlys 1-10 © Copyright 2012 Xilinx www. verilog.xilinx. Using scroll bar on the right. Explorer View after the Synthesis Process Note that when Solution1 folder is expanded in the Explorer view. reports corresponding to lower-level functions are also created.Vivado HLS Design Flow Lab Lab Workbook Figure 12. 4-1-6. scroll down into the report and answer the following question. systemC. and vhdl sub-folders under which report files. 4-1-5. and generated source (vhdl.

and interaction between them. © Copyright 2012 Xilinx www. Start the Design Viewer and understand the design behavior. 5-1-2. The design viewer will open showing various hardware blocks. Generated Interface Signals You can see ap_clk. Open a Design Viewer 5-1. Other signals are generated based on the design interface itself.xilinx. when the next computation is started (ap_start). Figure 13. number of states they span over. The report also shows the top-level interface signals generated by the tools. ap_done.com/university xup@xilinx. and when the computation is completed (ap_done).Lab Workbook Vivado HLS Design Flow Lab 4-1-7. Step 5 5-1-1. and ap_idle are top-level signals used as handshaking signals to indicate when the design is able to accept next computation command (ap_idle).com Atlys 1-11 . The ap_start. ap_rst are automatically added. Select Solution > Open Design Viewer to open the design viewer.

bb2. You can use the Up and Down arrows next to the CFG tab to traverse into or out of a level ( ). and Col boxes. Region 1.com . There is single entry point (entry block) and single exit point (return block). The main processing block is Row which consists of bb. Click on Region 4 box and observe that bb6 is selected in the left pane. This can be verified by clicking on the Row box in the Control Flow Graph (CFG) in the auxiliary pane view. Design Viewer Showing Synthesized Design It can be seen that there are two inputs (a and b matrices) and one output (res matrix). 5-1-4.Vivado HLS Design Flow Lab Lab Workbook Figure 14. Atlys 1-12 © Copyright 2012 Xilinx www. 5-1-3. bb4. and bb7. bb5. Double-click on the Row box in CFG and traverse down into it.com/university xup@xilinx. bb3. bb6. You will see Row is replaced by Region 4.xilinx. bb1.

xilinx. CFG of Row Loop If you move the mouse on Col box. Double-click Col block.Lab Workbook Vivado HLS Design Flow Lab Figure 15. If you move to Region 4 or Region 1.com Atlys 1-13 . it will not show latency or trip count as it really does not exert any latency. then Product block. you will see additional information on latency and trip count is displayed.com/university xup@xilinx. 5-1-5. since this is the block that performs real work. © Copyright 2012 Xilinx www. and then finally bb2 block to display the actual operations taking place.

5 and 6). Atlys 1-14 © Copyright 2012 Xilinx www. one multiply (mul) operation (the actual elements multiplication in phase 4. Since bb2 takes 4 clock cycles the total number cycles spent to compute is 12 and then one clock for entry into and exit of the loop gives total number of cycles spent in product is 14. and one shift left (shl) operation taking place. one subtract (sub) operation. hence the trip count of 3 and latency of 132 ((42+2)*3) can be seen on row block. hence the trip count of 3 and latency of 42 (14*3) can be seen on col block. If you move the mouse over product (after going one level up) you will see that the trip count is 3 and the latency is 12. which represents the product loop. The Actual Operation In this block. The product is called three times.Vivado HLS Design Flow Lab Lab Workbook Figure 16. Click X on the Schedule:matrixmul1 tab to close the design viewer.com . 5-1-6. The col is called three times. there are two read (loads) operations (to read a and b elements in phase 3). The trip count of three indicates that the loop will be visited 3 times. The entry into and the exit from matrixmul1 takes one clock each and hence total latency of 134. three add operations (one of them adding the computed result in phase 6).com/university xup@xilinx.xilinx.

A C/RTL Co-simulation Dialog box will open. © Copyright 2012 Xilinx www. A C/RTL Simulation Dialog 6-1-2. Select Solution Cosimulation or click on the simulations can be run. Step 6 Run the Co-simulation.com/university xup@xilinx. Figure 17. button to open the dialog box so the desired 6-1-1. Verify that the simulation passes.xilinx.Lab Workbook Vivado HLS Design Flow Lab Run CoSimulation 6-1. Click OK to run the System-C simulation. selecting SystemC and skipping VHDL and Verilog.com Atlys 1-15 .

In the console window you can see the progress and also a message that the test is passed. This eliminates writing a separate testbench for the synthesized design.com . Console View Showing Simulation Progress Atlys 1-16 © Copyright 2012 Xilinx www. Figure 18.com/university xup@xilinx. and then simulating the design.Vivado HLS Design Flow Lab Lab Workbook The RTL Co-simulation will run.xilinx. generating and compiling several files.

) of the Location field. © Copyright 2012 Xilinx www. and click Next. XC6SLX45 as Device.2 and create a project targeting XC6SLX452CSG324 part and VHDL as the preferred langauge. 7-1-1. -2 as Speed. 7-1-2.com Atlys 1-17 . select all the files.xilinx. In the Hierarchy window. 7-1-6. Click OK. and click Open. and click Next. Select Spartan6 as Family. 7-1-7.com/university xup@xilinx. Click on New Project … button. Type matrixmul_projnav in the project name field. 7-1-8. Click on the browse button ( click OK. 7-1-3. Click on the Add Source button ( ) and browse to c:\xup\hls\labs\lab1\matrixmul. 7-1-9. VHDL as the Preferred Language. Step 7 Start Project Navigator 14. Launch Project Navigator: Select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14. Click Finish to create the project. and 7-1-4. 7-1-5. Add VHDL design files generated during the synthesis.Lab Workbook Vivado HLS Design Flow Lab Create a Project in Project Navigator 7-1. make sure that matrixmul1 is Set As Top Module.2 > ISE Design Tools > (32-bit or 64-bit) Project Navigator. CSG324 as Package. and browse to c:\xup\hls\labs\lab1.prj\solution1\syn\vhdl.

).com . Setting Top Module Run Simulation 8-1.cfg from the c:\xup\hls\source\lab1 directory as the custom configuration file.xilinx.Vivado HLS Design Flow Lab Lab Workbook Figure 19. browse to c:\xup\hls\source\lab1 directory. Click on the Add Source button. and use matrixmul. Run the simulation. and double-click Atlys 1-18 © Copyright 2012 Xilinx www. 8-1-2. Select Simulation view ( matrixmult1_testbench. Set simulation time to 1600 ns.com/university xup@xilinx. Step 8 Add provided VHDL testbench from the c:\xup\hls\source\lab1 directory.vhd file to view its content. select matrixmul1_testbench. and click Open. 8-1-1.vhd file.

Right-click on the Simulate Behavioral Model in the Process window. and then ap_start is applied for one clock cycle. and then it is asserted at 1555 ns indicating that it can take next command.Lab Workbook Vivado HLS Design Flow Lab You will notice that the design is instantiated starting at line 88. the ap_clock generation process starts at 107. 8-1-6. ap_idle has been de-asserted (at 215 ns) indicating that the design is in computation mode. the matrix elements are input. © Copyright 2012 Xilinx www. In the ISim Properties form enter 1600 ns as the Simulation Run Time. Starting at line 130. and select Process Properties… 8-1-4.xilinx. Note that as soon as ap_start is asserted. browse to c:\xup\hls\source\lab1\matrixmul. Setting ISim Properties 8-1-5. click on the check box of Use Custom Waveform Configuration File.com Atlys 1-19 .wcfg and click Open. Double-click on the Simulate Behavioral Model in the Process window to start the simulation.com/university xup@xilinx. Figure 20. Simulation will run for 1600 ns and the waveform will be displayed. It remains de-asserted until ap_done is asserted at 1545 ns. Click OK to accept the settings. 8-1-3. The ap_rst is asserted for 1 clock cycle. and stimuli generation starts at line 116. click on the browse button of the Custom Waveform Configuration File field. This indicates 134 clock cycles of latency (1555 -215 => 1340 ns).

the Design Summary view will show resources consumption. View various part of the simulation and try to understand how the design works. Figure 22.com . res_we0. b_ceo signals and outputs resultusing res_d0. Complete Simulation Run 8-1-7. and double-click Implement Design process in the Process view to synthesis and implement the design. Close Project Navigator by selecting File > Exit. close the simulation by selecting File > Exit. 8-1-8. a_ceo. Switch to the Implementation view and implement the design. When the implementation run is finished. 8-2-3. click matrixmul1 in the Sources window. b_address. Atlys 1-20 © Copyright 2012 Xilinx www.Vivado HLS Design Flow Lab Lab Workbook Figure 21. view area of 100 ns and 500 ns. 8-2. Using Zoom In button.xilinx. 8-2-1. Select Implementation view ( ). 8-1-9.com/university xup@xilinx. and res_ce0. 8-2-2. Zoomed Area Observe that the design expects element data by providing a_address. When done.

com Atlys 1-21 . When the run is completed the implementation report will be displayed in the information pane. A Export RTL Dialog Box 9-1-2. © Copyright 2012 Xilinx www. 9-1-3. Click OK and the implementation run will begin. which are in PATH variable. and select VHDL and click on the Evaluate check box as the preferred language and to run the implementation tool.xilinx. button to open the dialog box so 9-1-1. You can observe the progress in the Vivado HLS Console window. will be run. Figure 23. In Vivado-HLS. Step 9 In Vivado HLS. select Solution > Export RTL or click on the the desired implementation can be run. export the design.com/university xup@xilinx. and run the implementation by selecting Evaluate option. A Export RTL Dialog box will open. selecting VHDL as a language. Click on the drop-down button of the Options field. The implementation tools.Lab Workbook Vivado HLS Design Flow Lab Implement the Design in Vivado HLS 9-1.

Close Vivado HLS by selecting File > Exit.xilinx. adding source files. Conclusion In this lab. simulated the design. you completed the major stages of the high-level synthesis design flow using Vivado HLS.com/university xup@xilinx. You also learned that how to use the Design Viewer capability to understand the scheduling. and implemented the design.com .Vivado HLS Design Flow Lab Lab Workbook Figure 15. Answer the following questions: Estimated clock period: Worst case latency: Number of DSP48A used: Number of FFs used: Number of LUTs used: 5. Answers 1. You created a project. Implementation Results in Vivado HLS 9-1-4. synthesized the design.55 ns 134 clock cycles 1 45 62 Atlys 1-22 © Copyright 2012 Xilinx www.