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2013-1087 (Reexamination Nos. 95/001,108 & 95/001,154)

IN THE UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT

RAMBUS, INC., Appellant, v. MICRON TECHNOLOGY, INC., Appellee.

Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board.

CORRECTED BRIEF FOR APPELLANT RAMBUS INC.

J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 Attorneys for Appellant Rambus Inc.

April 1, 2013

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CERTIFICATE OF INTEREST Pursuant to Federal Circuit Rules 27(a)(7) and 47.4(a), counsel for Appellant Rambus Inc. certify the following: 1. The full name of every party or amicus represented by us is: Rambus Inc. 2. The name of the real party in interest (if the party named in the caption is not the real party in interest) represented by us is: Rambus Inc. 3. All parent corporations and any publicly held companies that own 10 percent or more of the stock of any party represented by us are: None 4. The names of all law firms and the partners or associates that appeared for the parties now represented by us in the trial court or are expected to appear in this Court are: J. Michael Jakes, James R. Barney, Naveen Modi, Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP

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TABLE OF CONTENTS Table of Authorities ...................................................................................................v Statement of Related Cases ..................................................................................... vii Statement of Jurisdiction............................................................................................1 I. II. III. Statement of the Issues ....................................................................................2 Statement of the Case ......................................................................................2 Statement of Facts............................................................................................3 A. B. C. Introduction ...........................................................................................3 Claim 34 of the ’037 Patent...................................................................4 Background of the Technology at Issue ................................................5 1. 2. 3. 4. 5. D. Dynamic Random Access Memory ............................................5 “Asynchronous” Versus “Synchronous” DRAM Chips ...........................................................................................7 Prior Cases Involving Synchronous “Memory Devices” ......................................................................................9 Precharging of Sense Amplifiers ..............................................10 Objective Evidence of Non-Obviousness .................................17

The Rejection Based on Bennett in View of Wicklund or Bowater................................................................................................19 1. 2. 3. 4. The Examiner’s Determination of Nonobviousness .................21 Micron’s Appeal to the Board...................................................25 The Board’s Reversal of the Examiner’s Decision Confirming Claim 34 ................................................................28 The Board’s Determination That Bennett Rendered Synchronous DRAMs Obvious in 1990 ...................................34 ii

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IV. V.

Summary of Argument ..................................................................................39 Argument .......................................................................................................40 A. Standards of Review............................................................................40 1. Factual Findings of the Board Are Reviewed for Substantial Evidence Based on the Entire Closed Record, Including Any Findings of Fact Made by the Examiner ...................................................................................40 The Board Cannot Simply Rely on Its Own Expertise; It Must Point to “Concrete Evidence in the Record” to Support Its Findings ...............................................42 The Board’s Ultimate Conclusion of Obviousness Is Reviewed de Novo ....................................................................43

2.

3. B.

The Board Erred in Reversing the Examiner’s Determination That an Operation Code Containing Both a Write Instruction and an Automatic Precharge Instruction Was Not Obvious in 1990 ...................................................................43 1. The “Closed Record” in This Case Contains Unchallenged Findings of Fact by the Examiner That Undercut the Board’s Determination of Obviousness ..............44 The Examiner’s Factual Findings Support Only Nonobviousness; the Board’s Contrary Determination Lacks Substantial Evidence ..............................47 The Board Erred by Substituting Its Own Presumed Expertise for the Record Evidence Developed by the Examiner ...................................................................................51 The Board Also Ignored Rambus’s Evidence That Supported the Examiner’s Finding of Nonobviousness ........................................................................54

2.

3.

4.

C.

The Board Erred in Holding, Without Any Prior-Art Examples of Synchronous DRAMs, That Synchronous DRAMs Would Have Been Obvious in View of Bennett ..................56 iii

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VI.

Conclusion .....................................................................................................62

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TABLE OF AUTHORITIES Cases Page(s)

Baltimore & Ohio R.R. Co. v. Aderdeen & Rockfish R.R. Co., 393 U.S. 87 (1968) ..............................................................................................43 Brand v. Miller, 487 F.3d 862 (Fed. Cir. 2007) .................................................................... passim Gechter v. Davidson, 116 F.3d 1454 (Fed. Cir. 1997) ..........................................................................41 In re Gartside, 203 F.3d 1305 (Fed. Cir. 2000) ............................................................. 40, 41, 42 In re Glatt Air Techniques, Inc., 630 F.3d 1026 (Fed. Cir. 2011) ..........................................................................57 In re Gurley, 27 F.3d 551 (Fed. Cir. 1994) ..............................................................................56 In re ICON Health & Fitness, Inc., 496 F.3d 1374 (Fed. Cir. 2007) ..........................................................................43 In re NTP, Inc., 654 F.3d 1279 (Fed. Cir. 2011) ................................................................... 43, 61 In re Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012) ................................................................................9 In re Rambus, Inc. v. NVIDIA, Corp., 2013 WL 595881 (Patent Tr. & App. Bd.) .........................................................41 In re Zurko, 258 F.3d 1379 (Fed. Cir. 2001) ..........................................................................43 Pozen Inc. v. Par Pharm., Inc., 696 F.3d 1151 (Fed. Cir. 2012) ..........................................................................56 St. Clair Intellectual Property Consultants, Inc. v. Canon Inc., 412 Fed. Appx. 270 (Fed. Cir. 2011)..................................................... 42, 44, 53

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Universal Camera Corp. v. NLRB, 340 U.S. 474 (1951) ............................................................................................42 Statutes 35 U.S.C. § 134(b) .....................................................................................................1 35 U.S.C. § 141 ..........................................................................................................1 35 U.S.C. §§ 311-314.................................................................................................1

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STATEMENT OF RELATED CASES Appellee Micron Technology, Inc. filed another appeal from this reexamination, which was given appeal number 2013-1088 and was dismissed on December 21, 2012. Rambus is unaware of any other appeals or petitions taken in this reexamination proceeding. There are, however, a number of different matters pending in this Court and other courts that involve the patent-at-issue in this appeal, U.S. Patent No. 6,584,037 (“the ’037 patent”). 1. The following pending cases involve the ’037 patent. a. Rambus Inc. v. Hynix Semiconductor Inc., No. 5:05-cv-00334-

RMW (N.D. Cal.) (Whyte, J.). b. (Seeborg, J.). c. Rambus Inc. v. Micron Technology, Inc., No. 5:06-cv-00244Rambus Inc. v. LSI Corp., No. 3:10-cv-05446-RS (N.D. Cal.)

RMW (N.D. Cal.) (Whyte, J.). d. Rambus Inc. v. STMicroElectronics, N.V., No. 3:10-cv-05449-

RS (N.D. Cal.) (Seeborg, J.). 2. The following pending cases do not involve the ’037 patent but

involve patents that, like the ’037 patent, descend from Application No. 07/510,898 (“the ’898 application”).

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a.

Hynix Semiconductor Inc. v. Rambus Inc., No. 5:00-cv-20905-

RMW (N.D. Cal.) (Whyte, J.). This case is on remand from Appeal Nos. 20091299, -1347, 645 F.3d 1336 (Fed. Cir. 2011). b. Micron Technology, Inc. v. Rambus Inc., No. 1:00-cv-00792-

SLR (D. Del.) (Robinson, J.). This case is on remand from Appeal No. 2009-1263, 645 F.3d 1311 (Fed. Cir. 2011). 3. Several ex parte and inter partes reexaminations involving patents

descended from the ’898 application are pending at the U.S. Patent and Trademark Office (“PTO”). Of those, the following have been appealed to this Court. a. 2012). b. not yet complete). c. Rambus, Inc. v. Micron Technology, Inc., No. 2013-1192 (Fed. Rambus, Inc. v. Kappos, No. 2012-1634 (Fed. Cir.) (briefing In re Rambus Inc., No. 2011-1247, 694 F.3d 42 (Fed. Cir.

Cir.) (briefing not yet complete). d. (docketed). e. (docketed). Rambus, Inc. v. Micron Technology, Inc., 2013-1224 (Fed. Cir.) Rambus, Inc. v. Micron Technology, Inc., 2013-1228 (Fed. Cir.)

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STATEMENT OF JURISDICTION This appeal arises from two inter partes reexamination proceedings before the U.S. Patent and Trademark Office (“PTO”). See 35 U.S.C. §§ 311-314.

Micron Technology, Inc. (“Micron”), one of the requesters, appealed the examiner’s confirmation of the sole claim at issue to the Board of Patent Appeals and Interferences (“Board”), which had jurisdiction under 35 U.S.C. §§ 134(c) and 315(b)(1). The Board reversed the examiner’s confirmation of the claim on

January 27, 2012, and Rambus requested rehearing, which the Board denied on August 16, 2012. The Board’s decision was final and appealable. Rambus

appealed. This Court has jurisdiction under 35 U.S.C. § 141.

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I.

STATEMENT OF THE ISSUES 1. Did the Board err in reversing the examiner’s decision confirming claim

34, where the examiner had correctly found that none of the cited prior art discloses or renders obvious the use of an “operation code” that includes both a write instruction and an instruction to automatically precharge after writing, and where the Board found no error in the examiner’s underlying findings of fact but simply disagreed with his ultimate conclusion of nonobviousness? 2. Alternatively, did the Board err in determining that Bennett would have rendered obvious a “synchronous dynamic random access memory device” (“synchronous DRAM”), where Bennett does not disclose DRAMs at all and the cited prior art discloses only conventional asynchronous DRAMs, which would have been used in Bennett (if at all) as an array of multiple asynchronous DRAM chips? II. STATEMENT OF THE CASE Rambus appeals the Board’s reversal of the examiner’s decision confirming claim 34 of U.S. Patent No. 6,584,037 (“the ’037 patent”). After a thorough review of all the evidence, the examiner properly confirmed claim 34 over the cited prior art and rejected Micron’s obviousness arguments based on Bennett, Wicklund, and Bowater. On appeal, the Board found no error in the examiner’s underlying fact-finding yet overturned the examiner’s ultimate conclusion of

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nonobviousness.

The Board concluded—directly contrary to the examiner’s

finding—that a person of ordinary skill in the art in 1990 would have considered it obvious to combine the mainframe computer system of Bennett with an operation code that specifies both a write instruction and a precharge instruction (not disclosed in any of the cited references) and a single-chip synchronous DRAM (also not disclosed in any of the cited references). In reaching this conclusion, the Board substituted its own presumed expertise for the unrebutted record evidence developed by the examiner, which this Court has held is impermissible. See Brand v. Miller, 487 F.3d 862, 869 (Fed. Cir. 2007) (“[I]n the context of a contested case, it is impermissible for the Board to base its factual findings on its expertise, rather than on evidence in the record . . .”). Accordingly, the Board’s decision should be reversed. III. STATEMENT OF FACTS A. Introduction

By 1990, when Drs. Farmwald and Horowitz filed their landmark patent application from which the ’037 patent claims priority, the DRAM device was twenty years old, asynchronous, and, as stated by the Board, “ubiquitous” in the industry. Every DRAM device, then and today, requires for its operation a paired controller that accepts abstract host requests to read from or write to memory, translates each request into a series of DRAM-specific operations, and commands

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such operations to the DRAM device. It is uncontested that, in the twenty years before 1990, no one had conceived of a synchronous DRAM that uses an operation code containing both a read/write instruction and an instruction to automatically precharge after reading or writing. B. Claim 34 of the ’037 Patent

The ’037 patent claims priority to Application No. 07/510,898 (“the ’898 application”), filed on April 18, 1990. (A60.) Claim 34—the sole claim at issue in this appeal—recites: 34. A method of operation of a synchronous dynamic random access memory device, wherein the method comprises: sampling an operation code synchronously with respect to an external clock signal, wherein the operation code specifies that the memory device sample data to be written into a plurality of dynamic memory cells, and wherein the operation code further specifies that the memory device precharge a plurality of sense amplifiers; sampling the data, in response to the operation code, after a delay time transpires; sampling address information to identify a subset of the plurality of dynamic memory cells; writing the data to the subset of the plurality of dynamic memory cells using the plurality of sense amplifiers; and precharging the plurality of sense amplifiers in response to the operation code, wherein the plurality of sense amplifiers is precharged automatically after the data is written. (A92[27:64-28:20] (emphasis added).) 4

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C.

Background of the Technology at Issue 1. Dynamic Random Access Memory

The ’037 patent is generally directed to the structure, operation, and control of Dynamic Random Access Memory devices or “DRAMs.” DRAMs store

information in memory cells, which are typically arranged in a two-dimensional rectangular array. (A79[1:64-2:1]; A1600[¶15].) The array of cells includes

columns and rows, such that each cell can be accessed using a row/column address. (A79[1:64-2:1]; A1600[¶15].) Each memory cell contains a capacitor for storing a charge representing one bit of information; for example, a charged capacitor may represent a “1,” while a capacitor with no charge would represent a “0.” (Id.) A computer typically has many DRAMs controlled by a single memory controller. (See, e.g., A84[11:18-26] (discussing a computer with 100 DRAMs).) A central processing unit (“CPU”) can transfer information to or from a memory address using a memory controller. (A1599-601[¶¶13-20].) The memory controller accesses a designated row/column address in a given DRAM and performs either a read or write operation. (Id.) To read information, the memory controller sends instructions to sense the charge on the capacitor in that cell. To write information, the memory controller sends instructions such that the charge on the capacitor in that cell is changed to represent either a “0” or a “1.” (Id.)

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Information and control signals flowing between the CPU and the memory controller or between the memory controller and the numerous DRAMs can travel on one or more “buses,” each consisting of a series of wires or “lines” that connect the devices. (A80[3:55-4:38].) Prior-art computers typically had a primary bus that connected the CPU to the memory controller and a secondary bus that connected the memory controller to the numerous DRAMs, as shown in the figure below from the Wicklund reference (each set of two-way arrows represents a bus).

(A1442; see also A1600-01[¶¶19-20]; A1611[¶50]; A1625[¶92]; A1654[¶41].) Generally, instructions traveling along the primary bus are system-wide instructions such as instructions to access memory, while instructions traveling along the secondary bus—between the memory controller and the individual DRAMs—manage the detailed operations of the individual DRAMs in the memory array. (A1629[¶105].)

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A focus of the ’037 patent is to make the memory system more efficient so that data can be transferred faster than was possible in the prior art. (A81[5:3639].) This is accomplished, in part, by: (1) employing a synchronous memory interface between the memory controller and the DRAMs, i.e., one that utilizes an external clock signal to govern memory transactions with the individual DRAMs; and (2) using multi-bit operation codes that include both read/write instructions and instructions regarding “precharging.” 2. “Asynchronous” Versus “Synchronous” DRAM Chips

Prior to 1990 (the effective filing date of the ’037 patent), conventional DRAMs operated asynchronously, i.e., without being synchronized with an external clock signal. (A1601[¶20]; A79[2:48-51].) Read and write operations were conducted as soon as the memory controller requested them, and the DRAMs were able to respond. (A1601[¶20].) This was considered the most efficient way to access information because each DRAM transferred data as soon as possible after receiving a request for that data. (See A1880.) In contrast, the DRAMs disclosed in the ’037 patent are “synchronous” (A60), which means they operate differently than prior-art asynchronous DRAMs. The hallmark of a synchronous DRAM is that an external clock signal governs the timing of the read and write operations for all DRAMs on the bus. (A1601[¶21]; A80[3:12-15].) In a synchronous system, at least one signal line carries an external 7

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clock signal, such as the one shown below, which is used to synchronize all read and write operations for all the DRAMs on the bus. (A82[8:36-37]; A1601[¶21]; see A82[8:50-65]; A76[Fig. 14].)

In this manner, the memory controller and its DRAMs operate “synchronously” with each other. For instance, the memory controller can issue a read request to a particular DRAM and specify that the requested data must be returned in a precise number of clock cycles. (A1601-04[¶¶21-27].) Then, after that precise number of clock cycles has elapsed, that DRAM responds and the controller can check the data on the bus lines and know that it is the data associated with the earlier read request. (Id.) Meanwhile, in the intervening clock cycles, the memory controller can issue another request to another DRAM and start that process while the first DRAM is working to process the first read request. (Id.) In this way, transactions can be interleaved and “pre-scheduled” to occur at certain times, i.e., after a certain number of clock cycles. (Id.) While it was known prior to 1990 to include a clock on a primary bus (i.e., between the CPU and a memory controller), the bus between the memory controller and the DRAM chips was not operated synchronously. (A1601[¶20]; A1611[¶¶49-51]; A1625-26[¶¶92-93].) Instead, prior-art DRAMs typically came 8

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in arrays of many DRAMs, each of which was asynchronously connected to the memory controller, which in turn was connected (either synchronously or asynchronously) to a CPU via the primary bus. A1611[¶50]; A1625[¶92]; A1654[¶41].) 3. Prior Cases Involving Synchronous “Memory Devices” (See A1600-01[¶¶19-20];

In past cases involving other patents in the ’037 family, the asynchronous/synchronous issue has been extensively litigated. For instance, in U.S. Patent No. 6,034,918, the claims-at-issue recited a “synchronous memory device,” and this Court held that this term was not limited to a “single chip” memory device. In re Rambus Inc., 694 F.3d 42, 46-48 (Fed. Cir. 2012). As a result, this Court concluded that multiple DRAMs and their associated memory controller could collectively (in certain circumstances) be considered a “memory device.” Id. Under this interpretation, even if the individual DRAM chips

themselves were controlled asynchronously by a memory controller, if the entire collection of DRAMs and their memory controller was connected to a synchronous primary bus, then the whole collection could be considered a “synchronous memory device.” Id. That issue is not present here, however. In this case, claim 34 requires a “synchronous dynamic random access memory device,” as opposed to a generic “synchronous memory device,” as was at issue in the ’918 patent. (A92[27:649

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65].) The examiner construed this limitation to require “a synchronous DRAM chip, hence requiring the memory to be on a single integrated memory chip” (A1480 (emphasis added)), and neither Micron nor the PTO has challenged that construction (A1740; A29.) Thus, to determine whether a DRAM chip is

synchronous or asynchronous for purposes of claim 34, one must look to the specific bus to which that chip is attached, not some higher-level bus to which its associated controller may be attached. If the DRAM chip itself is attached to an asynchronous bus, then it is an asynchronous DRAM, regardless of whether there may be synchronous components upstream of its controller. (Id.) 4. Precharging of Sense Amplifiers

DRAMs sense (for reading) or store (for writing) a charge in a given cell using a “sense amplifier,” which is an electrical component that detects and amplifies the small amount of charge in a cell corresponding to a “0” or a “1,” such that the cell can be accessed for a read or write. The ’037 patent explains this basic configuration as follows, using the conventional terminology of “word line” and “bit line” for row and column, respectively. All modern DRAM, SRAM and ROM designs have internal architectures with a row (word) and column (bit) lines to efficiently tile a 2-D area. Referring to FIG 1, one bit of data is stored at the intersection of each word line 5 and bit line 6. When a particular word line is enabled, all of the corresponding data bits are transferred onto the bit lines. This data, about 4000 bits at a time in 10

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a 4 MBit DRAM, is then loaded into column sense amplifiers 3 and held for use by the I/O circuits. (A81[6:4-12].)

(A64.) As explained above, when a row address is sent from the memory controller, the information from each cell in that row is sent to the sense amplifiers. This is known as “opening” a row. (A1602-03[¶25].) In the demonstrative illustration below, the sense amplifiers are shown near the bottom of the figure. The third row has been opened, so the information from the third row has been copied to the sense amplifiers.

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0 1

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 0 1 0 1 0 1 0 0

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

Row Decoder

1 1 0 1 0 1 0 1

Column Decoder

Sense Amplifiers

When a particular column address is sent from the memory controller, the column decoder selects the corresponding sense amplifier and, depending on whether a read or write is being performed, the bit of information in that cell is read out or a new bit of information is written into that cell. In the illustration below, the memory controller has specified that a “1” should be written to the fourth column in the activated row. Thus, the bit on the fourth sense amplifier will be changed from a “0” to a “1.”

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0 1

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 0 1 0 1 0 1 0 0

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

Row Decoder

1 1 0 1 0 1 0 1

Column Decoder
1

Sense Amplifiers

Write Data from Controller
When the data has been written, the row can then be “closed,” such that the data from the entire row is transferred back to the row of memory cells, as shown in the illustration below. Note that a “1” has now been written into the fourth column of the third row.

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0 1

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 0

0 1 1 1 0 1 0 1 0 1

Row Decoder

1 1 0 1 0 1 0 1

Column Decoder

Sense Amplifiers

Before a new row can be loaded into the sense amplifiers, the sense amplifiers must be “precharged,” i.e., their charges must be preset to an intermediate voltage level between the voltages used to represent a “0” and a “1.” (A1602-03[¶25].) Much like balancing a seesaw, precharging enables the sense amplifiers to detect a logical 1 or 0 based on just a tiny quantity of charge in a cell. (Id.) In the art, DRAMs were known to operate in at least two modes: “normal mode” and “page mode.” (A83[10:22-46].) In normal mode, a new row is opened each time to access data, as shown in the first demonstrative illustration above. (Id.) Opening a new row takes time, however, which is generally undesirable in very high-speed memory systems. (Id.) An alternative to a “normal mode” access 14

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is a “page mode” access, in which data from the previously-opened row remains in the sense amplifiers and another column in that same row is accessed without the need to load a new row into the sense amplifiers. Page mode, however, is only advantageous if the next cell to be accessed is in the same row as the previous cell that was accessed. (Id.) The ’037 patent describes the advantages and disadvantages of these two different access modes as follows: In normal mode (in conventional DRAMS and in this invention), the DRAM column sense amps or latches have been precharged to a value intermediate between logical 0 and 1. This precharging allows access to a row in the RAM to begin as soon as the access request for either inputs (writes) or outputs (reads) is received and allows the column sense amps to sense data quickly. In page mode (both conventional and in this invention), the DRAM holds the data in the column sense amps or latches from the previous read or write operation. If a subsequent request to access data is directed to the same row, the DRAM does not need to wait for the data to be sensed (it has been sensed already) and access time for this data is much shorter than the normal access time. Page mode generally allows much faster access to data but to a smaller block of data (equal to the number of sense amps). However, if the requested data is not in the selected row, the access time is longer than the normal access time, since the request must wait for the RAM to precharge before the normal mode access can start. (A83[10:25-43].) In prior-art asynchronous DRAMs, the instruction that caused the sense amplifiers to precharge was a separate instruction from the instruction to read or 15

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write data. (A1541; A1602-03[¶¶24-25]; A1653-55[¶¶40-45].) The precharge instruction came (if at all) after the read or write operation was completed. (Id.) Alternatively, the absence of such an instruction allowed for the subsequent access to be in “page mode,” where the previously-opened row would remain open and the sense amplifiers would not precharge but, instead, would retain the data from the already-open row. The method recited in claim 34 of the ’037 patent operates differently than the prior art. Instead of using the prior-art method of sending a separate instruction to trigger precharging, the ’037 inventors realized that the precharge instruction could be combined together with a read or write request, such that the DRAM already knows whether to automatically precharge as soon as the read/write operation is completed, without the need for a separate instruction. 84[10:47-11:53].) (A83-

Such an automatic precharge instruction in a synchronous

DRAM allows the bus to be used only once per request, rather than twice, allowing the bus to be freed up to preschedule other operations. In the ’037 patent, the series of bits that contains the automatic precharge instruction and the read/write instruction is called an “operation code,” which, in one embodiment, is part of a larger package of information called a “request packet.” (A83[9:31-50].) The precharge instruction contained within the

operation code is described as follows: 16

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The access mode [contained in the operation code] also determines whether the DRAM should precharge the sense amplifiers or should save the contents of the sense amps for a subsequent page mode access. Typical settings are “precharge after normal access” and “save after page mode access” but “precharge after page mode access” or “save after normal access” are allowed, selectable modes of operation. The DRAM can also be set to precharge the sense amps if they are not accessed for a selected period of time. (A83[10:47-55].) One advantage of an operation code that contains both a read/write instruction and an automatic precharge instruction is that it frees up bandwidth and increases overall efficiency. As Mr. Murphy explained: By including such [automatic precharge] information in the operation code, additional flexibility is provided that improves the efficiency of the memory access. This auto-precharge feature also allows for selective precharging and helps free up control bandwidth, whereas a dedicated precharge command [as in the prior art] consumes additional bandwidth. (A1603[¶25].) 5. Objective Evidence of Non-Obviousness

The invention recited in claim 34 of the ’037 patent, including the novel use of synchronously-controlled DRAM chips to improve speed and efficiency, achieved tremendous commercial success and widespread acceptance in the industry. (A1641-42.) As Rambus’s expert, Mr. Murphy, explained:

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Dr. Michael Farmwald and Dr. Mark Horowitz, inventors of the ’898 application and the ’037 patent, conceived inventions embodied in the ’898 application and claimed in the ’037 patent that solved the memory bottleneck problem. In fact, the inventions disclosed in the ’898 application and claimed in the ’037 patent, as well as other patents based on the ’898 application, have been instrumental in increasing DRAM performance to meet the ever increasing demands of processors. **** Synchronous memory devices, such as those claimed in the ’037 patent, have been very successful, and have largely replaced conventional asynchronous memory devices. The industry has accepted the inventions disclosed and claimed in the ’037 patent, as shown by the numerous companies that have licensed the inventions claimed in the ’037 patent, as well as those claimed in other patents derived from the ’898 application. (A1641-42[¶7-8].) Indeed, Rambus’s DRAM technology was “widely considered ‘revolutionary’ in the industry.” (A2444[¶91]; see also A1855 (stating in March 1992 that Rambus had a “revolutionary memory chip technology . . . offer[ing] a tenfold speed boost to memory chips”); A1872; A1879; A1883; A1860 (describing Rambus’s approach “a fundamental change in the design of computer memory systems”). Moreover, based on his pioneering efforts in developing synchronous memory device technology, Dr. Horowitz received an IEEE award and was elected to the National Academy of Engineering. (A2859.) “His research has changed the way an entire industry thinks about memory interfaces and fostered a revolution in that industry. Memory access bandwidths have increased by an order of magnitude in just a few years as a result of the ideas he pioneered.” (Id.; see also A2863.) 18

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Mr. Murphy also explained that “Drs. Farmwald and Horowitz’s solutions to the bottleneck problem were received with skepticism by many experts in the field at the time they conceived the invention,” but this skepticism was eventually proven wrong, “as a majority of the memory devices available today (e.g., DDR, DDR2, DDR3, SDRAMs) employ features that are claimed in the ’037 patent.” (A1642[¶9]; see also A2446[¶105] (“The response to the early presentations in 1989-90 was ‘just disbelief’ that Drs. Farmwald and Horowitz would be able to achieve a 500 megabit per second DRAM data rate.”); A1865 (potential licensees expressed concern whether a computer’s drivers and receivers “could work at these frequencies.”); A1878 (system companies were “skeptical that [Rambus could] operate reliably at these speeds.”).) Mr. Murphy also explained that “other

attempts to solve the memory bottleneck problem without incorporating the features disclosed in the ’898 application and the ’037 patent were not successful.” (A1642[¶10] (citing “Burst EDO” and “High Speed Toggle” memory devices as examples).) Notably, Micron did not submit any expert declarations or other evidence rebutting these facts. D. The Rejection Based on Bennett in View of Wicklund or Bowater

Bennett, the primary reference relied on by the Board, discloses a mainframe computer system, circa 1982. (A1045.) The reference focuses on the interface 19

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between a primary bus, called the “Versatile Bus,” and various different types of “Users” connected to it. (A1045[Abstract]; A1625[¶91].) Bennett’s Figure 38, reproduced below, shows four such Users connected to a “V Bus” or Versatile Bus.

(A1070.) At 396 pages long, Bennett discusses many different types of Users that can be connected to the primary bus and many different attributes of the primary interface. (A1625[¶91]; see A1045-1440.) It does not disclose DRAMs, however, nor does it disclose precharging. (A1628[¶¶100-02]; see A26-27.) Wicklund and Bowater, the secondary references relied on by the Board, both disclose conventional, asynchronous DRAMs. (A1653[¶39]; A1443[2:6266]; A1654[¶42]; A1448[Abstract].) They both discuss algorithms for a memory controller to determine when to send an independent precharge instruction to those DRAMs. (A1654-55[¶¶43-45].)

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1.

The Examiner’s Determination of Nonobviousness

It was an accepted fact in the proceedings below that Bennett does not disclose the recited “operation code” that contains both a write instruction and an instruction to automatically precharge after writing. (A1011[7-10].) Indeed, as Micron conceded, Bennett does not disclose or discuss precharging at all. (A172425 (Micron’s reexamination request not alleging any disclosure of precharging).) And the examiner found that neither Wicklund nor Bowater discloses the claimed “operation code” containing both a write and a precharge instruction. (A1541.) Thus, although the examiner found that Bennett generally discloses an “operation code” (A1512), he found that no reference discloses the claimed “operation code” containing both a write instruction and an automatic precharge instruction, and he further found that such an operation code would not have been obvious to a person of ordinary skill in the art in 1990 (A1513; A1516-17). Wicklund discloses a memory system using conventional, asynchronous DRAMs, in which a memory controller guesses whether to precharge the sense amplifiers of the asynchronous DRAMs based on prediction algorithms. (A1444[3:6-9; 4:4-25].) Wicklund includes a write instruction, but whether to precharge is determined separately by the memory controller using an algorithm and is triggered by a separate and distinct precharge instruction (issued by the memory controller to the asynchronous DRAMs) that is not combined with any 21

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write instruction. (A1654-55[¶¶43-45].) As the examiner found, any precharge instruction in Wicklund is sent by the memory controller after the write instruction has already been sent and the write operation completed. (A1498; A1513.) The examiner found that Wicklund does not contain the claimed “operation code” that “specifies that the memory device precharge a plurality of sense amplifiers.” The examiner explained that, in Wicklund, “[t]here is no indication that precharge is automatically performed after data is written.” (A1496-97.)

Instead, in Wicklund, an instruction to write is sent and data is written, then (if necessary) a separate instruction to precharge is sent, and then the sense amplifiers are precharged. (See A1498 (“[Wicklund] does not disclose . . . [a] precharging instruction [that] came within the same operation code as the specifying of the sampling of the data to be written request.”); see also A1510; A1513.) Thus, as the examiner found, in Wicklund, “page mode is automatically turned on or off based on a prediction of whether or not the next access will be at the same DRAM row address as the last one.” (A1498.) That, as the examiner stated, is different from the claimed operation code giving a precharge instruction along with a write instruction, such that the precharge instruction is automatically carried out after the write is performed. (Id.) The examiner also rejected Micron’s argument that it would have been obvious to combine the precharging algorithm of Wicklund with an operation code 22

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in a synchronous system. As the examiner found, because Wicklund fails to disclose the required step in claim 34 of automatically precharging the sense amplifiers after a write instruction, its combination with a synchronous system— even one that discloses an operation code having a write instruction—would not constitute a prima facie case of obviousness. (A1538; A1540-41.) Bowater also discloses a memory system using conventional asynchronous DRAMs and a timing-based algorithm in a memory controller for determining precharge. In contrast to Wicklund, the memory controller in Bowater opens a row and keeps it open until a certain amount of time passes. (See A1500.) In other words, Bowater assumes that, regardless of what the previous access was, the next access will be in the same row. (A1462[7:54-56].) If the next access is not in the same row, just like in other prior-art asynchronous DRAMs, Bowater closes the row (thereby incurring a time penalty, see A83[10:40-43]), and the sense amplifiers are then precharged. If multiple accesses are in the same row, Bowater waits for a specified amount of time and then closes the row, on the premise that the row should only be left open for a limited period of time to preserve the integrity of data in an open row, even if the next access is to the same row. (A1462[7:54-8:8].) The examiner found that Bowater does not disclose the claimed operation code that includes both a write instruction and an automatic precharge instruction. 23

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(A1500-01 (“Bowater does not disclose that such precharge information is included in an operation code that also indicates a write operation as recited in claim 34 since Bowater is respon[ding] to a counter and not an instruction that is included with a same operation code that includes a specify[ing] of sampling data to be written.”); see also A1516.) As the examiner found, Bowater has no

operation code that includes a write operation and a precharge instruction, as recited by claim 34. (A1500-01.) Instead, Bowater has a timer, and after a certain amount of time the row is closed and the sense amplifiers are precharged in response to an independent instruction to precharge that is given to the DRAM separate from any read or write instruction. (Id.; A1516; A1654-55[¶¶43-45].) The examiner further explained that one would not have been motivated to include the precharge information of Bowater in an operation code. Specifically, he found that the precharge indication of Bowater “is based on a counter and there is no support for including this information along with [a] write request since that would defeat the purpose of the essential counter.” (A1501.) As he further explained, “[i]f Bowater provides precharge information that will automatically precharge after writing data, Bowater would not be able to change the time since the instruction would have already been sent.” (A1502.) Thus, the examiner found that none of Bennett, Wicklund, or Bowater includes an operation code with an automatic precharge instruction and a write 24

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instruction, and it would not have been obvious to a person of ordinary skill in the art in 1990 to include such an operation code in a synchronous system. For this reason, the examiner withdrew the rejections and confirmed claim 34. (A153941.) 2. Micron’s Appeal to the Board

On appeal to the Board, Micron argued that Bennett, while not disclosing precharging, discloses “an operation code that instructs the receiving memory device as to what function to perform.” (A1741-42; see also A1067.) Micron further argued that it would have been obvious in 1990 to include both a write request and an automatic precharge instruction in Bennett’s alleged operation code, notwithstanding that neither Bennett nor any other cited reference actually discloses this concept, and notwithstanding that the examiner had found precisely the opposite. Micron’s argument was not only contrary to the examiner’s findings, it was also contrary to the only expert testimony proffered on this issue. Rambus’s expert, Mr. Murphy, testified that in Bennett’s mainframe computer system, highlevel and low-level instructions would be generated by different parts of the system. (See A1628[¶102] (“Because Bennett is not focused on memory devices, it does not provide any disclosure about specific DRAM functions such as precharging.”); A1629[¶105] (“[T]he localized operation of precharging DRAMs 25

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after the completion of a row access is not something that would be handled by the processors in Bennett that generate requests to ‘memory’ as those processors would not be aware of the page boundaries [i.e., which row particular data is stored in] for the particular memory devices within the memory modules of Bennett.”).) As Mr. Murphy further explained, an instruction to precharge is a low-level instruction that would have been issued at the level of the memory controller for the DRAMs alone, whereas a read or write instruction would have been initiated by the CPU, translated by the memory controller, and then passed along separately to the DRAMs. (A1628[¶102]; A1629[¶105].) Indeed, in both Wicklund and Bowater, precharge instructions are generated by the memory controller, whereas read and write instructions are generated by the CPU—a higher level processor. Thus, as Mr. Murphy explained, if DRAMs were implemented in Bennett at all (despite not being taught), instructions to write and precharge would have been two different instructions, originated by two different parts of the system. (A1628[¶102]; A1629[¶105]; see also A1611[¶50].) Micron submitted no

evidence rebutting this testimony of Mr. Murphy. Indeed, Micron submitted no expert testimony at all during this reexamination proceeding. At oral argument before the Board, Micron argued for the first time that Bennett’s “read-modify-write” instruction constitutes a “multi-function” operation code because it specifies to both read and write in one instruction. (A1012[ll.4-8].) 26

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But, as Rambus explained, that instruction does not contain two independent and distinctly identifiable instructions. That is, when Bennett’s system is instructed to “read-modify-write” to a memory address, as shown in Figure 34 of Bennett, it reads the data in that memory address and writes a new value to that same address, all based on a single instruction. (See A1067; A1345[91:13-23].) The readmodify-write instruction has no independent portion that would allow it to, for example, only read or only write. (Id.) Thus, as Rambus explained to the Board, Bennett does not disclose a “bundled” operation code that gives two separate, independent instructions, such as 1) whether to read or write, and 2) whether to automatically precharge after the read/write operation has finished. (A1590-91.) Moreover, the examiner had already considered the disclosure of a “read modify write” instruction in Wicklund and other references and determined that such an instruction does not render obvious the concept of including both a write request and an automatic precharge instruction in a single operation code. (See, e.g., A1496 (noting that Wicklund “discloses the assertion of read, write and read modify write operation” (emphasis added); and A1513 (finding that Bennett in view of Wicklund does not render claim 34 obvious).) Thus, Micron’s “readmodify-write” argument had effectively already been considered and rejected by the examiner.

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3.

The Board’s Reversal of the Examiner’s Decision Confirming Claim 34

In its decision on appeal, the Board’s analysis of “Bennett with Wicklund or Bowater” spans a total of seven pages. (A29-35.) In those seven pages, the Board never identifies any specific errors in the examiner’s underlying findings of fact regarding the teachings of Bennett, Wicklund, or Bowater. (Id.) For instance, the Board found that “Bennett discloses synchronous memory chips” and further found that Bennett renders obvious the use of synchronous DRAM chips. (A29.) Although Rambus disagrees with those findings, they are nevertheless the same findings that the examiner made. (A1539.) Likewise, the Board adopted wholesale the examiner’s finding that “Bennett discloses controlling memory devices using operation codes.” (A30; A1512.) The Board also found that “Bennett discloses multiple functions in a memory write code,” referring specifically to the “read-modify-write code” disclosed in Figure 34 of Bennett. (A27; A30.) Although the examiner had not specifically addressed whether a read-modify-write (“RMW”) instruction constitutes a single- or multiple-function operation code, he repeatedly discussed the presence of RMW instructions in the prior art and concluded that they did not disclose or render obvious the operation code recited in claim 34, i.e., one that contains both a write instruction and an automatic precharge instruction. (See, e.g., A1496-97; A1504; A1540.) 28

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For instance, in discussing various combinations based on the Olson reference (not appealed by Micron), the examiner discussed the read-modify-write concept at length and rejected the notion that it inherently discloses the claimed operation code: Examiner agrees that it is further inherent with a RMW [read-modify-write] request that the sense amplifiers must be precharged “some time after a write operation”; however, the claims are not broad to cover any arbitrary time period. The claims specifically require that the precharging is indicated in the same operation code that specifies that the memory device must sample data to be written and that the precharging is responsive to the writing of data and not any other time period or instruction. (A1504.) The examiner similarly found that the RMW instruction in Wicklund did not render obvious an operation code that includes both a write instruction and an automatic precharge instruction, as recited in claim 34. (A1513; 1540-41.) Thus, the examiner was fully aware of RMW instructions and specifically rejected the notion that they inherently disclose or render obvious the operation code of claim 34. On appeal, the Board did not point to any factual errors in these findings by the examiner. (See A29-35.) Regarding Wicklund, the Board likewise did not dispute the examiner’s finding that any precharge instruction in Wicklund is issued as a separate instruction after a read/write instruction has already been received. (A1498.)

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Despite accepting the examiner’s finding that Wicklund teaches only separate instructions for writing and precharging, the Board found that “the precharge and write functions (and their signals) are intimately coupled together . . .” (A30.) Notwithstanding claim 34’s clear requirement that the write and

precharge instructions be given at the same time, the Board concluded that the alleged “intimate[] coupl[ing]” of these two separate instructions in Wicklund “support[s] the obviousness of the disputed limitations of claim 34 requiring the signals to be in a single op code”—flatly contrary to the Examiner’s conclusion of nonobviousness based on the same facts. (Id.) The Board further reasoned that “Bennett discloses controlling memory chips using multiple functions in a write code.” (Id.) Based on this, the Board found “it would have been obvious to place the prior art coupled write and precharge signals as described in the ’037 patent or Wicklund into Bennett’s op code which carries related write signals together, so that the modified chips of Bennett (DRAMs) can be precharged after a write function as was typically required in DRAMs.” (A31.) The examiner, in contrast, had reached the opposite conclusion (i.e., nonobviousness) based on the same facts. Specifically, the examiner had looked at Wicklund’s disclosure of separate write and precharge operations and concluded that this does not disclose or render obvious the claimed operation code, even if combined with Bennett. The examiner 30

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noted that, in Wicklund’s normal mode, the device “precharges prior to the writing of data that is at a new address and not automatically after data is written.” (A1513 (emphases added).) Accordingly, because combining Wicklund with

Bennett still would not result in the recited features of claim 34 (i.e., an operation code containing both a write instruction and an instruction to automatically precharge after writing), the examiner concluded there was no prima facie case of obviousness. (Id.) The Board justified its departure from the examiner’s conclusion of nonobviousness as follows: The Examiner’s rationale for nonobviousness based on these findings appears to be that row closing causes a precharge on the current row, and then writing on the next row occurs. (See [A1512-13].) While the findings underlying the rationale appear to be factually supported to an extent, the findings support obviousness, because the rationale does not consider that the controller signals a precharge on the DRAMs after writing in the normal mode. Also, the controller signals a precharge after shifting from the page mode to the normal mode and writing to a new row pursuant to the shift. (A32-33 (emphases in original).) Two things are notable about the Board’s justification for reversing the examiner’s finding of nonobviousness. First, the Board failed to indicate any error in the examiner’s underlying findings, acknowledging instead that they “appear to be factually supported to an extent” (without explaining what aspects, if any, are 31

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not factually supported). (Id.) Second, the Board cited no record evidence to support its conclusion that the examiner’s findings “support obviousness” rather than nonobviousness as the examiner found. Moreover, contrary to the Board’s suggestion that the examiner failed to consider certain facts, the examiner had in fact “consider[ed] that the controller signals a precharge on the DRAMs after writing in the normal mode.” (Id.) Specifically, the examiner had thoroughly reviewed this aspect of Wicklund and found: Wicklund precharges based on a “next access.” Thus, at best, Wicklund discloses that precharging occurs some time after the writing of data, however this does not disclose automatically precharging after writing data and wherein this precharging instruction came within the same operation code as the specifying of the sampling of the data to be written request. Precharging based on a next access is determined prior to memory access and this determination does not instruct a memory device to precharge automatically after data is written. (A1498 (emphasis added).) The Board never challenged this factual finding by the examiner as being incorrect. The Board also concluded that Wicklund’s prediction algorithm suggests that it would have been obvious to send the precharge signal with the write signal in advance of closing the row. (A31.) The Board cited Wicklund’s disclosure of closing a row after a number of page mode cycles to allow the sense amplifiers to refresh their charges. (Id.) The Board concluded—directly contrary to the 32

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examiner’s conclusion—that “it also would have been obvious to send a precharge signal with a write signal in an op code, before writing to the currently open DRAM row in a page mode, but after determining, pursuant to a clock, that the page mode time is about to expire, as Wicklund and Bowater suggest.” (Id. (internal citations omitted).) Again, though, the examiner had already considered this argument and rejected it: The claims require the automatic[ ] precharge of data after the writing of data not the automatic[ ] precharge after a counter has elapsed. In addition, assuming arguendo that this is an automatic[ ] precharge that occurs sometime after the writing of data, as noted above, this indication is based on a counter and there is no support for including this information along with [a] write request since that would defeat the purpose of the essential counter. (A1501 (emphasis added).) The Board did not address or even cite to this finding by the examiner in its decision on appeal. On rehearing, the Board reiterated that “[t]he thrust of [its] Decision is that it was widely known . . . that ‘prior art systems typically precharge DRAMs in the non-page (normal) mode after a read or a write option.’” (A10.) It further

reiterated that “the Decision simply describes the two separate signals as coupled in the prior art, because one follows the other in the normal read or write mode. As such, putting the two related signals into the same operation code would have been 33

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obvious, since Bennett puts other related instructions in the same operation code such as the read-modify-write operation code.” (A10-11.) Nowhere in its

rehearing decision did the Board point to any factual errors in the examiner’s decision or explain factually why its own belief about what a person of ordinary skill in the art would have considered obvious in 1990 was superior to the examiner’s conclusion, given that both conclusions were based on the same facts. 4. The Board’s Determination That Bennett Rendered Synchronous DRAMs Obvious in 1990

As explained above, the examiner construed a “synchronous dynamic random access memory device” in claim 34 to mean “a synchronous DRAM chip, hence requiring the memory to be on a single integrated chip.” (A1480 (emphasis added); see also A1539.) In arriving at this construction, the examiner relied on the ’037 patent’s specification, which makes clear that a synchronous DRAM device is a single chip. (A1480-82 (citing A80[3:46-49].) Neither Micron nor the Board has challenged this construction. Thus, regarding the “synchronous

DRAM” limitation, the question before the examiner and the Board was whether a person of ordinary skill in the art in 1990, reading Bennett (which does not disclose DRAMs) would have been motivated to connect a single DRAM chip directly to Bennett’s primary bus and operate it synchronously. It is undisputed that, while Bennett discloses many possible Users that can be connected to the synchronous Versatile Bus, it does not disclose DRAMs, even 34

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though DRAMs existed at the time of Bennett’s filing.

(A1628[¶100];

A1600[¶17].) Nevertheless, Micron argued that one of the disclosed Users in Bennett—the so-called “large memory” User—could hypothetically be made up of DRAMs, such that DRAMs are either “inherent or obvious.” (A1723 (“A person having ordinary skill in the art would have understood the disclosure of the large slower memory chips as an inherent or obvious description of DRAM based devices incorporating the synchronous bus interface.”).) The only DRAMs in use at the time of the claimed invention, however, were asynchronous DRAMs. (A1601[¶20].) For instance, Wicklund and Bowater both disclose conventional, asynchronous DRAM-based systems. The known way of using DRAMs at that time was by connecting many DRAM chips to a secondary bus having a dedicated memory controller. (A1625[¶92]; A1442; A1600-01[¶¶1920]; A1611[¶50]; A1654[¶41].) That whole group, i.e., the asynchronous DRAMs along with the secondary bus and a memory controller (collectively called a memory card or module), was then connected to a primary bus. (A1625[¶92].) Indeed, an expert retained by Micron conceded in litigation that Bennett’s “large memory,” to the extent it could be made up of DRAMs, “would have been composed of multiple chips.” (A1686 (emphasis added).) And Samsung, the other party that initially requested reexamination, made the same point in its request, i.e., that Bennett’s large memory “necessarily” would have been made of multiple 35

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chips. (A1842; see also A1625[¶92].) As Rambus explained to the Board, these admissions are highly relevant because the examiner’s construction of “synchronous dynamic random access memory device” specifically requires a single chip that operates synchronously (as opposed to multiple asynchronous chips that are connected to a memory controller that, in turn, is connected synchronously to a primary bus). (A1586-87.) Consistent with Micron’s and Samsung’s admissions, Bennett discloses that the “large memory” includes up to 232 addresses of 32-bit words (A1625[¶92] (citing A1347[95:58-59])), a number that even now cannot be contained on a single DRAM chip. (See A1600[¶17]). Moreover, as Mr. Murphy explained in an unrebutted declaration, Bennett’s architecture would not permit individual DRAM chips to be connected directly to Bennett’s primary bus. Specifically, Mr. Murphy testified that Bennett describes the VBI as being designed to accept complex connections, containing many different pins. (A1626-28[¶¶95-99].) If a single DRAM chip were to be connected to the primary bus, it would have to contain all of those pins and the complex circuitry that goes with them. (Id.) Mr. Murphy explained that DRAMs were desirable specifically because they were small and cheap, and adding so many pins and so much circuitry would have made each DRAM chip large and expensive and therefore undesirable. (Id.; see also A1303[8:10-12].) 36

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Despite these facts, the examiner found that Bennett rendered synchronous DRAMs obvious in 1990, based on its disclosure of “memory devices that receive[ ] a clock.” (A1539.) Although none of the cited prior-art references disclosed a synchronous DRAM, and despite Rambus’s evidence showing that no one in 1990 (or now, for that matter) would have connected a single DRAM chip directly to the synchronous primary bus in Bennett’s mainframe computer (akin to connecting a home’s driveway directly to a 16-lane superhighway), the Board nevertheless agreed with the examiner, finding that Bennett’s Figure 38 shows “memories” connected to a synchronous bus, which the Board concluded could be individual DRAM chips. (A26-27; A3-6.) The following annotated figures from Wicklund (top) and Bennett (bottom) summarize the Board’s holding on this point:

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As illustrated above, Rambus presented evidence (including admissions by Micron and Samsung and the unrebutted testimony of Mr. Murphy) that, to the extent DRAMs would be used at all in Bennett, they would have been incorporated as shown above in red (see arrow pointing to Device D), i.e., an entire group of asynchronous DRAMs and their controller would be attached to Bennett’s primary bus. The Board found, however, that it would have been obvious in 1990 to follow the blue path above (see arrow pointing to Device C) by attaching an individual DRAM chip directly to the synchronous Versatile Bus of Bennett’s mainframe computer system.

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The Board further addressed claim 34’s requirement that the synchronous DRAM include a “delay time” between a write instruction and the corresponding write operation. In finding this limitation obvious, the Board simply stated that Rambus’s argument “reduces to [the] single chip argument.” (A7.) In other words, according to the Board, if one were to modify Bennett to include a single DRAM chip connected synchronously to the primary bus, that chip would necessarily satisfy the claimed delay time limitation. But Bennett does not discuss the claimed delay time at all. (A1628[¶100].) Nor did the Board point to any other reference from which the delay-time limitation could be incorporated. IV. SUMMARY OF ARGUMENT The Board erred in reversing the examiner’s finding that an operation code having both a write instruction and an automatic precharge instruction was not obvious in 1990. Without identifying any specific errors in the examiner’s

underlying findings of fact, the Board nevertheless reached the opposite conclusion regarding obviousness. Simply put, the Board substituted its own presumed

expertise for the record evidence developed by the examiner regarding what a person of ordinary skill in the art would have considered obvious in 1990 in view of Bennett, Wicklund, and Bowater. When the examiner’s unchallenged findings of fact are given their due weight, the Board’s ipse dixit declaration of obviousness cannot withstand a substantial-evidence review. 39

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Alternatively, the Board erred in determining that Bennett would have rendered obvious a single-chip synchronous DRAM, where Bennett does not even disclose a DRAM, let alone a synchronous DRAM having the required delay time limitation. The evidence is overwhelming that, to the extent DRAMs would have been used at all in Bennett’s mainframe system, they would have been configured as an array of asynchronous DRAM chips (as in the prior art), collectively controlled (asynchronously) by a memory controller, which in turn would be connected to the synchronous Versatile Bus. The Court need not reach this issue if it reverses on the “operation code” issue outlined above. V. ARGUMENT A. Standards of Review 1. Factual Findings of the Board Are Reviewed for Substantial Evidence Based on the Entire Closed Record, Including Any Findings of Fact Made by the Examiner

This Court reviews factual findings of the Board for substantial evidence, based on a review that is “confined to the factual record compiled by the Board.” In re Gartside, 203 F.3d 1305, 1315 (Fed. Cir. 2000). “Under the substantial evidence standard of review, [the Court] search[es] for evidence, clearly set forth in the record below, to justify the conclusions that the Board has drawn.” Brand, 487 F.3d at 868.

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This Court’s review of a Board decision is necessarily based on a “closed” administrative record, as explained in Gartside: In appeals from the Board, we have before us a comprehensive record that contains the arguments and evidence presented by the parties, including all of the relevant information upon which the Board relied in rendering its decision. That record, when before us, is closed, in that the Board’s decision must be justified within the four corners of that record. Id., 203 F.3d at 1514. This Court has also “expressly held that the Board’s opinion must explicate its factual conclusions, enabling [the Court] to verify readily whether those conclusions are indeed supported by ‘substantial evidence’ contained within the record.” Id. (citing Gechter v. Davidson, 116 F.3d 1454, 1460 (Fed. Cir. 1997).) The “closed” record in an inter partes reexamination proceeding includes any findings of fact made by the examiner. Sometimes, the Board expressly incorporates the examiner’s findings into its own opinion. See, e.g., In re Rambus, Inc. v. NVIDIA, Corp., 2013 WL 595881, *8 (Patent Tr. & App. Bd.). Other times, the Board purports to adopt only those examiner findings that support its own decision, as it did here. (See A25 (“The findings in the RAN supporting the decision here are also adopted.”).) In either case, all of the examiner’s findings must be considered part of the record on appeal and must be given appropriate weight in determining whether the Board’s decision is supported by substantial 41

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evidence.

See Gartside, 203 F.3d at 1512 (“‘[S]ubstantial evidence’ review

involves examination of the record as a whole, taking into account evidence that both justifies and detracts from an agency’s decision.”) (emphases added) (citing Universal Camera Corp. v. NLRB, 340 U.S. 474, 487-88 (1951)); see also St. Clair Intellectual Property Consultants, Inc. v. Canon Inc., 412 Fed. Appx. 270, 276 (Fed. Cir. 2011) (unpublished) (stating that “an examiner in reexamination can be considered one of ordinary skill in the art”). 2. The Board Cannot Simply Rely on Its Own Expertise; It Must Point to “Concrete Evidence in the Record” to Support Its Findings

In Zurko, this Court made clear that, in determining patentability, the Board cannot simply rely on “common sense” or its own expertise without pointing to specific factual support in the record: As an administrative tribunal, the Board clearly has expertise in the subject matter over which it exercises jurisdiction. This expertise may provide sufficient support for conclusions as to peripheral issues. With respect to core factual findings in a determination of patentability, however, the Board cannot simply reach conclusions based on its own understanding or experience—or on its assessment of what would be basic knowledge or common sense. Rather, the Board must point to some concrete evidence in the record in support of these findings. To hold otherwise would render the process of appellate review for substantial evidence on the record a meaningless exercise.

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In re Zurko, 258 F.3d 1379, 1385-86 (Fed. Cir. 2001) (citing Baltimore & Ohio R.R. Co. v. Aderdeen & Rockfish R.R. Co., 393 U.S. 87, 91-92 (1968)); accord Brand, 487 F.3d at 869 (“[I]n the context of a contested case, it is impermissible for the Board to base its factual findings on its expertise, rather than on evidence in the record, although the Board’s expertise appropriately plays a role in interpreting record evidence.”). 3. The Board’s Ultimate Conclusion of Obviousness Is Reviewed de Novo

“Obviousness is a question of law that [this Court] review[s] de novo with underlying factual findings.” In re NTP, Inc., 654 F.3d 1279, 1297 (Fed. Cir. 2011); see also In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1378 (Fed. Cir. 2007) (“Although based on determinations of underlying facts, which we review for substantial evidence, the ultimate conclusion of obviousness is a legal question, which we review de novo.”). B. The Board Erred in Reversing the Examiner’s Determination That an Operation Code Containing Both a Write Instruction and an Automatic Precharge Instruction Was Not Obvious in 1990

The examiner correctly found that none of the cited prior art references discloses or renders obvious the claimed use of an operation code that includes both a write instruction and an instruction to automatically precharge after writing. Although the Board agreed with the examiner’s factual findings regarding those

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references “to an extent” and never pointed to any factual findings it disagreed with (see supra § III.C.3), it nevertheless reversed the examiner on the ultimate determination of obviousness. For the reasons explained below, this was legally erroneous. 1. The “Closed Record” in This Case Contains Unchallenged Findings of Fact by the Examiner That Undercut the Board’s Determination of Obviousness

The examiner made several findings of fact regarding Wicklund, Bowater, and the state of the art, which significantly undercut the Board’s determination of obviousness. The Board never challenged any of these findings, which were supported by unrebutted record evidence, as erroneous, and they remain part of the “closed record” in this case, reflecting the viewpoint of a person of ordinary skill in the art. See St. Clair, 412 Fed. Appx. at 276 (holding that examiners in These

reexamination can be considered those of ordinary skill in the art). unchallenged findings by the examiner include: State of the Art

• “[I]t would not have been recognized [in the art] that all DRAMs inherently received precharging information from an operation code. As noted in the applicants’ citation, conventional DRAMs, after a read operation, performed the precharge function only in response to an additional instruction—typically transmitted via a rising edge 44

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transition of the RAS strobe signal [not an operation code].

In

addition, conventional DRAMs did not automatically precharge, in response to an operation code, a plurality of sense amplifiers after sensing data.” (A1529 (emphasis in original).) Wicklund • “[T]he Examiner agrees with the Patent Owner that Wicklund fails to disclose the sending of [pre-charge] information to the memory device synchronously with respect to an external clock and that the precharge information causes the sense amplifiers to be automatically precharged after the data is written.” (A1495.) • “There is no indication [in Wicklund] that precharge is automatically performed after data is written.” (A1497.) • “[T]he Examiner notes that Wicklund precharges based on ‘a next access.’ Thus, at best, Wicklund discloses that precharging occurs some time after the writing of data, however this does not disclose automatically precharging after writing data and wherein this precharging instruction came within the same operation code as the specifying of the sampling of the data to be written request.” (A1498.)

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• “In both [possible situations in Wicklund,] precharging is not determined/invoked automatically after the writing of data but instead before. Thus, the Examiner disagrees with the Requester in that

Wicklund automatically precharged after writing data. Instead, as noted above, Wicklund precharges prior to the writing of data that is at a new address and not automatically after data is written.” (A1513.) Bowater • “The Examiner agrees with the Patent Owner that Bowater is unrelated to affirmatively precharging after a write operation and instead is a mechanism to allow the page to be left open—‘how long data can be left in the sense amplifiers[.]’ In addition, the Examiner agrees that Bowater does not disclose that such precharge information is included in an operation code that also indicates a write operation as recited in claim 34 . . .” (A1500.) • “The claims require the automatic[ ] precharge of data after writing of data[,] not the automatic[ ] precharge after a counter has elapsed [as in Bowater]. In addition, assuming arguendo that this is an automatic[ ] precharge that occurs sometime after the writing of data, as noted above, this indication is based on a counter [in Bowater] and there is 46

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no support for including this information along with write request since that would defeat the purpose of the essential counter.” (A1501.) • “In fact, precharge cannot be specified with a write request since Bowater discloses, e.g., in Figure 9, that Extra time period can be given before pre-charge. If Bowater provides precharge information that will automatically precharge after writing data, Bowater would not be able to change the time since the instruction would have already been sent.” (A1502.) These unchallenged findings of fact by the examiner—whom the law recognizes as a person of ordinary skill in the art—significantly undercut the Board’s ultimate conclusion of obviousness, as further explained below. 2. The Examiner’s Factual Findings Support Only Nonobviousness; the Board’s Contrary Determination Lacks Substantial Evidence

Based on the unchallenged findings of fact summarized above, the examiner declined to maintain the obviousness rejections based on Bennett in view of Wicklund or Bowater. Notably, this decision was based not on any perceived defect in Bennett (beyond the absence of the claimed operation code) but, rather, on the defects identified above in Wicklund and Bowater regarding the operationcode limitations. (See A1538 (“[T]he Examiner is not maintaining the 47

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[Bennett/Wicklund] rejection to the claims due to the noted deficiency of Wicklund.”); id. (“[T]he Examiner is not maintaining the [Bennett/Bowater] rejection to the claims due to the noted deficiency of Bowater.”).) Indeed, the examiner acknowledged that “the prior art [including Bennett] disclosed an operation code by issuing specific types of memory requests such as Write or Read Modify Write.” (A1539.) The examiner concluded, however, that combining these teachings with Wicklund or Bowater still would not satisfy the “operation code” limitations of claim 34 because of the defects in Wicklund and Bowater themselves. (See A1540-41.) On appeal, the Board agreed with the examiner’s factual findings “to an extent” (A32) and presented no specific disagreements with any of the examiner’s findings. (See A29-33.) The Board simply drew a different conclusion based on those findings, namely that a person of ordinary skill in the art in 1990 would have found it obvious to combine the separate write and precharge instructions of Wicklund or Bowater into a single operation code in Bennett that included both a write and an automatic precharge instruction. (See A30-33; A10-11.) Notably, the Board did not make any findings of fact or point to any evidence showing that any of the cited prior art references includes a single operation code containing both a write instruction and an automatic precharge instruction, nor did the Board

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disagree with the examiner’s specific factual findings that those references do not disclose such an operation code. (A30-33; A10-11.) Regarding Wicklund, the Board failed to rebut with substantial evidence the examiner’s specific finding that in both possible situations in Wicklund, “precharging is not determined/invoked automatically after the writing of data but instead before” and therefore “Wicklund precharges prior to the writing of data that is at a new address and not automatically after data is written.” (A1513.) The Board simply stated, without citing any record evidence, that “the [examiner’s] rationale does not consider that the controller signals a precharge on the DRAMs after writing in the normal mode” and, “[a]lso, the controller signals precharge after shifting from the page mode to the normal mode and writing to a new row pursuant to the shift.” (A32-33.) But the examiner had considered precisely these facts and found that they did not constitute an “automatic” precharging instruction, as required by claim 34. Specifically, the examiner acknowledged the following teaching of Wicklund: Wicklund follows by stating that “but if the new address is different from the current row address then the current page mode will have to be terminated and a new cycle started.” Thus the Examiner notes that precharge is invoked so that the new address can be sampled by the memory device.

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(A1513.)

Thus, the examiner specifically considered the fact that Wicklund

precharges in the normal mode, but he concluded that this does not satisfy claim 34 because Wicklund “does not disclose . . . [a] precharging instruction [that] came within the same operation code as the specifying of the sampling of the data to be written request.” (A1498; see also A1510; A1513.) In other words, Wicklund issues a precharge instruction only after it becomes aware that a new row must be opened based on a new read/write request; it does not precharge automatically after a write request based on that request’s operation code, as required by claim 34. Thus, as the examiner correctly found, simply combining Wicklund and Bennett would not satisfy claim 34 because there is no disclosure in Wicklund (or Bennett) of automatically precharging based on an operation code that includes both a precharge and a write instruction, as claim 34 specifically requires. The Board offered no substantial evidence to rebut this correct finding by the examiner. Likewise, with Bowater, the Board failed to rebut with substantial evidence the examiner’s specific finding that “there is no support for including [precharge] information along with write request since that would defeat the purpose of the essential counter [in Bowater].” (A1501 (emphasis added).) The Board also failed to rebut the examiner’s finding that, in Bowater, “precharge cannot be specified with a write request since Bowater discloses, e.g., in Figure 9, that Extra time period can be given before pre-charge. If Bowater provides precharge information 50

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that will automatically precharge after writing data, Bowater would not be able to change the time since the instruction would have already been sent.” (A1502 (emphasis added).) These factual findings by the examiner—which the Board did not challenge or even attempt to rebut with record evidence—preclude a prima facie case of obviousness based on Bennett in view of Bowater. Accordingly, the Board’s contrary conclusion (based solely on its own presumed expertise) lacks substantial evidence in the record. 3. The Board Erred by Substituting Its Own Presumed Expertise for the Record Evidence Developed by the Examiner

The facts of this case are very similar to those in Brand, in which this Court held that the Board had exceeded its authority under the Administrative Procedures Act. 487 F.3d at 870-71. Brand involved an interference proceeding in which one issue before the Board was whether senior party Brand had derived the claimed invention from junior party Miller. This issue turned, in part, on certain drawings that Miller had shown to Brand, depicting a certain type of screw called a “bugle headed screw dog.” Id. at 866. Notwithstanding an unchallenged declaration submitted on Brand’s behalf, the Board concluded that Miller had proven derivation based on the following analysis: The Board reasoned that “one skilled in the art . . . would have recognized [the] suitability [of Miller's bugleheaded screw dogs MX2002] for securely supporting a tapered flitch in the position depicted in [MX2001].” 51

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The Board did not cite any testimony or record evidence to support its conclusion. The Board further held that “[t]he ability of the bugle-headed screw dogs to tightly clamp the flitch would have been readily apparent.” The Board also held, in the alternative, that the information in MX2001, taken alone, was sufficient to teach one of ordinary skill in the art how to practice the method of the count. Again without citing record evidence, the Board concluded that the drawing in MX2001 disclosed the invention. Id. at 867 (citations to trial record omitted; brackets in original). On appeal, this Court held that the Board had “improperly substituted its own opinion for evidence of the knowledge of one of ordinary skill in the art.” Id. at 870. As the Court explained: The Board’s conclusion that “one skilled in the art . . . would have recognized [the] suitability [of Miller's bugle-headed screw dogs MX2002] for securely supporting a tapered flitch in the position depicted in [MX2001]” was not supported by any citation to the record. Similarly, the Board did not anchor in the record its conclusion that an artisan would have deduced from the drawing of a flitch in MX2001 standing alone a method of securely fastening a tapered flitch to a staylog, given that the drawing did not depict any dogs or holes in the flitch. **** The Board’s finding that an artisan would have known how to securely fasten a tapered flitch to a staylog using bugle-headed dogs does not represent a simple substitution of bugle-headed dogs for existing dogs, but detailed inferences as to the mounting process. Id. at 870 (citations to the trial record omitted; brackets in original). 52

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Here, as in Brand, the Board substituted its own presumed expertise in place of the examiner’s factual findings, which reflect the viewpoint of a person of ordinary skill in the art. See St. Clair, 412 Fed. Appx. at 276. Specifically, whereas the examiner had found that the combination of Bennett and Wicklund or Bowater did not constitute a prima facie case of obviousness, the Board reached the exact opposite conclusion based solely on its own assessment of what a person of ordinary skill in the art would have thought and done in 1990 given full knowledge of these references. As in Brand, the Board’s point of departure with the examiner “was not supported by any citation to the record.” 487 F.3d at 870. Specifically, when the Board explained why it disagreed with the examiner’s nonobviousness conclusion (A32-33), it failed to cite any evidence showing why the examiner’s conclusion was wrong. Instead, the Board simply stated that the examiner’s “findings

underlying the rationale appear to be factually supported to an extent” but that they “support obviousness” rather than nonobviousness. (Id.) In the entire three-

paragraph section in which the Board lays out its putative case against the examiner’s nonobviousness conclusion, the Board never cites to the record or explains where the examiner made any factual errors. Instead, the Board’s opinion appears to be simply that—an opinion as to what a person of ordinary skill in the art would have thought and done in 1990, given full knowledge of Bennett, 53

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Wicklund, and Bowater. Whether the Board has sufficient expertise in the field of DRAMs to justify this opinion is irrelevant, because such expertise, even if it exists, is not enough. As this Court made clear in Brand, the Board must base any substantive validity determinations on record evidence, not its own expertise. 487 F.3d at 870-71. Here, the overwhelming weight of the record evidence supports nonobviousness (as the examiner correctly found), not obviousness. 4. The Board Also Ignored Rambus’s Evidence That Supported the Examiner’s Finding of Nonobviousness

Not only did the Board ignore the examiner’s findings of fact, it also ignored Rambus’s unrebutted evidence regarding the alleged combinations of Bennett with Wicklund or Bowater. For instance, Rambus presented two unrebutted

declarations of Mr. Murphy, an expert in the field, who testified that, in prior-art devices like that described in Bennett, (1) a write instruction and a precharge instruction came from different sources, making it impractical and illogical to combine them into one operation code, and (2) the triggers for the write and precharge instructions were different events because the operations necessarily occurred at different times, and a whole new system would have been required to combine them in a single operation code. (Supra § III.B.4.) Specifically, Mr. Murphy explained that “the localized operation of precharging DRAMs after the completion of a row access is not something that would be handled by the processors in Bennett that generate requests to ‘memory’ 54

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as those processors would not be aware of the page boundaries for the particular memory devices within the memory modules of Bennett.” (A1629[¶105].) Micron presented no evidence to the contrary—only attorney argument. Thus, the

unrebutted evidence showed that, in Bennett, precharging instructions, if they existed, would have come from within the large memory, while requests to memory, such as read, write, or read-modify-write, would have been sent across the primary bus from the CPU. Because one request would have been generated internally and the other externally, it would have been impractical, and certainly not obvious, to combine them into a single operation code from an external source. (Id.) Likewise, Mr. Murphy explained that, in a prior-art asynchronous DRAM device, a DRAM would have been instructed to write only after a row had been opened, and it would have been instructed to precharge later, at the time it was decided to close the row. (A1629[¶104].) The disclosures of Wicklund and

Bowater fully support this position. Thus, the unrebutted evidence showed that a write instruction would have been initiated by a separate trigger at a separate time from a precharge instruction, and there was no clear way to issue those instructions at the same time. Rambus further presented evidence that one of ordinary skill in the art looking at Wicklund and Bowater would not have tried to combine write and 55

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precharge instructions into a single operation code because those references teach away from such a solution. Specifically, Wicklund teaches a prediction algorithm for determining when to precharge, and Bowater teaches a timing algorithm that assumes, in every case, that the next memory access will be in page mode. (Supra § III.C.1.) Both of these precharge algorithms point away from combining a write instruction with an automatic precharge instruction, as Mr. Murphy explained. (A1653-54[¶40]; A1654[¶43].) This Court has held that, when the prior art teaches a different way of accomplishing a result from that taken by the applicant, that constitutes a teaching away from the invention. Pozen Inc. v. Par Pharm., Inc., 696 F.3d 1151, 1164-65 (Fed. Cir. 2012); see also In re Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994) (“A reference may be said to teach away when a person of ordinary skill, upon reading the reference, . . . would be led in a direction divergent from the path that was taken by the applicant.”). Accordingly, the Board

additionally erred in not considering that both of the secondary references it relied upon, Wicklund and Bowater, teach away from the claimed invention. C. The Board Erred in Holding, Without Any Prior-Art Examples of Synchronous DRAMs, That Synchronous DRAMs Would Have Been Obvious in View of Bennett

The Board’s holding that synchronous DRAMs would have been obvious to use in Bennett’s mainframe computer system in 1990 is unsupported by substantial evidence. None of the prior art references that the Board relied on disclose 56

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synchronous DRAMs, and there is no evidence that anyone has ever, to this day, modified Bennett in the manner suggested by the Board, i.e., attaching a single DRAM chip directly to Bennett’s primary bus, akin to attaching one’s residential driveway directly to a 16-lane superhighway. As the evidence overwhelmingly established, Bennett’s Versatile Bus—the backbone of a mainframe computer system circa 1982—was not designed to directly interface with a single DRAM chip, in the manner suggested by the Board. Accordingly, the Board’s finding that this feature would have been obvious in 1990 is not supported by substantial evidence. See In re Glatt Air Techniques, Inc., 630 F.3d 1026, 1029-30 (Fed. Cir. 2011). As explained above, Bennett discloses only one type of memory that even Micron asserted could have been made up of DRAMs, namely Bennett’s “large memory.” As also explained above, this large memory in Bennett would have contained many DRAM chips connected together on a separate, secondary bus and operated asynchronously. (Supra § III.D.4.) Indeed, an expert retained by Micron in litigation readily conceded that the “large memory” described in Bennett “would have been composed of multiple chips, and that each chip would have at least one memory array.” (A1686; see also A1588; A1625[¶92]; A1842 (Samsung

conceding same in reexamination request).) Thus, although the Versatile Bus in Bennett operates on a clock signal (i.e., synchronously), to the extent DRAMs 57

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would have been implemented in Bennett (despite not being taught), the evidence shows that each individual DRAM would have operated on a separate, secondary bus connected to a memory controller, and they would have been controlled asynchronously, as in Wicklund and Bowater. (Id.) The Board, however, attempted to piece together other teachings from Bennett to assert that Bennett would have rendered obvious the use of synchronous DRAMs. Specifically, the Board relied on Bennett’s use of synchronous very large scale integrated circuit (“VLSIC”) devices to assert that those devices represented synchronous memory chips, which could have been replaced with synchronous DRAMs. (A29 (citing A26-27).) But VLSIC devices were not, contrary to the Board’s assertions, simply memory chips, nor were they interchangeable with DRAMs. Indeed, they did not necessarily include memory at all, contrary to the Board’s assertions. (See A26-27 (citing A1305[12:14-38]

(broadly discussing VLSIC as a single chip, but not mentioning memory); A1306[14:19-24] (same); A1317[35:59-68] (stating that Users may be

implemented as modules, or multi-chip devices, and that “[t]hese modules may themselves be implemented as VLSIC devices,” but never stating that memory in particular could be implemented as anything other than a multi-chip device); A1319[39:59-61] (describing layout of VBI); A1332-33[66:9-67:18] (comparing asynchronous and synchronous primary buses).) 58

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More important, neither the examiner nor the Board pointed to any evidence suggesting that a person of ordinary skill in the art in 1990 would have been motivated to implement DRAMs as anything other than the known prior-art configuration, e.g., as multiple asynchronous DRAMs connected asynchronously via a secondary bus to a memory controller, as shown in Wicklund and Bowater. This entire group could have been connected to Bennett’s primary bus via a VBI interface, and there appears to be no dispute that such a configuration would not have satisfied the “synchronous DRAM” limitation of claim 34, as that term has been properly construed, because the DRAMs themselves would have been asynchronous. Moreover, the evidence is overwhelming that this is how a person of ordinary skill in the art in 1990 would have implemented DRAMs in Bennett, had he chosen to do so. A1842.) The Board never really acknowledged Rambus’s evidence on this point but concluded, nevertheless, that it would have been obvious to implement a singlechip synchronous DRAM in Bennett merely because asynchronous DRAMs were “ubiquitous” at the time: Bennett discloses synchronous memory chips. (B1, B2). DRAMs were a well-known, if not dominant, form of a memory chip device at the time of the invention. . . . For example, Wicklund shows that DRAMs were the most popular form of memory chips at the time of the 59 (A1625[¶92]; A1627-28[¶¶98-100]; A1686; A1588;

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invention. (W1.) Neither Rambus, nor the Examiner, disputes that DRAMs were ubiquitous memory chips. (A29.) Contrary to the Board’s apparent logic, the mere fact that DRAMs were “ubiquitous” in 1990 does not, in and of itself, mean it would have been obvious to implement them as synchronous memory chips attached directly to a primary bus. To the extent DRAMs were ubiquitous in 1990, they were ubiquitous as groups of asynchronous DRAMs controlled by a separate controller. In short, there is no evidence to support the Board’s finding that a person of ordinary skill in the art in 1990 would have been motivated to take a single DRAM chip out of a large prior-art DRAM array, such as that shown in Wicklund or Bowater, and attach it directly to the primary bus of Bennett’s mainframe computer system, without any intervening memory controller or secondary bus. To be sure, there is no evidence that anyone skilled in the art ever did so, nor is there any evidence suggesting that they would have wanted to do so in 1990. Further compounding its error, the Board failed to cite any evidence (let alone substantial evidence) showing that the “delay time” limitation in claim 34 would have been obvious from Bennett. The examiner had made no findings regarding the claimed “delay time,” having already confirmed claim 34 based on the lack of the claimed “operation code.” (Cf. A1524-25 (not addressing “delay time” argument for other combinations of references based on lack of operation code).) The Board dismissed Rambus’s delay time argument by simply saying that 60

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it “constitutes another version of Rambus’s single chip argument.” (A6.) In other words, the Board apparently assumed that the claimed delay time would have necessarily been present in Bennett based on its previous assumption that Bennett renders obvious a synchronous DRAM device. Yet this is not true. As Mr. Murphy explained in an unrebutted declaration, Bennett discloses many different types of parameters, but nowhere in its nearly 400 pages does it disclose the “delay time” recited in claim 34: None of the configuration parameters [in Bennett] are related to controlling the delay between a request and a response within the system. [A1307-08[15:22-17:54].] The configurability of the eight parameters provides 31,045 different combinations. (Id.) The flexibility provided by the Versatile Bus Interface Logics of Bennett require a great deal of support circuitry, which is evident from the voluminous Bennett disclosure that includes well over a hundred figures and even more columns of text describing the structure of the interface. (A1626[¶95.]) The Board failed to point to any evidence that the “delay time” limitation is actually disclosed in Bennett. Moreover, the Board failed to show that the delay time limitation of claim 34 is necessarily inherent in a synchronous memory system. Given Rambus’s specific argument that Bennett does not disclose a device satisfying the delay time limitation of claim 34 (A4102), the Board erred in failing to provide evidence that the delay time limitation would have necessarily been satisfied by any synchronous DRAM. Cf. NTP, 654 F.3d at 1302 (reversing 61

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Board’s finding of inherent anticipation when prior art reference was silent on the limitation). VI. CONCLUSION For the foregoing reasons, this Court should reverse the Board’s decision finding the ’037 patent invalid as obvious and reinstate the examiner’s finding of nonobviousness.

Dated: April 1, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 Attorneys for Appellant Rambus Inc.

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CERTIFICATE OF COMPLIANCE I certify that the foregoing BRIEF FOR RAMBUS INC. contains 12,987 words as measured by the word-processing software used to prepare this brief.

Dated: April 1, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000

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CERTIFICATE OF SERVICE I hereby certify that copies of the foregoing BRIEF FOR RAMBUS INC. were served upon registered counsel by operation of the Court’s CM/ECF system on this 1st day of April, 2013. Henry A. Petri, Jr. Novak Druce Connolly Bove + Quigg, LLP 1875 Eye Street, NW, 11th Floor Washington, DC 20001 henry.petri@novakdruce.com

/s/ Kay Wylie

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