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QUESTIONS ASKED BY N.M.DEVASHRAYEE SIR AND USHA MEHTA MAM IN CLASS 2010-2011 1. Define DOPING.

Doping is defined as INTRODUCTION of impurity into the intrinsic silicon or lightly doped Silicon. 2. How DOPING and (Alloying) AMALGAMATION is different? Doping creates effect at Atomic Level and Alloying at Molecular Level. So, Doping changes Electrical And Chemical Properties.Where as Alloying changes Physical Properties. 3. What is III-V Compunds? Name the P-Type And N-Type Impurity used for the same? These are heterogenous compounds which are the base of Modern day VLSI HIGH SPEED CIRCUITS. For Ex GaAs is a III-V semiconductor.Zn is a p type impurity and Sulphur is n type. 4. Draw C-V Characteristics of N-Type And P-Type MOS structure? How will you analyze for the defects using the same? 5. Which type of Wafer is used in VLSI circuits? Why? Or Why Not? P-Type <100> Silicon is used due to following reasons:Only 4 Atom per Unit Cell and so Higher Mobility Less Interface Trapped Charges Less Fixed Oxide Trapped Charges

6. Explain the dependence of Doping, Fermi Level, Flat Band Voltage, Capacitance Dielectric. 7. What do you mean by Self Alligned Polysilicon Gate?Why it is called So? In Self Alligned Polysi technology, The gate is put Before the doping is done . And thus Source and Drain are automatically aligned to Gate and is so called. 8. Aluminium cannot be used for Self Alligned Gate? Why? If Al is put before doping it will melt in the process of high Temperature which Al(M.P. =550 C)cannot handle. 9. What are the problems associated with self Alligned Gate Technology? Non Planar Topography.Ans to this is LOCOS. Fully Recessed LOCOS.(Silicon is etched to have surface Planarity)To have more planarity SWAMI and SILOS are used. 10. What are the limitations of LOCOS technique? Give Solutions. Birds Beak Problem in which the active area penetrates below the Gate and creates a Birds Beak. SWAMI and SILOS 11. Why Si3N4 is not directly incorporated onto the silicon? Bcoz it creates Stress. Therefore Oxide is also sometimes reffered to as STRESS RELIEF OXIDE. 12. Why Na or Nd < 10^23..or 10^18 ? Limitation is imposed by Number Density Of Silicon which is 5.02 X 10^22 for Si and 4.42 X 10^22 for GaAs. 13. What is Flat Band Voltage? Why it is always Negative? The voltage required to compensate the bend in the Energy Level which is caused by bringing two different materials together. As it has always to oppose the BEND in energy level, it is always Negative. 14. Define the following:- Threshlod Voltage,Electron Affinity, Work Function and Band Gap?

Vt:- The minimum voltage required for producing the inversion condition in the MOS device is called Vt (Electron Affinity):- It is minimum energy required to remove an electron from Conduction Band to Vaccuum. Work Fn:- Minimum energy required to remove an electron from FERMI LEVEL to Vaccuum. Band Gap:- The difference between Conducntion State Valence State. For Si it is 1.12eV, For Ge its 0.66eV(0.7eV), For GaAs its 1.42eV. 15. Differentiate Surface Mobility and Bulk Mobility? Are they different in magnitude? How? Mobility of electrons or Holes on the Surface of Semiconductor is drastically different than in bulk. This is Because of two reasons:- 1) Doping level is different(Active and Substrate are differently Doped) and 2) greater electric field is experienced by Surface electrons as E=dV/dx, And Voltage is applied at the surface. 16. W/L of Depletion mode MOSFET(Load) is smaller than Driver for an inverter? 17. Explain Figure of Merit of MOSFET. 18. Current in Saturation Region is ideally Constant. Why? 19. Why Drain and Source Terminals are to be reverse biased wrt Substrate in MOSFET? OR Why We form junctions of p-type on n substrate and Vice Versa, Why Not P on P and n ON n? To avoid Leakage. If Source and Drain are not reverse biased majority of the current will flow into the bulk. Observe carefully if N on N is made it is not any of the device.!!!! 20. Explain Voltage Bootstrapping. Where it is required? In dynamic circuits the voltage is definitely dropped into the pass transistor. This voltage level is required to be boosted if it is to be fed to next level of the circuit o.w. next level is weakly driven. For this direct Vdd supply is given to the node through the control transistor to BOOST(or BOOTSTRAP) the voltage level. 21. Noises On Chip. 22. Glitch. Example of a circuit which produces the same. 23. Mass Action Law. Np=ni2 24. TO CHECK WITH AMISHA MAM..*****W/Lp=2.5W/Ln.For DigitalWhat for Analog.??? Explain. No constraints!!!!For digital circuits FALL TIME and RISE TIME are the important parameters for Synchronization as it decides the SAMPLING INSTANT, whereas in analog the SAMPLING INSTANT is derived from the frequency of the ANALOG signal and is independent of the The W/L ratio of the transistors are purely derived frm the specs. For an inverter the thumb rule is (W/L)n = 5 (W/L)p. 25. Nand Implementation is preferred over Nor Logic. Explain Why? -In Nand PMOS are in parallel and so it takes half a time to charge the node as compared to NOR implementation.i.e. is FASTER than NOR logic. 26. **** To check on GOOGLE..Doping of Source and Drain are equal? Explain clearly. NOT ALWAYS. There is a doping profile in which DRAIN is lightly doped and is reffered to as Lightly Doped Drain. 27. Symmetric inverter.What it is? Why it is preffered? (W/L)p=2.5 (W/L)n.For mobility balance.To make tphl and tplh equal. 28. Give the expression of the Depletion layer width in a MOSFET? And so explain how PUNCH THROUGH can be avoided.

29. What is Fermi Level Of Energy? It is the level of energy where probability of finding an electron and hole is equal. 30. Draw High Frequency and Low frequency Model of any MOSFET. 31. Is Fermi level exactly in the middle of the Conduction and Valence Band ?Justify. No. Ef=(Ec+Ev/2)+ln(Nv/Nc)(KbT/2) 32. Why Fermi moves down when the doping is of Acceptor type.? (Similar for donor) Intorduction of Acceptor impurity causes the introduction of new energy Levels near the conduction band. This forces Intrinsic Fermi level to shift down as the prob of finding the hole at intrinsic level increases and is needed to be balanced.Similarly for Donor, It introduces energy levels near the Valence Band, and so the Fermi level gets pulled up. 33. *******Is mobility of electrons in Germenium is greater than Si? Why? Yes. For Ge un=3500, Si=1400. This is because electrns are more active in Ge due to its low bandgap.. This is not so in si. 34. Explain the problem of Latch UP? How it can be solved. The problem prominent in CMOS circuits where pnpn or npnp Thyristors are created which shorts the Supply to ground is Latch Up. Solution is use Deep Ion Implantation and SOI(By SIMOX Technology.) 35. Why do we Study INVERTER ONLY.Why not ANDOR.or any other gate.? This is COPYRIGHT ANSWER. 36. Explain different types of interconnects. Metal (Al) Interconnects (Cannot be crossed), Aluminium+Cu(0.5%) ( To avoid Electromigration, But still cannot be crossed) PolySilicon Interconnect (Can be crossed) 37. Why connection between Active and Passive devices is done through Aluminum only i.e. Interconnections? Following reasons:-Its Adhesive to Silicon, Cu being more corrosive than Al,No technology for Dry Etching of Cu, Cu being unable to form self passivating Oxide(such as Al2O3), Al is a better option. 38. What is Sheet Resistance and How to measure it? Sheet Resistance is the resistance of the sheet of one layer of Semiconductor. Its unit is /[], i.e Ohms per square. To find the total resistance of the substrate or active regions it is multiplied with no of squares piled up to form the given region.It is essentially[p(rho)/t]. 39. How will we determine if Substrate is doped or Not?? (Range of resistivity of silicon is to be mentioned here.) Measure its resistance and then take decision(Refer Pucknell) 40. What important role does RC time constant plays in each layer of MOSFET? 41. What is Lambda in MICROWIND? (Technology/2) 42. What is METAL1,2,3,4 in MICROWIND? Metals of different thickness and width meant for interconnection s and Supply or Ground lines. 43. What do you mean by LINEAR and NON LINEAR ICs?

44. What do you mean by EFFECTIVE GATE LENGTH? Why the designed Gate Length is always Greater than the Fabricated one? Explain mathematically.

Leff=L 2 Ld. Where Ld is the gate length diffused inside the gate in MOSFET. The Ld is almost directly proportional to the Jucntion Depth And so modern day VLSI devices demands the SHALLOW JUCNTIONS. Mathematically Ld=xj (sqrt((1+(2xds/xj)))-1),Ld is lateral diffusion under gate.xds is depletion width.

45. MOSFETS acts as Ideal Current source in ___________ Region. 46. What is Gate ENCROACHMENT? How To reduce it? SAME AS 44. 47. Comment about modern materials used for GATE dielectric. Also provide the state of art dielectric thickness in modern technology. High K Dielectric such as Zirconium Oxide(20),Hafmium Oxide(epsilon=12) , Tantanum Oxide(25), Titanium Oxide(40) etc. For 45 nm technology tox(SiO2)=1nm,High K =3.5-4nm. Here Leff for 45 nm technology is about 25-40nms.

48. Why DARK ROOMS are required? Properties of SILICON. 49. Interconnect Thickness is not SCALED DOWN in the SCALING of MOSFETS. WHY? The current carrying capacity is not to be disturbed. If thickness is scaled, Area is reduced and if A is reduced, Resistsnce increases and causes more power dissipation in form of heat which is undesirable. 50. Poly is preferred over Aluminum interconnects. Why?Crossing is possible in poly. 51. Can Refractive index of Glass Be changed? Yes. Dope the glass with materials such as Boron and the refractive index may be changed. 52. In High Speed Circuits DIRECT BAND GAP SCs are used? Why? Explain Clearly. 53. Silicon cannot be used to fabricate LED/ LASER diode. WHY? Silicon is INDIRECT BANDGAP material. To have emission, It is necessary to change the energy as well as Momentum for which external energy be needed to be supplied in form of heat which is never possible in VLSIs. 54. *****Explain the methods to improve the RC Time Constant of VLSI circuit. -Low K interconnect, Highly conducting material be used as interconnect,Use multilevel metaliization. 55. Silicon cannot be used to fabricate devices such as Light Sources and Light Detectors.Comment. 56. Dynamic circuits are more suitable for Synchronous circuits. Why? Dynamic circuits require Charging and Discharging(Refreshing) at each clock. In synchronous ckts this can be facilitated easily and so dynamic circuits are preffered. 57. CMOS cannot implement PIPELINE..Why? 58. When the MICROWIND IS CAPABLE OF CONVERTING .v into layout, Why we need LAYOUT EDITOR? Explain number 34 and answer is therein. 59. Explain the terms THROUGHPUT, LATENCY and maximium Clock Frequency in PIPELINING. Throughput= Latency=Initial Delay To obtain first O/P. Max Clock freq=

60. What do you mean by Charge Sharing problem in Precharge Evaluate Logic implementation. The parasitic capacitance of the next stage is undeterministic in PE logic. This could lead to erroneous interpretation as some of the charge may be eaten up by Parasitic Capacitance. 61. MOS is a DIODE? Justify.Ha ha.. 62. What do you mean by MILLER INDICES? Relate it with Qinterface Qoxide. <100><110><111> are miller Indices. It suggests the no of atoms in a single unit and the orientation of the crystal. 63. Why 100 silicon is preferred over 111? Low Qinterface and Low Qox. 64. What do you mean by OHMIC CONTACT? Comment on Rectifying Contact. Ohmic-Bidirectional. RECTIFYING(Unidirectional) 65. What is DEEP DEPLETION is MOSFET? 66. In short channel MOSFET mobility at bulk is greater than Surface. Why? In short channel MOSFETs, Vertical electric field is significant which results in scattering of electrons and thus reduces the effective electron mobility at the surface wrt bulk mobility. 67. Mobility is Constant? How? NO. Function of DOPING and TEMPERATURE. 68. What do you mean by Passivation Layer? 69. What is meant by INTERDIELECTRIC. In multilevel Metallization each of the layer is to be separated by a Dielectric and is reffered to as INTERDIELECTRIC. 70. Why HIGH PRESSURE OXIDATION is required for BIPOLAR device fabrication? 71. Why linear growth is converted in Parabolic while oxidation is going on? 72. How to measure the quality of Oxide? C-V Measurements, SIMS.Thickness by Ellipsometer 73. Why HCL or TCE is used in Wet oxidation? 74. How to measure the Gate Oxide Thickness? 75. At High temperature P or B are not static. Will this affect quality of oxide?How? 76. What do you mean by redistribution of Dopant in Oxidation? 77. Effect of poor quality oxide on NMOS and PMOS. 78. Explain the concept of Solid Solubility. 79. What is segregation coefficient? 80. Threshold voltages of FIELD and GATE OXIDES be different. Why? 81. Silicon is photosensitive or not? Comment. 82. What decides the thickness of photoresist in lithography? 83. What are MASK ALLIGNMENT MARKS? 84. Explain the effect of Wavelength of UV rays used in Lithography. 85. Explain FSM. Its types. 86. What do you mean by Registered O/P?

87. ******Design Digital HOLD circuit. 88. What is SPREADING RESISTANCE? 89. What do you mean by RESISTIVITY SWING in silicon. 90. What do you mean by BUFFER SOLUTION? 91. Comment on radiation hardened devices. 92. Why DRAIN and SOURCE have n+ Doping and not simply n doping? 93. What is LDD(LIGHTLY DOPED DRAIN)? To avoid HOT ELECTRONS which are emmited by Source and enters the Gate. 94. Why is TRANSCONDUCTANCE an important parameter of MOSFET? Explain. 95. What do you mean by resolution? Give approximate value for TEM. 96. What are Non Destructive Techniques? In modern day VLSI circuits, measurements of the manufactured devices is a great challenge. While measuring the parameters, instruments may create DAMAGE to wafer and is so called DESTRUCTIVE testing strategy. 97. Why Not GaAs Technique is not replacing Si Technology? High Temperature reliability. As GaAs is a compound semiconductor it decomposes under high Temperature conditions. And so silicon devices are preferred. Also, the manufacturing conditions of GaAs devices are very stringent. 98. Why VACCUUM is required for Electron Beam Lithograpgy? To Increase Mean Free Path of electrons. And to make the environment GAS Free which could react with anything. 99. 1 TORR = ___ mm Hg. 100. Give advantage of HF LAST method in Cleaning.

It forms a bond with H-Si-H and prevents the undesired oxidation of the silicon. 101. 102. What do you mean by High K Dielectric Material? Where it is used? Give its advantages.Now its clear. Why Aluminium is not used in todays High Speed VLSI circuis? Explain Junction Spiking Errors and

Electromigration And Stress Migration. Why Al-Si is used as Metallization Material? Why Al-Si-Cu is used as Metalllization material. 103. In an attempt to reduce the Transistor size we decrease L..! To compensate these effect why dont we increase

W to improve the Driving Capability. Explain.

104. 105. 106. 107. 108. 109.

Difference Between Transistor and JFET. As we have studied Mosfets are advantageous and Transistors. Then Transistors are not used at all???? Explain. Explain the difference between Transistors and JFETS. *********Why P-Well Only and Not N-Well????Technology is optimized to work on p type-wafers. *********What do you mean by Sintering and where it is used? How do we measure the Doping Concentration in an Junction? Which method is better out of SIMS(Secondary

Ion Mass Spectroscopy) and Spreading Resistance Method? Why? 110. Why Only Quartz is used in making all the furnaces?

111. 112. 113. 114. 115. 116. 117.

Discuss Isolation Techniques.-LOCOS, FOX , Deep Trench Isolation. Discuss Limitations of CMOS Technology.-Low Switching, Low Current Drive capacity. Compare Si with III-V Compuond Semiconductors. Pg. 519 Sze. How to reduce the Short Channel Effects? Using Ultrashallow Junctions. (Pg 524 Sze.) Explain The relation between Channel Length and Vt Roll OFF. Which is the most favourable candidate for Modern day Metallization? Why? Cu-(Low K Material)Silicides for Submicron Level devices-Low Electromigration and Lower parasitic resistance Maximum Allowable temperature Rise Of Si is a function of the Band Gap Of Semiconductor.

Because BandGap is a function of temperature. As Eg lowers we start losing control over the devices. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. 129. 130. 131. Explain SOI Technology. Give its advantages and Disadvantages. Explain the advantage of using Poly Gate? What do you mean by Self Alligned Gate technology. *********Can Inductor be manufactured on Chip? Explain. What are the ways in which The Capacitors can be Manufactured in an IC. reverse P-N Diode and MOS. What are the ways in which The Resistors can be Manufactured in an IC? How the concept of Sheet resistance is used to calculate the resistance of the Doped region and the channel? Junction Depth is a function of Diffusivity of the Dopant. Explain. What do you mean by Silicide? Where it is used ? What is CMP Chemical Mechanical Polishing? Define the term PLASMA. Explain its Application in VLSI. Name the etchants for the following materials:Sio2->Buffered HF Si3N4->Buffered HF Al-> HNO3 Au-> KI Mo-> H3PO4+HNO3+CH3COOH+H2O Pt-> HNO3+HCL+H2O W-> Very Complex etchant(No Need To remember) GaAs->H2SO4+H2O2+H2O What is Raster Scan and Vector Scan in Electron Beam Lithography. What is the limit to the scaling? (etaKbT/e)ln(Fan ins.) What is Isotropic and Anisotropic Ion Etching?Reactive Ion Etching.

In Isotropic etching dx/dy(where y is vertical and x is horizontal dimension) is 1 i.e. etching affects the film underneath also, i.e. in x direction. Where as in anisotropic etching dx/dy = 0. i.e. no lateral etching is done and IONS being heavier, do not etch Laterally.

132.

Define the Following Terms:Second Order Effects, Vt Roll Off, Threshold Mismatch, DIBL, Leakage Curents Why Second Order? (And Not third or Fourth.) Junction Leakage Electromigration Segregation Co-Efficient Junction Depth Ring Oscillator Resolution of SEM Reactive ION ETCHING(RIE)-Dry Etching RTA- Rapid Thermal Annealing Threshold Voltage Roll Off Lateral Diffusion Multilevel Metallization Gettering Wafer Cleaning Locked State Of PLL Designing a Digital circuit means adhering to Specs that suggests the value of V(ol) Designing an Analog Circuit means adhering to specs that suggests the value of ???? Surface Mobility Velocity Saturation GIBL DIBL Conductance (gm) Cut-Off Frequency Transit Frequency And Transit Time Figure Of Merit Of MOSFET() Short Channel Effects & Narrow Channel Effects Subthreshold Conduction Channel Shortening Punch Through Hot Electron Effect Substrate Effects Ohmic Contacts and Schottky Contacts Work Function Electron Affinity Inversion Of Channel in MOS:Weak And Strong Yield Yield Strength Step coverage Problem Thin Oxide and Field Oxide Thermionic Emission Surface Potential Surface Recombination Sputtering SIMOX Technology Solid Solubility Junction Spiking Sintering Process Dissociation Effect in Diffusion Intrinsic And Extrinsic Diffusion Plasma Electrical Over Stress Oxide Breakdown Hot carrier Degradation Punch Through. Setup Time & Hold Time Electrostatic discharge (ESD)

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