.

ADDA16
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User's Guide

Digital Signalprocessing Technology Norbert Nlker & Adolf Klemenz GbR Gelderner Strae 36 D - 47647 Kerken phone +49 (0) 2833 / 570 977 fax email www +49 (0) 2833 / 33 28 info@dsignt.de http://www.dsignt.de

D.Module.ADDA16 User's Guide

Revision History

D.Module.ADDA16 Revision History

1.0 July 2004

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D.Module.ADDA16 User's Guide

Contents

1 INTRODUCTION............................................................................................. 4 2 DSP INTERFACE............................................................................................ 6

2.1 Address Decoding.............................................................................. 6 2.2 Registers ........................................................................................... 8

2.2.1 FS Register............................................................................................ 9 2.2.2 CONFIG Register................................................................................... 9 3 A/D CONVERTER......................................................................................... 11

3.1 Analog Inputs................................................................................... 11 3.2 Sampling Clock................................................................................ 12

4 D/A CONVERTER......................................................................................... 14

4.1 DAC Updates (LDAC) ...................................................................... 17 4.2 Analog Outputs ................................................................................ 18

5 POWER SUPPLY.......................................................................................... 19 6 PINOUT ........................................................................................................ 20 7 MECHANICS ................................................................................................ 22 8 ELECTRICAL CHARACTERISTICS.............................................................. 23

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Contents

List of Tables and Figures:

Table 2-1 DSP Bus Interface Signals ................................................................. 6 Table 2-2 Address Decoding: 64K bank select ................................................... 7 Table 2-3 Address Decoding, 16 word sub-bank select ...................................... 7 Table 2-4 ADDA16 Registers............................................................................. 8 Table 3-1 Analog Input Signals........................................................................ 11 Table 3-2 Sampling Clock Signals ................................................................... 13 Table 4-1 Analog Output Signals ..................................................................... 18 Table 6-1 D.Module.Connector, blank fields are not connected ........................ 20 Table 6-2 Analog Input Connector Pinout ........................................................ 21 Table 6-3 Analog Output Connector Pinout...................................................... 21

Figure 1-1 D.Module.ADDA16 Block Diagram..................................................... 4 Figure 1-2 Location of Jumpers .......................................................................... 5 Figure 3-1 Sampling Clock Circuit .................................................................... 12 Figure 4-1 DAC Interface.................................................................................. 14 Figure 5-1 D.Module.ADDA16 Mechanics ......................................................... 22

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Introduction

1 Introduction
The D.Module.ADDA16 is a 16 bit, 250 KSPS, 4-channel A/D and D/A converter board, suitable for the D.Module family of DSP Computer Modules. Four A/D channels are converted synchronously using Successive Approximation Converters (SAR). This architecture provides a very short delay from sampling to availability of the digital output word, and is best suited for control loops, where any delay will result in increased dead time, complicating the control algorithm. Synchronous sampling preserves the phase information of the input channels. The analog inputs are high-impedance differential inputs, but can also be driven from single-ended sources by grounding the IN- input. The D/A converters are followed by a second order smoothing filter and provide a single-ended bipolar output. The DACs can be updated synchronously with the ADC sampling frequency, or operate in free running mode, i.e. the output is updated immediately after a write to the corresponding DAC. A third mode combines unsynchronized writes to the DACs with simultaneous update of 2, 3 ,or all four channels.

Vref

ADC0 In+ ADC0 InADC1 In+ ADC1 InADC2 In+ ADC2 InADC3 In+ ADC3 In-

+ AD7663 + AD7663 + AD7663 + AD7663 CNVST LDAC Config progr. Divider int. Clock ADC and DAC Registers LDAC (DAC Update)

DAC0

Vref

DAC1

AD5544 DAC2

DAC3

EXT_CLKIN EXT_CLKOUT
FS_Register

Figure 1-1 D.Module.ADDA16 Block Diagram

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Introduction

1 A B C

16

32

JPGND

F G H I J K L M N O P

JPA16

JPA17

T U V

Figure 1-2 Location of Jumpers JPGND connects the analog to the digital ground. It is closed by default using a 0 ohms resistor. If your system already provides a AGND-DGND connection you must open this jumper to avoid a GND loop. JPA4,5,16,17, and 18 select the ADDA16 base address.

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JPA4

JPA5

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DSP Interface

2 DSP Interface
The D.Module.ADD16 is memory-mapped to the DSP module's IOSEL memory space. It occupies a contiguous address space of 16 addresses. The base address is determined by five address jumpers on the board. The data bus is connected to the upper 16 data bits of the DSP. Data format is 2's complement, hence the sign bit (MSB) of the converters and the DSP sign bit match, independent of the DSP data bus width. Two interrupt outputs can be configured to request exception handling for ADC or DAC from the DSP. Many DSP boards also allow to use these interrupts as DMA trigger events for background data acquisition with minimum DSP load. Pin U2 U3 U4 U5 U6 U7 U8 U9..U14 U15..U30 V12..V14 Signal nRD nINT0 nINT1 nWR BUSCLK nRESET nIOSEL A0..A5 D15..D31 A16..A18 Type input output, o.d. output, o.d. input input input input input bidir, hi-z input Comment read strobe, active low Interrupt line 0 to DSP, active low interrupt line 1 to DSP, active low write strobe, active low DSP external bus clock reset input, active low DSP memory area select signal DSP address bus DSP data bus DSP address bus

Type: o.d = open drain output, hi-z = high impedance, bidir = bidirectional Table 2-1 DSP Bus Interface Signals

2.1 Address Decoding

Five address jumpers on the D.Module.ADDA16 allow to select the base address of the board. If a jumper is closed, the corresponding DSP address line must be '1' to decode the board, if a jumper is open, the corresponding address line must be '0'. jumper. Jumper JPA18 .. JPA16 decode a 64K address block, jumper JPA5 and JPA4 decode a 16 words sub-block. This allows to select one of 32 possible address blocks.

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The following tables shows the possible address offsets from IOSEL base address. Please note that Texas Instruments C6000 processors use a different addressing scheme (byte addressing), and always drive A18 high in IOSEL memory area. 64 K Bank Select JPA18 open open open open closed closed closed closed JPA17 open open closed closed open open closed closed JPA16 open closed open closed open closed open closed Base Address C6000 DSP Modules not possible other nIOSEL + 0 nIOSEL + 0x01.0000 nIOSEL + 0x02.0000 nIOSEL + 0x03.0000 nIOSEL + 0x04.0000 nIOSEL + 0x05.0000 nIOSEL + 0x06.0000 nIOSEL + 0x07.0000

nIOSEL + 0 nIOSEL + 0x04.0000 nIOSEL + 0x08.0000 nIOSEL + 0x0C.0000

Table 2-2 Address Decoding: 64K bank select Inside this 64 K block, address jumpers A4 and A5 allow to select one 16 word area out of a 64 word block: 16 Word Sub-Bank Select JPA5 open open closed closed JPA4 open closed open closed Base Address Offset C6000 DSP Modules 0x00 0x40 0x80 0xC0 0x00 0x10 0x20 0x30 other

Table 2-3 Address Decoding, 16 word sub-bank select The default settings are JPA18 closed, JPA17 and JPA16 open, JPA5 and JPA4 open, hence the factory setting base address is IOSEL + 0x00000 on C6000 DSP modules, and IOSEL + 0x40000 on other DSP modules.

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DSP Interface

2.2 Registers
Six registers provide access to the A/D and D/A converters and to the board configuration. Address Offsets in () brackets are valid for C6000 DSPs: Offset Register Width 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits Comment read: ADC channel 0 write: DAC channel 0 read: ADC channel 1 write: DAC channel 1 read: ADC channel 2 write: DAC channel 2 read: ADC channel 3 write: DAC channel 3 read/write: sampling frequency selection read/write: configuration register

0x00 (0x00) ADDA0 0x01 (0x04) ADDA1 0x02 (0x08) ADDA2 0x03 (0x0C) ADDA3 0x04 (0x10) FS 0x05 (0x14) CONFIG

Table 2-4 ADDA16 Registers The 16 bit wide ADDA0..ADDA3 registers provide direct access to the A/D and D/A converters. Data from the A/D converters is serially transmitted to the bus interface. A shift register for each ADC performs serial-parallel conversion, and a state machine starts ADC readout as soon as the ADC signals conversion complete. This scheme minimizes system noise, especially during the ADC sampling period. The ADC interface is buffered, hence data can be read while the next conversion result has already started to shift in. An interrupt is generated as soon as the ADC data is copied from the shift register to the buffer. Data is written to the D/A converters via a serial interface too. The bus interface provides parallel to serial conversion. The DAC interface is buffered, but only one level deep. If the first DAC has been written, the data is immediately copied to the shift register and transferred to the DAC. Now the second DAC value can be written. This data is held in the buffer and not copied to the shift register before the first DAC transmission is completed. During this time the buffer is not available for new data, hence you have to wait for the first transmission to finish before the third DAC value can be written. Each time the DAC buffer is ready for a new transfer, an interrupt is generated. You may also poll the DAC_READY flag in the CONFIG register to determine if the interface is ready to accept new data.

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DSP Interface

For a detailed description of DAC access methods please refer to chapter 4, D/A Converter. The FS register allows to select the sampling frequency, either generated onboard via a programmable divider, or an external clock fed to EXT_CLKIN. The CONFIG register selects the interrupt mapping and the D/A converter update scheme (LDAC). The sampling clock output EXT_CLKOUT can be enabled for cascading multiple ADDA16 boards, or synchronizing other peripherals, and the status of the D/A converter data transfer can be read.

2.2.1 FS Register Bit 15..8 Bit 7. 0 undefined on read operations, don't care on writes ADC Sampling Frequency 0x00 selects external sampling clock provided from EXT_CLKIN 0x0F .. 0xFF select an internally generated sampling clock. The clock is generated from a 4 MHz quarz oscillator by this equation: fs = 4MHz / (FS_REG + 1) values < 0x0F result in a sampling clock > 250 kHz and are not supported. The reset value of this register is 0x00

2.2.2 CONFIG Register Bit 15..8 Bit 7 undefined on read operations, don't care on writes write: EXT_CLKOUT_ENABLE a 1 written to this bit will enable the EXT_CLKOUT output, a 0 will disable this output and put it into high impedance. read: DAC_READY a 1 signals the DAC buffer is ready to accept new data, if 0, the DAC buffer is full and new data cannot be accepted.

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Bit 6, 5

read/write: INT1_DAC, INT1_ADC these bits determine the nINT1 interrupt output usage: 00 - not used, high impedance 01 - ADC interrupt 10 - DAC interrupt 11 - not allowed

Bit 4, 3

read/write: INT0_DAC, INT0_ADC these bits determine the nINT0 interrupt output usage: 00 - not used, high impedance 01 - ADC interrupt 10 - DAC interrupt 11 - not allowed

Bit 2 .. 0

read/write LDAC these bits determine the DAC update mode: 000 - DAC is updated following each write to any DAC 001 - DAC update after writing to DAC 1 010 - DAC update after writing to DAC 2 011 - DAC update after writing to DAC 3 100 - DAC update synchronous with ADC conversion start 101, 110, 111 - reserved, not allowed Please refer to chapter 4.1, DAC Updates (LDAC) for a detailed description of DAC update modes.

The reset value of the CONFIG register is 0x00.

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A/D Converter

3 A/D Converter
The analog-to-digital converters are successive approximation converters with 16 bit resolution and a maximum sampling frequency of 250 kHz. Conversion time is 1.25 s, acquisition time is 2.75 s, independent of the sampling clock. The digital output is serially transmitted to the DSP bus interface, where it is converted into a parallel output word. Data format is 2's complement . A 0V input converts to a 0x0000 output word, -2.5V input converts to 0x8000, and the maximum positive input voltage of 2.4999V converts to 0x7FFF. An LSB is 76.3 V. The serial transmission from ADC to the bus interface is clocked with 40 MHz. The transmission and loading of the parallel buffer takes 18 clock cycles = 450ns. Hence, the ADC latency time is 2.75s + 1.25s + 450 ns = 4.45s.

3.1 Analog Inputs

The analog input interface is a buffered differential amplifier which accepts input voltages of +/- 2.5V. Single-ended inputs can be connected by grounding the INinput. The output of the differential amplifier is fed to the A/D converter input. Pin G1 G2 H1 H2 I1 I2 J1 J2 K1 K2 L1 L2 M1 M2 Signal ADC0 IN+ ADC0 INAGND AGND ADC1 IN+ ADC1 INAGND AGND ADC2 IN+ ADC2 INAGND AGND ADC3 IN+ ADC3 INComment Channel 0 non-inverting input Channel 0 inverting input Analog Ground Analog Ground Channel 1 non-inverting input Channel 1 inverting input Analog Ground Analog Ground Channel 2 non-inverting input Channel 2 inverting input Analog Ground Analog Ground Channel 3 non-inverting input Channel 3 inverting input

Table 3-1 Analog Input Signals No anti-aliasing filters are provided on the D.Module.ADDA16. If the input signal contains spectral components above the Nyquist frequency (1/2 sampling fre D.SignT 2004 Doc #1.0 11

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A/D Converter

quency), external band limiting filters are required. The required filter order depends on the out-of-band energy levels: the filter should ideally attenuate any outof-band signals to be 90 dB below the full-scale input. i.e. if out-of-band signals are present at 30dB below full-scale, the filter should provide additional 60 dB attenuation. The wide analog input bandwidth (800 kHz) of the converters allows to use the ADDA16 in a sub-sampling configuration if the input signal is inherently bandlimited, like in the intermediate frequency stage of a receiver.

3.2 Sampling Clock

The A/D converter conversion start signal is generated from an on-board oscillator or provided externally via EXT_CLKIN. The FS Register is used to set the sampling clock source and frequency.

CLK CNVST 1D LOAD

40 MHz Clock Source

div 10

CLK FS_REG == 0 CNT == 0

FS Reg.

EXT_CLKOUT_ENABLE

EXT_CLKIN

EXT_CLKOUT

Figure 3-1 Sampling Clock Circuit The 40 MHz internal clock source is pre-divided by 10, and fed to a preset-able down counter, which is preset from the module's FS register. If the FS register is programmed to a value different from 0, the counter output is used as the conversion start signal. If the FS register is 0, the external sampling clock from EXT_CLKIN is used. The conversion start signal is re-synchronized to the 40 MHz master clock. This synchronization flip-flop is powered from the analog supply voltage to minimize jitter and noise on the conversion start signal.

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A/D Converter

The EXT_CLKOUT output can be enabled and used to feed slave ADDA16 boards if more than four input channels are required, or synchronize other peripheral devices to the sampling clock. For an eight-channel system, stack two ADDA16 boards and configure as follows: Board 1 is the master, it generates the sampling frequency. Set the desired sampling frequency and enable this board's EXT_CLKOUT output. Board 2 is the slave board. It is configured for external sampling clock. Leave this board's EXT_CLKOUT disabled. (also remember to select a different base address for Board2) Finally connect EXT_CLKOUT to EXT_CLKIN. This will route Board1 EXT_CLKOUT to Board 2 EXT_CLKIN. Pin C22 C23 Signal EXT_CLKIN EXT_CLKOUT Comment external sampling clock input external sampling clock output

Table 3-2 Sampling Clock Signals

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D/A Converter

4 D/A Converter
The digital-to-analog converters use a serial data interface too. The DSP bus interface logic provides the parallel-to serial converter. Data is clocked into the DAC with a 40 MHz clock. A transmission takes 20 clock cycles. The DAC settles to 1 LSB accuracy in 2 s. Adding the 500 ns for serial transmission, the DAC latency is 2.5 s, which must be taken into account as deadtime in control loops. The DACs itself use straight binary coding, but the bus interface logic converts 2's complement into straight binary, so the DSP can write it's native 2's complement data to the DAC. A 0x8000 translates to -2.5V on the output, a 0x0000 to 0V output, and 0x7FFFF to +2.4999V. The software designer must take care to avoid 2's complement overflows, as this will generate full-scale signal spikes on the DAC output. Most DSPs provide internal saturation logic to prevent 2's complement overflow.

The DAC interface is single-buffered. The buffer can be written by the DSP while a serial transmission to the DAC is in progress. This allows to write two DACs almost immediately following each other, but if 3 or 4 DACs should be written, the DSP program must wait for the buffer to be free before the data for DAC2 and DAC 3 is written.

Load

40 MHz DSP Addr 0 and 1 DSP Data DSP Write DACBuffer DAC Serial Data In

DACShifter

Transmission Request

Shift Complete

Control Logic

Interrupt, DAC_READY

Figure 4-1 DAC Interface

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D/A Converter

On a write to one of the four DAC registers the bus interface latches the 16 data bits and the two least significant address lines, which determine the DAC to write to. A transmission request signal is generated. If no shift operation to the DAC is currently in progress, the shifter is loaded with the buffer content and immediately starts shifting out the data to the DAC. Simultaneously with the shifter load signal, an interrupt is generated, rsp. the DAC_READY flag is set. The DSP can then write the next data word to the DAC buffer. Again, a transmission request is generated, but now the control logic delays the shifter load until the current shift is completed. The DAC interface will generate an interrupt every time a shift is completed, hence every 500 ns. This corresponds to the maximum DAC update rate of 250 kHz for all four channels. Each individual DAC is written every 2 s, corresponding to it's required settling time. In most systems slower update rates will be used. You can either synchronize DAC writes to the ADC interrupt, or use a DSP timer interrupt if an update frequency different from the ADC sampling frequency is required. Many systems will also use "on demand" DAC writes, i.e. write to the DAC only if the output value needs to be changed. The DSP programmer should use one of the following programming techniques: only one DAC is used in the system: Direct writes to the DAC are possible, either programmed, from an interrupt, or DMA triggered.

two DACs are used: After writing to the first DAC the serial transfer starts immediately and the buffer is free again to accept the data for the 2nd DAC. Poll the DAC_READY flag before writing to the 2nd DAC to make sure transfer has started and the DAC buffer is free. The latency caused by polling the DAC_READY flag is approximately 50 ns ADDA16_DAC_WRITE (0, data); while (!(ADDA16-cfg & ADDA16_DAC_READY)); ADDA16_DAC_WRITE (1, data);

three or four DACs are used: always poll the DAC_READY flag before writing to a DAC, or use interrupt transfers. Polling DAC_READY will block your program for only 50 ns before the 2nd DAC can be written, but for 500 ns each before writing to the 3rd and the 4th DAC. If this time is not tolerable use interrupts as shown in this program fragment:

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void dac_int (void) { static int idx = 1; ADDA16_DAC_WRITE (idx, data); /* write to next DAC */ if (++idx == 4) { ADDA16->cfg &= ADDA16_INT1DAC; /* disable INT1 */ idx = 1; } } void main (void) { install_interrupt (SIG_INT1, dac_int); ... for (;;) { ... ADDA16_DAC_WRITE (0, data); /* write to DAC 0 */ ADDA16->cfg |= ADDA16_INT1DAC; /* enable DAC-Int */ } }

After the first DAC is written from the main program, DAC interrupts are enabled by setting the corresponding bit in the ADDA16 Configuration Register. As soon as the DAC buffer is free, an interrupt will be generated, and interrupt nd function dac_int() will be executed. In this function the 2 DAC is written, and variable idx in incremented. As soon as the buffer is free again, dac_int() is invoked again. Now the third DAC is written. After the buffer is free, dac_int() will be executed for the last time. Now the fourth DAC is written. idx will increment to 4, and further DAC interrupts are disabled by clearing the interrupt enable bit, until enabled again.

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D/A Converter

4.1 DAC Updates (LDAC)

Writing to a DAC will only store the data in the DAC's internal buffer register, but not update it's output. The LDAC signal is used to update the DAC output. The D.Module.ADD16 supports three configurations to generate LDAC, which are configured in the LDAC bitfield of the ADDA16 configuration register : 1. following any write to a DAC, LDAC is generated as soon as the transfer is complete 2. LDAC is generated only after writing to the second, third, or fourth DAC. 3. LDAC is synchronous with the ADC sampling frequency The first option, always generate LDAC following a write, is useful for on demand DAC writes, if phase relation between DAC channels is not important, or if only one DAC is used. Immediately after the write, the DAC will change it's output. This option is selected by writing a 0 to the LDAC bitfield. The second option will synchronously update the selected DACs after the last one is written. To control a 3-phase motor for example, three DACs are required and all should be updated synchronously to provide exact phase relationship. In this case, set the LDAC bitfield to 2. Now write the output values to DAC0, DAC1, and DAC2. After the last write (to DAC2), all three DACs synchronously update their outputs. If DAC update and ADC conversion should by synchronized, start writing the DACs in the ADC interrupt service. The last option is used if ADC sampling and DAC update should be synchronous and occur at exactly the same time. This configuration minimizes jitter on the DAC outputs. Typically the program will write to the DACs in the ADC interrupt service, to be synchronous. Exact phase relation between DAC channels is maintained as long as all DACs are completely written before the next conversion start (and hence LDAC) occurs. This can only be guaranteed for sampling frequencies below approx. 133 kHz: Following conversion start, it takes 4.5 s until the ADC interrupt is generated. If DAC writes are started now, it will take additional 2 s (4 x 500 ns) to write all four DACs. The total time from Conversion start until the DAC writes are complete is 6.5 s. This is the minimum sampling period to guarantee synchronous updates. Adding some extra time for interrupt latencies results in 7.5s, or 133 kHz maximum sampling frequency. This option is selected by writing a 4 to the LDAC bitfield.

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D/A Converter

4.2 Analog Outputs

The DACs are followed by an I-V converter, which translates the DAC output current into a voltage, and a 2nd order Butterworth smoothing filter. This filter attenuates the high frequency switching spikes generated by DAC code transitions. and smoothes the output waveform. The analog output is single-ended with +/- 2.5V full-scale output. The Butterworth filters are factory set to a corner frequency of 100 kHz. Custom corner frequencies are available on demand. Large capacitive loads on the outputs add a pole to the transfer function and will increase ringing and overshot, and, in extreme cases, cause instability. Capacitive loads > 100 pF should be connected via a series resistor (approx. 100 ohms). To avoid gain loss the input of the driven circuit should be a high impedance input. It is also possible to compensate the pole formed by the capacitive load with a series RC combination from output to AGND. Pin G31 G32 H31 H32 I31 I32 J31 J32 K31 K32 L31 L32 M31 M32 Signal DAC0 OUT AGND AGND AGND DAC1 OUT AGND AGND AGND DAC2 OUT AGND AGND AGND DAC3 OUT AGND Channel 0 output Analog Ground Analog Ground Analog Ground Channel 1 output Analog Ground Analog Ground Analog Ground Channel 2 output Analog Ground Analog Ground Analog Ground Channel 3 output Analog Ground Comment

Table 4-1 Analog Output Signals

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Power Supply

5 Power Supply
The ADDA16 module requires a bipolar analog power supply, and a single digital 3.3V power supply. The analog power supply is +/- 5V. For best performance a power supply build around a mains transformer and linear regulators should be used. The powersupply rejection ratio of the op-amps and converters used on the ADDA16 will attenuate power-supply noise up to 60dB. However, attenuation decreases with increasing frequency. High frequency noise, as produced by switch mode power supplies, cannot be sufficiently attenuated by the components and will degrade performance: high frequency noise may modulate the input and output signals, and is aliased into the baseband during conversion. A switch mode supply with linear post regulation doesn't cure the problem, because linear regulators suffer from bandwidth limitations too. If a switch mode supply must be used, add passive LC filters in the supply rails, tuned to the specific noise spectrum of the switcher. An excellent choice for a low-noise switch mode supply is the Linear Technology LTC1533 switching regulator. The digital power supply can be taken directly from the DSP supply. It powers the bus interface circuits, the serial interfaces to the data converters, and the sampling clock divider. This may add some jitter to the sampling clock, but this jitter is attenuated later by resynchronization in an analog-powered D-type flip-flop. Digital and Analog ground return paths should ideally be interconnected close to the converters. Only one interconnection should exist in the entire system. A jumper (JPGND) on the D.Module.ADD16 provides this connection. If your system already has interconnected AGND and GND, open jumper JPGND on the ADDA16 board. If multiple boards are cascaded, only one should have JPGND closed. Some experiments may be required to determine the best location for AGND-GND connection, depending on your system layout.

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Pinout

6 Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A VCC B GND nRD nINT0 nINT1 nWR BUSCLK nRESOUT nIOSEL A0 A1 A2 A3 A4 A5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D15 D15 GND C T U V

A16 A17 A18

-AVCC AGND +AVCC

EXT_CLKIN EXT_CLKOUT

GND

VCC

GND

Table 6-1 D.Module.Connector, blank fields are not connected

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Pinout

Pin F G H I J K L M N O P

1 +AVCC (use as output only!) ADC channel 0 IN+ AGND ADC channel 1 IN+ AGND ADC channel 2 IN+ AGND ADC channel 3 IN+ VCC (use as output only) rsvd rsvd

2 -AVCC (use as output only ) ADC channel 0 IN AGND ADC channel 1 IN AGND ADC channel 2 IN AGND ADC channel 3 IN GND (use as output only) rsvd rsvd

Table 6-2 Analog Input Connector Pinout

Pin F G H I J K L M N O P

31 +AVCC (use as output only!) DAC channel 0 OUT AGND DAC channel 1 OUT AGND DAC channel 2 OUT AGND DAC channel 3 OUT VCC (use as output only) rsvd rsvd

32 -AVCC (use as output only ) AGND AGND AGND AGND AGND AGND AGND GND (use as output only) rsvd rsvd

Table 6-3 Analog Output Connector Pinout

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Mechanics

7 Mechanics

max component height on top 1,59 mm

: 4,50 mm

4,85 mm 4,76 mm

max component height on bottom: 2,50 mm

7,96 mm

78,74 mm 2,54 mm1,27 mm 7,62 mm 2,54 mm 12,70 mm A B C

21 3, m m

53,34 mm

35,56 mm

2,54 mm 2,54 mm T U V 1 76,20 mm 83,82 mm 32

Figure 5-1 D.Module.ADDA16 Mechanics

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Electrical Characteristics

8 Electrical Characteristics
Power Supply analog: +/- 5V 150mA digital: +3.3V 400mA Operating Temperature 0 .. +70C Analog Inputs Input Voltage Input Resistance Input Bandwidth Analog Outputs Output Voltage Output Load A/D Converter Resolution Acquisition Time Conversion Time Sampling Frequency D/A Converter Resolution Settling Time Smoothing Filter Digital Inputs Digital Outputs DSP Interface Timing Read: Write: Access Time (Addr, nRD, nIOSEL to data valid) > 30 ns Data Setup to rising edge of nWR or nIOSEL: > 20 ns Data Hold from rising edge of nWR or nIOSEL: > 0ns 4, differential (single-ended by grounding IN-) +/-2.5V 200 kOhm differential, 100 kOhm single-ended 800 kHz 4, single ended +/- 2.5V > 2 kOhm 4, successive approximation 16 bit 2.75 s 1.25 s 16 .. 250 kHz internal, 0..250 kHz external 4, R2R ladder 16 bit 2 s to 1 LSB for a full-scale step 2nd order Butterworth, cutoff frequency 100 kHz TTL, 5V tolerant, 10 pF input capacitance TTL, 5V TTL compatible, max. +/-4mA

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