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.ADDA16

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User's Guide

Digital Signalprocessing Technology Norbert Nölker & Adolf Klemenz GbR Gelderner Straße 36 D - 47647 Kerken phone +49 (0) 2833 / 570 977 fax email www +49 (0) 2833 / 33 28 info@dsignt.de http://www.dsignt.de

D.Module.ADDA16 User's Guide

Revision History

D.Module.ADDA16 Revision History

1.0 July 2004

© D.SignT 2004

Doc #1.0

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.................2 Analog Outputs ..................... 11 3.......... 6 2...........................................Module.............................................................ADDA16 User's Guide Contents 1 INTRODUCTION...........................................................................................................................................................................................................................................SignT 2004 Doc #1....................................................................2 Registers ........................................1 DAC Updates (LDAC) .........2 Sampling Clock..0 2 ...............................................2........................... 19 6 PINOUT ............................................................. 22 8 ELECTRICAL CHARACTERISTICS............................................................1 FS Register...... 11 3.................. 14 4.................... 9 2.......2............... 6 2...........................................................................2 CONFIG Register............ 23 © D........ 8 2....................1 Address Decoding......................................................................... 20 7 MECHANICS .............................................................. 12 4 D/A CONVERTER........................................1 Analog Inputs................................................. 18 5 POWER SUPPLY............................................................................................................................................D...................... 9 3 A/D CONVERTER...................................................... 17 4................................. 4 2 DSP INTERFACE................................

........................ 22 © D..... 12 Figure 4-1 DAC Interface...............Module...............................................................................D......................................................ADDA16 Block Diagram............................................... 16 word sub-bank select ......ADDA16 User's Guide Contents List of Tables and Figures: Table 2-1 DSP Bus Interface Signals ............................... 14 Figure 5-1 D............... blank fields are not connected ........... 7 Table 2-3 Address Decoding......................................Module.......Module............ 5 Figure 3-1 Sampling Clock Circuit ............................................... 4 Figure 1-2 Location of Jumpers ................... 21 Table 6-3 Analog Output Connector Pinout............................................................................................ 8 Table 3-1 Analog Input Signals.................................................Module..................................................................................................................................Connector....... 13 Table 4-1 Analog Output Signals ... 6 Table 2-2 Address Decoding: 64K bank select ................................................................................ 11 Table 3-2 Sampling Clock Signals .. 18 Table 6-1 D......0 3 ..................................... 21 Figure 1-1 D.........ADDA16 Mechanics ......................................................... 7 Table 2-4 ADDA16 Registers...... 20 Table 6-2 Analog Input Connector Pinout .............................SignT 2004 Doc #1...

and is best suited for control loops.e.ADDA16 User's Guide Introduction 1 Introduction The D. Clock ADC and DAC Registers LDAC (DAC Update) DAC0 Vref DAC1 AD5544 DAC2 DAC3 EXT_CLKIN EXT_CLKOUT FS_Register Figure 1-1 D. complicating the control algorithm. Four A/D channels are converted synchronously using Successive Approximation Converters (SAR).or all four channels. Divider int.ADDA16 Block Diagram © D. The DACs can be updated synchronously with the ADC sampling frequency. where any delay will result in increased dead time. but can also be driven from single-ended sources by grounding the IN.input.Module.Module family of DSP Computer Modules. The analog inputs are high-impedance differential inputs. or operate in free running mode.ADDA16 is a 16 bit.SignT 2004 Doc #1.0 4 . suitable for the D.D. 4-channel A/D and D/A converter board.Module. the output is updated immediately after a write to the corresponding DAC.Module. Vref ADC0 In+ ADC0 InADC1 In+ ADC1 InADC2 In+ ADC2 InADC3 In+ ADC3 In- + AD7663 + AD7663 + AD7663 + AD7663 CNVST LDAC Config progr. 250 KSPS. 3 . i. A third mode combines unsynchronized writes to the DACs with simultaneous update of 2. The D/A converters are followed by a second order smoothing filter and provide a single-ended bipolar output. This architecture provides a very short delay from sampling to availability of the digital output word. Synchronous sampling preserves the phase information of the input channels.

and 18 select the ADDA16 base address. It is closed by default using a 0 ohms resistor.SignT 2004 Doc #1. If your system already provides a AGND-DGND connection you must open this jumper to avoid a GND loop.16.Module.0 JPA18 JPA4 JPA5 5 . JPA4.17. © D.ADDA16 User's Guide Introduction 1 A B C 16 32 JPGND F G H I J K L M N O P JPA16 JPA17 T U V Figure 1-2 Location of Jumpers JPGND connects the analog to the digital ground.D.5.

o. active low DSP external bus clock reset input. active low interrupt line 1 to DSP. Jumper JPA18 .V14 Signal nRD nINT0 nINT1 nWR BUSCLK nRESET nIOSEL A0.U14 U15. active low Interrupt line 0 to DSP. the corresponding address line must be '0'. It occupies a contiguous address space of 16 addresses. Many DSP boards also allow to use these interrupts as DMA trigger events for background data acquisition with minimum DSP load. Two interrupt outputs can be configured to request exception handling for ADC or DAC from the DSP. active low write strobe.1 Address Decoding Five address jumpers on the D.U30 V12. The base address is determined by five address jumpers on the board.D. o. independent of the DSP data bus width.ADDA16 User's Guide DSP Interface 2 DSP Interface The D. Data format is 2's complement. hi-z input Comment read strobe.A5 D15. the corresponding DSP address line must be '1' to decode the board. The data bus is connected to the upper 16 data bits of the DSP.. This allows to select one of 32 possible address blocks.ADD16 is memory-mapped to the DSP module's IOSEL memory space.D31 A16.d = open drain output. output.Module.d. active low DSP memory area select signal DSP address bus DSP data bus DSP address bus Type: o. If a jumper is closed.. © D. hence the sign bit (MSB) of the converters and the DSP sign bit match.... jumper.. bidir = bidirectional Table 2-1 DSP Bus Interface Signals 2.0 6 . if a jumper is open.ADDA16 allow to select the base address of the board.d. input input input input input bidir. hi-z = high impedance.. Pin U2 U3 U4 U5 U6 U7 U8 U9. jumper JPA5 and JPA4 decode a 16 words sub-block. JPA16 decode a 64K address block.A18 Type input output.Module.Module.SignT 2004 Doc #1.

and always drive A18 high in IOSEL memory area. Please note that Texas Instruments C6000 processors use a different addressing scheme (byte addressing).0000 nIOSEL + 0x03.0000 nIOSEL + 0x08.0000 nIOSEL + 0x0C. 16 word sub-bank select The default settings are JPA18 closed.Module. address jumpers A4 and A5 allow to select one 16 word area out of a 64 word block: 16 Word Sub-Bank Select JPA5 open open closed closed JPA4 open closed open closed Base Address Offset C6000 DSP Modules 0x00 0x40 0x80 0xC0 0x00 0x10 0x20 0x30 other Table 2-3 Address Decoding.0000 nIOSEL + 0x05.0 7 . JPA5 and JPA4 open.0000 nIOSEL + 0x06.0000 nIOSEL + 0x04.SignT 2004 Doc #1. JPA17 and JPA16 open.0000 Table 2-2 Address Decoding: 64K bank select Inside this 64 K block.ADDA16 User's Guide DSP Interface The following tables shows the possible address offsets from IOSEL base address.D.0000 nIOSEL + 0 nIOSEL + 0x04. and IOSEL + 0x40000 on other DSP modules. 64 K Bank Select JPA18 open open open open closed closed closed closed JPA17 open open closed closed open open closed closed JPA16 open closed open closed open closed open closed Base Address C6000 DSP Modules not possible other nIOSEL + 0 nIOSEL + 0x01. © D. hence the factory setting base address is IOSEL + 0x00000 on C6000 DSP modules.0000 nIOSEL + 0x02.0000 nIOSEL + 0x07.

but only one level deep.ADDA3 registers provide direct access to the A/D and D/A converters. This data is held in the buffer and not copied to the shift register before the first DAC transmission is completed. the data is immediately copied to the shift register and transferred to the DAC. You may also poll the DAC_READY flag in the CONFIG register to determine if the interface is ready to accept new data. Now the second DAC value can be written.D. Each time the DAC buffer is ready for a new transfer. During this time the buffer is not available for new data.2 Registers Six registers provide access to the A/D and D/A converters and to the board configuration.ADDA16 User's Guide DSP Interface 2.0 8 ..SignT 2004 Doc #1. an interrupt is generated. The bus interface provides parallel to serial conversion. A shift register for each ADC performs serial-parallel conversion. If the first DAC has been written. Data is written to the D/A converters via a serial interface too. Data from the A/D converters is serially transmitted to the bus interface. especially during the ADC sampling period. hence data can be read while the next conversion result has already started to shift in. hence you have to wait for the first transmission to finish before the third DAC value can be written. Address Offsets in () brackets are valid for C6000 DSPs: Offset Register Width 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits Comment read: ADC channel 0 write: DAC channel 0 read: ADC channel 1 write: DAC channel 1 read: ADC channel 2 write: DAC channel 2 read: ADC channel 3 write: DAC channel 3 read/write: sampling frequency selection read/write: configuration register 0x00 (0x00) ADDA0 0x01 (0x04) ADDA1 0x02 (0x08) ADDA2 0x03 (0x0C) ADDA3 0x04 (0x10) FS 0x05 (0x14) CONFIG Table 2-4 ADDA16 Registers The 16 bit wide ADDA0.Module. The ADC interface is buffered. The DAC interface is buffered. This scheme minimizes system noise. and a state machine starts ADC readout as soon as the ADC signals conversion complete. © D. An interrupt is generated as soon as the ADC data is copied from the shift register to the buffer.

or an external clock fed to EXT_CLKIN. read: DAC_READY a 1 signals the DAC buffer is ready to accept new data.SignT 2004 Doc #1.8 Bit 7 undefined on read operations.2.D.Module. either generated onboard via a programmable divider. The CONFIG register selects the interrupt mapping and the D/A converter update scheme (LDAC). The reset value of this register is 0x00 2. © D. don't care on writes ADC Sampling Frequency 0x00 selects external sampling clock provided from EXT_CLKIN 0x0F . or synchronizing other peripherals..2. 0 undefined on read operations. if 0.ADDA16 User's Guide DSP Interface For a detailed description of DAC access methods please refer to chapter 4. The clock is generated from a 4 MHz quarz oscillator by this equation: fs = 4MHz / (FS_REG + 1) values < 0x0F result in a sampling clock > 250 kHz and are not supported.. don't care on writes write: EXT_CLKOUT_ENABLE a 1 written to this bit will enable the EXT_CLKOUT output. 2. The FS register allows to select the sampling frequency. the DAC buffer is full and new data cannot be accepted. D/A Converter.2 CONFIG Register Bit 15.1 FS Register Bit 15. The sampling clock output EXT_CLKOUT can be enabled for cascading multiple ADDA16 boards. and the status of the D/A converter data transfer can be read.0 9 .. 0xFF select an internally generated sampling clock. a 0 will disable this output and put it into high impedance.8 Bit 7.

0 10 . 5 read/write: INT1_DAC.ADDA16 User's Guide DSP Interface Bit 6. © D.ADC interrupt 10 .not allowed Bit 4.DAC update after writing to DAC 3 100 .DAC update after writing to DAC 1 010 .reserved.Module.not used. high impedance 01 . 111 .not used.. DAC Updates (LDAC) for a detailed description of DAC update modes. not allowed Please refer to chapter 4. INT1_ADC these bits determine the nINT1 interrupt output usage: 00 . high impedance 01 . 0 read/write LDAC these bits determine the DAC update mode: 000 . INT0_ADC these bits determine the nINT0 interrupt output usage: 00 .DAC update after writing to DAC 2 011 .DAC interrupt 11 .DAC is updated following each write to any DAC 001 .not allowed Bit 2 . The reset value of the CONFIG register is 0x00.SignT 2004 Doc #1. 110.ADC interrupt 10 .D.1.DAC update synchronous with ADC conversion start 101.DAC interrupt 11 . 3 read/write: INT0_DAC.

acquisition time is 2.45µs. The digital output is serially transmitted to the DSP bus interface. Pin G1 G2 H1 H2 I1 I2 J1 J2 K1 K2 L1 L2 M1 M2 Signal ADC0 IN+ ADC0 INAGND AGND ADC1 IN+ ADC1 INAGND AGND ADC2 IN+ ADC2 INAGND AGND ADC3 IN+ ADC3 INComment Channel 0 non-inverting input Channel 0 inverting input Analog Ground Analog Ground Channel 1 non-inverting input Channel 1 inverting input Analog Ground Analog Ground Channel 2 non-inverting input Channel 2 inverting input Analog Ground Analog Ground Channel 3 non-inverting input Channel 3 inverting input Table 3-1 Analog Input Signals No anti-aliasing filters are provided on the D.Module.Module. The transmission and loading of the parallel buffer takes 18 clock cycles = 450ns. where it is converted into a parallel output word. and the maximum positive input voltage of 2. 3.ADDA16 User's Guide A/D Converter 3 A/D Converter The analog-to-digital converters are successive approximation converters with 16 bit resolution and a maximum sampling frequency of 250 kHz. The serial transmission from ADC to the bus interface is clocked with 40 MHz.75µs + 1. An LSB is 76.4999V converts to 0x7FFF. Hence.25µs + 450 ns = 4. A 0V input converts to a 0x0000 output word. -2. If the input signal contains spectral components above the Nyquist frequency (1/2 sampling fre© D.0 11 .75 µs.ADDA16.5V.1 Analog Inputs The analog input interface is a buffered differential amplifier which accepts input voltages of +/. the ADC latency time is 2. Conversion time is 1.25 µs. independent of the sampling clock.SignT 2004 Doc #1.2. The output of the differential amplifier is fed to the A/D converter input.5V input converts to 0x8000. Single-ended inputs can be connected by grounding the INinput.D. Data format is 2's complement .3 µV.

This synchronization flip-flop is powered from the analog supply voltage to minimize jitter and noise on the conversion start signal. CLK CNVST 1D LOAD 40 MHz Clock Source div 10 CLK FS_REG == 0 CNT == 0 FS Reg.SignT 2004 Doc #1. The FS Register is used to set the sampling clock source and frequency. i. and fed to a preset-able down counter. The wide analog input bandwidth (800 kHz) of the converters allows to use the ADDA16 in a sub-sampling configuration if the input signal is inherently bandlimited. the external sampling clock from EXT_CLKIN is used.2 Sampling Clock The A/D converter conversion start signal is generated from an on-board oscillator or provided externally via EXT_CLKIN. The required filter order depends on the out-of-band energy levels: the filter should ideally attenuate any outof-band signals to be 90 dB below the full-scale input. © D. the counter output is used as the conversion start signal. If the FS register is programmed to a value different from 0.Module. EXT_CLKOUT_ENABLE EXT_CLKIN EXT_CLKOUT Figure 3-1 Sampling Clock Circuit The 40 MHz internal clock source is pre-divided by 10. 3.0 12 . which is preset from the module's FS register.D.ADDA16 User's Guide A/D Converter quency). The conversion start signal is re-synchronized to the 40 MHz master clock. if out-of-band signals are present at 30dB below full-scale. like in the intermediate frequency stage of a receiver.e. external band limiting filters are required. the filter should provide additional 60 dB attenuation. If the FS register is 0.

Module. Leave this board's EXT_CLKOUT disabled.D.ADDA16 User's Guide A/D Converter The EXT_CLKOUT output can be enabled and used to feed slave ADDA16 boards if more than four input channels are required. it generates the sampling frequency. or synchronize other peripheral devices to the sampling clock. This will route Board1 EXT_CLKOUT to Board 2 EXT_CLKIN. Board 2 is the slave board.SignT 2004 Doc #1.0 13 . It is configured for external sampling clock. stack two ADDA16 boards and configure as follows: Board 1 is the master. For an eight-channel system. Pin C22 C23 Signal EXT_CLKIN EXT_CLKOUT Comment external sampling clock input external sampling clock output Table 3-2 Sampling Clock Signals © D. Set the desired sampling frequency and enable this board's EXT_CLKOUT output. (also remember to select a different base address for Board2) Finally connect EXT_CLKOUT to EXT_CLKIN.

The DAC settles to 1 LSB accuracy in 2 µs.5V on the output.Module. This allows to write two DACs almost immediately following each other. The DAC interface is single-buffered.ADDA16 User's Guide D/A Converter 4 D/A Converter The digital-to-analog converters use a serial data interface too. but the bus interface logic converts 2's complement into straight binary. Load 40 MHz DSP Addr 0 and 1 DSP Data DSP Write DACBuffer DAC Serial Data In DACShifter Transmission Request Shift Complete Control Logic Interrupt.0 14 . but if 3 or 4 DACs should be written.SignT 2004 Doc #1. Most DSPs provide internal saturation logic to prevent 2's complement overflow. The software designer must take care to avoid 2's complement overflows.D. Data is clocked into the DAC with a 40 MHz clock. a 0x0000 to 0V output.5 µs. which must be taken into account as deadtime in control loops. as this will generate full-scale signal spikes on the DAC output. and 0x7FFFF to +2. the DAC latency is 2. Adding the 500 ns for serial transmission. DAC_READY Figure 4-1 DAC Interface © D. The buffer can be written by the DSP while a serial transmission to the DAC is in progress. The DACs itself use straight binary coding. A transmission takes 20 clock cycles. The DSP bus interface logic provides the parallel-to serial converter.4999V. so the DSP can write it's native 2's complement data to the DAC. the DSP program must wait for the buffer to be free before the data for DAC2 and DAC 3 is written. A 0x8000 translates to -2.

data). but for 500 ns each before writing to the 3rd and the 4th DAC. either programmed. hence every 500 ns.0 15 . which determine the DAC to write to.D. The DSP programmer should use one of the following programming techniques: • only one DAC is used in the system: Direct writes to the DAC are possible. Many systems will also use "on demand" DAC writes. corresponding to it's required settling time. rsp. or use a DSP timer interrupt if an update frequency different from the ADC sampling frequency is required. but now the control logic delays the shifter load until the current shift is completed. a transmission request is generated. the shifter is loaded with the buffer content and immediately starts shifting out the data to the DAC.e. ADDA16_DAC_WRITE (1. Simultaneously with the shifter load signal. Again. Polling DAC_READY will block your program for only 50 ns before the 2nd DAC can be written. • two DACs are used: After writing to the first DAC the serial transfer starts immediately and the buffer is free again to accept the data for the 2nd DAC.ADDA16 User's Guide D/A Converter On a write to one of the four DAC registers the bus interface latches the 16 data bits and the two least significant address lines. In most systems slower update rates will be used. Each individual DAC is written every 2 µs.Module. The DAC interface will generate an interrupt every time a shift is completed. or DMA triggered. an interrupt is generated. A transmission request signal is generated. Poll the DAC_READY flag before writing to the 2nd DAC to make sure transfer has started and the DAC buffer is free. the DAC_READY flag is set.SignT 2004 Doc #1. If this time is not tolerable use interrupts as shown in this program fragment: © D. • three or four DACs are used: always poll the DAC_READY flag before writing to a DAC. data). The latency caused by polling the DAC_READY flag is approximately 50 ns ADDA16_DAC_WRITE (0. You can either synchronize DAC writes to the ADC interrupt. The DSP can then write the next data word to the DAC buffer. If no shift operation to the DAC is currently in progress. while (!(ADDA16-cfg & ADDA16_DAC_READY)). i. write to the DAC only if the output value needs to be changed. This corresponds to the maximum DAC update rate of 250 kHz for all four channels. from an interrupt. or use interrupt transfers.

/* write to DAC 0 */ ADDA16->cfg |= ADDA16_INT1DAC. and further DAC interrupts are disabled by clearing the interrupt enable bit.. until enabled again. for (. and variable idx in incremented. idx will increment to 4.) { . As soon as the buffer is free again. dac_int() will be executed for the last time.D.0 16 . ADDA16_DAC_WRITE (0. © D. } } void main (void) { install_interrupt (SIG_INT1. DAC interrupts are enabled by setting the corresponding bit in the ADDA16 Configuration Register.SignT 2004 Doc #1. . Now the third DAC is written. After the buffer is free. /* enable DAC-Int */ } } After the first DAC is written from the main program. /* disable INT1 */ idx = 1. and interrupt nd function dac_int() will be executed. Now the fourth DAC is written. an interrupt will be generated. dac_int() is invoked again. data).. ADDA16_DAC_WRITE (idx. As soon as the DAC buffer is free.ADDA16 User's Guide D/A Converter void dac_int (void) { static int idx = 1.... In this function the 2 DAC is written. /* write to next DAC */ if (++idx == 4) { ADDA16->cfg &= ˜ADDA16_INT1DAC. data).Module. dac_int).

5 µs until the ADC interrupt is generated. LDAC is synchronous with the ADC sampling frequency The first option. The second option will synchronously update the selected DACs after the last one is written. is useful for on demand DAC writes.ADDA16 User's Guide D/A Converter 4.SignT 2004 Doc #1.5µs. or 133 kHz maximum sampling frequency. The LDAC signal is used to update the DAC output. the DAC will change it's output. third.1 DAC Updates (LDAC) Writing to a DAC will only store the data in the DAC's internal buffer register. The D. This can only be guaranteed for sampling frequencies below approx. or if only one DAC is used.Module. 3. but not update it's output. This option is selected by writing a 4 to the LDAC bitfield. and DAC2. © D. it takes 4. to be synchronous. LDAC is generated as soon as the transfer is complete 2. This is the minimum sampling period to guarantee synchronous updates.5 µs.ADD16 supports three configurations to generate LDAC. Adding some extra time for interrupt latencies results in 7.Module. LDAC is generated only after writing to the second. The total time from Conversion start until the DAC writes are complete is 6. following any write to a DAC. if phase relation between DAC channels is not important. Typically the program will write to the DACs in the ADC interrupt service. 133 kHz: Following conversion start. The last option is used if ADC sampling and DAC update should be synchronous and occur at exactly the same time. which are configured in the LDAC bitfield of the ADDA16 configuration register : 1. This option is selected by writing a 0 to the LDAC bitfield. Exact phase relation between DAC channels is maintained as long as all DACs are completely written before the next conversion start (and hence LDAC) occurs. it will take additional 2 µs (4 x 500 ns) to write all four DACs. all three DACs synchronously update their outputs. or fourth DAC. DAC1. After the last write (to DAC2). start writing the DACs in the ADC interrupt service. set the LDAC bitfield to 2. If DAC update and ADC conversion should by synchronized. Now write the output values to DAC0. This configuration minimizes jitter on the DAC outputs. always generate LDAC following a write.0 17 . three DACs are required and all should be updated synchronously to provide exact phase relationship. In this case. To control a 3-phase motor for example.D. Immediately after the write. If DAC writes are started now.

The Butterworth filters are factory set to a corner frequency of 100 kHz. and.SignT 2004 Doc #1. To avoid gain loss the input of the driven circuit should be a high impedance input. Capacitive loads > 100 pF should be connected via a series resistor (approx. and smoothes the output waveform.5V full-scale output. Large capacitive loads on the outputs add a pole to the transfer function and will increase ringing and overshot.Module. in extreme cases.2.D. The analog output is single-ended with +/. It is also possible to compensate the pole formed by the capacitive load with a series RC combination from output to AGND.2 Analog Outputs The DACs are followed by an I-V converter. This filter attenuates the high frequency switching spikes generated by DAC code transitions.0 18 . and a 2nd order Butterworth smoothing filter. Custom corner frequencies are available on demand. Pin G31 G32 H31 H32 I31 I32 J31 J32 K31 K32 L31 L32 M31 M32 Signal DAC0 OUT AGND AGND AGND DAC1 OUT AGND AGND AGND DAC2 OUT AGND AGND AGND DAC3 OUT AGND Channel 0 output Analog Ground Analog Ground Analog Ground Channel 1 output Analog Ground Analog Ground Analog Ground Channel 2 output Analog Ground Analog Ground Analog Ground Channel 3 output Analog Ground Comment Table 4-1 Analog Output Signals © D. which translates the DAC output current into a voltage. 100 ohms).ADDA16 User's Guide D/A Converter 4. cause instability.

An excellent choice for a low-noise switch mode supply is the Linear Technology LTC1533 switching regulator. but this jitter is attenuated later by resynchronization in an analog-powered D-type flip-flop. This may add some jitter to the sampling clock. and the sampling clock divider. A switch mode supply with linear post regulation doesn't cure the problem.3V power supply.SignT 2004 Doc #1. High frequency noise. Digital and Analog ground return paths should ideally be interconnected close to the converters. tuned to the specific noise spectrum of the switcher. The powersupply rejection ratio of the op-amps and converters used on the ADDA16 will attenuate power-supply noise up to 60dB. the serial interfaces to the data converters. The digital power supply can be taken directly from the DSP supply. The analog power supply is +/. cannot be sufficiently attenuated by the components and will degrade performance: high frequency noise may modulate the input and output signals. and a single digital 3. © D. Some experiments may be required to determine the best location for AGND-GND connection. add passive LC filters in the supply rails.D. For best performance a power supply build around a mains transformer and linear regulators should be used.Module. If your system already has interconnected AGND and GND.ADD16 provides this connection. It powers the bus interface circuits. attenuation decreases with increasing frequency. and is aliased into the baseband during conversion. because linear regulators suffer from bandwidth limitations too. only one should have JPGND closed. open jumper JPGND on the ADDA16 board.ADDA16 User's Guide Power Supply 5 Power Supply The ADDA16 module requires a bipolar analog power supply. depending on your system layout. as produced by switch mode power supplies.0 19 .5V.Module. If multiple boards are cascaded. Only one interconnection should exist in the entire system. A jumper (JPGND) on the D. However. If a switch mode supply must be used.

SignT 2004 Doc #1.Module.0 20 .Connector. blank fields are not connected © D.Module.D.ADDA16 User's Guide Pinout 6 Pinout Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A VCC B GND nRD nINT0 nINT1 nWR BUSCLK nRESOUT nIOSEL A0 A1 A2 A3 A4 A5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D15 D15 GND C T U V A16 A17 A18 -AVCC AGND +AVCC EXT_CLKIN EXT_CLKOUT GND VCC GND Table 6-1 D.

ADDA16 User's Guide Pinout Pin F G H I J K L M N O P 1 +AVCC (use as output only!) ADC channel 0 IN+ AGND ADC channel 1 IN+ AGND ADC channel 2 IN+ AGND ADC channel 3 IN+ VCC (use as output only) rsvd rsvd 2 -AVCC (use as output only ) ADC channel 0 IN AGND ADC channel 1 IN AGND ADC channel 2 IN AGND ADC channel 3 IN GND (use as output only) rsvd rsvd Table 6-2 Analog Input Connector Pinout Pin F G H I J K L M N O P 31 +AVCC (use as output only!) DAC channel 0 OUT AGND DAC channel 1 OUT AGND DAC channel 2 OUT AGND DAC channel 3 OUT VCC (use as output only) rsvd rsvd 32 -AVCC (use as output only ) AGND AGND AGND AGND AGND AGND AGND GND (use as output only) rsvd rsvd Table 6-3 Analog Output Connector Pinout © D.0 21 .D.SignT 2004 Doc #1.Module.

54 mm 12.76 mm max component height on bottom: 2.70 mm A B C 21 3.Module.56 mm 2.27 mm 7.62 mm 2.34 mm 35.85 mm 4.42 mm 22 . m m 53.D.74 mm 2.Module.54 mm1.54 mm 2.59 mm : 4.96 mm 78.54 mm T U V 1 76.SignT 2004 Doc #1.0 58.50 mm 4.ADDA16 User's Guide Mechanics 7 Mechanics max component height on top 1.ADDA16 Mechanics © D.50 mm 7.82 mm 32 Figure 5-1 D.20 mm 83.

5V tolerant.0 23 . +/-4mA © D.. 100 kOhm single-ended 800 kHz 4. max.75 µs 1.5V 200 kOhm differential.250 kHz external 4.2.5V 150mA digital: +3. +70°C Analog Inputs Input Voltage Input Resistance Input Bandwidth Analog Outputs Output Voltage Output Load A/D Converter Resolution Acquisition Time Conversion Time Sampling Frequency D/A Converter Resolution Settling Time Smoothing Filter Digital Inputs Digital Outputs DSP Interface Timing Read: Write: Access Time (Addr.D.SignT 2004 Doc #1.Module.25 µs 16 . nIOSEL to data valid) > 30 ns Data Setup to rising edge of nWR or nIOSEL: > 20 ns Data Hold from rising edge of nWR or nIOSEL: > 0ns 4. 5V TTL compatible.ADDA16 User's Guide Electrical Characteristics 8 Electrical Characteristics Power Supply analog: +/.5V > 2 kOhm 4. 10 pF input capacitance TTL.. successive approximation 16 bit 2. differential (single-ended by grounding IN-) +/-2. R2R ladder 16 bit 2 µs to 1 LSB for a full-scale step 2nd order Butterworth.3V 400mA Operating Temperature 0 . 250 kHz internal. 0. single ended +/. cutoff frequency 100 kHz TTL. nRD..