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15th International Power Electronics and Motion Control Conference, EPE-PEMC 2012 ECCE Europe, Novi Sad, Serbia

Three-Level Hysteresis Current Regulation for a Three Phase Neutral Point Clamped Inverter
R. Davoodnezhad, D.G Holmes, B.P McGrath
School of Electrical and Computer Engineering, RMIT University, Melbourne, Australia reza.davoodnezhad@student.rmit.edu.au, grahame.holmes@rmit.edu.au, brendan.mcgrath@rmit.edu.au
Abstract This paper presents a new hysteresis current regulation strategy for a three-phase three-level neutral point clamped (NPC) inverter. The strategy uses the zero-crossing of the fundamental component of the phase leg switched voltage to select the output voltage level, with only one hysteresis comparator required per phase leg. The same average voltage is then used to vary the hysteresis band as the load back-emf changes in order to maintain a constant switching frequency. Next, the strategy is extended to a threephase NPC inverter by subtracting the common mode interacting current from the total phase leg current error before making any switching decision. The three-phase leg current errors are also synchronized to a fixed clock frequency to further improve the frequency regulation and obtain a line to line harmonic performance that is close to open-loop phase disposition (PD) pulse width modulation. Keywords multilevel hysteresis control, neutral point clamped inverter.

I.

INTRODUCTION

Multilevel voltage source inverters (VSI) are now well-accepted in high power applications which need high waveform quality, using an array of semiconductor switches connected in series/parallel combinations. Of the three major multilevel topologies, the neutral point clamped inverter (NPC) is attractive in many applications such as distributed generation systems, variable speed drives and static VAR compensators. This is because of its simple construction, single source DC bus voltage and low bus capacitor count [1][2]. Current regulation of this inverter is an important requirement for such applications, with the most common strategy being a linear controller employing a carrier-based or a SVM modulator. However this type of controller can suffer from limited dynamic response and requires precise knowledge of the output load parameters. In contrast, non-linear current regulation strategies such as hysteresis are an attractive alternative due to their load robustness, fast dynamic response and inherent overload protection capability [3]. The application of hysteresis strategies to two-level, and to single phase leg multilevel inverters using multiple band (MB), multiple offset (MO) and time based strategies, is reasonably well established. However, the extension of MB and MO strategies to a three-phase context is less straightforward [4][5][6]. These strategies use n-1 hysteresis bands for an n level inverter which can introduce DC tracking errors that require compensation as the number of DC voltage levels increases. Furthermore,

the multiple hysteresis bands of these strategies make it difficult to vary the hysteresis bands to maintain a constant switching frequency and they also fail to maintain the neutral point voltage at 50% of the overall DC bus voltage. Another alternative is time based hysteresis [5][6], which combines digital logic with only one set of hysteresis bands, so that an out-of-band current error selects the appropriate output voltage level to bring the error back within the band. However this strategy also degrades the dynamic response of the controller. The hysteresis strategy proposed in this paper uses the fact that the active switched output voltage of a three-level inverter must change its polarity at the zero-crossing of its switched voltage fundamental component. This means only one hysteresis comparator is required per phase leg. The average voltage is calculated by measuring the transition times of the switching signals [7]. The same averaged voltage is also used to vary the hysteresis band magnitudes to maintain a near constant switching frequency, with its associated improved harmonic performance. Finally, the hysteresis switching signals generated from the comparator are combined with digital logic to generate multilevel switching signals that are similar to an open-loop phase disposition (PD) PWM switching pattern. The controller is then extended to suit a three phase system by compensating for the common mode interacting current in a similar way as is done for two-level inverters [7]. Finally the three-phase current errors are synchronized to a fixed clock frequency. The result achieves a line-line harmonic performance that is very similar to open-loop PD PWM, with the attendant harmonic benefits [8]. The dynamics of the new proposed controller have been verified both at higher switching frequencies, and with a low pulse PWM ratio of f sw f o = 15 , suitable for high power and aerospace applications [9]. II. THREE-LEVEL VARIABLE BAND HYSTERESIS Fig. 1 shows the overall structure of a single leg neutral point clamped inverter controlled by the proposed three-level hysteresis controller, feeding into a series RL impedance with an AC backemf E (t ) . This load model is an excellent representation of most AC load systems. From Fig. 1 the phase load equation can be written as: dI (t ) V (t ) = RI (t ) + L + E (t ) (1) dt where V (t ) = 0,VDC depending on the inverter state.

978-1-4673-1972-0/12/$31.00 2012 IEEE

DS2c.14-1

S1a
VDC + Z VDC + -

I * I h to I * + I h ( I * is the reference current). During


period (T+ t1+ ) , the inverter output voltage is 0 and the load current ramps from I * + I h to I * I h . During

S2a
N

I (t ) R
V (t )

E (t)

period t1 when the averaged inverter output voltage is


VDC , the load current ramps from I * + I h to I * I h .

S 1a
S2a

During period (T t1 ) when the inverter output voltage is 0, it ramps from I * I h to I * + I h . Now, separating the load current into a fundamental target component and a ripple component, i.e.

I * (t) +

e (t )
Ih (t)

Stot(t)
CPLD

3 Level Variable Hysteresis Band Calculation

S12a,avg (t )
S12a (t)

S 1a ( t ) S 1a ( t ) S 2 a (t ) S 2 a (t )

I (t ) = I f (t ) + I r (t )

(2)

R (t)

Fundamental Component Calculation/ Zero-Crossing Detection

and assuming negligible load resistance R , from (1) the rate of change of the ripple current component I r (t ) is given by: dI r (t ) V (t ) Vavg (t ) = (3) dt L where Vavg (t ) = E (t ) + L dI f (t ) dt . Since Vavg (t ) is essentially constant between successive switching events, the switching times can be expressed using (3) as: 2 LI h 2 LI h , (4a) t1+ = T+ t1+ = VDC Vavg (t ) 0 Vavg (t )

Fig. 1: Single leg NPC inverter employing the proposed three-level variable band hysteresis controller

Fig. 2 shows the three-level hysteresis current regulation switching process for fixed band operation, where the averaged voltage of the switched output voltage is shown as an equivalent fundamental sinusoid. As shown in Fig. 1, the new controller recognises when the sign of the per-switching-cycle averaged output voltage changes polarity, and adjusts the inverter gate signals accordingly to change the inverter switched output polarity as commanded by the (single) hysteresis regulator. Variable band operation now proceeds as follows. During the representative time period t1+ while the averaged inverter output voltage is positive, the inverter output voltage is +VDC and the load current ramps from

t1 =

2 LI h , VDC Vavg (t )
2 LI hV DC

T t1 =

2 LI h 0 Vavg (t )

(4b)

Solving (4a) and (4b) for the switching periods gives


T+ = E (t ) V DC Vavg (t )

, Vavg (t ) = +ve

(5a) (5b)

T =

E (t ){ VDC + E (t )}

2 LI hVDC

, Vavg (t ) = ve

I h can now be varied to make T+ = T = T = 1 f sw over

the fundamental cycle as E (t ) and I f (t ) change, using:


I h = I h _ max Vavg (t ) VDC 1 + Vavg (t ) VDC where Ih _ max =

(6)

I (t ) I (t )

2Ih
(a)

V (t )

T1 T2 T3

VDC . Under this condition, the hysteresis 2Lfsw switching frequency f sw will be essentially constant. The per-switching-cycle averaged inverter voltage Vavg (t ) can be measured using a capture/timer port on the

VDC

t1

Vavg (t ) T

R(t )

t1
Negative Output

(b)

VDC
(c)

Positive Output

supporting DSP controller, which records against a continuously cycling internal timer, the instance of each inverter switching transition. The average output voltage (i.e. the duty cycle) is then readily calculated as T2 T1 Vavg (t ) = 2VDC (7) T T 0.5 3 1 where T1 , T2 , T3 are the switching instances in Fig. 2.

Fig. 2: Three-level hysteresis current regulation process (a) view of reference and actual current, (b) (c) one fundamental cycle of the threelevel switched and average output voltage. Note that the switching frequency is artificially low for clarity.

The variable band can also be fine tuned to lock the switching to a fixed reference clock using the zero crossing of the current error [7]. Fig. 3 shows the concept of this process, where t ref ,1 is the time occurrence of the first zero-crossing by the expected current error and

DS2c.14-2

Expected Current Error position Uncorrected Current Error position Ih dIh

(a)

III.

OUTPUT VOLTAGE POLARITY CHANGE AND SWITCHING SIGNAL GENERATION

tref ,1 terror,1
tr dt
Clock

Inverter switches early to correct error

tref ,2

terror,2

dt/2
Clock

T/2 Time(s)

Current Error Synchronizing Clock at 5 kHz

(b)

Current Error (A)

-2 -4 0.009

0.012 0.013 0.014 0.015 Time (s) Fig. 3. Identification of current error zero-crossing timing errors (a) conceptual block diagram (b) experimental validation

0.010

0.011

terror ,1 is the time occurrence of the first zero-crossing by

the actual current error. The time difference t error ,1 t ref ,1 will propagate to the second half switching cycle and become terror , 2 t ref , 2 unless a correction in the variable band ( I h ) is made in the first half switching cycle. From Fig. 3a and using similar triangles, the following relationship is developed

Ih I I h = h (8) T 2 T 2 + t From (8), the band offset required to correct the time error in the first half switching cycle is then I h t = I h 2 f s t T 2 so that from (9) the new corrected variable band is

I h =

(9)

I h , new = I h + I h (10) In fact it is unnecessary to explicitly measure the current error zero crossing times, since they occur essentially midway between the rising and falling edge of the inverter switched output pulses, as shown in Fig. 2. Hence the zero crossing times are adequately given by: Z1 (T1 + T2 ) 2 , Z 2 (T2 + T3 ) 2 , etc (11) Since the switching times T1 , T2 , T3 have already been recorded by the DSP controller using the timer/capture port for the average inverter voltage calculation, no additional hardware detection circuitry is required to implement this correction. The fine-tuned variable band results in a more constant switching frequency, as illustrated in the experimental result shown in Fig. 3(b).

selection signal R (t ) and the inverter phase leg switching signals S 1a (t ) and S 2 a (t ) . Fig. 6 shows the output current error, which is precisely bounded within the hysteresis limits of 1 .5 A (set to achieve the 1 kHz switching frequency). Fig. 6 also shows the active switched pulse S 12 a (t ) , the inverter output polarity signal R (t ) and the reconstituted per-switching-cycle averaged phase leg output voltage (generated by a spare DAC output from the DSP).
I (t)
*

S 2 a (t ) from the single hysteresis comparator output, in conjunction with the inverter output voltage polarity command R (t ) . The decoding logic generates a switching pattern that is essentially equivalent to threelevel modulation of a single leg three-level NPC inverter using PD PWM [8], to achieve the best possible harmonic performance. The state table in Fig. 4 shows the relationship between the phase leg switch states and the phase leg switched output. Note that state 3 (S1a=1, S2a=0) is explicitly not allowed since it produces a high impedance switched output which has no useful function. The averaged output zero-crossing detection logic is implemented in the supporting DSP controller. The input to the DSP capture/timer port is S 12 a (t ) , which is ONE for an active switched output of either polarity, and ZERO for a 0V phase leg output. The DSP calculates the per-switching-cycle averaged inverter voltage from this signal using (8), and then extrapolates the result to predict when the polarity of this voltage will change. R (t ) is set by the DSP to command the correct switched output polarity from the neutral point clamped phase leg, based on this calculation. Figs. 5 and 6 show experimental results achieved using this new hysteresis control strategy, operating at a low switching frequency of 1 kHz with fixed band hysteresis for clarity. Fig 5 shows the absolute value of the active switched output pulse S 12 a (t ) , the polarity

Fig. 4 shows the new single comparator multilevel hysteresis current controller for a single phase leg, and its associated combinational logic. This logic produces the required phase leg switching commands S 1a (t ) and

S1a
VDC +

+ e (t) - I (t) Ih(t)

S tot (t )

S 2a
N

S1a (t ) S1a (t )
Average Voltage Zero-Crossing R (t ) Detection

Z
VDC + -

S1a
Z

S 2a (t ) S 2a (t )
S12a (t )
Output State NPC inverter

State 1 2 3 4

S1a S2a
0 0 1 1 0 1 0 1

S 2a

VDC
0 Hi Z

V DC

Figure 4 : Combinational logic circuit to decode the total switching signal into gate switching signals.

DS2c.14-3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0.00

Hysteresis Switching Siganl Stot (t)

Level Selection Signal R (t)

TABLE I: INVERTER PARAMETERS. Parameter Overall DC Link Voltage (2*VDC) Filter Inductance (L) Output Resistance (R) Switching Frequency (fs) Fundamental Frequency (fo)

Value 200 V 18 mH 16 2500 Hz 50Hz

S1a (t)

S2a (t)

IV.

IMPLEMENTATION IN A THREE PHASE SYSTEM

0.01

Time (s)

0.02

0.03

Fig. 5: (a) Hysteresis switching signal Stot(t) generated by hysteresis comparison of current error and hysteresis band (b) gate switching signals (S1a(t) & S2a(t)), 1 kHz switching frequency.
S12a,avg(t)/ R(t)(V) S12a (t)(V) Current Error (A)
2 0 -2 6 4 2 0 2.0 1.5 1.0 0.5 0.0 0.000 0.005 0.010 0.015 0.020 0.025 0.030

The system is extended to three phases by constructing three separate current regulators. The load equation for each phase now becomes dI (t ) Vx (t ) = L x + RI x (t ) + E x (t ) + U 0 (t ) , x a, b, c (12) dt where U 0 (t ) is the load floating neutral point voltage. The phase currents can be separated into non-interacting s Ix (t ) and interacting (t ) components [10] according to

Time (s)

Fig.6: Experimental (a) current error (b) phase leg switching signal (S12a(t)) (c) phase leg averaged fundamental component and the level selection signal, 1 kHz phase leg switching frequency.

Fig. 7 shows experimental results for the new controller operating with both fixed and variable hysteresis bands to regulate the current into a single leg three-level NPC inverter with parameters listed in Table1. Fig. 8 shows the output voltage harmonic spectrum for both the fixed band, variable band and fine tuned variable band hysteresis controllers, where the harmonic improvement achieved by the variable hysteresis band to keep the switching frequency more constant can be clearly seen.
6 4 2 0 -2 -4 -6 2 0 -2 150 100 50 0 -50 -100 -150 0.000

s I x (t ) = I x (t ) + (t ) , x a, b, c (13) If the common mode voltage is now equated to d (t ) U 0 (t ) = L R (t ) (14) dt Eqn. (12) can be simplified using (13) and (14), to give: dI s (t ) s (t ) + E x (t ) , x a, b, c Vx (t ) = L x + RI x (15) dt This is identical to a single phase leg hysteresis controlled system and hence the previously developed single phase leg three-level variable hysteresis band concepts can be immediately applied to the three phase system. In a balanced three phase system, the sums of the three phase currents and backemf voltages are always zero. Hence summing (12) across three phases gives:

U 0 (t ) = 1 3 [Va (t ) + Vb (t ) + Vc (t )] (16) Now, if R is assumed to be small, the interacting current can be directly calculated as:
1 1 [Va (t ) + Vb (t ) + Vc (t )] dt , (17) U 0 (t )dt = L 3L Fig. 9 shows the proposed three phase variable band hysteresis control system that achieves this control

(t ) =

Fixed Band Operation

Reference

Actual

6 4 2 0 -2 -4 -6 2 0 -2 150 100 50 0 -50 -100 -150 0.000 0.030

Variable Band Operation

Output Current (A)

Reference

Actual

Output Voltage (V)

Current Error (A)

0.005

0.010

0.015 Time (s)

0.020

0.025

0.005

0.010

0.015 Time (s)

0.020

0.025

0.030

Fig. 7 : Experimental results of the proposed controller for three-level NPC inverter. (a) Output current (b) Current error and hysteresis band (c) Three-Level output voltage

DS2c.14-4

0 10

Phase Voltage Harmonic Spectrum Fixed Band Fund Freq = 50Hz Switching Freq = 2500Hz WTHD (200th Harmonic) =1.64%

-1 10

Phase Voltage Harmonic (p.u)

-2 10 0 10

Variable Band Band Fund Freq = 50Hz Switching Freq = 2500Hz WTHD (200th Harmonic) =1.45%

-1 10

-2 10 0 10

Fine-tuned Variable Band Fund Freq = 50Hz Switching Freq = 2500Hz WTHD (200th Harmonic) =1.32%

-1 10

-2 10 0

500

1,000

1,500

2,000

2,500

Frequency(Hz)

3,000

3,500

4,000

4,500

5,000

5,500 6,000

Fig. 8: Experimental phase leg voltage harmonics of single NPC phase leg under hysteresis current regulation: (a) fixed band (b) variable band, (c) fine tuned variable band, m = 0.9

multiplexer and a DAC, where the DAC output switches to either a scaled positive, zero or negative DC bus voltage depending on the three phase voltage polarity commands {Ra (t ), Rb (t ), Rc (t )} and three phase switching signals {S12 a , S12b , S12c } . The logic decoder is implemented using a MAX II CPLD. Fig. 10 shows the experimental results achieved for a pulse ratio of 50 ( f s = 2500Hz, fo = 50 Hz ), while Fig. 11 shows the matching results for a pulse ratio of 16 ( f s = 800Hz, f o = 50Hz ). The excellent current tracking and near constant switching frequency (except near polarity changes of the output voltage) achieved by the strategy in both cases can be clearly seen. Since the zero-crossings of three-phase current errors are synchronized to a fixed clock in the same way as the single NPC phase leg, the harmonic performance of the controller should be close to the known optimal PD PWM. Fig. 12 confirms this result, showing the characteristic separate five-level line-to-line switching of PD modulation, with only limited switching leakage between levels, and a harmonic voltage spectrum which is quite similar to open-loop PD PWM. The major inaccuracy occurs during the adjacent voltage level
6 4
Three Phase Currents (A)

strategy. The three phase sinusoidal reference currents are generated using a TMS320F2810 and digital to analog converters. The DSP is also responsible for calculating the three phase average voltages and generates the variable hysteresis bands accordingly. The three-level three-phase scaled phase leg voltages are reconstructed using the switched states of the phase legs with an analog
S1a
S1b S 1c

2 0 -2 -4 -6 0.00 4 2 0 -2 -4 4 2 0 -2 -4 4 2 0 -2 -4 0.00 100 0 -100 100 0 -100 100 0 -100 0.00

Phase a

Phase c

Phase b

Reference

Va
S1a

I a (t )
Vb
S1b

R
I b (t ) Vc I (t ) c
S 1c

L L

Eb (t )
U0

VDC

Ec (t)

Variable Band & Current Error (A)

VDC

S2a

S 2b

S 2c

Ea (t )

0.01 Phase a

Time (s)

0.02

(a)

0.03

Phase b

Band Clamp to Avoid High Switching

S 2a

S 2b

S 2c

Phase c

* Ia (t )

ea (t )

Sa,tot (t )
Ih,a (t)

- I (t ) a
* Ib ( t )+

CPLD

Sb,tot (t )
Sc,tot (t)

eb ( t )

Logic Decoder
S12a

I c ( t )+

ec (t )

Ih,b (t)
Ra(t) Rb(t) Rc (t)

S12b S12c

Three Phase Voltages (V)

- I (t ) b - I (t ) c
DAC
1 3L

S1a S2a S1b S 2b S 1c S 2c

0.01

Time (s) Phase a

0.02

(b)

0.03

(t )

I h,c (t )

1- Three Phase Average Voltage DSP Calculation 2- Three Phase Pos/Neg Cycle Detection 3- Three Phase Three-Level Variable Band Calculation

Phase b

DAC
0V
s VA s VB

Phase c

-1

s VDC

0.01

Time (s)

0.02

(c)

0.03

s VC

Multiplexer

Fig. 9: Three phase three-level NPC inverter feeding backemf type load with three-level variable band hysteresis controller structure

Fig. 10: Experimental results of the proposed controller for three-level NPC inverter (fs/fo=50, modulation depth=0.9). (a) Three phase output currents (b) Three phase current errors and variable hysteresis bands (c) Three phase line to neutral voltages

DS2c.14-5

Phase a Phase b Phase c

Three Phase Currents (A)

Three Phase Line to Line Voltages (V)

200 100 0 -100 -200 200 100 0 -100 -200 200 100 0 -100 -200 0
0 10

Vab Vbc

-2

-4

Vca

Reference
-6 0.0 0.01 0.02

Time (s)

0.03

0.04

0.05

(a)

0.06

8 4 0 -4 -8 8 4 0 -4 -8 8 4 0 -4 -8 0.0
100 50 0 - 50 -100 100 50 0 - 50 -100 100 50 0 - 50 -100 0.0 0.01 0.02 0.03

0.01

0.02

Time (s)

0.03

0.04

0.05

(a)

0.06

Line to Line Voltage Harmonic Spectrum Fine-tuned Variable Band Fund Freq = 50Hz Switching Freq = 2500Hz WTHD (200th Harmonic) =0.93%

Phase a
Harmonic Magnitude (p.u)

Current Errors (A)

Phase b

-1 10

Phase c 0.01 0.02 0.03 0.04 0.05

Time (s)
Phase a

0.06

(b)

-2 10 0

500

1,000

1,500

2,000

2,500

3,000

3,500

4,000

4,500

5,000

5,500 6,000

Frequency (Hz)

(b)

Three Phase Voltages (V)

Fig. 12: Experimental results of three phase (a) line to line voltages (b) line to line harmonic spectrum. (fs/fo=50, modulation depth=0.9).

VI.
Phase b

REFERENCES

Phase c
0.04 0.05 0.06

(c) Time (s) Fig. 11: Experimental results of the proposed controller for three-level NPC inverter (fs/fo=16, modulation depth=0.9). (a) Three phase output currents (b) Three phase current errors and variable hysteresis bands (c) Three phase line to neutral voltages

transitions, where the controller has to clamp the variable hysteresis above zero as shown in Fig 10(b) to maintain switching control during the transition. V. SUMMARY This paper has presented a new variable hysteresis band regulation strategy for a three level NPC multilevel inverter. The strategy uses the polarity change of the averaged output voltage of a phase leg, to command the phase leg switches using a single hysteresis comparator circuit. This significantly improves the performance of the system compared to previous strategies. The hysteresis bands are then varied using the same averaged voltage to maintain a near constant phase leg switching frequency. Finally, the interacting error for a three phase system is removed before the hysteresis control of each phase leg, to achieve high quality, high performance current regulation. The work has been confirmed both in simulation and experimentally.

[1] J. Rodriguez; S. Bernet, P.K. Steimer, I.E. Lizama, "A Survey on Neutral-Point-Clamped Inverters" IEEE Trans. on, Ind. Electron, vol.57, no.7, pp.2219-2230, July 2010 [2] A. Nabae; I. Takahashi, H. Akagi, "A New Neutral-Point-Clamped PWM Inverter," IEEE Trans. on, Ind. Appl., vol.IA-17, no.5, pp.518-523, Sept. 1981 [3] M.P. Kazmierkowski, L. Malesani, "Current control techniques for three-phase voltage-source PWM converters: a survey" IEEE Trans. on, Ind. Electron., vol.45, no.5, pp.691-703, Oct 1998 [4] G.H. Bode, D.G. Holmes, "Implementation of three level hysteresis current control for a single phase voltage source inverter" Proc. IEEE, PESC, 2000, vol.1, no., pp.33-38 vol.1, 2000 [5] A. Shukla, A. Ghosh, A. Joshi, "Hysteresis Modulation of Multilevel Inverters" IEEE Trans. on , Power Electron., vol.26, no.5, pp.1396-1409, May 2011 [6] Poh Chiang Loh; G.H. Bode, D.G. Holmes, T.A Lipo, "A timebased double-band hysteresis current regulation strategy for singlephase multilevel inverters," IEEE Trans. on, Industry Appl., vol.39, no.3, pp. 883- 892, May-June 2003 [7] D.G. Holmes; R. Davoodnezhad, B.P. McGrath, "An improved three phase variable band hysteresis current regulator," Power Electron. and ECCE Asia (ICPE & ECCE), 2011 IEEE 8th International Conference on , vol., no., pp.2274-2281, May 30 2011-June 3 2011 [8] B.P. McGrath, D.G. Holmes, T. Lipo, "Optimized space vector switching sequences for multilevel inverters," IEEE Trans. on , Power Electron, vol.18, no.6, pp. 1293- 1301, Nov. 2003 [9] B.P. McGrath, S.G. Parker, D.G. Holmes, "High performance current regulation for low pulse ratio inverters," Energy Conversion Congress and Exposition (ECCE), 2011 IEEE , vol., no., pp.750757, 17-22 Sept. 2011 [10] Q. Yao, D.G. Holmes, "A simple, novel method for variablehysteresis-band current control of a three phase inverter with constant switching frequency," Ind. Appl. Society Annual Meeting, 1993., Conference Record of the 1993 IEEE , vol., no., pp.11221129 vol.2, 2-8 Oct 1993

DS2c.14-6