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Mod 1:Logic Families - DTL-TTL-ECL-I2L & CMOS. Comparison of circuits.

Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in,Fan out

Integrated Circuits
Module 1 Logic Families - DTL - TTL - ECL - I2L & CMOS. Comparison of circuits. Tristate logic Propagation delay - power dissipation - Noise margin window profile - comparison -Fan in Fan out

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Diode Transistor Logic This is simple DTL Nand gate but this works only marginally

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If all inputs are high,the diodes are reverse biased and so no current flows thru them current goes to transistor and the transistor saturates and VOUT goes low. If any input goes low, the base current is diverted out through the input diode. The transistor cuts off and VOUT goes high. This is a NAND gate. n The gate works marginally because VD = VBEA = 0.7V.

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If all inputs are high, Vx = 2.2V and the transistor is saturated. If any input goes low (0.2V), Vx=0.9V, and the transistor cuts off.

Mod 1:Logic Families . Advanced Schottky TTL STD TTL CHARACTERISTICS Propagation delay=9 ns 5V 2V High 0 V to 0.4 mv .Low power Schottky TTL.low power TTL. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in.8V Low Noise Margin=0.DTL-TTL-ECL-I2L & CMOS.High speed TTL . to provide a reasonable tPLH.Fan out  The added resistor RD provides a discharge path for stored base charge in the BJT.8V=logic 0 2 V to 5 V=logic 1 Good speed Low manufacturing cost Wide range of circuits Availability in ssi and msi 0. TTL-Transistor Transistor Logic     Depends only on transistor to perform logic operation Most popular and widely used Here transistor operates in saturated mode Here basic gate used is NAND ADVANTAGES     DEMERITS      Tight Vcc tolerance Relatively high power consumption Moderate packing density Generation of noise spikes Susceptible to power transients SUBFAMILIES:Std TTL . Schottky TTL . Comparison of circuits.

8 V TOTEMPOLE O/P ‘Q3 sits above Q4’=TOTEMPOLE .8 V across the stray and o/p capacitances b/w C & E of Q4. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in.thus current flows thru R1 to base of Q2 and Q2 turns on Current thru Q2’s emitter flows into the base of Q4 and so Q4 =ON The collector current of Q2 flows thru R2 and so produces a drop across it thereby reducing the voltage at collector of Q2 Thus Q3=OFF Since Q4 is ON.Vo is at low level Output=LOGIC 0 Case 2:when either A or B or both are low: BE junctions of Q1 are forward biased.DTL-TTL-ECL-I2L & CMOS.Multi emitter Transistor.all current flows into base of Q3 and Q3=ON. Since Q2 is off.This is called a Totempole arrangement Diodes D1 and D2 protect Q1 from being damaged by –ve spikes of voltage at input When –ve spikes appear . Comparison of circuits.4 to 3.Thus Q4 =OFF Q3 gets enough base current bcoz Q2 is off(Since no current flows into collector of Q2. CB junction is forward biased.) Thus base of Q1 is at 0.8 V=LOGIC HIGH When Q4 is off.but here there is a voltage of 3.no current flows through it.So current flows to ground through emitter.7V which cannot forward bias the BE jn of Q2 Therefore Q2 is OFF.Phase Splitter Q3 sits above Q4.4 to 3. Q2.So no current flows thru emitter of Q1.B. V o/p=Vcc – Vr2 –VBE3 – VD =3. Fan out=10 TWO INPUT TTL NAND GATE Q1. Therefore it gets charged to 3.diodes become forward biasedand conduct spikes to Ground Diode D: ensures that Q3 and Q4 do not conduct simultaneously Q3:acts as an emitter follower WORKING Case 1:When both i/ps are high : both BE junctions of multiemitter Q1 are reverse biased.Q4 does not get required base drive .Fan out Fan in=8.4 to 3.(here CB jns are R.Mod 1:Logic Families .

Inclusion of Q3 and D makes the current thru R4=0 in o/p low state.So it acts as a sink for input current of load gate Q4 is the current sinking transistor or pull down transistor coz it brings o/p to its low state.VBE OF Q4=0.Since Q4 gets base drive from Q2 ADVANTAGE OF TOTEMPOLE: Even though ckt can work with Q3 and D removed. Since Q4 is in on state a large current can flow thru it to ground .Mod 1:Logic Families .The low o/p impedance provides a small time constant for charging up any capacitive load on the o/p Thus active pullup reduces current in LOW STATE and provides very fast rise time waveforms in HIGH state Current Sinking A TTL ckt acts as current sink in low state ie it receives current from i/p of the gate driving it.power dissipation increases.Fan out   At any time only one will be conducting..DTL-TTL-ECL-I2L & CMOS. Comparison of circuits. CURRENT SOURCING: A TTL ckt acts as a current source in HIGH state in that it supplies current to the gate it is driving.by connecting R4 directly to collector of Q4.This is ensured by diode D Q4=ON. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in.7.thus power dissipation decreases In o/p high state .Q3 acts as an emitter follower with its associated low o/p impedance.Q3 is the current sourcing transistor or pull up transistor bcoz it pulls up the o/p voltage to its high state .

e the active pull up of totempole is not present.Mod 1:Logic Families . Totempole 2.the pullup transistor Q3 and diode D are omitted)i. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in.Fan out TTL LOADING AND FAN OUT There is a limit on the amount of current a TTL o/p can sink in Low state(IOLmax )source in HIGH state(IOHmax).e. _________________________________________________________________________________ NOTE:there are 3 configurations for TTL 1.Instead only an external . Open collector 3.Using these limits we can find fan out ie max no of i/ps that can be connected to a ttl o/p HIGH state fanout= IOHmax /IIH LOW state fanout = IOLmax /IIL The smaller of these 2 values is taken as actual fan out capability. Comparison of circuits.the o/p is at Q4 with nothing connected to it( i.DTL-TTL-ECL-I2L & CMOS. Tristate OPEN COLLECTOR In open collector.

Mod 1:Logic Families .Fan out resistor R is connected to Vcc from collector of Q4.To achieve this we will need 2 more nand gates.Wheras the same thing can be performed by simply tying the o/ps of NAND gates 1.this is called passive pull up. Comparison of circuits.when any of the gate o/ps go to a low state.the common o/p point also goes LOW as a result of shorting to ground through ON transistor .2.This is called Wired AND operationbcoz the and is obtained by simply connecting o/p wires together With this. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in. WIRED AND OPERATION Sometimes the o/p of a no of NAND gateshave to be AND ed.DTL-TTL-ECL-I2L & CMOS.3 as shown in fig.Since R is a passive element.

e in this state the changes in A does not affect the o/p. Comparison of circuits.DTL-TTL-ECL-I2L & CMOS.HIGH IMPEDANCE (Hi-Z) state. i.It is called tristate TTL bcoz it allows three possible o/p states:HIGH. The o/p acts like an open or floating terminal which is neither a HIGH nor LOW It is not exactly an open ckt. The Enabled state(E=1) Here the ckt works as a normal inverter bcoz the high voltage of E has no effect on Q1 or Q2 2. In hi-z state:   both the transistors in totempole arrangement are turned off.The Low at E forward biases the emitter base junction of Q1 and shunts current in R1 away from Q2 . The Disabled State(E=0) When E=0.Mod 1:Logic Families .the circuit goes into its Hi-Z state regardless of the state of Logic i/p A. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in.r.so that o/p terminal is a high impedance to ground or Vcc.Fan out TRISTATE TTL: It utilizes the advantage of high speed of totempole and wire ANDing of open collector configuration.t ground or Vcc The circuit has two i/ps-A is the normal logic i/p and E is an enable i/p that can produce the Hi-Z state.There are 2 states for operation based on the E i/p 1. LOW.but has a very resistance (in MΩ range) w.

35 Fan out=8 Dis adv-It requires one more step in manufacturing than Mos I2L Inverter Some discrete gates are not available in I2L.Fan out I2L-integrated Injection logic              Newest of logic families Used in LSI and VLSI Constructed using only bipolar transistors Absence of resistors makes it possible to intergrate a large no of gates on a single package.So complete microprocessors are obtained on a single chip Easily fabricated economical(low cost) Low power consumption(since no R) Speed power product is a constant and very small ≈4 picojoule Tpd=1 ns PD=1mW Noise Margin=0.DTL-TTL-ECL-I2L & CMOS. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in.The opn of an I2L inverter can be explained using this fig which behaves in same way as an I2L inverter.Mod 1:Logic Families .The p-n-p transistor Q1 serves as a constant current . Comparison of circuits.

Comparison of circuits. A HIGH i/p acts as a current source. The injected current flows into base of Q2turning it ON and making the o/p LOW The o/p transistor has two collectors making it equivalent to two transistors with parallel base and emitters.The direction in which current flows after entering node X depends on i/p level.DTL-TTL-ECL-I2L & CMOS.Instead of a collector resistor. A low i/p is a current sink.Mod 1:Logic Families .Thus it produces two equal o/ps. Thus Q2 is off and o/p is HIGH.Fan out source that injects current into node X.thus diverting currents from the base of Q2.o/ps r connected directly to i/ps of other I2L gates.injected current flows into i/p. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in. . I2L NAND gate The I2L NAND gate is simply an inverter with i/ps connected directly together at the inverter i/p. When i/p =low.

the corresponding o/p transistor is ON and o/p is acurrent sink i. If either or both i/ps are HIGH.the injected current turns on Q2 making the o/p LOW This is how NAND operation is performed I2L NOR The I2L NOR is simply two inverters with their o/ps connected together.Mod 1:Logic Families .Fan out If either i/p A or both A and B are LOW(current sinks). i.both the o/p transistors are OFF.e. . Comparison of circuits.e o/p= HIGH ECL-Emitter coupled logic Also called current mode logic or current steering logic It is the FASTEST of all logic families due to following reasons. o/p=LOW If both the i/ps are LOW.DTL-TTL-ECL-I2L & CMOS. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in.the injected current flows intop the i/ps and Q2 remains OFF(HIGH) If both the i/ps are HIGH.

2.Difficult to achieve good noise immunity(low noise margin) 2. an NMOS or PMOS or CMOS.e.Current drawn is steady 2. 7. Advantage Simpler Inexpensive to fabricate Require less power Have better Noise Margin Greater supply voltage range Higher Fan out Much Lesser chip area reqd Disadvantage 8.Thus they are simple to fabricate and require only a small space Comparison with Bipolar Logic Families 1.DTL-TTL-ECL-I2L & CMOS. 3. Power consumption increased since transistors are not saturated 3.e. 4. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in. transistors are not allowed to go into saturation.Problem of cooling the heat produced by high power dissipation ADVANTAGES: 1. It is a non saturated logic i.There are no resistors and diodes.where a fixed bias current less than Ic(sat) is switched from one transistors collector to another Metal Oxide Semiconductor Logic(MOS) It requires only one basic element i.Its negative supply voltage and logic levels are not compatible with other families 5.which occupy large space.Fan out 1.Transistors are prevented from going into saturation when i/p changes from LOW to HIGH by choosing logic levels very close to each other DISADVANTAGES: 1.ECL gated don’t experience large switching transients WORKING: Operates on the basis of current switching. Limited voltage swing.So storage time delays are eliminated and speed of operation increases 2. Comparison of circuits. Currents are kept high and the o/p impedance is so low that circuit and stray capacitances can be quickly charged and discharged 3. 6.High cost 4. Slower in operating speed .Mod 1:Logic Families . It is called Emitter coupled logic bcoz here the emitters of two BJTs are joined(coupled) at their emitters. 5.

Fan out 9.In LSI.bcoz of MOSFET in current path.indicating that noise margin increases with an increase in power supply.Mod 1:Logic Families . Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in.      CMOS Inverter It consists of an NMOS transistor Qn and a PMOS transistor Qp.VLSI and ULSI for Large memories.So Qp isOFF and Qn=ON.So Qp is ON and Qn=OFF. VGSn=-5 V and VGSp=0 V .It is slower than TTL so hardly used in MSI and SSI CMOS The CMOS family uses both P and N channel MOSFETS in the same ckt to realize several advantages over PMOS and NMOS.CMOS with large Vdd is preferred It draws almost zero current from driving gate. Susceptible to static charge damage Uses 1.So in noisy environments. It can be operated at higher voltage resulting in increased noise immunity: Noise margin is the same in both HIGH and LOW states .large microprocessors due to its ease of fabrication and large packing density. Comparison of circuits.calculator chips.DTL-TTL-ECL-I2L & CMOS. VGSn=0 V and VGSp=+5 V.Thus Vout=0 V .The i/p is connected to the gates of both the devices.There is always a high resistance b/w b/w VDD Terminal and ground.So fanout is very high Very small o/p resistance compared to NMOS Speed of CMOS decreases with increase in load. This results in very low power consumption it has increased complexity and lower packing density than NMOS and PMOS.  It is faster and consumes less power than other MOS families.NM=30%VDD.The +ve supply voltage is connected to source of PMOS and source of NMOS is grounded   When Vin =0 V(LOW).Thus Vout=5 V When Vin=+5V(HIGH).

Fan out CMOS NAND Here Q1 and Q2 are parallel connected PMOS transistors and Q3 and Q4 are series connected NMOS. Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in. Comparison of circuits.VGS1=VGS2=-5 V .DTL-TTL-ECL-I2L & CMOS.  When A=0 V and B=0 V.Mod 1:Logic Families .

Tristate logicPropagation delay-power dissipation-Noise margin window profile-comparison-Fan in. Comparison of circuits.DTL-TTL-ECL-I2L & CMOS.Mod 1:Logic Families .Fan out .