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School o Llectrical Lngineering and Computer Science

\ashington State Uniersity, Pullman, \A-99163.

1his tutorial is an introduction to Cadence tool or circuit layout and simulations. It deals with the
layout o the circuits and their simulations using Cadence packages.

Virtuoso or layouts
Analog Artist Lnironment or design simulations.

Virtuoso is the layout editor tool o Cadence. 1he simulations o the designs can be done using the
Analog Artist Lnironment.

oggivg ovto tbe |^ .,.tev.

At the SUN systems log in screen enter your LLCS log in ID, change the enironment to Common
Desktop Lnironment ,CDL, in the options menu ollowed by pressing OK and then enter your
password ollowed by LN1LR.

Creativg a ror/ivg airector,

Once logged in successully, open a terminal window. 1o do this you can do one o the ollowing

1. Right click on the desktop and go to the 1ools option, then choose 1erminal.
2. Click on the button aboe Perormance management meter on the ront panel. Choose 1his

Now at the prompt gto`, type mkdir Cadwork to create a working directory named Cadwork. All
the work done will be stored in this directory.

tartivg Caaevce

1o start cadence, type rcad at the command prompt. 1his starts Cadence in the background and you
should get a window with the icfb Command Interpreter Window (CIW) as below.

1he Library manager window, which looks like this, also opens.

\ou will also get a "\hat's New" window which you can read and then close or minimize.

1o iew the help manuals, click the lelp button on the icb window.

Creativg a tibrar,

1he ist task is to create a design library. 1o create a library, go to
1he ollowing window opens. Lnter the name o your library say tutorial in the text box.

I you want to store the library at a dierent path, enter the name in the path text box. Lg.
Next click on the radio button Attach to an existing tech library. 1his displays a drop down menu
box. lrom the menu box choose the technology you want to use. In this tutorial we shall use
TSMC 0.2u CMOS018 (6M, sblock, HV FET) technology, which is the CMOS 180nm ,0.18m,

1hen click the OK button. 1his will create a library with name tutorial, attached to 1SMC 180nm

Look at the Library manager window. 1his new library created should be an entry in it under the
column Library.

Creativg a cettrier for a,ovt eaitor

Once you hae created a design library, you can start to put your design into it. In this tutorial we
shall create an inerter.
Now to create a cell-iew go to

lrom the drop down menu box o Library name, choose the library you want the current cell-iew
to be in. In the present case, it is the tutorial library.

Lnter the name o your cell-iew say inerter in the text box. 1hen choose the Virtuoso rom the
drop down menu called 1ool. Virtuoso is the layout editor.

Clicking the OK button should open the layout editor and the LS\, which look as ollows:

1he LS\ window contains a list o all the layers aailable in the technology being used ,here 1SMC
180nm,. 1he layers must irst be selected rom this window to draw them in the layout editor.
Get acquainted with the Virtuoso Layout editor window. On the let side are arious shortcuts to
commonly used commands such as: sae, it, edit, zoom in and out, stretch, copy, moe, delete,
undo, instances, path, rectangle, ruler etc. 1hese commands and many more can also be accessed
rom the menu.

De.igv vrerter
Now let us create an inerter in the editor. 1o create an inerter we need a PMOS transistor, an
NMOS transistor. A transistor is ormed by the oerlap the actie ,p-actie or PMOS and n-actie
or NMOS, and poly layer ,polysilicon, layers. In this tutorial we shall use the MOSIS SCMOS
,Scalable CMOS, scalable design rules. 1hese design rules are -based designed rule set, all design
rules are expressed as unction o . lollowing table shows the alues o or arious technologies.

1echnology 1echnology name in NSCU 1ool
AMI 1.5m
AMI 1.6u ABN ,2P, NPN, 0.8
AMI 0.5m
AMI 0.6u C5N ,3M, 2P, high-res, 0.3
lP 0.5m
lP 0.6u AMOS141B ,3M, sblock, thin-
ox cap,
1SMC 0.35m
1SMC 0.4u CMOS035 ,4M,sblock,lV lL1,
1SMC 0.25m
1SMC 0.3u CMOS025 ,5M,lV lL1,
1SMC 0.18m
1SMC 0.2u CMOS018 ,6M,sblock,lV lL1,

1he alue or this tutorial is 0.1

1he design rules set can be ound at MOSIS`s website

In this tutorial we shall layout an inerter with PMOS and NMOS transistors o minimum size.
According to the design rules the minimum length o transistor equals 2 ,the minimum width o
polysilicon,, while minimum width equals 3 ,the minimum width o actie,diusion,.

a,ovt of vrerter

1he instances o the PMOS and NMOS transistors are already aailable in the technology library.
lor an NMOS transistor, go to
1he ollowing window should open

Click on Browse and the ollowing Library Browser window should open.

Under the Library column choose NSCU_1echLib_tsmc02 ,this is the technology we are using, and
under the Cell column choose the nmos cell and click Close button.
Place the instance o the NMOS transistor in the Layout Lditing window as ollows

1o reeal the nmos transistor with all its layers click Shit- and the NMOS transistor is shown.

In the similar way obtain an instance o the PMOS transistor and place it aboe the NMOS
transistor such that the distance between n-actie layer ,green, and n-well layer is 0.6 ,6,. \ou can
use the ruler to measure the lengths in the Layout Lditor window.

Since both the transistors in an inerter hae the same input, we shall connect the gates with
polysilicon layer. Choose the poly layer and draw a rectangle as shown in the ollowing igure. In the
inerter, the output terminal is the contact o the drains o the two transistors. Draw a rectangle o
metal1 layer and place it such that it touches the metal layers o the contacts in the two transistors.

Now or the power and ground rails, draw two metal1 rectangles and place those at 0.3 unit distance
rom two actie regions, as shown in igure. Connect these two metal layers to the source o the
transistors with metal1 layer to complete the contact between the transistor and power rails.

1he bulks o the two transistors must be connected to proper oltages. lere the n-well o PMOS
must be tied to Vdd while the bulk o NMOS must be tied to ground. Goto CreateContact. lrom
the drop down box choose M1_N contact and place it on the power rail as shown in igure. Goto
CreateContact. lrom the drop down box choose M1_P contact and place it on the ground rail as
shown in igure. 1o reeal the contacts press Shit- and to hide them press Ctrl-.

1he M1_N contact must be inside the n-well, so draw a rectangle with n-well layer so that it encloses
the contact by at least 0.1 units on all sides.

It is a good practice to periodically keep checking or design rule errors. Goto VeriyDRC. 1he
ollowing window appears.

linish by clicking OK. I any design rules hae been iolated, they would be marked on the layout.
Usually a simple rule iolation could result in multiple errors.

Now we shall create pins to mark the input terminal, output terminal, VDD and GND. Goto
CreatePin, the ollowing window appears.

In the 1erminal Names ield enter the ollowing labels: In, Out, VDD, GND. lor Mode select sym
pin ,i it is not already selected,. Select Display Pin Name, or I,O 1ype select input and chose poly
or Pin 1ype. Now moe the cursor to the Virtuoso window, you will ind that it now carries a
rectangle box with In` letters. Place it at the mid point o the polysilicon layer. Clicking once
places the poly layer and a second click o the let mouse button ensures that the label is attached to
the layer. Go to the CreatePin orm and change I,O 1ype to output and the Pin 1ype to metal1.
Moe the cursor back to the Virtuoso editor and place this layer at the center o the metal1 layer that
connects the transistor Drains. Click once to place the layer and one more time to attach the label.
Go to the CreatePin orm and change I,O 1ype to input. Back on the Virtuoso editing window
place this pin at the center o the metal1 layer ,power rail, aboe the p-type transistor. Click once to
place the layer and second time to attach the Vdd label. Repeat the aboe procedure to attach the
gnd label on the metal1 layer below the n-type transistor. 1he Pin type must be same as the layer on
which they are place.
Click on the Sae button or go to Design Sae to sae the layout.
Run the DRC again and i any design rule iolations occur, correct them. Repeat this until there are
no errors. Ones the DRC is passed, goto VeriyLxtract.

Click on the Set Switches button and select tract_ara.itic_ca., and /ee_tabet._iv_etractea_rier
click OK. 1he rest o the inormation in this window should be correct by deault, inish by clicking
OK. 1his should create an extracted iew o the inerter layout. Simulation can be perormed on
this iew. 1o open the extracted iew, in the library manager window, select the library 1utorial`
under library column, inerter` in the cell column, and double click on extracted iew` in the iew
column. 1he ollowing window should open.


lor the simulations o the designs we use the Analog Artist Lnironment tool. In the Virtuoso
Layout Lditing window o the extracted iew, start by going to 1oolsAnalog Lnironment.
1his will open the Airma Artist Circuit Design Lnironment simulation window, which is as
shown below

1he design should be set to the right Library, Cell and View.

Now go to SetupSimulator,Directory,lost.

lrom the window that opens up select the simulation type as spectreS rom the drop down menu.
linish by clicking OK. 1hen go to SetupStimulusLdit Analog. lrom window that opens up
choose the radio button graphical and click OK

The window shown below opens. This is the window in which the stimulus to the inverter is
defined. Observe that the inputs defined in our layout are the entries in this window.

Click on Oll IN,gnd! Voltage dc, in the text box. Change the lunction to a pulse. And enter the
pulse parameters as shown and click the change button. Obsere the input IN change rom o to

Now select and enable the Vdd input, gie it a dc alue o 5V and click the change button. Obsere
Vdd change rom o to on. linish by clicking OK. Similarly gie gnd a dc alue o 0.

Next we hae to gie the type o analysis to be perormed. Let us perorm a transient analysis or
20ns. So go to AnalysisChoose or click the second button on the right o the window. Click the
transient analysis radio button and enter the stop time as 20n. linish by clicking OK.

Now we hae to choose the outputs to be plotted in the waeorm iewer.
Go to Outputs1o be plottedSelect on schematic.
1hen the editor window automatically comes into ocus. Click on the polysilicon layer or input and
metal layer or output. Notice that these metal layers are highlighted. Go back to the Analog Artist
Lnironment window and now there are two entries in the output section o the window. 1hese are
the signals that will be displayed. 1o start the simulations click on the button showing the traic
light ,with green,. Ater simulations are done the waeorm window opens and displays the signals
IN and OU1 as shown.

Click on this button Switch Axis mode in the waeorm iewer to display the waeorms separately.
\ou can use the crosshair to make measurements on the waeorms. 1hey can be obtained by
clicking the buttons Crosshair marker A, Crosshair marker B or using the hot keys a and b.

1he netlist generated by the simulator can be iewed by going to
SimulationNetlistDisplay linal Netlist
It is a good idea to sae the state o simulation, i you want to redo any o the simulations without
haing to re-enter eerything rom scratch. 1o sae the current state o the simulation, in the Analog
Artist Lnironment window go to SessionSae state. In the window that opens, enter the name
or the state o simulation to be saed.

1o redo a saed simulation, ollow this procedure. \hen the Analog Artist Lnironment window
opens, go to SetupSimulation.

lrom the window that opens select the simulation type as SpectreS rom the drop down menu.
linish by clicking OK. 1hen go to SessionLoad state. A window as ollows opens.

lrom this select the state you want to load and inish by clicking OK. 1he preiously saed state o
simulation is loaded and you can make any changes i needed and continue with simulation.