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IMPLEMENTATION OF HUFFMAN DECODER IN FPGA USING VERILOG

A PROJECT REPORT Submitted by P. ABHIRAM (41501106001) S. ANAND (41501106005) W. ANAND (41501106006)

in partial fulfillment for the award of the degree of BACHELOR OF ENGINEERING in ELECTRONICS AND COMMUNICATION ENGINEERING

S.R.M. ENGINEERING COLLEGE, KATTANKULATHUR-603 203, KANCHEEPURAM DISTRICT. ANNA UNIVERSITY : CHENNAI - 600 025 MAY 2005

BONAFIDE CERTIFICATE

Certified that this project report "IMPLEMENTATION OF HUFFMAN DECODER IN FPGA USING VERILOG" is the bonafide work of " P. ABHIRAM(41501106001), S. ANAND (41501106005) and W. ANAND (41501106006) " who carried out the project work under my supervision.

Prof. S. JAYASHRI HEAD OF THE DEPARTMENT ELECTRONICS AND COMMUNICATON ENGG. S.R.M.Engineering College Kattankulathur - 603 203 Kancheepuram District

Mr.B.RAMACHANDRAN SUPERVISOR Assistant Professor ELECTRONICS AND COMMUNICATON ENGG. S.R.M.Engineering College Kattankulathur - 603 203 Kancheepuram District

ACKNOWLEDGEMENT We take sincere efforts to acknowledge the guidance and the advice of all the people who have helped us in completing the project successfully. We grab this opportunity to thank our reve re d director Dr.T.P.Ganesan for providing us with an opportunity to carry on with the project. We take immense pleasure in expressing our thanks to our respected principal Prof.R.Venkatramani, B.E, .M.Tech; F.I.E.who has always been a source of inspiration for us.

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We are greatly obliged to Dr. S. Jayasri, PhD, Head of the Department, Electronics and Communication Engineering for her constant enc oura geme nt throughout the project. We express our gratitude to our guide Mr.Ramachandran, Asst. professor of department of Electronics and communication engineering for his guidance and timely suggestions that helped us go through the tough times of the project. We are indebted to Mrs. Susila, Sr. lecturer Department of Electronics and Communication engineering for conducting timely reviews which helped us completion of our work in time. We also express our since re thanks to all our college staffs and frie nds for their sugge stions and encoura ge ment.

ABSTRACT Digital bandwidth compression of data in is the important due to the

limitations

inherent

transmission

medium.

Algorithms ba sed on Huffman coding are effective and ha ve become feasible with efficient use of bandwidth. The purpose of this project is to present a tutorial and implementation on Huffman coding and decoding techniques. The project also deals with the implementation of Huffman decoder on a xilinx Spartan La ngua ge. CONTENTS Abstract List of Tables List of Figures CHAPTER 1 Page No iii vii viii FPGA using Verilog Hardware Description

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2. Definitions 2.2.2. Huffman Decoding Techniques 3. Introduction CHAPTER 2 2. Introduction To Huffman coding 3. The VLSI design process 4.3 A Data Compression Model CHAPTER 3 3.2 Classification of Methods 2.2 Design Flow using Verilog v 1 2 2 2 6 9 12 16 17 18 21 21 22 24 25 25 26 28 29 .1 Look-Up Table Method CHAPTER 4 4.1.1.4. Very Large Scale Integration 4. De velopme nts in the field of VLSI 4. Reconfigurable computing CHAPTER 5 5.1 A Brief History of Verilog 5. Adaptive huffman coding 3.1 Fundamental Concepts 2.1 Dealing with VLSI circuits 4.3 Classification of VLSI Designs 4.4.1.1.1. Data Compression 2. Verilog 5.

1 Decoding procedure 29 30 31 31 33 34 36 37 38 40 41 41 41 44 45 45 46 47 48 48 CHAPTER 8 8.3. Performance Characteristics 6.4 RTL design and test bench creation 5.9 Synthesizing Verilog CHAPTER6 6.5 RTL verification 5.4. FPGA technology 6.6 Le vels of Abstraction 5.4 Post-Synthesis Simulation 6.2.4.3 Synthesis 6. Design Entry 6.4.5 Implementation 6.6 Rapid development cycles CHAPTER 7 7.4.2 Behavioral Simulation] 6. Implementation of Huffman decoder 7.4.3 Syste m-le vel Verification 5.7 Design process 5.4. FPGA Implementation Overhead 6. Applications of Huffman coding 8.4.1.1.1 Huffman Coding of the Image Data 49 49 vi .8 System level 5.5. General Overview 6. FPGA design flow 6.

3 Huffman Decoding in MP3 CONCLUSION APPENDIX REFERENCES LIST OF TABLES 52 53 55 56 70 Name of the table 3.1. Pixel Number and Huffman Code of Cross mark LIST OF FIGURES page no.2.3 Huffman Code for the Messa ge Figure 2. 13 14 15 18 51 51 Name of the Figure Figure 2.1. 3 3 7 8 vii .2. Each Character's Appearance Frequency 3. Fixe d Lengt h Code 3.The Huffman Codi ng i n MP3 8.8.2 Retrie ve Message Figure 2.4 A dynamic Huffman code page no. Huffman Code 3.2. Huffman Coded C ross Image 8.3.1 Look-Up Table Method 8. 2.1 A block-block code Figure 2.

1 System Diagram Figure 3.4.2.1 Block diagram Figure 8.Figure 3.1 Huffman Coding of the Ima ge Data 12 15 29 32 34 39 43 43 44 48 50 viii .4.1.2: FSM Editor Figure 6.1Design Flow using Verilog figure5.6 .1 Design process Figure 6.1: HDL Editor Figure 6.4.1: Basic Spartan-II Block Diagram Figure 6.7.2.1 Le vels of Abstraction figure5. Huffman Code Decoding Figure5.3: Block Diagram Editor Figure 7.

effective compression techniques are becoming essential. For a give n pro bability de nsity function of symbol set. At the same time. the necessity of efficient data compression schemes for storage and transmission was felt. Video. and hence they are optimal for uncorrelated sequences. often used in lossy compression schemes as the final step after decomposition and quantization of a signal. This would amount to a storage requirement of around 8 -9MB for PCM audio samples. Due to the explosion of multimedia applications. But due to relatively expensive on-chip memory and expensive bandwidth connecting PCs (Personal Computer) through Internet. The a vailability of fa st processors e nable d applica tio ns that need high MIPS. VLSI technology is enabling faster DSPs providing more computational power. Huffman coding is a loss-less compression technique. Data compression reduces the number of bits required to store and transmit the information. Storing of an uncompressed signal requires a large amount of space. Huffman's minimum redundancy encoding minimizes the a ve ra ge numbe r of b its re quired to represent the data.1. coders exploit the symbol probabilities independent of previous symbol. Huffman coding uses unique variable length code words and no Huffman code is prefix of the othe r codes in the table. Huffma n coding is one of the Variable Length Coding (VLC). the memory is becoming cheaper though not at the same rate as that of processo r speed. Huffman coding is useful for the statistical information redundancies using reduction of to encode bit-rate by exploring a "minimum Usually set" of entropy and entropy-coding technique. by assigning short codes to frequently occ urrin g symbols a nd lon ge r codes to inf requently occurrin g symbols. 9 . INTRODUCTION Compression technology has gained significance due to various reasons. This resulted in a spurt of activities generating Audio. Imaging and Speech codec (coder/decoder) standards. A typical audio clip lasts for at least 3 minutes.

2. Definitions A code is a mapping of source messages (words from the source alphabet alpha) into codewords (words of the code alpha bet be ta).1. The source me ssa ge s are the basic u nits into which the string to be represented is partitioned. where blockbloc k indicate s that the sou rce messa ge s an d co deword s a re of fixed le ngth and va riable-va riable c odes map variable-len gth sou rce messa ge s into va riable-length c ode words. source messa ge 0 1 10 message codeword a b c 000 001 010 10 aa bbb cccc codeword source . 1 }. b.2. For purposes of explana tion. The definitions and assumptions necessary to a comprehensive discussion and evaluation of data compression methods are discussed.1 and a variablevariable code is given in Figure 2. d. block-variable. space}.1.2. alpha = { a.Data Compression 2. e. A block-bloc k code for EXAMPLE is shown in Figure 2. using Figure 2. f. Codes can be categorized as block-block. or they may be strings of symbols. the len gth of the c ode d messa ge would be 120. g. For string EXAMPLE.2 the length would be 30. These basic units may be single symbols from the source alphabet.1 c ode. variable-block or variable-variable.1 Fundamental Concepts A brief introduction to information theory is provided in this section. beta will be taken to be { 0. The following string of characters is used to illustrate the concepts defined: EXAMPLE = aa bbb cccc ddddd eeeeee fffffff gggggggg. If the string EXAMPLE were coded using the Figu re 2. c.

the data compression methods are free-parse model differs in a defined-word fundamental way from the classical coding paradigm. or messages may be defined to consist of alphanumeric and non-alphanumeric strings. When so urce messa ge s of va ria ble len gth are allo wed. For example.2: Figure 2. That is. The codes featured in this survey are of the blockva ria ble. Most of the known schemes. All codes involving fixed-length source messages are. ASCII mapping and an examples block-block alphabet of 64 (or 256) single characters onto 6-bit (or 8-bit) code words. a s they do not provide compression. the set of source messages is determined prior to the invocation of the coding scheme. by default. the mappin g from sou rce messages to code words is one-to-one). the coding algorithm itself pa rse s the en semble in to va riable -length seq uences of symbols. variable-va riable.e. defined-word codes. in text file processing each character may constitute a message. In free-parse methods.. These a re not disc ussed. each token may represent a message. the question of how a message ensemble (sequence of messages) is parsed into individual messages arises.1: A block-block code The EBCDIC. Many of the algorithms described here are defined-word schemes. and va riable-block types.11 100 101 110 111 d e f g space 011 100 101 110 111 ddddd eeeeee fffffff gggggggg space Figure 2. In Pascal source code. codes. A code is distinct if each codeword is distinguishable from e ve ry othe r (i. A distinct code is uniquely decodable if every 11 . oldest are and most of widely used codes.

In order to decode a message encoded using the codeword set { 1. 00 } is an example of a code which is uniquely decodable but which does not have the prefix prope rty.2 Classification of Methods In addition to the categorization of data compression schemes with respect to message and codeword lengths. we now define related terms. that is. All uniquely decodable block-block and variable-block codes are prefix codes. each of these features is desirable. Prefix codes are instan taneously decodable. then the first codeword would have been 100000). The code with codewords { 1. lookahead is required. Clearly. For example.2 are both distinct. restorin g t he coded message to i ts original form. the y ha ve the desirable property that the coded me ssa ge can be parsed into codewords without the need for lookahead. but this can not be de termined until the last (tenth) symbo l of the message is read (if the string of zeros had been of odd length. the coded messa ge 11 could be decode d as eithe r ddddd o r b bbb bb. The decoder performs t he i nve rse ope ratio n. The e ncoded messa ge ma y be referred to as an encoding of the source ensemble. The process of transforming a source ensemble into a coded messa ge is co ding or encoding. which re qu ires that no codeword is a proper prefix of any other codeword. 00 }. 100000. these 12 . the first codeword of the messa ge 100000 0001 is 1.1 and Figure 1. The codes of Figure 1. The algorithm which constructs the mapping and uses it to transform the source ensemble is called the encoder. In this section. For example. 100000. A uniquely decodable code is a prefix code (or prefix-free code) if it has the prefix pro pe rty. but the code of Figure 1. 2.2 is not uniquely decodable.codeword is identifiable when immersed in a sequence of codewords. a code has been defined to be a mapping from a source alphabet to a code alphabet.

the assignment of codewords to source messages is based on the probabilities with which the source messages appear in the messa ge en semble. Me ssages which appear mo re frequently a re represented by short codewords.A Huffman co de for the me ssa ge EXAMPLE (code len gth=117). so that a given me ssa ge is represen ted by the same code word every time it a ppea rs in the me ssa ge ensemble. If EXAMPLE were coded using this Huffman mapping. The classic static defined word scheme is Huffman coding [Huffman 1952]. A static metho d is o ne in wh ich the ma pping from the set of messa ges to the set of codeword s is fixed before tran smission be gins. A code is dynamic if the mapping from the set of messages to the set of codewords changes over time. In Huffman coding. A Huffman code for the ensemble EXAMPLE is given in Figure 2.methods are classified as either static or dynamic. messages with smaller probabilities map to longer codewords. These probabilities are determined before transmission begins.3 -. For example. The assignme nt of codewo rds to messa ge s is ba sed 13 . dynamic Huffman c oding involve s computing an a pproximation to the proba bilities of occurrence "on the fly" .3. the length of the coded messa ge would be 1 17 source messa ge a b c d e f g space probability 2/40 3/40 4/40 5/40 6/40 7/40 8/40 5/40 codeword 1001 1000 011 010 111 110 00 101 Figure 2. as the en semb le is bein g transmitted.

the short codeword will be mapped to one of the higher probability messa ge s and x will be mapped to a longer code word.4 -. A message x may be represented by a short codeword early in the transmission because it occurs frequently at the beginning of the ensemble. for a pa rticula r word to occur frequently for short periods of time then fall into disuse for long periods. common in a wide va riety of text type s.4 presents a dynamic Huffman code table corresponding to the prefix aa bbb of EXAMPLE. As a n illustration. The term adaptive will be used for the remainder of this paper. 14 . in that they adapt to changes in ensemble characteristics over time. the fact that these codes adapt to changing characteristics is the source of their appeal. Dynamic codes are also referred to in the literature as adaptive. at this point in time b has higher frequency and therefore is mapped to the shorter codeword. source messa ge a b space probability 2/6 3/6 1/6 codeword 10 0 11 Figure 2. Later. even though its probability of occurrence over the total ensemble is low. when the more probable messages begin to occur with higher frequency.on the values of the relative frequencies of occurrence at each point in time. Figure 2. Some ada ptive methods ada pt to chan ging patte rns in the so urce while others exploit locality of reference. Although the freq uenc y of space over the en tire messa ge is grea ter than that of b.A dynamic Huffman code table for the prefix aa bbb of messa ge EXAMPLE. Locality of reference is the tende nc y.

2. the sender must choose one of the k previously-agreed-upon codes and inform the receiver of his choice (by transmitting first the "name" or number of the chosen code). Thu s. and the time required for 15 . Static Huffman coding requires two passes: one pass to compute probabilities and determine the mapping. The mapping may preface each transmission (that is. There are two dimensions along which each of the schemes discussed here may be measured. In addition. In one-pass methods the encoder defines and redefines the mapping dynamically. the goal is speed. the time required for the encoder to generate the coded message. each file sent). during transmission. algorithm complexity and amount of compression. When data compression is used in a data transmission application.3 A Data Compression Model In orde r to discuss the rela tive me rits of data comp ression techniques. Speed of transmission depends upon the number of bits sent. An algorithm may also be a hybrid. a framework for comparison must be established. The decoder must define and redefine the mapping in sympathy.All of the adaptive methods are one-pass methods. in essence " learn in g" the mappin g as code words a re receive d. and a second pass for transmission. For each transmission. the fact that an initial scan is not needed implies a speed improvement in the adaptive case. sender and receiver maintain identical codebooks containing k static codes. neither completely static nor completely dynamic. only one scan of the ensemble is required. In a simple hybrid scheme. the mapping determined in the first pass of a static coding scheme must be transmitted by the encoder to the decoder. or a single mapping may be agreed upon and used for multiple transmissions. as lo ng as the encoding and decoding times of an adaptive method are not substantially greater than those of a static method.

entropy imposes a lower bo und o n the numbe r of bits re qu ired for the c ode d messa ge. For a dynamic scheme. The a ve ra ge information conte nt o ve r the source alphabet can be c omputed b y weightin g the information content of each source letter by its probability of occurrence. scheme.3: H = 2. Given that message EXAMPLE is to be encoded one letter at a time.the decoder to recover the original ensemble. Since the length of a codeword for message a(i) must be sufficient to carry the information content of a(i). yielding the expression SUM{i=1 to n} [-p(a(i)) lg p(a(i))]. leaving only the informational content. and the decoding algorithm. it is clea r that x is not at all informa tive since it had to occur. When data is compressed. This definitio n has intuitive appeal. This quantity is referred to as the entropy of a source letter. the entropy of its source can be calculated using the probabilities given in Figure 1. the more u nlikely x is to a ppea r. The measure of information of a source message x (in bits) is -lg p(x). there are just two algorithms: the encoding algorithm. variable length codewords must be used if the lower bound is to be achieved. he nce t he la rger its i nfo rmation content. and the decoding algorithm. the encoding algorithm. or the entropy of the source. so that the minimum number of bits contained in an encoding of EXAMPLE is 116 16 . the smalle r the value of p(x. Simila rly. For a static there analyze: construction algorithm. in the case that p(x=1. The total number of bits must be at least as large as the product of H and the length of the source ensemble. and is denoted by H. the goal is to re duce re dunda nc y. it is nonetheless are three necessary algorithms that to the algorithm the be map efficient in order for the scheme to be practical.894. Since the value of H is generally not an integer. In a data storage application. although the degree of compression is the primary concern.

Introduction To Huffman coding The latest trend in data compression is Variable Length Decoder for Huffman codes. we ma y sa y that Huffma n encoding produces a file whose size is 49% of the original ASCII file. This yields a compression ratio of 6/2. 17 . Using the decoder we can obtain the original data from the compressed data. Clearly the meaning of this term is the average le ngth of a coded messa ge. The Huffman c ode in the above EXAMPLE in 117 bits. ` The amount of compression yielded by a coding scheme can minimizing codeword be measured by a compression ratio. 3. or 2. The definition C = (a ve ra ge messa ge len gth)/(average c odeword length) captures the commo n meaning.9. We will use the term average codeword le ngth to repre sent this quantity. Alternatively.H uffma n uses average me ssa ge length. with which the amount of the digital data is compressed. representing compression by a facto r of more than 2. which is a comparison of the length of the coded messa ge to the le ngth of the original en semb le.9 bits per character. Since redundanc y is defined to be a ve rage codewo rd le ngth min us entropy and entropy is constant average for a given length probability minimizes distribution. as a measure of the efficiency of a code. The term compression ratio ha s been defined in se veral wa ys. then the average me ssa ge length is 6 bits. redundanc y. If we think of the characters of the ensemble EXAMPLE as 6-bit ASCII characters. SUM p (a (i)) l(i). or that 49% comp ressio n has been achie ve d.

1 System Diagram The figure 3. There is a sentence in which only 5 characters A to E are used. Suppose the following example.Figure 3. The sender transmits the compressed data using Huffman codes. Symbol Frequency to appear A B C D E 15 7 6 6 5 18 . Since the Huffman code length is not fixed. and the decode r uncomp re sses the data and recove r the origina l data. The system is divided into two large blocks such as Sender and Decoder. the decoder has to find out the length of each code while processing.1 shows the system diagram. CEACDABABCEABADACADABABADEACBADABCADAEE In total there are 39 characters. In the following sections. the basics of the Huffman codes are explained in o rde r the students who has the digita l design kno wled ge to challenge the design task. The table 1 show the each cha racte r's appea rance fre que nc y.

Symbol Frequency to appear Bit Pattern A B C D E 15 7 6 6 5 000 001 010 011 100 Total bits 15*3=45 7*3=21 6*3=18 6*3=18 5*3=15 Total 117bits Table 3.Table 3. The table 3 shows the the example using the Huffman code. Since there are totally 39 alphabets. If you w an t to express the sente nce as a digital data. you will notice the appearance frequency of 'A' is ma ximum. Fixed Length Code In order to express the 5 alphabets. Since the appearance frequency of 'A' is high. if we use shorter length code for 'A'. 19 . The total number of bits are reduced from 117 to 87 bits. you can assign fixed length bit pattern to each alphabets. the amount of digital da ta to ex press the sentence can be decreased.1. 39*3=117 bits are needed to express the sentence in digital data. One method to do this is to use the Huffman code. Each Character's Appearance Frequency From the table 1.2. Please see the table 2. 3 bits-length code is used. In the table 2 example used the 3 bits fixed length code.

2.3. the word 'BAD' can be expressed '1000110'. Huffman Code Decoding The bit stream '01100111' has to be analyzed from the be ginnin g. the decoding method will be explained. which is 7 bits length.Symbol A B C D E Frequency to appear 15 7 6 6 5 Huffman code 0 100 101 110 111 code length 1 3 3 3 3 Total bits 15*1=15 7*3=21 6*3=18 6*3=18 5*3=15 Total 87bits Table 3. then fin d out a matching Huffman Co de. Figure 3. Instead. Using the figure 2. once the matched Huffman code is 20 . Since the code length is not fixed. Huffman Code Using the Huffman code in tha table 3. the bit stream '01100111' can be analyzed from the beginning then the word 'ADAE' can be recovered.

Adaptive huffman coding Adaptive Huffman coding was first conceived independently by Faller and Gallager. The c ode is ada ptive. In this source the messa ge proba bilitie s. at first the code '0' is found.1. Then you can know the alphabet 'D' and the code length of 3. All of these methods are definedword schemes which dete rmine the map ping from source messa ge s to codewords based upon a remain optimal for the running estimate of the estimates. one-pass methods are not very interesting if the number that of of bits the they transmit is significantly greater than two-pass scheme. the enc ode r is " learnin g" the characteristics of the source. Knuth contributed improvements to the original algorithm and the resulting algorithm is referred to as algorithm FGK. A mo re recent version of adaptive Huffma n coding is described by Vitter. Of course. Another advantage of these systems is that they require only one pass over the data. In the exa mple of the figure 2. After 3 more bits are analyzed. The Huffman code satisfies the condition of " any code of the group does not match the any prefix of other code of the group". the code '110' will be found. chan ging so as to current way. Then the decoding method explained above can only generate the original data. The decoder must learn along with the encoder by continually updating the Huffman tree so as to stay in synchronization with the encoder. In essence. Then yo u can know the alphabet 'A' and the code length of 1. 3. 21 .detected. Then you can restart the analysis from the second bit. ada ptive Huffman codes resp ond to locality. the first bit of the next code can be found.

Number of bits to be extracted from the bit-stream fo r e ve ry symbol sea rch depen ds upon the maximum Huffma n code length in the table. The performance of the adaptive methods can also be worse than that of the static method.2. 3. Remaining bits are put back into the bit-stream. Look up table metod N. 2. 3. can be better than that of static Huffman coding. Number of rows in the table will be 2L where L is maximum Huffman code length.In tere stin gly. Huffman Decoding Techniques The three types of decoding techniques are 1. Huffman symbols are decoded within one search since extracted bits from the bit-stream gives address to the symbol in the table.1 Look-Up Table Me thod In this technique. the adaptive method of Faller. providing typical compression factors of 30-40%. Th is does not c ontrad ict the optimality of the static method as the static method is optimal only over all methods which assume a time-in va riant ma pp in g. Huffman code length for each symbol is stored in the table to determine the number of bits used for decoding a symbol. 2. 22 . The performance of compact is quite good. the performance of these method s. where the next symbol starts. Huffman tables used by the algorithm should be converted in the form of look-up table as explained below. Upper bounds on the redundancy of these methods are presented in this section.level look up table method Binary tree search method 3. As discussed in the introduction. Gallager and Knuth is the basis for the UNIX utility compact. in te rms of number of bits transmitted. Tables used for this technique must contain entry of symbols with its corresponding Huffman code lengths.

The first row of the table has. Huffman code length = 1 and Huffma n code = 0. Number of bits required to append Huffman code = 3 – 2 = 1. the number of rows in the converted = 23 . In th is wa y. Since Huffman code len gth is less tha n the maximum value. Bits required to append Huffman code = 3 – 1 = 2 000 = 0 001 = 1 010 = 2 011 = 3 These a re the four a dd re sses f rom 0 to 3.Procedure for Table Conversion: Table 1 is use d to demonstrate conversion of a valid Huffma n Table into LookUp form Table 3. fo r whic h symbol = 0 and Huffman code length = 1 in the converted table.1 The above table has maximum Huffman code length of 3. other ad dre sses of the table e nt ries are calculated. it can have symbol entries more than one in the con ve rted table. 110 = 6 111 = 7 Add resses 6 a nd 7 will ha ve symb ol = 1 and Huffman code len gth = 2. Since the maximum code length for Table1 is 3. Next row of the table has symbol = 1. Addresses for the look -up ta ble entries a re calculated as: Bits required for appending Huffman code Maximum Huffman code length – Length of Huffman code. Huffman code length = 2 and Huffman code = 3.2. symbol = 0.

First 3 bits give address "100" (= 4). hence 2 bits are put back into the bit-stream. This is the field which involves packing more and more logic devices into 24 . This method requires huge memory for tables having long Huffman codes and hence inefficient for such tables. The bit-stream pointer now points to 5th bit in the bit-stream.2 Example of a Decoding Procedure : Let " 10 00110" be a valid bit-stream. Since 3 is the maximum Huffman code length of Table2.2. Again e xtract 3 bits " 011" (= 3) to get the next symbol from the bit-Stream. This is the fastest Huffman Decoding Technique. B ut it is ve ry useful for the tables having small Huffman codes. which corresponds to symbol 3 and Huffman code length = 3 in the look-up table. Since 3 bits are extracted f rom the bit-stream and the actual length of Huffman code is 1. This ad dress give s symbo l = 0 and Huffman c ode len gth = 1. In this wa y the symbols are sea rched in Lo ok-Up Table method. extract 3 bits from the bitstream. 4. Very Large Scale Integration: VLSI stands for " Ve ry Large Scale Integration". 3 its bits from the bit–stream = 1 for and corresponding symbol Huffman code length = 2. put back 1 bit into the bit-stream. Table2 below shows converted Huffman Table for Table1: Table3. addressing Aga in "110" extract (= 6).table will be 2 = 2 3 = 8.

1 Dealing with VLSI circuits: Digital VLSI circuits are predominantly CMOS based.. All the miniaturisatio n involves new things to consider. but the beha viou r remains the same. Whats so special in our case is that there are many possible ways to do this. The way normal blocks like latches and gates are implemented is differen t from what students ha ve seen so far. frequencies is increased consumption of power. your bran d new state -of the-art digital camera.. which we will look at in later sections. Large complicated circuits running at very high frequencies ha ve o ne big problem to tackle . Circuit Delays.smaller and smaller areas. there ca n be 25 . Power. there can be multiple layers of different mate rials o n the same silic on..the problem of de lays in propagation of signals th rough ga tes a nd wires . Coupled with the fact that surface areas ha ve decreased.. the y can actually beco me comparable 2. Laying out the circuit components is task common to all branches of electronics. 4.. A lot of thought has to go into actual implementations as well as design. your computer. Another to effect of the high clock operation speeds. Layout. VLSI circuits are e ve rywhere .. This has two-fold effect devices consume batteries faster. heat poses a major threat to the stability of the circuit itself. Thanks to VLSI. circuits that would have taken boardfuls of space can now be put into a small space few millimeters across! This has opened up a big opportunity to do things that were not possible before. e ve n for areas a few micrometers across! The operation speed is so large that as the dela ys add up. Let us look at some of the factors involved . 1. and heat dissipation increases. the cell-phones. 3. and what have you. All this involve s a lot of expertise on man y fronts within the same field. you r ca r.

making it either easy or difficult to implement the components on the silicon. in two ways. Layout can also affect the fabrication of VLSI chips. This la nguage is use d to de sign the c irc uits at a high-le vel. 26 Coding Verification .different component arrangements of and the smaller parts so for the same on. All modern digital designs start with a designer writing a hardware description of the IC (using HDL or Hardware Description La ngua ge ) in Verilog/VHDL. which describes what the circuit is supposed to do. which work in a similar fashion. we can say that the Verilog can be called as the " C" of the VLSI industry. Without going into details. A Verilog or VHDL program e ssen tially d esc ribes the ha rdwa re (logic gates. The choice between the two is determined by the way we chose the layout the circuit components. It can eithe r be a behavioural description.a wafer with repeated number of identical Ics. 4. The power dissipation and speed in a circuit present a trade-off. Flip Flops. The VLSI design process A typical digital design flow is as follows: Specification Architecture RTL RTL Synthesis Backend Tape Out to Foundry to get end product…. or a structural description. the other is affected. counters etc) and the interconnect of the circuit blocks and the functiona lity. which describes what the circuit is made of.2. There are o ther la ngua ge s for describin g circu its. if we try to optimize on one. suc h as Ve rilog.

Fo r more complex analo g chips suc h a s data con ve rters. Classification of VLSI designs 1. 4.B oth forms of de sc ription a re then used to ge nera te a very low-le vel desc riptio n that actua lly spells out ho w all this is to be fabricated manufacture on the silicon of chips. b uildin g u p to a cell level. Phase Locked Loops. the flow changes somewhat. the This will result in the IC. There is a hardware description language called AHDL but is not widely used as it does not accurately give us the behavioral model of the circuit because of the complexity of the effects of parasitic on the ana lo g be ha vior of the circuit. the design is d one at a transisto r level. Man y ana lo g chips a re what a re termed as “flat” or non-hierarchical designs. ve ry small portion of analog design can be automated. 27 . Analog: Small transistor count precision circuits such as Amplifiers. the n a block le vel a nd the n integrate d at a chip le vel.3. This is true for small transistor count chips such as an operational amplifier. Sensors etc. or a filter o r a powe r ma na gement c hip. Data converters. intended A typical analog design flow is as follows: In case of analog design. Specifications Architecture Circuit Design SPICE Simulation Layout Parametric Extraction / Back Annotation Final Design Wh ile digital design is high ly automate d now. filters.

etc. and do it well. calenda r. and they are all closely related to each other. Together. consider the fact that the digital wristwatch normally consists of a single IC doing all the time-keeping jobs as well as extra features like ga mes. 4. It in volves fab ricatin g circuits that can be reprogrammed on the fly! And no. that when programmed act just like normal electronic circuits. Reco nfigurable computing: Reco nfigu rable c omputing is a ve ry interesting a nd pretty recent de ve lo pment in microelectro nics.2 Application Specific Integrated Circuits: Progress in the fabrication of IC's has enabled us to create fast and powerful circuits in smaller and smaller devices. we are not talking about microcontrollers running with EEPROM inside.signal filters. The biggest application of this ability is found in the design of ASIC's. etc. 3. They are so designed that by changing or 28 . This also means that we can pack a lot more of functionality into the same area. SoC or Systems on a chip: These are highly complex mixed signal circuits (digital and analog all on the same chip).each device is created to do a particular job. A network processor chip or a wireless radio chip is an example of an SoC. These are IC's that are created for specific purposes . To go to extremes. The most common application area for this is DSP . Reconfigurable computing involves specially fabricated devices called FPGA's. image compression.4. Developments in the field of VLSI There are a number of directions a person can take in VLSI. these developments are going to make possible the visions of embedded systems and ubiquitous computin g.

Verilog is intended to be used for ve rificatio n through simulation. The first ve rsion of the IEEE standard fo r Ve rilo g was published in 1995. One could think of many such applications. This is the complete authoritative definition of the Verilog H DL.using an FPGA to try out a new design before it is actually fabricated. at different times. If we use a reconfigurable platform. Applied to electronic de sign. The IEEE Verilog standard document is known as the Lan gua ge Reference Manual. or LRM. This can drastically reduce de velopme nt cycles. A revised version was published in 2001. the FPGA's can be made to behave like any circuit we wish. and also sa ve some mone y tha t wo uld ha ve been spent in fabricating prototype IC's. 5. this is the current version. not the least of which is prototyping . We co uld ha ve a microprocessor that could optimise itself for every task that it tac kled! Or then co nside r a system tha t is too big to impleme nt on hardware that may be limited by cost. Verilog V erilog is a Hardwa re Description Lan gua ge. We know that running complex programs can benefit greatly if sup port wa s b uilt into the ha rdware itself. Consider for example. or other constraints. we could design the system so that parts of it are mapped onto the same hardware. This fantastic ability to create modifiable circuits a gain opens up new possibilities in microelectronics. 29 . a textual format for describing electronic circuits and systems. for test analysis (testability analysis and fault grading) and for logic synthesis." reprogrammin g" the c onnections be tween nume rous sub module s. microprocessors which are partly reconfigurable. The Verilog HDL is an IEEE standard . for timing analysis.number 1364.

Cadence Design Systems acquired Gateway in 1989. with the intention that it should become a standard. See the appropriate Knowhow section for more details about SystemVerilog. howe ve r. The Verilog HDL is now maintained by a non profit making organisation. 5. or PLI. and with it a hardware description lan gua ge. which is also expected to become an IEEE standard in 2005. Ca dence put the language (but not t he simulat or) into the publ ic domain. 30 . This is a collection of software routines which permit a bidirectional interface between Verilog and other lan gua ges (u sually C). IEEE Std 13 64 also defines the Programming Langua ge Interface.1 A Brief History of Verilog The history of the Verilog HDL goes back to the 1980s. Accellera. Verilog-XL.A further revision of the Verilog standard is expected to be published in 2005. Note that verilog is not an abbreviation for VHDL HDL Verilog and VHDL are two different HDLs. nonproprie tary langua ge. In 1990. OVI had the task of taking the langua ge through the IEEE standardisation procedure. which was fo rmed from the merge r of Open Verilog International (OVI) and VHDL International. Accellera .the organisation that oversees developments in the Verilog language . when a company called Gateway Design Automation developed a logic simulator. and with it the rights to the language and the simulator.has also published the SystemVerilog extensions to Verilog. They have more similarities than differences.

For more details. each step described in the following sections may be split into several smaller steps. Syste mVe rilog. see the Systemverilog section of Know-How There is also a draft standard for analog and mixed-signal extensions to Verilog. which extends Ve rilo g.e. This is the current version. Accellera ha ve also been de ve loping a new standard. and parts of the de sign flow will be ite rated as errors are unc ove red. gate array.2 Design Flow using Verilog The diagram below summarizes the high level design flow for an ASIC (i. 1364 2001. SystemVerilog is also expected to become an IEEE standard in 2005. A re vised version was pu blished in 2001: IEEE Std. 31 . although a further revision is expected in 2005. In a practical design situation. 136419 95. Verilog-AMS 5. standard cell) or FPGA.In December 1995 Verilog HDL became IEEE Std.

Alternatively. This is one motivation for SystemVe rilo g.4 RTL design and testbench creation 32 . Verilog may be used to model and simulate aspects of the complete system containing one or more ASICs or FPGAs.Figure 5.2. 5. this ma y be a partial desc ription that abstracts certain properties of the system. whic h enhances Ve rilo g in this area. Verilog is not ideally suited to system-level mode ling.3 System-level Verification As a first step. This may be a fully functional description of the system allowing the specification to be validated prior to commencing de tailed design.1 5. such as a performance model to detect system performance bottle-necks.

RTL simulation is usually one or two o rde rs of magnitude faster than ga te le vel simulatio n. verification can be a real bottleneck. complex designs. a nd can be used for different purposes at va riou s sta ge s in the design process. 5. and 20-30% of the time synthesizing and verifying the gates. and experience has shown that this speed-up is best exploited by doing more simulation. and are sometimes performed by different design teams in isolation to ensure that the specification is correctly interpreted. 5. This it has provides features another for motivation for SystemVerilog development. This starts by capturing the design in Verilog at the register transfer level. not spending less time on simulation. The RTL Verilog should be synthesizable if au toma tic logic synthe sis is to be use d.Once the overall system architecture and partitioning is stable. le vels of de tail. In practice it is common to spend 70-80% of the design c yc le writing a nd sim ulating Ve ril og at and a bo ve t he registe r transfer level. Test case ge neration is a major task that requires a disciplined approach and much engineering in ge nuity: the quality of the final ASIC or FPGA de pends on the co ve ra ge of these test case s. the detailed design of each ASIC or FPGA can commence.e.5 RTL verification The RTL Verilog is then simulated to validate the expediting testbench fu nctionality a ga inst the specification.6 Levels of Abstraction Verilog descriptions can span multiple levels of abstraction i. These two tasks are complementary. and capturing a set of test cases in Verilog. 33 . For today's large.

used for the verification of digital designs. so can be used to model the func tionality of a system at a high le vel of abstraction.Figure 5.6. This is useful at the system analysis and partitioning stage.1 At the highest level. circuits. used the detailed digital Syn thesis to ols tran sform R TL de scription s to gate le vel. Verilog contains stochastical functions (queues and random probability distributions) to support pe rf ormance modeling. Verilog supports gate and switch level descriptions. Verilog which are supports for Register Transfer design Level of descriptions. V erilog supports abstract beha vioral modeling. including gate and switch 34 .

test vectors. The central portion of the diagram shows the parts of the design process whic h will be impacted b y Ve rilo g. most of these functio ns a re not included in the 1364 standard. taking checkpoints. with many tools this is based on Tcl. can also be used to describe simulation environments. which is an industrystan dard tool lan gua ge. Mo st simulators ha ve their own comman d languages. but are proprietary to particular simulators.7 Design process The diagram below shows a very simplified view of the electronic system design process incorporating Verilog. Verilog can be used to control simulation e. 5. tracing waveforms. static and dynamic timing analysis. Verilog and analysis.g. Howe ve r. expected results. restarting from time 0. With some tools. testability analysis and fault grading.level logic simulation. setting breakpoints. results comparison 35 .

Unlike VHDL. throughput and queuing but only in so far as those built-in langua ge features allow. Verilog restricts the designer to working with predefined system functions and tasks for stochastic simulation and can be used for modeling performance. Designers occasionally use the stochastic level of abstraction for this phase of the design process. This is to some extent addresse d by SystemVerilo g.1 5.Figure 5.8 System level Verilog is not ideally suited for abstract system-level simulation.7. 36 . prior to the hardware-software split. wh ich has support for user-defined types and overloaded operators which allow the designer to abstract his work into the domain of the problem.

Verilog can be used to simu late gate leve l fano ut load in g effects and routing d ela ys through the import of SDF files. Analog Because of Ve rilo g's fle xibility as a programming lan guage. The RTL le vel of abstraction is used for functional simulation prior to synthesis. it is a level of abstraction adopted by the EDA tools (synthesis and timing analysis. 37 . from functional simulation. it has been stretched to handle analog simulation in limited cases. The gate level of abstraction exists post-synthesis but this level of abstraction is not often created by the designer. Verilo g tools provide an integrated design environment in this area. switch level simulation and worst case timing simulation. There is a draft standard – Verilog-AMS – that addresses 5.9 Synthesizing Verilog Synthesis is a broad term often used to describe very different tools. This is best suited to gate arrays and programmable devices such FPGAs. for example).Digital Verilog is suitable for use today in the digital hardware design process. Synthesis can include silicon compilers and fu nction ge nera to rs used by ASIC vendors to produce re gula r RAM and ROM type structure s. Syn thesis is n ot a panacea ! It is vital to tac kle High Level Design using Verilog with realistic expectations of synthesis. manual design and logic synthe sis do wn to gate-level simulatio n. Synthesis in the context of this tutorial refers to generating random logic structures from Verilog descriptions. Verilog is also suited for specialized implementation-level de sign ve rificatio n to ols suc h as fault simulation.

which is by far the most common. devices manufactures by Actel 38 .The definition of Verilog for simulation is cast in stone and enshrined in the Language Reference Manual. It is not sufficient that the Verilog is functionally correct. such as synthesis. FPGA technology FPGAs are chips.g.1-2002) but no vendor ad heres strictly to it. The chips may be programmed either • once: Antifuse technology. 1364. the Verilog must be matched to the idiosyncrasies of the particular synthesis tool being used. it must be written in such a way that it directs the synthesis tool to generate good hardware. which are programmed by the customer to perform the desired functionality. devices manufactured by Quicklogic • se ve ral times: Flash base d. We will concentrate on RTL synthesis. and moreover. Other tools which use Verilog. The essence of RTL code is that operations described in Verilo g a re tie d to pa rticular clock c yc les. 6. g. allowing the RTL testbench to be easily re-used for gate-level simulation. The synthe sized netlist exhibits the same clock-by-clock cycle behaviour. e. There is an IEEE standard fo r Ve rilo g syn thesis (IEEE Std. e. will make their own interpretation of the Ve rilo g langua ge. We shall tackle some of these idiosyncrasies in this Verilog tutorial. The re are currently three kinds of synthe sis: • • • behavioral synthesis h igh-le vel synthesis RTL synthesis There is some overlap between these three synthesis domains.

some devices allo w even pa rtial re-configuration during operation allows new approaches and applications buzzword “reconfigurable computing”. • Flash FPGAs . keep their configuration after power-off .Devices ma y be re-programmed se ve ral thousand times and a re non-volatile.ASIC replacement for small volumes.Unlimited re-programming .• Dyn amically: SRAM based.Additional circuitry is required to load the configuration into the FPGA after power on . E. .Re-configu ration is very fast. but hardly for already manufactured boards. General Overview 39 . . de vices manufactured b y Actel. i.1. Cypress.Re-configuration takes several seconds • SRAM FPGAs . that searches for a specific DNA pattern. e.Devices are configured by burning a set of fuses. Altera. Xilinx each technology has its own advantages. the chips may be updated in the field . Once the chip is configured. or a mobile phone that downloads the latest protocol update 6. it cannot be altered any more.e.Currently the dominating technology . a circuit.Expensive .Bug fixes and updates possible for new PCBs.With only marginal additional effort. Lucent. g. Atmel. which shall be discussed only very briefly: • Antifuse FPGAs: .g.

however most of them follow a Common approach: A regular. surrounded by a perimeter of programmable Input/Output Blocks (IOBs). flexible. The following paragraphs describe the a rchitectu re impleme nted b y Xilinx Spartan-II FPGAs. programmable architecture of Configurable Logic Blocks (CLBs). which is typically used in highvolume applications where the versatility of a fast programmable solution adds benefits. a de vice family launched in mid 2000.1: Basic Spartan-II Block Diagram 40 . shown in Figu re 6.1.1. The u ser-programma ble gate a rra y.1. families slightly differ in their architecture and feature set. is compose d of five major configurable elements: • IOBs provide the interface between the packa ge p ins and the internal logic • CLBs provide the functional elements for constructing most logic • Dedicated BlockRAM memories of 4096 bits each • Clock DLLs for clock-distribution delay compensation and clock domain control • Versatile multi-level interconnect structure Figure 6. These functional elements are interconnected by a powerful hierarchy of versatile routing channels.There different are several families of FPGAs These available device from semiconductor companies.

This section 41 provides the performance . As the feature of distributed RAM is part of the overhead. helps to estimate the overhead created by the programmable logic fabric. The IOBs are located around all the logic and memory elements for easy and quick routing of signals on and off the chip. we have to take it into account he re. gives an impression of t he o ve rhea d in geo metric un its. First. Each configuration bit has to be stored in a single flip-flop. The ove rhead of 5 9 implies. 6. Values stored in static memory cells control all the configurable logic elements and interconnect resources. Assuming e ve ry bit drives a single add itional gate is ve ry conservative.15-micron FPGA easily reaches die size parity with a 1. Taking the squa re roo t of this result. we calculate the number of configuration bits required for a single logic slice. Performance Characteristics According to the data sheets. The block RAM bits are excluded from this calculation.As can be seen in Figure 6. compared to a standard-cell ASIC. as the block RAM implementation is close to the ideal implementation and therefore can be directly compared between ASICs and FPGAs. FPGA Implementation Overhead Having a gate-count metric for a device. 6.2micron standard-cell ASIC.1.2. This flipflop in turn. the CLBs form the central logic structure with easy access to all support and routing structures.1. These gates numbe rs ma y be divided by the typical gates per slice to ga in an imp ressio n of the “ ga tes pe r gates” implementation overhead. controls a specific a ttribute of the lo gic cell’s be ha vior. These values load into the memory cells on power-up. Spartan-II devices provide system clock rates up to 200 MHz and internal performance as high as 333 MHz.3. that a 0. and can reload if necessary to change the function of the device.

platforms and sites. For all performance data it should be remembered. Using these editors is a convenient way of creating FSMs by graphical entry of bubble diagrams. howe ve r this is highly dependent on the design. On the other side. all values are reported in MHz. The main advan ta ge 42 . Design Entry Design Entry is the process of creating the design and entering it into the development system. 6. these examples have been described in VHDL and ran through the standard synthesis and implementation tools to ach ie ve an un derstan ding of the “ real world” performance. The routing delays are highly dependent on device utilization and the quality of the place & route process. Most tools create VHDL from the graphics representation. Unlike the data sheet figures.1. text may not be the most convenient wa y of editin g a design . The following methods are widely used for design entry: • HDL Editor • State Machine Editor • Block Diagram Editor Typing a design into an HDL Editor is the most obvious way of enterin g high-le ve l langua ges like VHDL in to the de velopme nt system.characteristics of some common functions. the worst delay is reported. special editors are available. In the case of multiple inputs and outputs. auto completion or language templates to speed-up de sign entry. Recent editors offer functionality like syntax highlighting. The ma in a dvanta ge of usi ng a n HD L Ed itor fo r design entry is that text files are simple to share across tools. For creating finite state machines.4. but hide this process completely from the use r. FPGA design flow 6. that about 50% of the delays are caused by routing delays.4.

For creating structural designs. Figure 6. On the other side. sharing a design across tool or platform boundaries may be difficult. with the drawback of a reduced compatibility across tool or platform boundaries.4.1: HDL Editor 43 . that the graphical representation is much easier to understand and maintain. that the graphical represe ntation is easie r to understand and maintain. Again.is. these tools create VHDL or EDIF from the graphical representation and hide this process from the user. block diagram editors are available. Like FSM editors. the main advan ta ge is.

2: FSM Editor Figure 6.Figure 6.4.4.3: Block Diagram Editor 44 .

e. tracing signals is difficult.4. 6. pe rf orm re -timing. Chip synthesizers optimizations. i. To do so. a highle ve l or behavioral simulator is used. and registers. Timing information is either not available or preliminary based on statistical assumptions which may not reflect the actual design. The downside of behavioral simulation is that specific properties of the target architecture. thus giving the developer a quick and complete understanding of the design. 6. na mely timing and resource usa ge are n ot covered. or optimize the ir results acco rding to given constraints.6.4. Recent tools can duplicate registers.4.3 Synthesis Synthesis is the process of translating VHDL to a netlist. FPGA development is much like software de ve lo pmen t. and breakpoints may be set. which executes the design by interpreting the VHDL c ode like any othe r pro grammin g language. which is built from a structure of macros. perform multiplexers. g. As the design hierarchy is flattened and optimized. like RAMs or ROMs are treated as black boxes. post-synthesis simulation is performed. Specific cores. re ga rdless of the target architecture. as the design is not synthesized. adders. procedures and functions may be traced.4 Post-Synthesis Simulation After performing chip synthesis.e. the design is verified by performing behavioral simulation. sign als a nd varia bles may be watched.2 Behavioral Simulation After design entry. The entire process is very fast. especially hierarchy flattening and optimization of combinational paths. At this stage. Due to the mapping of the 45 .

5 Implementation Implementation is the process of translating the synthesis output into a bitstream suited for a specific target device. 46 . 6. all in stance s are assigned to ph ysical locatio ns on the silicon. The result is a single netlist containing all instances of the design during mapping.4.design into very basic macros. or don’t-cares ha ve been resolved in unexpected ways. until the timing constraints are either met. most likely initialization value s ha ve been o mitted. all macro instances are mapped onto the target architecture consisting of LUTs. With this step completed. or the tool fails to further improve the timing. IOBs. This step is much like the linking step in software development. This process consists of the following steps: • Translation • mapping • Place & route During translation. The process continues. This is usually a n iterative process. Du ring place & route. especially RAMs and ROMs are resolved. simulation time is lengthy. When postsynthesis results differ from behavioral simulation. and registers. all instances of target-specific or external cores. guided by timing constra ints provided by the designer. the design is completely described in primitives of the ta rget a rchitecture.

and is radically different from the normal way we write programs. This parallel nature is something very suitable for hardware since the logic circuits are is inherently pa rallel in nature. Implementation of Huffman decoder 7. that is still under de velopme nt.its not based on the normal idea of " sequence of instructions".6 Rapid development cycles The traditional method of designing hardware is a long and winding p rocess.6. Prelimina ry stu dies ha ve shown that La va can actually create better circuits than VHDL itself. is La va.1 Block diagram 47 . whe re the first person to get in normally gains a large advan ta ge. called "functiona l p rogramming" . going thro ugh many sta ge s with spec ial effort spent in design verificat io n at e ve ry sta ge. is very long. since it affords a high-level view of the system. Another quite different language. FP itself is pretty old. This is because it assumes parallel execution as a part of its structure . This pro ve s to be rather undesirable in case of large expanding market.4. with many competitors trying to grab a share. This is based o n an e sote ric bra nch of compute r scie nce. We need alternatives to cut down on this time so that new ideas reach the market faster. Thi s mea ns tha t t he time from drawing board to marke t. without losing sight of low-level features 7.

pulse. If no match is found the next bit is shifted and a compariso n with a look-up table is made a gain. 12. The comparator compares the output from the shift register with the look-up table.Shift Register Figure 7. 9. 10.route the gate components according to the design specifications. The Xilinx design software is used to place. 7. A new bit gets shifted into the shift register for every clock 48 . The input is taken bit by bit and stored in a shift register. The simulated synthesized as explained in the above chapters. 6. If a match is found the output is stored in an output register and the con tents of the in put shift re giste r is cleared. 3.2 Decoding procedure 1. The above process is done till all the bits are decoded. A counter is used to keep track of the number of bits being shifted into the shift register. above verilog procedure code is then is implemented and using ModelSim software with verilog HDL. 5. 8. The 2.1 7. 4. The same process is done till a match is found. The output of the shift register is given to a comparator whose other input is from a look-up table. 11.

3 bits can exp ress the le vels. 8. Applications of huffman coding 8.1. Since the right image (cross mark) is organized by 8x8=64 pixels. Since there a re 8 levels. the darker the pixel gets.13. 14. Then there are 8 levels of the pixel intensity.1 is 8 kinds of pixel intensities. The softwa re ge ne rates a bit file which is then dow nloa ded onto a FPGA Spartan kit. The larger the number increases. The hardware is then tested with a given set of bitstream. Each pixel (picture element) is organized by 3 b its. @ Figu re 8. 49 .1 shows a one example of the black and White ima ge da ta.1 Huffman Coding of the Image Data Figure 7. simply the image needs 64x3=192 bits. The center number is the level. The most bright pixel is 0. Black and White Ima ge The left figure in the figure 7.

2.1. Huffman Coded Cross Image The table 8. Pixel Number Huffman Code 7 0 0 0 0 0 0 7 0000 0 6 1 1 1 1 6 0 0 1 5 2 2 5 1 0 0 1 2 3 4 2 1 0 0 1 2 4 3 2 1 0 0 1 5 2 2 5 1 0 0 6 1 1 1 1 6 0 1 1 1 1 1 1 1 1 1 011 1 011 1 1 0000 1 1 1 1 1 1 0000 0001 011 011 0001 011 0010 0101 0101 0010 011 011 0101 0100 0011 0101 011 011 0101 0011 0100 0101 011 011 0010 0101 0101 0010 011 0001 011 1 1 011 1 011 1 011 0001 1 1 7 0 0 0 0 0 0 7 0000 50 . In total. the cross mark image can be expressed Then compression ration 168/192=87. Shows more details of the pixel number and its Huffman code of the cross mark.The table 4 shows an example to apply the Huffman code to this image.5%. in Most 168 frequently bits. Pixel Number Frequency Huffman Code Code length 0 (white) 1 2 3 4 5 6 7 (black) 24 16 8 2 2 4 4 4 1 011 0101 0100 0011 0010 0001 0000 1 3 4 4 4 4 4 4 Total bits 24 48 32 8 8 16 16 16 Total 168bit Table 8. appeared the pixel number of 0 is corresponds to the code '1'.

Table 8.2. Pixel Number and Huffman Code of Crossmark 8.2. The Huffman Coding in MP3 In the MP3 encoder at the end of the perceptual coding process, a seco nd c ompre ssion process is ru n. Howe ve r, this second rou nd is not a pe rceptual co ding, but rathe r a more traditional compression of all the bits in the file, taken together as a wh ole. To use a loose analogy, you might think of this second run, called the " Huffman coding," as being similar to zip or other standard compression mechanisms (in other words, the Huffman run is completely lossless, unlike the perceptual coding techniques). Huffman coding is extremely fast, as it utilizes a look-up table for spotting possible bit substitutions. In other words, it doesn' t ha ve to " figure a nyth in g o ut" in orde r to do its job. The chief benefit of the Huffman compression run is that it compensates for those areas where the perceptual masking is less efficient. For example, a passa ge of music that co ntains man y sounds happening at once (i.e., a “polyphonous" passage) will be nefit grea tly from the maskin g filter. Howe ve r, a musical phrase consisting only of a single, sustained note will not. Howe ve r, th is passa ge can be compressed very efficiently with more tra ditional means, d ue to its high le ve l of red undancy. On a ve ra ge, an a dditio nal 20% of the total file size can be sha ved du ring the Huffman cod in g.

Huffman Decoding in MP3 The great bulk of the work in the MP3 system as a whole is placed on the encoding process. Since one typically plays files more frequently than one encodes them, this makes sense.

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Decoders do not need to store or work with a model of human psychoacoustic principles, nor do they require a bit allocation procedure. All the MP3 player has to worry about is examining the bitstream of header and data frames for spectral components and the is side information but an stored (often) alongside fancy them, and onto then your reconstructing this information to create an audio signal. The pla ye r nothing interface collection of MP3 files and playlists and your sound card, encapsulating the relatively straightforwa rd rules of decoding the MP3 bitstream format. While there are measurable differences in the efficiencyand audible differences in the quality-of various MP3 decoders, the differences are largely negligible on computer hardware manufactured in the last few years. That's not to say that decoders just sit in the background consuming no resources. In fact, on some machines and some operating systems you'll notice a slight (or even pronounced) sluggishness in other operations while your player is running. This is particularly true on operating systems that don't feature a finely grained threading m odel, such a s Mac OS and most ve rs ions of Wi nd ows. Li nu x and, to an even greater extent, BeOS are largely exempt from MP3 skipping problems, given decent hardware. And of course, if yo u're liste ning to M P3 a udio streamed o ve r the Inte rnet, you'll get skipping problems if you don't have enough bandwidth to handle the bitrate/sampling frequency of the stream. Some MP3 decoders chew up more CPU time than others, but the differences between them in terms of efficiency is not as great as the differences between their feature sets, or between the efficienc y of va riou s encode rs. Cho osing an MP3 pla ye r becomes a que stion of cost, extensibility, au dio quality, and appearance.

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CONCLUSION We have presented a novel method for Huffman decoding using FPGA. The system can be used directly as the final stage for Multimedia decoders like JPEG, MPEG. This method uses a serial input method of input with a look up table approach for decoding. This is a better option compared to the parallel approach to Huffman decoding which is used in present system of Huffman decoding which when implemented on an FPGA uses more number of flip-flops and computational power. Though the system presented above uses more time then the parallel approach for decoding, it will not be a constraint in the present scenario because modern FPGA’s uses much faster clock timing. The coding was done in Verilog hardware description language instead of the standard VHDL used in the present system which is complex than Verilog. The advantages of the above system on FPGA are that Reprogrammable, quickly debuggable, less power and space requirements on the FPGA chip. The look-up table method is the most common and the most widely accepted method for Huffman decoder than the other systems available for decoding. Thus the proposed system lays minimal strain on the FPGA and extracts maximum output for the given input.

APPENDIX Look up table for English alphabets: A 1101 B 001101 C 01100 D 0010 E 101 F 111100 G 001110 H 0100 I 1000

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reg [8:1] tout. // declaring huffman module input clk.clk).J 11111100 K 11111101 L 01111 M 01101 N 1100 O 1110 P 111101 Q 111111100 R 1001 S 0101 T 000 U 01110 V 001100 W 001111 X 111111101 Y 111110 Z 11111111 Source code for Huffman decoder: module huffmanmod(out.in.in. integer i=0.ou tp ut and the type wire [8:1] out. reg [9:1] bitshift. output out. //initializing design initial begin 54 . //declarin g in put.

bitshift = 9'b0. $di spla y(" the outpu t is %d Q" . i=i+1. tout=8'b0. i=0.tout ).in}. end 9'b111111101: begin tout=8'b00011000. end endcase 55 . end always @(posedge clk) begin //shifting the bits bitshift = {bitshift[8:1].//making all registers 0 bitshift=9'b0. bitshift = 9'b0. $displa y(" the output is %d X" .tout). i=0. if (i == 9) casex(bitshift) 9'b111111100: begin tout=8'b00010001.

t o u t ) . i=0. $display(" the output is %d J". bitshift = 9'b0. 56 .else if (i == 8) casex(bitshift) 9'b?11111111: begin tout=8'b00011010. bitshift = 9'b0. end 9'b?11111101: begin tout=8'b00001011. $ d i s p l a y ( " t h e o u t p u t i s % d Z" .tout). i=0. $ d i s p l a y ( " t h e o u t p u t i s % d K" . i=0. bitshift = 9'b0. t o u t ) . end endcase else if (i == 6) casex(bitshift) 9'b??? 001101: begin tout=8'b00000010. end 9'b?11111100: begin tout=8'b00001010.

i=0. $display("the output is %d P".tout). end 9'b??? 001110: begin tout=8'b00000111.bitshift = 9'b0.tout). bitshift = 9'b0. end 9'b??? 111101: begin tout=8'b00010000. $display("the output is %d F". i=0. end 9'b??? 111100: begin tout=8'b00000110. bitshift = 9'b0. $display(" the output is %d B". i=0. bitshift = 9'b0. $displa y(" the output is %d G" . bitshift = 9'b0. i=0.tout). end 9'b??? 001100: begin tout=8'b00010110. 57 .tout).

bitshift = 9'b0. $displa y(" the output is %d W". $displa y(" the output is %d Y" . end 9'b??? 001111: begin tout=8'b00010111. end Endcase else if (i == 5) casex(bitshift) 9'b???? 01100: begin tout=8'b00000011.i=0. i=0. end 9'b???? 01111: 58 .tout). i=0. i=0. $displa y(" the output is %d V" . bitshift = 9'b0.tout). $display(" the output is %d C". bitshift = 9'b0.tout). end 9'b??? 111110: begin tout=8'b00011001.tout).

59 . $ d i s p l a y ( " t h e o u t p u t i s % d L" . bitshift = 9'b0. $display(" the output is %d M" . bitshift = 9'b0. i=0.tout). i=0. i=0. end 9'b???? 01101: begin tout=8'b00001101. bitshift = 9'b0. end endcase else if (i == 4) casex(bitshift) 9'b?????1101: begin tout=8'b00000001. end 9'b???? 01110: begin tout=8'b00010101.tout). $displa y(" the output is %d U" . bitshift = 9'b0. i=0. t o u t ) .begin tout=8'b00001100.

end 9'b?????1100: begin tout=8'b00001110. 60 .tout).tout). bitshift = 9'b0. bitshift = 9'b0. i=0. end 9'b?????0010: begin tout=8'b00000100.tout).tout). $displa y(" the output is %d H" . end 9'b?????0100: begin tout=8'b00001000. $disp la y(" the ou tput is %d I" . i=0.$displa y(" the output is %d A" . bitshift = 9'b0. $displa y(" the output is %d D" . i=0. end 9'b?????1000: begin tout=8'b00001001. bitshift = 9'b0. i=0.

bitshift = 9'b0.tout). $display("the output is %d S".tout). end 9'b?????1001: begin tout=8'b00010010. $displa y(" the output is %d O" .$displa y(" the output is %d N" . end 9'b?????0101: begin tout=8'b00010011. i=0. $display(" the output is %d R". end endcase else if (i == 3) casex(bitshift) 9'b??????101: 61 . bitshift = 9'b0. bitshift = 9'b0. i=0.tout). end 9'b?????1110: begin tout=8'b00001111.tout). i=0.

i=0. bitshift = 9'b0. endmodule module stimulus. bitshift = 9'b0. tout ). end endcase else. always #1 clk = ~clk. initial clk=1'b0. i=0. end //assigning the output to the wire output assign out=tout. wire [8:1] out. $disp la y(" the ou tput is %d T" . 62 . reg in.begin tout=8'b00000101. tout ). $disp la y(" the ou tput is %d E" . end 9'b??????000: begin tout=8'b00010100. //stimulus block reg clk.

#2 in=1'b1. #2 in=1'b0. #2 in=1'b0. 63 //bitstream //bitstream 1110 //bitstream 1100 //bitstream 1000 //bitstream 001110 //bitstream 0010 #2 . #2 in=1'b1. #2 in=1'b0. initial begin #in=1'b1. #2 in=1'b0. #2 in=1'b1. #2 in=1'b1.huffman1 h1(out. in=1'b0. #2 in=1'b0. #2 in=1'b0. #2 in=1'b0. #2 in=1'b1. #2 in=1'b0.clk). #2 in=1'b0. #2 in=1'b1. #2 in=1'b0. #2 in=1'b1. //bitstream 0101 #2 #2 in=1'b1. #2 in=1'b0. #2 in=1'b1. #2 in=1'b0. #2 in=1'b0.in. #2 in=1'b0. #2 in=1'b1. #2 in=1'b0. in=1'b1. 000 #2 in=1'b0. #2 in=1'b1. #2 in=1'b1. #2 in=1'b1.

#2 in=1'b0. #2 in=1'b1. #2 in=1'b0. #2 in=1'b1. #2 in=1'b0. #2 in=1'b0. #2 in=1'b1. #2 in=1'b0.#2 in=1'b0. #2 in=1'b1. #2 in=1'b1. #2 $stop. #2 in=1'b1. #2 in=1'b1. end endmodule Simulation Results //bitstream 000 //bitstream 01110 64 .

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4. “Verilog HDL” Prentice Hall.REFERENCES 1. www. Samir Palnitkar. ISBN 0130449113 5. Zulkalnain Mohd Yusof. Chin-Chen Chang.scholar. Ji-Han Jiang. Universiti Teknologi Malaysia 3. “An Efficient Huffman Decoding Method Based on Pattern Partition and Look-up Table” 2. “Introduction to data compression” by khalid sayood 66 . 2nd Bk&CD edition. Zulfakar Aspar. FPGA design guides from XILINX.com 6. Ishak Suleiman. Published 2003. “Parallel Huffman Decoder with an Optimize Look UP Table Option on FPGA” Faculty of Electrical Engineering.google. and Tung-Shou Chen.