Release Notes

Active-HDL 9.1
Release Notes

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TABLE OF CONTENTS

Table of Contents
What's New in Version 9.1?.......................................................................................................................... 4 Licensing................................................................................................................................................. 4 Compiler and Simulator........................................................................................................................... 6 Debugger............................................................................................................................................... 11 Simulation Database............................................................................................................................. 11 Unified Coverage Database................................................................................................................... 12 Statement/Branch Coverage................................................................................................................. 12 Path Coverage....................................................................................................................................... 13 Integration with Aldec Verification Tools................................................................................................ 13 Libraries................................................................................................................................................. 13 Design Flow Manager............................................................................................................................ 14 Design Browser..................................................................................................................................... 16 Console................................................................................................................................................. 16 HDL Editor............................................................................................................................................. 17 VHDL Code Browser............................................................................................................................. 17 Block Diagram Editor............................................................................................................................. 17 State Diagram Editor............................................................................................................................. 18 Accelerated Waveform Viewer.............................................................................................................. 19 Scripts.................................................................................................................................................... 20 IP Protection.......................................................................................................................................... 23 Active-HDL Interfaces and Wizards....................................................................................................... 24 Installation............................................................................................................................................. 26 Documentation...................................................................................................................................... 26 Others.................................................................................................................................................... 26 Problems Corrected in Version 9.1........................................................................................................ 27

increase design productivity and the speed of behavioral.1. 10/24/2011) Licensing  Active-HDL 9.1.1 provides many new features and enhancements that simplify team-based design. These changes do not take any functionality away from the existing configuration or tool set and they are made in order to improve product launch time and to minimize time of querying the features. The product license file provides configuration information for the features to which you have access. The release notes describe new options and updates available in Active-HDL 9. However. an updated license is required in order to fully utilize Active-HDL 9. The latest version requires a valid maintenance contract as of 9/1/2011. Active-HDL 9.1 (BUILD 2353. and timing simulation of VHDL.1 .4205.Active-HDL™ 9. License Features ASDB to CTF Conversion ASDB to CTV Conversion ASDB to LST Conversion ASDB to Macro Conversion ASDB to SES Conversion ASDB to TSSI Conversion ASDB to VCD Conversion BDE I/O Port Conversion Functions Changes Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into BDE 4 of 32 Active-HDL 9. For more information refer to the License Maintenance section of the Licensing chapter. refer to ActiveHDL Configurations for more information about available product configurations. RTL.1 requires validation of your existing maintenance contract. Verilog®. SystemC™.1? The following is a brief overview of new features and changes introduced to Active-HDL 9. Please. SystemVerilog and EDIF projects.1 is offered in an FPGA vendor-independent edition and supports all leading C/HDL synthesis and implementation tools which can be started directly from the Active-HDL environment. The installation program automatically installs all system libraries and allows selecting both target FPGA technology and vendor-specific libraries required for running HDL simulation. What's New in Version 9.  Changes to the licensing features have been introduced. Not all features and enhancement described are available in every product configuration or OEM edition.

1 5 of 32 .Follow Object Handel-C Code Debug Handel-C Co-simulation Verilog Handel-C Co-simulation VHDL HDE User Actions Player HDE User Actions Recorder Verilog-HDE VHDL-HDE OVA File Support PSL File Support Import Actel Coreconsole design Import Altera Quartus projects Import Altera SOPC Simulation Script Import Mentor Modelsim Project Import Synplify/Synplify Pro Project Import Viewlogic Project Import Xilinx EDK Simulation Script Import Xilinx ISE Project State Diagram Multi-Process VHDL Generator Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into Design Entry Merged into new Import 3rd Party Tools Merged into new Import 3rd Party Tools Merged into new Import 3rd Party Tools Merged into new Import 3rd Party Tools Merged into new Import 3rd Party Tools Merged into new Import 3rd Party Tools Merged into new Import 3rd Party Tools Merged into new Import 3rd Party Tools Merged into FSM Active-HDL 9.

can be determined by using the new checklicense macro command. 11. refer to the Using 6 of 32 Active-HDL 9. For more information.9. Compiler and Simulator NOTE: Due to internal changes in the compiler and simulator as well as updates in third-party tool libraries.ability to simulate Altera Verilog IP with a VHDL only License (Optional license feature) TCL Scripting Verilog RTL & Gate Performance Optimization Unified Coverage Database (ACDB) Altera (Simulator Verilog IP with VHDL Simulator only license)  Active-HDL requires FlexNet ver. If you update Active-HDL to version 9. e.1 .) An advantage of this solution is the unification in notation of the hierarchical names and the removal of ambiguities that could appear when using multiple top-level units during simulation.1 and do not re-compile your design libraries. (Previously.Import 3rd Party Tools New Feature in 9. Recompile all library units. all user-defined libraries should be re-compiled after the installation of Active-HDL 9. all absolute hierarchical names must begin with the hierarchy separator followed by the name of the top-level unit. the following error message will be displayed in the Console window: # ELBREAD: Warning: Files created by the old version of the compiler found.1 . /testbench/UUT/START. The installation program of version 9.ini file stored in the \Dat subfolder.all Import features are now controlled by one feature (except Xilinx Foundation Import) Merged into Design Entry Merged into Verilog Simulation (Speed depends on configuration) New Feature in 9.1 .ability to us the Unified Code Coverage Database (Configuration dependent) New Feature in 9. (SPT50899)  The license configuration with which VSimSA has been started. Hierarchical Names Specification  The specification of hierarchical path names reported and accepted by the simulation environment has been standardized. To select the license configuration.1. All existing designs will not have any problems associated with re-compiling the libraries.1 delivers and installs only the updated system and vendor-specific libraries that do not require re-compilation after Active-HDL is installed.g. With this release. the highest available licence feature is fetched/used.  The license features selected when starting the VSimSA simulation environment can be specified in the license. When not specified. the name of the top-level unit was omitted.1.ini: default vsimsa feature= The value provided in the configuration file can be either ACTIVEHDL_VSIMSA_EE (Expert Edition EE) or ACTIVEHDL_VSIMSA (Plus Edition PE). for example: default vsimsa feature=ACTIVEHDL_VSIMSA.1 . modify the following line in the license. # ELBREAD: Error: Library '<library_name>' has incompatible format.

Start with type T2 and apply constraints to subsequent dimensions -.). type T is array (integer range <>) of bit_vector. allowing unconstrained elements is a new feature of IEEE Std 1076™-2008.g.An unconstrained array type T1 holding unconstrained bit_vectors. type T2 is array (integer range <>) of T1. This variable is equivalent to the Use hierarchy separator option in the Preferences dialog box. By default.constraints applied to a subtype subtype ST is T(0 to 1)(15 downto 0). for example: -.1 7 of 32 . More complex types can be constrained in stages. This optimization resulted in reduced simulation run times for designs using Altera IP. (SPT48401)  Simulation performance of VHDL designs containing particular uses of the wait until constructs has been improved. Similarly. (SPT49537)  The names of the force and noforce procedures (available in the aldec_tools package of the pre- installed aldec library) have been changed to force_signal and noforce_signal. -.) working in the GUI mode present absolute hierarchical paths as the standardized hierarchical paths. signal s2: ST.) All objects of type T must be eventually constrained. Note that the declaration provides constraints neither for array dimensions nor the element type. subtype ST2 is T2(1 to 2). (SPT60751)  Support for VHDL 2008 (IEEE Std 1076™-2008) has been continuously extended.  All the debugging tools (e.until a fully constrained subtype ST4 is received. for example: -. type T1 is array (integer range <>.Active-HDL | Hierarchical Names topic of the Active-HDL help.  The character used for separating the hierarchy levels in hierarchical paths can be changed by using the new $hierarchyseparator predefined variable. Constraints can be applied either in an object declaration or in a declaration of a subtype of type T. etc.An unconstrained array type holding unconstrained elements of type T1. the hierarchical paths returned by the simulator begin with the hierarchy separator followed by the name of the top-level unit. Some macros or HDL code using ambiguous hierarchical names for single top-level module simulations may require an update. The use of the relative hierarchical names with a reference to the design region defined by using the env command remains unchanged. HDL Editor. Memory Viewer.constraints applied at object declaration signal s1 : T(0 to 1)(15 downto 0). -. the slash character is used as the hierarchy separator. (Unconstrained array dimensions were allowed by earlier VHDL versions. Waveform Viewer. Active-HDL 9. VHDL Compilation and Simulation  Simulation of concatenation expressions has been optimized. -. Watch. The change has been introduced as force is the reserved keyword of IEEE Std 1076™-2008. Advanced Dataflow. integer range <>) of bit_vector. The following new VHDL 2008 features are supported in this version of Active-HDL:  Arrays of unconstrained elements are supported. respectively. The allowed separators are a slash (/) or a dot (.

constraints must be provided at object declaration. -. Since the elements of the record are not constrained. not just vhdl_cover_off. -. signal s2 : ST3(open)(open)( 7 downto 0 ). the argument that relaxes several LRM requirements) has been extended to allow declaring entity attributes within an 8 of 32 Active-HDL 9. --FOO: vhdl_cover_on A labeled pragma behaves identically to an unlabeled pragma.e. (SPT47326)  All VHDL pragmas can be labeled. type T1_unconst is array (natural range <>. except that it can be disabled at compile time by using the -ignore_pragma <pragma_label> argument of the acom command. a label followed by a colon is placed in front of the pragma (and behind the comment mark): --FOO: vhdl_cover_off report ("VHDL code inside pragmas vhdl_cover_off / vhdl_cover_on.1 . natural range <>) of bit. you could invoke the compiler as follows: acom -ignore_pragma FOO file. (Those pragmas disable compilation of an enclosed block. For example. type REC is record elem1 : T1_unconst. 1 to 2). type T2_unconst is array (character range <>) of T1_unconst.vhd Any pragma can be ignored. signal s1 : ST4. to disable the pragma labeled FOO in the listing above.An unconstrained array type T1_unconst holding unconstrained bits.A record type of unconstrained elements.Subtype ST3 is not fully constrained. For example. -.) (SPT48050)  A record type or a subtype of unconstrained elements is supported. i.An unconstrained array type T2_unconst holding unconstrained elements of type T1_unconst. elem2 : T2_unconst. an object of the REC type must be constrained either in an object declaration or in a declaration of a subtype of the REC type. Pragmas are labeled similarly to other statements. subtype ST4 is ST3(open)(open)(7 downto 0).Declare two signals. -. you could label and selectively ignore pragmas vhdl_comp_off and vhdl_comp_on. (SPT50387)  The functionality of the -relax argument of the acom command (i. Note the use of the open keyword to indicate that the dimension has already been constrained. so the missing -. end record."). -.e.subtype ST3 is ST2(open)(1 to 2.

you will have to either: . For example. SystemVerilog Compilation and Simulation (Design Constructs Only)  The automatic variables can be referenced by predefined or user-defined PLI tasks and functions.a queue part-selection cannot be passed as an argument to a system task. The latter option will work only if constructs outside the scope of IEEE Std 1364-1995 are not used.  Assigning fixed-size arrays to dynamic arrays or queues and vice-versa is supported for one- dimensional arrays.  Dynamic arrays of events are supported. Previously. (SPT47858)  Declarations of interfaces can be nested inside modules. event merging was supported only for events that were declared as dynamic class members. instance. such as the $display task.e. (SPT50706)  Parameterized virtual interfaces and parameterized classes containing those interfaces as their protected members can be compiled separately.  Events can be passed as task arguments. or . or '%s' is a Verilog 2001 keyword If your Verilog code happens to use the above mentioned keywords. One limitation applies . The actual error message depends on the context where the keyword is used. the compiler conforms by default to IEEE Std 1364™-2005. Now. If used in source code. use.  Struct literals containing keys are supported.y:3}. the following assignment to the s structure with two integer fields named x and y is now possible: s = '{x:2. (SPT48434)  Virtual interfaces can be declared within the compilation-unit scope.run compilation in the Verilog'95 mode. In this case.e. (SPT60377)  Constant references are now supported. Previously. the keywords will trigger an error (except for the Verilog'95 mode) because Active-HDL does not yet support Verilog configurations. In the previous version of Active-HDL.  The Verilog compiler recognizes the following keywords in all working modes (except for Verilog'95. the wildcard index was emulated by using the reg[511:0] type.architecture of that entity. it will cease to compile. In the previous versions. (SPT47049)  The wildcard index type (*) for associated arrays is fully supported. only the static variables could be passed as arguments for these subroutines. This functionality is required for compiling some models from selected vendor libraries.  Part selections are available for queues. i.  Event merging is fully supported.: Verilog configurations are not supported yet. and liblist. i. Active-HDL 9.change the identifier names and recompile. the compilation mode set with -v95 argument of the alog command or the equivalent GUI option): config. only a literal without keys (s = '{2. (SPT48955)  Events can be passed by reference. design.) could be used.3}. cell. endconfig.1 9 of 32 . Library refreshing will not be possible either. (SPT49762) Verilog Compilation and Simulation  The default standard for compilation started from the GUI has been changed.

removal_limit. (SPT47170)  Using the non-compile-time constants. [tcheck_cond].  The %p format for the $display and $write families of tasks can be used with an optional 0 field. in such cases compilation was stopped.  Parameters can now be defined to be of type string. that is. hndl). Double-clicking this message opens the source file in the referenced location. (SPT49568)  Error reporting in case of encountering duplicate declarations in Verilog/SystemVerilog source files was improved. 0}}. 0. [notifier]."  The $recovery system timing check can be used according to the syntax similar to $recrem: $recovery(reference_event. Queues of strings are now supported. baz:'{0. 0}}. c2:'{foo:0. The syntax described in the IEEE Std 1800™-2009 standard. constant. the compiler reports an appropriate warning and continues the compilation. null}  Function and task prototypes are now accepted in modports. This feature is especially useful when the design resources are stored across multiple directories.  Multidimensional packed arrays being elements of packed structures are supported. SPT18965.UUT' cannot be found. [delayed_clk]. for example: int i = 3. 0. c1:'{foo:0. e. In case an infinite inclusion occurs. SPT19609. This field indicates that nested properties should not be printed recursively. the user can identify the source of the problem by referring to the warning message.  The compilation time warning message "Bind target tb. for example: $display ("%0p". It is an out-of-standard extension which was implemented to improve user convenience. Connection rules will be checked during elaboration. SPT49444. 0.UUT has not been found. SPT46003. the above operation would trigger a syntax error. In case a circular inclusion is detected. Previously. baz:'{0. parameter. [tstamp_cond]. (SPT17331. data_event. // str = "rep rep rep " In previous versions of the compiler. If the hndl class handle contains properties that are themselves class instances. Along with an error message. <class handle>. SPT50787)  Non-constant expressions are allowed as the multiplier operands in a string replication operation. (String constants had to be used as a workaround. SPT49623. bar:0.) (SPT46696)  Initialization at declaration for multidimensional packed arrays is supported. without removal_limit argument can also be used: 10 of 32 Active-HDL 9. genvar. SPT48960.1 . SPT48584." which appeared when an undeclared unit was bound to the project using the bind construct was changed to "Bind target 'tb. <class handle>. [delayed_data]). they will be output as <class handle> or null. string str = {i{"rep "}}. recovery_limit. in hierarchical names is now supported. bar:0. (SPT46383)  Circular `include dependency is not considered a compilation error.g. Using blind compilation. A sample output for %p could look as follows: '{i:1. the compiler reports a reference to the previous occurrence of the declaration. 0. such parameters were not supported. c3:null} Using 0 in the format specifier (%0p) would limit the output in the following manner: '{1. Previously.

d. SPT47861) Mixed-Language Compilation and Simulation  The bind SystemVerilog construct is supported and can be used to bind SystemVerilog verification code to VHDL units. The new option facilitates the use of built-in commands and it can predict:  The names of the macro commands  The names of files and folders being arguments of the built-in commands. SPT48860. SPT49076. The above statement will bind the vcheck unit to all instances of the flp entity. manipulated.1 11 of 32 .uut VHDL instance. SPT47127. When binding to an entity. or change conditions that trigger the breakpoint. Pressing the Tab key in the VSimSA Console displays the names of matching items based on their initial letters typed in the command prompt. merged. $asserton. Refer to the Scripts section for additional information. use the entity name (e. q ). (SPT60773)  The $urandom() and the $urandom_range() system functions are supported. e. or acquired from the command line by using the new functionality of the asdbman command. the size of the ASDB file may be reduced by two orders of magnitude. The size reduction depends on the design and the selection of recorded signals. temporarily disable. (SPT15297)  The data layout in the simulation database has been optimized resulting in appreciably smaller ASDB file sizes. version 9. In the new tab. (SPT60502) SystemVerilog Assertions  The $assertkill. The following example shows binding to the top. enable.1 can still load ASDB files recorded by the previous versions of Active-HDL 9. Simulation Database  Simulation databases (*. an optional parameter value assignment. The bind target can be either a VHDL hierarchical name or a VHDL entity. and $assertoff assertion control system tasks are now supported. you can manipulate all the breakpoints set on the cover statements by using the bc macro command. (SPT48610. Syntax of the statement consists of the bind keyword followed by a VHDL target and a SystemVerilog module instantiation. an instance name and a list of port connections. [ notifier ] ]). (SPT46266) Debugger  The Cover Breakpoints tab has been added to the Breakpoints dialog box. in selected usage scenarios. You can expect newly recorded ASDB files to be half the size on the average compared to ASDB files recorded in the previous version of Active-HDL.g. (SPT46060. The module instantiation consists of a module identifier.$recovery ( reference_event . e. d.uut vcheck vcheck_1( clk. (SPT51137) bind top. or remove a breakpoint. data_event . for example: bind flp vcheck vcheck_1( clk. However.g. q ).g. flp) instead of the instance name.asdb) can be created. SPT49077) Batch-mode Compiler and Simulator  The Auto-Complete feature has been implemented in the VSimSA command prompt. timing_check_limit [ . Active-HDL. when only a few signals are recorded.

Unified Coverage Database  The new unified storage format of the coverage database has been introduced . Additionally. SPT46242)  The Subprograms tab has been added to the Code Coverage Viewer. acdb enable. (SPT46241. the debug mode should be enabled during compilation of VHDL and Verilog source files (pass the -dbg argument of the acom and/or alog commands) and then initialize simulation with the -acdb argument of the asim command. if a subprogram is declared in an external library. ACDB can currently store the following coverage types (the support for other coverage types is pending):  Statement Coverage  Branch Coverage The unified format allows exchanging databases with coverage data between Aldec products. older versions of Active-HDL (e. (SPT18514)  Tools for navigating through coverage results in the Code Coverage Viewer were improved.1 . However. its name is not presented. The main new features of the new database are:  Dynamic control of coverage data during simulation with the new acdb clear. etc. if the subprogram resides in the current working library.3). (SPT50527) Statement/Branch Coverage  Generation of text and HTML reports from Statement Coverage statistics has been enhanced to allow excluding covered lines and including the context of not covered lines in the report.3) will not be able to read ASDB files recorded by Active-HDL version 9.Aldec Coverage Database (ACDB). For more information. two buttons are available for 12 of 32 Active-HDL 9. refer to the Coverage Database topic in the on-line documentation. Refer to the Scripts section for additional information.  Possibility to save data of different coverage types to the same database during simulation  Possibility to merge coverage data from multiple simulation runs into a cumulative database (temporal. transferring coverage data from external tools into Aldec simulator. acdb disable.1 or newer. When browsing the results by Expressions. and acdb save commands. acdb off.the software (e. by Active-HDL version 8.g.  The amount of memory allocated by the module recording signals to the simulation database (ASDB) has been reduced. The ACDB database can store coverage data from the entire simulation or it can contain a snapshot made at any moment of the simulation process. spatial. To collect coverage data. viewing. customizing the report process. merging coverage results. Otherwise.g. SPT46190. The browsing buttons available for different types of results depend on the selection made in the Browse By list box. The new tab replaced the Unused subprograms tab and now it presents statistics for two categories of subprograms: subprograms that were executed at least once during simulation ( Used subprograms) and for those that were not executed at all during simulation (Unused subprograms). and generating reports with coverage statistics. version 8. its name is preceded by the name of this library. and heterogeneous use cases)  Generation of HTML reports for advanced analysis of coverage statistics  The C-based API (compliant with Accellera Unified Coverage Interoperability Standard) allows building procedures for coverage analysis.

Additionally. The change introduced to the names of the libraries may affect proper compilation and simulation of older designs migrated to version 9. The change does not apply to the simulation libraries dedicated to the Lattice technology. SPT47726. covered or not covered lines. the Source column of a Path Coverage report contained only a piece of code showing the most nested and explicit expressions while parental conditions were assumed to be met and omitted in the report. may require additional updates. Note that the product-specific files are stored separately. Block. The following Aldec products are supported:  ALINT  Riviera-PRO  Active-HDL VSimSA  Riviera-PRO VSimSA Two modes of operation are available: automatic (based on the options specified in the Design Settings dialog box). SPT47508. SPT47150. libraries specified in the Libraries tab of the Synthesis Options dialog box. four buttons are available for the next or previous. the "_VER" suffix is used. SPT50601. or Statement coverage types. In the current version.1 13 of 32 . or mistakenly removed. the Source column can also contain information about selected or all implicit conditional expressions that form individual program paths. while still sharing the same design resources. SPT48023.browsing to the next/previous line with expression coverage data. SPT47266. Refer to the Scripts section for additional information. Active-HDL 9. Path Coverage  In previous versions. In the previous versions. Designs settings and (re)sources where vendor libraries are specified. etc. for example arguments passed to the alog or asim commands user-defined macros. For more information refer to the Verifying Designs in ALINT and Launching Simulation in RivieraPRO/VSimSA topics of the Active-HDL Product Help (Help | Product Help). SPT60476. The additional lines showing parental conditions are reported if the Nested depth option available in the Expression/Path Coverage category of the Design Settings dialog box is enabled or when the -pac_nested_depth argument of the asim command is passed. automatically generated scripts.1:  All Verilog vendor libraries have been renamed. and manual (all actions are controlled by a custom script). the "OVI_" prefix was used in the names of the libraries. SPT50602. When browsing by Branch.1. Now. SPT60727) Libraries The following general changes have been implemented to the libraries delivered with Active-HDL 9. Integration with Aldec Verification Tools  Active-HDL offers a new feature that enables projects to be moved from Active-HDL to other Aldec products (ALINT and Riviera-PRO). (SPT47012. the options in the File Properties (Compile tab) or Design Settings (Verilog Compilation/Simulation categories) dialog boxes. This allows switching between Aldec products dedicated for different design stages. The interface can launch your designs in those tools based on the options specified in Active-HDL. source code presented in that column is formatted and the line indentation corresponds to nesting levels of the conditional expressions in original VHDL source code. which protects them from being overwritten.

Lattice Synthesis & Implementation in Diamond 1.1 . Lattice Diamond LSE 1. Lattice Diamond 1.1 4. Mentor Graphics® Precision RTL 2011a. Version 2. Verification Libraries 1. The ieee_proposed library has been updated to the latest version (released in September 2010). Lattice® Diamond LSE 1. MAXV_VER) 2. OVI_POWR)  Updated Libraries System Libraries 1. you will be asked to register if you have not already.1. refer to the Vendor-Specific Libraries chapter. OVI_MACHXO2. (SPT48790) HDL Synthesis 1.2  New Schematic Libraries Implementation 1.aldec.2 (ARTIX7.09 Implementation 1. For detailed information on resolved issues. Please note. POWR.0 Synthesis & Implementation 3. 2. ARRIAIIGZ_HSSI_VER. ALTERA_LNSIM_VER. ARRIAIIGZ_PCIE_HIP_VER. see the documentation provided by the OVL team and available in $aldec/vlib/ovl/std_ovl/docs. For the complete list of all the pre-compiled vendor libraries delivered with Active-HDL 9.1 (SPT49380. Altera Quartus® II 11.3 (MACHXO2. ARRIAIIGZ_VER. QuickLogic® QuickWorks™ 2010.5. Altera Quartus® II 10. Lattice Diamond 1. Accellera's Open Verification Library (OVL) delivered with Active-HDL ( $aldec/vlib/ovl) has been upgraded to version 2.0 SP1 (ALTERA_LNSIM. Xilinx ISE™ 13.4.1 SP3 2. Actel® Designer 9. Synopsys® FPGA Synthesis F-2011. KINTEX7. Xilinx ISE 13. For additional information about availability of discontinued libraries. VIRTEX7) NOTES: 1.1 Synthesis & Implementation 2. SPT49634. ARRIAIIGZ_HSSI.com/ContactSupport/. ARRIAIIGZ. ARRIAIIGZ_PCIE_HIP. please contact Aldec Technical Support at http://support. MAXV. Lattice Diamond LSE 1.1 4. Altera Quartus II 11.The following updates have been introduced to the system and vendor-specific libraries:  New Simulation Libraries Implementation 1.3 3. Design Flow Manager  New Flowcharts HDL Synthesis 1. SPT49713) 14 of 32 Active-HDL 9. 61 2.3 6.2 5.5 is a bug-fixing release.

1 (supports Quartus II 10.09 for Actel (supports Synplify Pro E-2010.0 SP1) 3.1 SPA.7.1 (supports ispLEVER 8. Xilinx ISE/WebPack 13.2  Updated Flowcharts HDL Synthesis 1.228.1 SP1) 3.1 SP1A. Xilinx® ISE/WebPack 12.1 (supports Designer 9.254OEM for Actel.03 (supports FPGA Synthesis E-2011.1 4.09 (supports FPGA Synthesis E-2010.2 8. Lattice Synthesis & Implementation in Diamond 1. Designer 9.03A) 17. Xilinx PlanAhead 12.1 SP1) 10.0 (supports Quartus II 11. Actel Designer 9. Xilinx PlanAhead 13.254OEM for QuickLogic) Implementation 1. Mentor Graphics® LeonardoSpectrum 2010 (supports LeonardoSpectrum 2010a) 11.1 SP3) 2. Lattice Synthesis & Implementation in Diamond 1.3 XST VHDL/Verilog 21.09 for Lattice (supports Synplify Pro E-2010. Xilinx ISE/WebPack 12. Precision RTL 2010a Update2. Actel Designer 9. Xilinx PlanAhead 13.3 2. 61) (SPT61384) 12.09 SP2) (SPT50545) 13.03L) 19. Synopsys Synplify Pro D-2010.09) 15. Synopsys® Synplify®/Synplify Pro/Synplify Premier/Premier with Design Planner E-2010. Synopsys Synplify Pro D-2009.4 XST VHDL/Verilog 22.1 10. Lattice Diamond 1. and Precision RTL 2010a Update2.1 15 of 32 . Synopsys Synplify Pro E-2010. Lattice Synthesis & Implementation ispLEVER 8.03L) 20. Xilinx ISE/WebPack 12. Xilinx ISE/WebPack 13.2 Implementation 1.2 (SPT60407) 6. Lattice Diamond 1.0 (supports Actel Designer 9.0 (supports Altera Quartus II 10.03 for Lattice (supports Synplify Pro D-2010. Lattice ispLEVER 8. Synopsys Synplify Pro E-2010.0 SP1) 4.3 9. Designer 9.12 for Lattice (supports Synplify Pro D-2009. Xilinx PlanAhead 12.4 3. Synopsys Synplify/Synplify Pro/Synplify Premier/Premier with Design Planner E-2011. Mentor Graphics Precision RTL 2010 Synthesis (supports Precision RTL 2010.1 SP1) 7.3 8.0 SP3A) 2.03 for Actel (supports Synplify Pro E-2011.1 5.1 SPB. Mentor Graphics Precision RTL 2011 Synthesis (supports Precision RTL 2011a.09L-SP2 and Synplify Pro E-2011. and Designer 9.2 XST VHDL/Verilog Physical Synthesis 1. Altera Quartus II 11.09A-1) 16.4) Active-HDL 9. Xilinx ISE/WebPack 13.09 (supports FPGA Synthesis F-2011. Lattice ispLEVER Classic (supports Lattice ispLEVER Classic 1.1 SP2.3 6. Xilinx ISE/WebPack 13. Synopsys Synplify/Synplify Pro/Synplify Premier/Premier with Design Planner F-2011.1 XST VHDL/Verilog 23.03 SP2) 14.4 9. Xilinx ISE/WebPack 12. Designer 9. Altera Quartus II 10. Designer 9.1 SP1. Synopsys Synplify Pro E-2011. Altera Quartus II 10.12LC-1) 18. Lattice Diamond 1.1 (supports ispLEVER 8.

QuickLogic QuickWorks 2010 (supports QuickWorks 2010. it will be remembered in the subsequent Active-HDL sessions. i.aldec. The support for the *. SPT50743)  The Windows Explorer submenu was added to the context menu of the Files tab.1. The Libraries tab has been added to the Lattice Diamond LSE flowcharts. while compiling sources with the use of the acom or alog commands).e. by selecting the Initialize Simulation command from the Simulation menu is still available. defining file names (e. Once the Make local copy option has been set by the user. SPT49823. NOTE: For additional information about availability of discontinued flowcharts.exe). or specifying message identifiers to the msginfo command. To take advantages of the new functionality. please contact Aldec Technical Support at http://support. If needed. (SPT45203. the Design Flow Manager automatically generates the constraint file. This setting is also included in the export/import of Active-HDL settings performed by the Preferences Manager (prefman. The Lattice Synthesis & Implementation in Diamond 1. By clicking on a file or a folder with the right-mouse button and then selecting the Windows Explorer submenu. (SPT60584) Xilinx flowchart 1.lpf constraint files has been added to the Synthesis & Implementation flowcharts. (SPT61041) 3.com/ContactSupport/. The glbl.1 .1 flowchart has been supplemented with the new Synthesis tool list box on the General tab of the Synthesis and Implementation Options dialog box. you can access the same options that correspond to the selected item and are available in the context menu of Microsoft Windows® Explorer. commands and their parameters in the Console window. The new tool can be run from the PostLayout Tools pop-up window accessible from the Design Flow Manager. changing paths with the use of the cd macro. Initialization of simulation run in two separate steps. The simulation unit(s) can be selected from the expandable file structure or from a list of library units displayed in the Files tab under a library icon.4. (SPT51087) 2. When this type of the flowchart is selected and the file does not exist. The new option allows selecting the default synthesis tool that will be used during synthesis and implementation of a project in the Lattice Diamond environment. The new tab allows specifying additional libraries and HDL files used during design synthesis.g. Please note.  Active-HDL remembers the user's choice entered in the Make local copy check box available in the Add Files to Design dialog box. 16 of 32 Active-HDL 9. (SPT50139. (SPT60187) 2.1)  Flowchart Changes and Improvements Lattice flowchart 1.v file (required during timing simulation started from within the Design Flow Manager) stored in the \$aldec\dat subdirectory has been updated to the version compatible with ISE 13. by selecting the top-level unit(s) and then.4. The new feature facilitates entering paths. The flowchart allows running the IBIS model writer. simply type in the first letters of a command and press the Tab key. Design Browser  Simulation can now be initialized directly from the Files tab of the Design Browser window by selecting a single or multiple design units and selecting the Initialize Simulation command from the context menu. Executing the command for the selected design unit(s) automatically sets the top-level. you will be asked to register if you have not already. All matching commands will pop up and you will be able to select the desired command from the list. you can always redefine your choice in the dialog box. (SPT51124) Console  The Auto-complete functionality has been implemented. first. The Autocomplete feature also aids in choosing command arguments.

(SPT47504. each item added to a block diagram was represented by equivalent HDL code in generated source file.) inserted on a block diagram can be excluded from processing. In the Active-HDL 9. The structure of source code. design units and objects. process/always blocks. The color of the highlighting can be customized in the Appearance category. absolute paths are printed to the Console.SPT50678)  An absolute file path is printed to the Console window when a file attached to the design tree is dragged and then dropped from the Files tab of the Design Browser window. attributes. are presented in the docked Code Browser window in the form of an expandable list. manual selection of a word or a portion of text causes other occurrences of this selection to be highlighted. (SPT47405. suggestions. data types. Block Diagram Editor  The terminals can be aligned. e. (SPT45853)  Instances of design units and special text blocks (e. declared libraries. etc. By default.1 17 of 32 . packages. process/always blocks. SPT49501) VHDL Code Browser  Active-HDL introduces a new tool dedicated to analysis of VHDL source code edited in the HDL Editor window. otherwise a relative path is printed. When it is enabled. The default zoom can be restored by holding the Ctrl key and clicking the mouse-wheel or the Zoom to Original Size toolbar button.g. statements. etc. Previously. (SPT61521)  File path information printed to the Console can be controlled with the use of the new Use absolute paths in messages option available in the Preferences dialog box. or issues encountered while analyzing VHDL code can be sent to Aldec Technical Support.g. Each item displayed in this window represents a corresponding VHDL construct. relative paths are printed to the Console. The Code Browser delivered with Active-HDL 9.1 is available in a preliminary version and any comments. it is repeated in the same form in a message. symbols. SPT60823)  Error message tooltips can be enabled or disabled by using the Enable message tooltips option in the HDL Editor category of the Preferences dialog box. Clicking an item allows viewing its declaration in the edited source document. Previously. when trying to select one or several lines of code. which might be inconvenient in some cases. and special text block was already available. SPT50018. interface. (SPT51225)  Highlighting of words and user-defined phrases in now possible. When the Enable phrases highlighting option is enabled in the HDL Editor category of the Preferences dialog box. the file path information depends on how the files were compiled: if the absolute path was used during compilation. This option can also be set by setting the $absolutepaths predefined variable. (SPT47503. It allows analyzing a source file before it is compiled to a working library. Note that in the previous versions alignment of fubs. HDL Editor  The view in the HDL Editor window can be zoomed in or out by using the Ctrl key and the mouse- wheel or the Zoom In and Zoom Out toolbar buttons. The viewer is integrated with the built-in editor and follows changes introduced to a source file during design development. SPT60822)  Breakpoints are toggled by double-clicking on the margin of the HDL Editor window. signal assignments. Otherwise. breakpoints were toggled by a single click.

wires.  Transcription of state machine ports and parameters into Verilog code can be performed in accordance to the IEEE Std 1364-1995 or IEEE Std 1364-2001 standard.) with the active view of the Accelerated Waveform Viewer and observe the history of values for the objects selected on a block diagram. (SPT48836)  The range attribute of arrays can be used for specifying the generate parameter in VHDL Generate For blocks.current version. or collecting coverage data. Note that using the Generate For blocks allows matching the generated instance names with indices of connected port slices. In the previous versions. the framework is split horizontally and the highlighted diagram objects and corresponding waveform signals are presented in separate views. SPT49060)  The new Synchronize with Waveform option has been implemented. Clock Enable. clicking the right-mouse button started a process of drawing a fub. When the synchronization is turned on. such ports could be transcribed in accordance to the IEEE Std 1364-1995 standard only. (SPT48827)  An action of the right-mouse button can be customized in the Preferences dialog box. ports of fubs and symbols. The synchronization between the Block Diagram Editor and the Accelerated Waveform Viewer can be turned on/off from the BDE Edit toolbar. This can be realized with the improved Port Properties dialog box.) Such declared signals can then be assigned their special function in the Machine Properties dialog box. (In case of the Reset signal. (SPT48998)  The rules of preserving the letter case for VHDL identifiers have been improved. and Reset text boxes. or the States tab of the View/Sort Objects window. SPT49420. and record types in VHDL) can be assigned a special purpose. For example.csv) with state encoding data by using the Save/Load FSM Encoding options from the FSM menu. synthesis. When the option is enabled. the options available in the tab were rearranged for better visibility and accessibility. The text box has replaced a pop-up window that was available under the Advanced button. Extended identifiers. this can also be a range of bits. i. Clock Enable. (SPT48043) 18 of 32 Active-HDL 9. the following declaration of the Generate For block is supported: g0: for i in Bus'range generate. it is possible to synchronize the view in the Block Diagram Editor window showing highlighted diagram objects (terminals. (SPT46883. The options that allow you select the type of pragma or block generation of a portion of source code are available in the Exclude submenu of the context menu of a block diagram item. identifiers surrounded with backslashes. Along with this change. Previously. or Reset. are created only in those cases where it is necessary to distinguish between Verilog objects instantiated in VHDL code whose names differ with letter case only. You can specify a text file (*.e. you can decide whether generated HDL code will include additional pragmas preventing a portion of HDL code from compilation. (SPT45900) State Diagram Editor  Encoding of a state machine can be saved to or loaded from a file. Since the current version. (SPT44990. the Save/Load buttons in the General tab of the Machine Properties dialog box. buses. Clock. etc. the setting of the Right-click action option in the Block Diagram Editor category allows selecting between drawing a fub and panning a block diagram.e. i. which allows using the dotted and indexed notation in the Clock. (SPT45846)  Particular bits selected from complex type ports (including vector types in VHDL and Verilog.1 . An individual block diagram sheet is synchronized with a corresponding waveform document. It is also possible to omit the selected design objects during generation of HDL code. SPT50549)  The Custom text box was introduced to the Reset tab of the Machine Properties dialog box.

When a Standard Waveform Viewer file (*. The sets can be freely modified.  The stimulators can be saved to a file and then reused in a subsequent simulation session or another design.if this option is enabled. SPT50029)  The Clicking on the column header sorts signals option has been moved to the Columns tab.e.for AWC files saved with the AWC save format allows using AWC with any ASDB option enabled. they can be created from scratch. in the Binary point spin box of the Signal Properties dialog box.awf) containing stimulators is used. By default. (SPT47907. the binary point is located to the right of the least significant bit. This can be achieved by specifying the position of the binary point in a vector. i. (SPT50028. asking if a copy of the simulation database should be created. this option is disabled to prevent from frequent waveform reloading and decreasing performance of the viewer. The number specified in the Binary point spin box determines the number of least significant bits that will be considered a fractional part of the vector.e. (SPT49716)  Two new options were introduced to the pop-up menu of the waveform objects that allow you to quickly change their representation radix and notation without the need to access the Signal Properties dialog box.  The AWC documents originated from other simulations can be connected to running simulation. stimuli can be imported as a separate set and saved to stimulators. This setting can be restored to its original state in the Waveform Preferences dialog box. the position of the binary point is set to 0. (SPT47035)  The Accelerated Waveform Viewer is able to represent vectors as fixed-point numbers.when enabled.these two options were introduced along with the removal of the Create copy of Simulation Database option from the Save as dialog box. i.set with other stimulus definitions. automatically traces relevant signals while opening Waveform Configuration files ( *. This can be accomplished by using the new command Connect To Simulator that automatically traces all relevant signals and links the AWC file to the current simulation database.set file created in a design directory ($dsn). Stimulators are defined and grouped in sets. previously added signals are not removed from the Accelerated Waveform Viewer at the initialization of simulation. or if the AWC file should be linked to an existing one.awc). Stimuli defined manually in the Stimulators dialog box are saved automatically by Active-HDL to the stimulators.1 19 of 32 . By default. (SPT47907. In the dialog box. you can make your selection a default action to be executed without a prompt. Error reporting has been improved in case when an incorrect generation style is selected for a finite state machine. Instead. i. (SPT47909)  The Create copy of Simulation Database option has been removed from the Save as window. (SPT48255) Accelerated Waveform Viewer  The following new options that improve handling of waveform objects and allow optimizing performance of the Accelerated Waveform Viewer have been added to the Waveform Preferences dialog box:  Preserve signals when simulation is initialized . each set of stimulators can contain unique stimuli definitions applied to user-defined signals (same or different). SPT48367)  Trace signals when loading AWC document .  Do not ask to create a copy of simulation database when saving AWC file and Create a copy of simulation database . the waveform viewer automatically refreshes the view during simulation while zooming or scrolling waveforms. updated or removed. The options are available as the Radix and Notation submenus in which Active-HDL 9. SPT48367)  Reload waveform while zooming and scrolling when simulation is running .e. a dialog box pops up when saving an AWC file for the first time.

row height. (SPT50931)  A signal can be added to the Waveform Viewer multiple times. e. i. SPT48154.g. (SPT61101) Scripts The following changes have been introduced to the Active-HDL macro commands:  The command output redirected to a file. however.  The Value Matching edit box was added to the Compare Selected Signals and Compare Waveforms dialog boxes. their properties are controlled individually. The option corresponds to the new -value_matching argument of the asdbcompare macro command and it allows specifying which signal values will be considered identical in the comparison process. Refer to the Scripts section for additional information.g. (SPT49732)  The support for virtual objects has been enhanced.e. etc.txt. you can type in precisely a new time value to which the cursor will be moved. In this mode.you can select the desired representation format. You can define and assign user-defined aliases to waveform objects by using the Use Alias option in the Signal Properties dialog box or an appropriate command in the Console window. or -2008 arguments multiple times. notation. analog representation. binary point. The only restriction for the options to be available is that only scalar signals of the same type can be members of the virtual objects. SPT48702. The size of the font in the List View has also been increased. -2002. known from the Standard Waveform Viewer and the Memory Viewer. color. order of bits. SPT50598)  Signal aliases have been implemented. (SPT50344)  The -check_sensitivity_list argument of the acom command used to check sensitivity lists of VHDL processes is no longer supported. The following object properties can be changed in the Signal Properties dialog box: radix. It is recommended to use the Aldec ALINT verification tool to verify source code against potential coding errors. (SPT60998) 20 of 32 Active-HDL 9. refer to the Scripts section. do runme. i.do > report. (SPT45262.e. the values should be entered similarly as in the syntax of the asdbcompare command. no longer contains the message prefix defined by the $messageprefix variable (by default. Additionally. in which case they are applied recursively through the structure of a selected object.1 .) of the Signal Grid and Waveform View pane have been changed in order to improve legibility of objects names and values. (SPT45803. virtual objects or complex objects coming from source code. This functionality. auto-calculate range. i. allows displaying real values of signals as easy-to-recognize design mnemonics. notation. etc. SPT48146. (SPT22574)  Double-clicking a tooltip displayed in the context menu of the Cursors View pane presenting the position of a timing cursor switches it to the edit mode. e. SPT49439. SPT61050)  The time units displayed in a tooltip of a corresponding active timing cursor can be changed by selecting the desired unit from the Time Unit submenu available in the context menu of the Cursors View pane. SPT49438)  The default display settings (font size. the lower part of the Waveform Viewer window presenting the names of the timing cursors.  The acom command allows specifying the -93.e. For additional information.) but the measurements are always drawn for individually selected signals. Note. SPT46421. thus changing the representation format of all its components. In the new edit box. from-to analog range. (SPT45380. The behavior of members of virtual objects remains unchanged. its value is: #). An additional advantage is that the new options can be applied to objects that contain signals of heterogeneous types. each argument can precede one source file or it can be followed by a number of sources. of a record type. that all instances of the signal share the same properties (radix.

the commands will not report differences between the 0.asdb) but also selected design objects stored in the databases. The arguments allow specifying the kind of ports or signals to be included in the resulting database (-in.asdb) from an existing one by filtering out the specified data (asdbman filter). -f allows defining a text file containing a list of all arguments to pass. The command allows creating a new database file (*. merging several databases into a single file (asdbman merge). and File Properties dialog boxes. -internal. when executed with the argument -value_matching 0=L-:L=0-:-=0L. or acquiring information about an existing database and its content (asdbman info).  The -na argument of the alog command can be assigned a value specifying the types of assertions/covers that will be excluded from processing during compilation and simulation. or printing (aliasprint) the information about aliases. -out. Previously. i. With this argument you can specify which signal values will be considered identical in the comparison process. and -ports). only the 4-state parameter constants could be controlled. The command also allows you to remove previously defined signal aliases. Both the arguments can be passed multiple times in the command line. SPT16370)  The -f <filename> argument has been added to the syntax of the asdbcompare command. L and signal values. It is also possible to compare two objects by using the -signals argument. (SPT50403)  The functionality of the asdbman command has been changed.  The asim command can assign values to 2-state parameter constants in SystemVerilog units. For the additional information. loading from a file (aliasload).  The asdbcompare command allows comparing not only complete simulation database files (*. OVA assertions/covers (-na ova). refer to the Waveform Viewer section. the -na argument could be used to disable all defined assertions/covers. or specifying the list of signals by means of an external file (-signal_list). Previously. The new argument allows assigning an alias to a signal when adding the signal to the waveform viewer.1 21 of 32 . For example. or SystemVerilog assertions/covers (-na sva). With the new commands you can automate the control over signal aliases without the need to use the GUI tools. (SPT60660)  The alias. To assign Active-HDL 9.e. The aliaswave command (or wavealias) allows assigning an alias to a particular signal or to a group of signals in a selected design region. (SPT49045.  Commands for manipulating signal aliases have been implemented. for SystemVerilog. The commands allow creating (aliascreate). SPT50931)  New arguments were added to the syntax of the asdbman filter command. Design Settings. The new functionality of the command allows disabling all (-na all) or selected assertion/cover types.  A new command for controlling signal aliases in the Waveform Viewer has been implemented. (SPT50349)  The -xevd argument has been added to the syntax of the acom and alog commands. saving to a file (aliassave). aliaspar. Instead of passing individual arguments in the command line. -inout. (SPT15692. The new argument allows disabling extended vacuous evaluations for corresponding implication operators. PSL assertions/covers (-na psl). SPT16370)  The -alias argument has been added to the syntax of the add wave macro command. (SPT15692. The objects of the same name in both databases can be specified with the new -signal argument. aliasswitch commands are supported in the Tcl and Compatibility modes. OVA or PSL assertions/covers written as comment in Verilog source code (-na emb). The -f argument of the acom command can now be specified in the command line multiple times. An equivalent for this argument has also been implemented in the GUI.  The asdbcompare and wavecompare macro commands have been supplemented with the -value_matching argument. removing (aliasremove). The corresponding GUI settings are also available in the Preferences.

This has been achieved by introducing the new -unit argument. the Source column in the Path Coverage report will present additional lines of source code showing conditional expressions coming from parent nesting levels that implicitly form a program path. The new commands allow enabling and disabling cover breakpoints.  The averilog command is no longer supported. refer to the Hierarchical Names Specification section. PSL. but also the undocked document windows. The same functionality can also be controlled in the timing cursor context menu. The -sv_root argument defines the location where the simulator should start looking for library files set with the -sv_liblist or -sv_lib arguments. Presenting additional code fragments may make path analysis easier especially in case of composite paths formed by nested statements.  The following new commands that allow importing third-party projects or simulation scripts into 22 of 32 Active-HDL 9.1. specify the -g or -G arguments in the syntax of this command.  The awfhierarchy command has been implemented.the values. The arguments control collecting the coverage data to the ACDB database. For additional information. -acdb_cov. (SPT50421)  Three arguments were added to the syntax of the asim command: -acdb.  The close and closedocument commands used with the -all argument close not only the windows docked in the application framework. and -acdb_file. which facilitates identifying the source of the problem. The new command allows updating hierarchical paths of objects stored in the Standard Waveform Viewer files coming from previous versions and used in Active-HDL 9. (SPT50744)  The -strobe_time argument has been added to the syntax of the expwave command. The former allows setting breakpoints on OVA. and SystemVerilog covers while the latter deletes breakpoints previously set by using the bc command.bde or *.  The -sv_liblist and the -sv_root arguments have been implemented in the syntax of the asim command. The new argument is available in the Advanced mode.  The bc and bcd commands have been added. opened from Active-HDL. (SPT50511)  The measurement command has been enhanced. When the new argument is used.1 .  Contents of the error message returned by the env command in case of receiving an incorrect hierarchical path were refined. it allows displaying not only statistics for measurements inserted to the Accelerated Waveform Viewer window (measurement print) but also inserting and deleting measurements (measurement set and measurement delete). -sv_liblist specifies a location of a file that contains a list of DPI libraries to be loaded by the simulator. (SPT60103)  The cursor command allows controlling the time unit with which the timing cursors are displayed in the Accelerated Waveform Viewer. The argument allows specifying time intervals between subsequent dumps of signal values stored in the Standard Waveform File (*. The command allows checking not only if a file exists in the specified location (exist -file) but additionally if a variable is defined (exist -var).asf) to the $dsn\Compile subfolder of an active design. Now.awf). The improved message contains path information.  The bde2code and fsm2code commands have been implemented. (SPT60521)  The exist command has been enhanced. see the Accelerated Waveform Viewer section for details. The commands are equivalent to the Generate HDL Code option from the Diagram or FSM menu and they can be used to generate HDL code from a block or state diagram file (*. (SPT22574)  The enablebc and disablebc commands have been introduced.  The -pac_nested_depth argument has been added to the syntax of the asim command.

importsopc. however. The following changes have been introduced to the predefined Active-HDL variables:  The $exitonerror variable is supported. Previously. e. IP Protection  The vencrypt utility has been deprecated and removed from the default installation of Active-HDL. Setting the variable to 1 is useful in command-line processing when failed macros should not block execution of remaining scripts. During such operations less memory is allocated and the execution is faster than in the previous release.Active-HDL have been implemented: importcoreconsole. asim. wave -varray "REM" /testbench/SYS_CLK_G/TR(2:1)(3:4) Previously. alog. importqsys. All the commands are equivalent to the respective import options available in the File | Import menu. (SPT60312)  The scripterconf command allows resetting the environment of the command interpreter in the selected working mode. the compiler (alog) Active-HDL 9.  The onerror command is now supported in the Tcl and Compatibility modes. a virtual group for the TR multidimensional array can be created by using the wave command: type arr is array (1 to 5) of integer.  The vsimsado macro command was updated so that the scripts converted by the command were compatible with the most recent versions of Riviera-PRO. it makes Active- HDL exit when a macro specified as a command line argument fails. The variable influences the execution of DO macro commands in the Tcl/Compatibility mode or Tcl scripts containing the acom. buildc.  The new $tclerrornotboolean predefined variable has been added. A slice can be selected from arrays of any dimensions. the use of the -reset argument caused that the default environment and interpreter settings were set simultaneously in all the working modes. or edfcomp commands. and importsynplify. Otherwise. (SPT49739)  The performance of adding multiple objects to the Waveform Viewer by using the wave -rec * syntax has been improved. type multiarr is array (1 to 3) of arr. For example. (SPT46257)  The vencrypt command is no longer supported. only in the Tcl mode.1 23 of 32 . The current syntax of the command is as follows: scripterconf [-reset] [-do | -tcl | -msim] (SPT50448)  The transcript command is synchronized with the Command transcript on option in the Console category of the Preferences dialog box.g. variable TR : multiarr.  The quietly command is ignored in the Tcl and Compatibility modes. When the variable is set to 0 (or is not specified yet). Note. the command returns the execution status (0 when failed and 1 if succeeded) but a macro/script is not terminated. (SPT47570)  The wave command can be used to add signal slices to the Accelerated Waveform Viewer. the macro execution is terminated with an error or the error can be handled with the use of the onerror or catch commands. importquartus. that this change influences the order in which signals are added to the waveform. if the variable is set to 1. Although encrypting Verilog source files with vencrypt is no longer possible. a slice could only be used for vectors. importedk. importise.do macro. When it is set to 1 in the startup.

protectip. The new proxy for the SCC interface has been implemented that allows using the recent versions of Perforce. they can be accessed only from the context menu of the MS Windows® Explorer.1 .exe) delivered as part of the IP protection package has been updated to version 1. (SPT48713)  Team Foundation Server 1. The following changes and improvements have been made to the built-in source revision control interface:  Perforce 1. If you require support for older MATLAB version contact Aldec Support.exe). For other possible methods of encryption with the ALDEC public key. (SPT49387) Active-HDL Interfaces and Wizards The following changes and improvements have been made to the built-in Active-HDL DSP interfaces:  Interface to Simulink®/MATLAB® 1. Consequently.  The Xilinx ISE Project option allows importing projects coming from versions 13. Note that Aldec provides another tool for encrypting HDL source files . The following changes and improvements have been made to the import of third-party projects ( File | Import):  Active-HDL allows importing simulation scripts of Altera Qsys. Instead.2 of Xilinx ISE. SPT51072)  TortoiseCVS / TortoiseSVN 1. The Team Foundation Server 2010 source revision control system is supported. The SCC interface for Perforce has been improved and now it can be also used when ActiveHDL is installed on a workstation with 64-bit. (SPT51174) 2. (SPT50336. refer to a technical documentation provided by a vendor of an encryption tool.  The OpenSSL utility ($aldec\bin\openssl.0c. the ALDEC public key (specified in the ActiveHDL documentation) must be inserted into IP source code. version of Windows 7™. The version of P-code used for setup.  The protectip encryption tool is delivered along with the Active-HDL installation as a stand-alone program (protectip. 10. The program allows encrypting source files prepared according to the requirements outlined in the latest revisions of the VHDL and Verilog standards (IEEE Std 1076™2008 and IEEE Std 1364™-2005).  Active-HDL allows compiling source code encrypted by other vendors.1 SP1 and 11. The import process can be initialized by using the new Altera Qsys Simulation Script option.1 and 13. To allow the compiler to decrypt such source files. they cannot be used directly via the built-in Source Revision Control interface of Active-HDL. (SPT49213).pl script that was available on request in the previous versions of ActiveHDL.0.0. To provide access to 24 of 32 Active-HDL 9. MATLAB versions earlier than R2007b are no longer supported by the installation script delivered with Active-HDL.will still be able to compile already encrypted files.  The Altera Quartus II Project option allows importing projects coming from Quartus II ver. Relevant information has been added to the Source Revision Control topic of the Active-HDL Help | ActiveHDL Tools chapter in the on-line documentation. prior to the encryption.p installation script in the MATLAB environment was upgraded to version R2007b as the previous format was announced obsolete in R2010b and will not be supported in future MATLAB versions. Since the TortoiseCVS and TortoiseSVN applications do not provide the SCC API. The executable file stored in the $aldec\bin subdirectory has replaced the protectip.

(SPT50745) The following changes and improvements have been made to the built-in Active-HDL simulation interfaces:  VHPI Interface 1.. Then. refer to the Design Browser section. int low = svLow(hnd. 1).1 25 of 32 . 1). for example. 3. You can define your own templates for headers and footers in which you can use predefined or custom variables that will be translated to appropriate portions of a text at the moment of rendering the PDF document. For additional information. task t1. Note that an exported task can use event control statements allowing you to synchronize execution of C/C++ code with events in a simulated model. for example: import "DPI-C" task put_array(inout int open_arr[]). int a[15:8]. it could be an array declared as: int a[100]. int high = svHigh(hnd. int a[0:7]. Having prepared the template files for headers Active-HDL 9. 1). A number of functions is available to query the array. The vhpiLanguageP property (an extension to the IEEE Std 1076-2008 standard) has been implemented in the VHPI interface. For a complete list of functions. 1). int right = svRight(hnd. Open arrays can be used as formal arguments of imported tasks and functions. 1). 1). the time in the simulator will have advanced by 100 time units. The actual argument for such task or function can be an array with arbitrary dimensions.h header file. The header contains a brief description of each function. By the time the task completes and control returns to C/C++. Exported DPI tasks consuming time are now supported. endtask The task can be then called from C/C++ source code.these tools directly from Active-HDL. On the C/C++ side. int inc = svIncrement(hnd. etc.. This property allows identifying the source language of an object whose handle was passed as an argument to the vhpi_get function.  DPI Interface 1. int length = svLength(hnd. This option provides the list of commands that are available in the context menu of the MS Windows Explorer. DPI open arrays are supported. in the new Headers and Footers category. you can specify different headers and footers for different sections of the PDF documentation. 2. int size = svSize(hnd. see the \PLI\Include\svdpi. define the following task: export "DPI-C" task t1. an open array is accessible as a variable of the svOpenArrayHandle type. The following improvements have been made to the Active-HDL wizards:  Export to PDF Wizard 1. the Windows Explorer option has been added to the pop-up menu of the Design Browser."). int dim = svDimensions(hnd).. The SystemVerilog chandle type is supported in the DPI interface. 1). for example: int left = svLeft(hnd. For the put_array task in the listing above. You could. #100 $display ("Task completed. Headers and footers of design documentation can be freely customized.

a message window informing that the file was delivered by a trusted publisher is displayed. SPT49831)  The Tools and External HDL Editors categories of the Preferences dialog box were 26 of 32 Active-HDL 9. Internal links in PDF files generated for the Active-HDL designs or workspaces can be supplemented with additional information that refers you to names and page numbers of topics which they point to. (SPT49745)  The code sign certificate has been implemented.exe file is launched.chm) has been removed from the installation of Active-HDL.wsp) which is stored in the local design directory and excluded from the source control operations. (SPT45849) 2. (SPT15450.ctf).  The descriptions of the Active-HDL and VSimSA macro commands have been merged and now they are available in the Active-HDL Macro Language chapter in the Active-HDL User Guide. etc. Instead.2011. In the Strobe group of options. (SPT49334)  Verilog and VHDL protected source files (*.vp) are recognized within the Active-HDL environment as HDL files rather than external files. you can define the values of a specified signal at which the exported data will be sampled. Previously.  The VSimSA Standalone Simulation Environment Manual ( vsimsa.and footers. The help topics dedicated to the VSimSA environment and the batch mode compilation and simulation have been moved to respective sections of the Using Active-HDL chapter in the Active-HDL User Guide (avhdl. SPT47293)  New Source File Wizard The New Source File Wizard allows specifying signedness of ports of the generated VHDL or Verilog design entities. you can specify the radix and notation for objects exported to a custom text file ( *. This feature also applies to block diagram and state diagram entities targeted to those HDL languages.chm). This solution prevents propagating compilation status information between different machines working on the same design resources. (SPT20008. automatically including them in the design compilation. (SPT48631)  The Print Design Files and Print Workspace options allow printing design files on any of the printers installed to the operating system. (SPT60086) Documentation  The ACDB API Reference Guide has been added to the Active-HDL on-line documentation. By using this feature. you can reuse them in various designs with a few clicks of a mouse button. only the default system printer was available for these options. Others  Compilation status information is no longer stored in the compile.cfg file.vhdp and *.1 . The new reference guide is available in Active-HDL Reference Guides section of the References page. (SPT45850)  Export Waveforms Wizard The Export to CTF page of the Wizard has been refined and supplemented with new options. you will significantly improve legibility of the printed copies of design documentation. Now. This allows verifying whether a copy of Active-HDL has been altered since it was signed by Aldec. (SPT46837) Installation  The installation program of Active-HDL has been upgraded to InstallShield ver. this information is saved to a separate file (*. This change results with highlighting the syntax of such files. When the setup. Inc.

(SPT51156)  The Active-HDL Preferences Manager (prefman. (SPT50793) VHDL Compilation and Simulation  An issue with simulation performance in case when large variables declared inside procedures were used was resolved. SPT50894. (SPT49749)  An issue with continuous assignment inside two mutually exclusive branches of a conditional generate construct was corrected. (SPT60130)  The following defects resulting in occurrence of compiler or simulator errors were fixed: SPT49294. (SPT21050)  A defect in a mechanism that incorrectly resolved hierarchical references to parameters inside generate blocks was fixed.) (SPT60530) Active-HDL 9. the SecureIP license feature was not released after a simulation session was terminated. (SPT51171. SPT61594. SPT60431. In the current version. SPT49762. Now. the VHDL compiler is invoked. the issue is corrected. the Verilog compiler was used to compile PSL files in VHDL projects. (SPT49756)  In the previous versions.exe) supports export/import of settings specified for EDA tools defined in the Integrated Tools category of the Preferences dialog box. This issue was resolved. if.1 27 of 32 . The categories are now called User Tools and File Tools correspondingly and can be found in the Tools section. SPT49765. passing arguments to the standalone VHDL compiler ( vcom.1 Licensing  Previously. SPT51065. SPT60573. Now. SPT61029. (The warning is printed when one of case block conditions may render values that duplicate another condition in the same case block. (SPT49633) Problems Corrected in Version 9. SPT51172)  Contents of the VCP2905 warning message have been refined. the application area of the user-defined tools has been extended. SPT49571.exe) through a text file was not possible. (SPT49629)  The license-related error messages contain information about the design region where unsupported constructs were used. Active-HDL and VSimSA reported an incorrect license error message when a maximum number of users was reached. refer to the Active-HDL Product Help ( Help | Product Help). SPT61423. (SPT49193)  In the previous version. or case generate statements was fixed. SPT60875. SPT61505. the issue is resolved. Verilog/SystemVerilog Compilation and Simulation  An issue causing that wrong simulation results were produced for designs using unnamed generate blocks was resolved. this issue is revised. SPT50635)  Previously. SPT60472.  The Tools | Windows category of the Preferences dialog box was updated: the Accelerated Waveform Viewer option was added and the Waveform Editor option was renamed to Standard Waveform Editor so that the behavior of both windows could be controlled.reorganized. (SPT50252)  An issue that caused an elaboration failure in case of using external names of objects instantiated with for. Now. For more information. SPT51019. (SPT48911. Additionally. SPT60608. (SPT49958)  Incorrect results were returned by the array 'RANGE attribute. SPT50255. SPT50956.

this issue is revised. SPT49657. (SPT61601) HDL Editor  Previously.1 as the implementation tool has been fixed. The problem occurred only if there were many files synthesized as a macro and if the Add sources for hdlMacro components to synthesis option was selected on the Libraries tab of the Synthesis Option dialog box. the issue is revised. This issue is resolved. (SPT49362)  In specific circumstances. SPT51165) Design Flow Manager  An issue with running the Synopsys Synplify Pro D-2010. This issue was corrected.1 . and Impl. VHDL code generated for generic declarations could contain a 28 of 32 Active-HDL 9. (SPT48993)  A defect that caused that preparing files to a synthesis took a very long time in some certain circumstances has been corrected. (SPT51063) SystemC Compilation and Simulation  Previously. SPT50830. SPT49543. (SPT49139)  A defect that caused that an undocked HDL Editor window disappeared from the Windows taskbar when the HDL Editor window was blocked above other windows with the Stay on top option was fixed. Mixed-language Simulation  An issue was resolved that caused that the simulator running in the SLP mode produced incorrect results for a VHDL design instantiating a SecureIP Verilog module. SPT60886. The following defects resulting in occurrence of compiler or simulator errors were fixed: SPT49455. (SPT61774) Block Diagram Editor  An issue with generating VHDL code from block diagrams created in older versions of Active-HDL and containing declarations of generics defined in the special text blocks was revised.  An issue with assigning pins during implementation executed with the use of a Tcl script generated by using the Generate implementation script option in the Altera Quartus II flowcharts was revised. SPT61779. (SPT61619)  An issue causing an application error while adding/removing breakpoints or moving splitters was fixed. breakpoints did not stop simulation if they were set in encrypted source code. (SPT50658)  An issue with displaying the last character of a comment was corrected. SPT51154. Script option of the Synplify D-2010. Now. (SPT51086)  An issue causing an error in the Tcl engine when running a script generated by using the Generate Synth. using the Outdent option in the HDL Editor might result in deleting a line of code. (SPT50780)  An issue preventing to employ the Lattice Diamond LSE 1. when a design path contained a space character. SPT49527. (SPT50926. Now. building SystemC applications resulted in compilation failures.03 flowchart was revised. (SPT48315)  In very specific circumstances.1 implementation tool is selected has been corrected. SPT51027.03 for Lattice flowchart when the Lattice ispLEVER 8. SPT50924. (SPT50628) C/HDL Debugging  In previous versions. the Print Preview option did not preserve the settings for the margin specified in the Page Setup window once a text document was closed and then reopened.

SPT49540. modifying a Simulink model during co-simulation. and later on VHDL code was generated for that fub.  A defect causing a co-simulation interface to Simulink to hang every two simulation runs was revised. (SPT49527)  An issue resulting in occurrence of an error while creating a subsystem library for System Generator was fixed. (SPT47432) Active-HDL Interfaces and Wizards  A defect causing an internal error during conversion of Verilog source code was corrected. State Diagram Editor  Previously. (SPT47438)  An issue with code generation in case when an initial value for a generic contained multiple Don't care (-) characters was resolved. The issue was resolved. (SPT50920)  An issue that prevented from successful co-simulation finish in case of specific diagrams instantiating combinatorial HDL black-boxes was revised. (SPT50526)  Previously.e. the error is changed to a warning and the option inserting a synthesis attribute can be used properly. the State Diagram Editor issued an error reporting too many characters in a line of VHDL source code generated from a state diagram document. first the fub was drawn on the block diagram with such ports. This version of Active-HDL resolves this issue.g. (SPT49483) Accelerated Waveform Viewer  An issue causing an application error while adding signals to the waveform viewer in case a simulation database (*. e. The issue might occur when a top-down design strategy was followed. assigning synthesis attributes to pins or terminals of Verilog modules worked incorrectly.  In the previous versions.redundant semicolon. PORT(INDEX-1:0). (SPT60466)  A defect was fixed that caused that each add list command used after the wave command opened a new list window when the Tcl or the Compatibility mode was in use. e.g. Now. (SPT50217.asdb) was located on a network drive was corrected. This issue was resolved. (SPT51250)  There was an issue resulting with incorrect VHDL code being generated for bus ports whose left- hand or right-hand indices were declared on the block diagram by using a minus (-) operator. (SPT50588)  A defect causing an application error while adding signals to the waveform viewer that was first undocked and then docked was resolved. (SPT61002)  The following defects resulting in occurrence of an application error were fixed: SPT49386. when the ENUM_ENCODING type attributes without text concatenation (VHDL only) option was checked and Xilinx XST was selected in the Code Generation Settings dialog box. The issue was corrected. (SPT61553) Active-HDL 9. Now. the issue is resolved. (SPT50543)  An issue where the Code2Graphics Conversion Wizard did not convert a specific file was resolved. i.1 29 of 32 . (SPT51209)  An issue was corrected that might obstruct opening state diagram files containing embedded bitmap images. by adding an HDL Black-Box or the System Generator Black-Box module to a block diagram might cause the co-simulation interface to be frozen. SPT50418)  Attempts to place SystemC modules from the Symbols Toolbox on a block diagram resulted in application crash.

ASDB: No more events will be recorded. the following error could occur while signals were added to the waveform: ASDB: ASDB server error (Unknown ASDB server error). Now. This issue might occur when the command was called from a script file that was passed as a command line argument to Active-HDL. Now.1 . (SPT60713)  An issue with filtering the results returned by the find command by port directions was fixed. the message is presented correctly. (SPT50984) Console  An issue with the Clear log file option in the Preferences dialog box being ignored was corrected. (SPT49358)  An issue with forcing signals presented in a waveform in case a simulation database was located on a network drive was resolved. (SPT50728. (SPT50581)  Previously. (SPT50433)  An issue with setting an SDF file with the designsdffile command has been resolved. different than the design folder can be chosen. The issue resulted in console log file (console. i. when a simulation database was generated on a network drive.e. by using the msginfo command.log) being cleared. SPT60483) Documentation  The missing description of the `ifdef _VCP compiler directive was added to the Compiler Directives topic of the Active-HDL Help | Using Active-HDL | Compilation | Verilog Compilation chapter in the on-line documentation. ASDB file may be damaged. this issue is resolved. (SPT61637)  An issue with the use of the left/right buttons on mouse-scroll wheel was corrected. user-defined colors assigned to named-row objects were set to defaults when design files were recompiled and a simulation session was restarted. (SPT50902) 30 of 32 Active-HDL 9. Now. (SPT49566) Scripts  The performance of the addfile command has been improved. the issue is corrected. regardless of the setting of this option. The description can also be accessed from the Console. The location other than default.  A defect in the scripterconf command executed from Tcl scripts was revised. (SPT49728)  In previous versions. An issue causing an application error while expanding virtual object containing an array of records was corrected. (SPT50336)  Information about compilation of VHDL files containing embedded PSL code was updated. (SPT49256)  An issue was corrected where the working mode of the command interpreter was not changed when requested by the scripterconf command. the scripterconf command executed from a macro run in the Do mode returned an incorrect message informing about a newly set working mode. (SPT46092)  The list of the Source Revision Control systems supported by Active-HDL was updated in the on- line documentation. (SPT47824)  The description of the VCP2905 warning message was added to the Message Reference Guide. (SPT49256)  An issue with parsing file name arguments enclosed in the quotation marks has been resolved. (SPT49081)  Previously.

(SPT45246)  Compilation of files containing non-printable characters in comments is possible now. This issue was corrected. SPT60992. The issue appeared when the Verilog-like hierarchy separator was selected in the Preferences menu and SLP mode was in use. (SPT50319)  The Serial Receiver sample design and the SystemC Transactor Wizard were refined.1 31 of 32 . (SPT50675)  When a file link was copied between two designs in the same workspace. specific functions in the GUI could be blocked. the copied item contained an incorrect file reference. SPT60993) Active-HDL 9. (SPT50251)  During operation of some Tcl scripts. This issue has been resolved.Others  The problem concerning data loss of internal signals when displaying on waveforms has been fixed. (SPT51197)  An issue with source files being randomly excluded from compilation was resolved. The Using SystemC Transactor Wizard Application Note was updated accordingly. an incorrect message saying that file is empty was issued. Previously. (SPT48870.

Inc. Inc. . NV 89074 Tel: +1 702 990 4400 Toll Free: +1 800 487 8743 Fax: +1 702 990 4414 Active-HDLTM is a trademark of Aldec.NOTES Aldec. Corporate Headquarters 2260 Corporate Circle Henderson. All other trademarks or registered trademarks are property of their respective owners.