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Analog layout design
Kanazawa University Microelectronics Research Lab. Akio Kitagawa
n-well p substrate p-well n substrate n-well p-well
n-well process p-well process Twin-well process
(The impurity concentration is optimized.)
p- or n- substrate n-well p-well n-well p- substrate
(The wells can be electrically isolated each other.)
Deep n-well (Triple-well process)
Triple well process active (MOSFET) n-well deep n-well retrograde p-well active
Twin-well process active (MOSFET) n-well active
p n-well deep n-well p-substrate
Shallow trench isolation (STI)
VDD cannot invert the MOS interface.
FOX: Field Oxide (Thickness = 100nm) GOX: Gate Oxide (Thickness = several nm)
Layout and cross section (Twin well) poly (G) contact S B poly (G) D Contact S D Wn B Wp p-active p-active n-active n-active B S G D contact D Ln Lp B S G D D n-well Field Oxide FOX p+ n+ n+ FOX p-substrate n+ p+ n-well p+ FOX n-ch MOSFET p-ch MOSFET 5 .
Layout and cross section (Triple well) contact poly (G) S B Contact D poly (G) S D Wn B Wp p-active p-active B n-active S G D contact D n-active Ln Lp B S G D D n-well Field Oxide FOX p+ n+ deep n-well n+ FOX p-substrate n+ p+ n-well p+ FOX n-ch MOSFET p-ch MOSFET 6 .
– ex. Via. FOX and GOX is generated from the pattern on the active layer. poly layer Legend of layers n-well n-active (n+) p-active (p+) poly contact metal-1 via-1 metal-2 metal-2 layer via layer metal-1layer contact layer FOX p-active layer n-well layer 7 n+ p-sub poly p+ p+ n-well Layout n-active layer Cross section .Layers • Layer numbers are assigned to Well. Active. Silicide Protect. Poly. Metal. respectively. • Some layer is automatically generated from the pattern on the drawn layer. and Dummy. Contact.
A semiconductor company accepts only the design that is passed the specified design rules. triggering a parasitic pnpn or npnp structure. – Warranty of dimensional precision in micro fabrication – Warranty of precision on electrical characteristics – Prevention of latch-up(NOTE) triggered by parasitic bipolar-transistors • • Design rule violation is automatically detected and reported in DRC (Design Rule Check).Design Rules • • Semiconductor foundry allows the designers to design only the layout pattern on the top view. 8 . NOTE: Latch-up The inadvertent creation of a low-impedance path between the power supply rails of a CMOS circuit. The designers have to design the layout according to design rules which is fixed for each technology. – The thickness of layers are fixed by the semiconductor foundry. The purpose of design rule is as follows.
spacing to well = 2 (inside) min. width = 2 min. spacing to poly = 1 metal-1 rule min. width = 2 min. spacing 2 active (p+. spacing = 2 min. width = 2 min. extension beyond contact = 1 min. extension beyond via-1 = 1 9 . spacing to well = 1 (outside) min.Example of design rules (1) Geometry Rules n-well p-active poly-1 2 2 2 2 1 1 2 2 1 Via-1 2 2 2 1 contact Metal-1 2 poly rule min. n+) rule min.
Example of design rules (2) Minimum Density Rules Fine featured processes utilize CMP (Chemical-Mechanical Polishing) to achieve planarity.. connected to a thin oxide transistor. 10 SG . collect charge from the processing environment (e. Effective CMP requires that the variations in feature density on a layer be restricted.g. SF(poly) SF(M1) ܰ ܵி ܵீ Antenna Rules (Process-Induced Damage Rules) The "Antenna Rules" deal with process induced gate oxide damage caused when exposed poly-silicon and metal structures. reactive ion etch) and develop potentials sufficiently large to cause Fowler Nordheim current to flow through the thin oxide. The rules require that the area of the polysilicon and metal over field oxide divided by the area of the transistor gate (thin oxide area) must be less than Np (where Np is a limit that depends on the process and on design targets).
Verifications of the layout design • DRC (Design Rule Check) – Detection of the design rule violation • ERC (Electrical Rule Check) – Detection of the open/short error • LVS (Layout VS Schematic) – Equivalence checking between layout and schematic The layout design checker has a batch processing mode and interactive mode. 11 .
– The parallel placement of interconnect raise a crosstalk of signals. – The long interconnect acts as a parasitic inductor or LC resonator. especially poly-Si. C. and R can improve the production tolerance and mismatch. • Noise and jitter characteristics – The parasitic resistance. act as a thermal noise source. • Precision of the circuit operation – Common centroid layout of MOSFET. 12 . – Symmetric layout of interconnect can improves the production tolerance and skew of the digital signal (delay) and analog signal (phase lag).Influence on circuit performance of the layout • Frequency response in high-frequency region – The parasitic resistance and the parasitic capacitance raise an unintended pole and zero.
(1) Layout of the MOSFET 13 .
Layout sample of MOSFET n-ch p-ch n-well n-active (n+) p-active (p+) poly contact G G metal-1 via-1 metal-2 S D D S B B 14 .
Parasitic of MOSFET Parasitic Long W LD L LS D G S B G D capacitance Drain junction C j W LD RG R□ W L CgsWL B C j W LS Gate resistance S (R□: sheet Gate-Source capacitance resistance) • Long W: large time constant of gate poly-Si • Long W: large thermal noise of gate poly-Si • Long LD. LS: large parasitic capacitance and resistance of drain/source area • Few number of contact: Shift or fluctuation of substrate potential How can you design the MOSFET with larger W? 15 .
Fingered MOSFET MOFET should be sectioned to reduce the gate resistance. B Multiply = 4 (W/4 ｘ 4) 16 . W/L < 10 is recommended. W/4 High-performance MOSFET array W 1 R□ L gm gm: trans-conductance Finger Abutment G D S g m y21 dI ds dVgs This condition is often met in the case of W/L < 20.
Reduction of the drain junction capacitance (single MOSFET) LD W W/2 D Abutment G S S LD D S W C j LD 2 C DB C jWLD > C DB Cj = Capacitance of drain bottom pn junction per area (F/m2) 17 .
Reduction of the drain junction capacitance (series MOSFET) D LD LD S D S W Abutment SLGmin D D/S S W C p 2C jWLD > C p C jWSLG min 18 Cj = Capacitance of drain bottom pn junction per area (F/m2) SLGmin = minimum gate spacing .
Dummy gate The dummy pattern may be formed to reduce the production tolerance. G D B S Dummy gate Dummy gate 19 .
G D B S 20 .Interdigitated body contact The body/well contact may be added to immobilize the substrate/well potential in the very large MOSFET.
and vertical runs of metal (or poly) are used to input and to output the signals.IN1 IN2 OUT VDD Layout of logic gate • • • High area utilization Constant height of all cell Horizontal runs of metal are used to supply power (Rail). Outline box of the cell poly-1 n+ p+ Contact n-well Metal-1 Metal-2 Via-1 VSS 21 2NAND .
1%) 22 . (around ±1%) – Use of The repeat of warp of the fundamental unit • The devices of the different shape and direction match very poorly.g. – Use of the dummy pattern – Use of the common centroid pattern • Trimming is necessary if you expect more precise matching.(less than ±0. a current mirror). a differential pair.Matching layout • Matching layout is used to enhances the relative precision of device pair (e.
Distribution of GOX thickness Flux of O2 G G Temperature and flow distribution in the oxidation furnace GOX n+ S n+ D FOX GOX n+ S n+ D FOX Distribution of GOX thickness Fluctuation of Vth and Ids several % 23 .
The array should be symmetric around both the x and y-axis. The centroid of the matched devices should coincident. 2.Common centroid layout • The fluctuation of the device characteristics may be canceled using the common centroid. 3. A B B A 4 segments A B B A 4 segments A B B A B A A B 8 segments A B B A B A A B A B B A B A A B 16 segments24 . Each matched device should consist of an equal number of segments oriented in either direction. 1.
Segmentation and Placement for common centroid layout W/2 MOSFET A W Dummy Dummy D Matched devices MOSFET B GA S GB D Dummy Dummy D GB S GA D Distribution of device parameter 25 .
Layout sample of a differential pair VSS D2 D1 D2 VSS Dummy G2 poly-1 n+ p+ Contact S12 Metal-1 Metal-2 Via-1 G1 S12 G2 Dummy D1 G1 VSS D2 G2 S12 26 .
(2) Layout of the passive devices 27 .
05% 0.2 – 2.7 fF/m2 0.4% 0. Poly2/Poly1 Cap. p+ Resister Poly Resistor N-well Resister Values 2.8 – 1.05% 0. Coefficient 50 ppm/V 50 ppm/V 200 ppm/V 200 ppm/V 100 ppm/V 10k ppm/V p+ diff. 28 .4% 1% 50 ppm/℃ 50 ppm/℃ 1500 ppm/℃ 1500 ppm/℃ 1500 ppm/℃ 8000 ppm/℃ Volt.4% 0. Resistor 50 – 80 /□ The mismatch error on a chip is very small. Coefficient 0.0 fF/ m2 80 – 150 /□ 20 – 40 /□ 1 k– 2k /□ Mismatch Temp.Example of the characteristics of the passive device Component MOS Cap.
18m CMOS process) VDD (Shield) Poly-2 Poly-1 N+ VDD (Shield) Metal-x+1 Capacitor Metal Metal-x FOX(SiO2） N-well FOX(SiO2） N+ N-well P-substrate P-substrate Poly Capacitor MIM Capacitor 29 .25m CMOS process) • MIM Capacitor (After 0.Structure of MIM capacitor • Poly Capacitor (Before 0.
if the dummy is not specify.) 30 MIM Capacitor with the dummy CM . The dummy metal may work as a parasitic capacitance.Layout sample of a MIM capacitor Metal-5 ＝ Metal-4 CMIM Cp Dummy CM Device model with parasitic Metal-4 CM Capacitor Metal (CM) Metal-5 VIA4 Dummy (The dummy metal is automatically inserted.
Structure of spiral inductor Metal-4 Top metal Metal-1 Slit (prevent the induction current) Top M4 M1 VSS (Shield) FOX(SiO2) VIA4 CF L RS CF CP Top Metal Device model with the parasitic Top metal or dedicated layer for inductor is used. The inductor is dissipative in the chip area. Substrate Cross section 31 .
Structure of the resistance M1 VDD (Shield) N+ Active Protect P+ N-well P-substrate Active M1 FOX Silicide N+ N-well P-substrate Active FOX VDD (Shield) M1 p+ resistor Poly N+ N-well P-substrate n-well resistor FOX poly resistor 32 .
Layout sample of a poly resistor L (recommended L/W > 5) W RS : Sheet Resistance R RS poly Device model with the parasitic Metal-1 W L Protect (non-silicide area) p-select. n-select or high-resistance 33 .
Common centroid layout of a resistor pair R１ R１ R2 Dummy R2 Metal-1 p+ diffusion Dummy 34 .
(3) Shielding and guard ring 35 .
Flicker noise. 36 . shot noise – The noise floor depends on the circuit design quality • Quantization noise – Noise resulting from the finite digital word size – The SNR (signal-to-noise ratio) depends on the accuracy of ADC and DAC. • Coupled noise (Crosstalk) – Noise resulting from the signals adjacent circuits deeding into each other – The noise immunity depends on a layout.Type of noise • Inherent noise – Noise resulting from the discrete and random movement of charge in a device – Thermal noise.
Type of coupled noise Electromagnetic model • Capacitive coupling • Inductive coupling • Substrate current → → → Circuit model Parasitic capacitance Parasitic inductance Parasitic resistance 37 .
Capacitive coupling Analog circuit Vdig Digital signal Analog signal Vsig Rout Cc Vanalog Cs Analog circuit Vsig 1 SNR j Cc Rout Vdig 38 .
Shielding of interconnects Shielding plate W Digital line 3W GND p-substrate p-substrate Shielding line Signal Analog circuit Digital circuit Analog line analog VSS 39 .
Shielding of substrate Analog signal Digital signal FOX Shield Noise (charge and discharge) n+ Shield n-well p-substrate Cross section 40 Capacitor VDD FOX n+ VDD .
(termination of electric field) Guard ring n-guard ring (absorption of minority carrier) p-guard ring Analog circuit Digital circuit (noise source) analog VSS p-substrate digital VDD digital VSS 41 .
Inductive coupling Analog circuit Magnetic flux S I2(t) I1(t) Digital signal current Current GND I2(t) I1(t) t 42 The induction noise is in proportion to the loop area S of the signal and power line. .
The mirror symmetry intensifies the induced current.Translational symmetric layout (In-phase circuit) ○ magnetic flux Analog circuit Analog circuit magnetic flux × VDD VSS VDD VSS The translational symmetry reduces induced current. 43 .
Vin VDD Adjacent placement VSS Increase the distance Vout Digital Circuit VDD Adjacent placement VSS Analog Circuit 44 .Pin assignment The analog input should be arranged in a perpendicular direction on digital output and the power supply pin.
Bypass capacitors on VDD. 45 . VSS lines p-substrate→VSS VDD The noise in the VDD. Small MOS capacitors under the power line. VSS line is bypassed through the bypass capacitors.
(4) ESD (Electrostatic Discharge) Protection 46 .
VSS Input Pad VDD CMOS Circuit VSS Input Pad VDD FOX FOX p+ n+ p-substrate n-well Schematic Cross section NOTE: If the inductive load is used the output. the amplitude of the output signal is larger than power supply voltage. In this case.Input Pad with ESD protection The ESD protection is required to prevent the damage of the GOX of a MOSFET from the static charge buildup. 47 . the ESD protection diode must be connected tandemly.
Layout sample of pad ESD protection Pad Layer n-well n-active (n+) p-active (p+) poly-1 contact metal-1 via-1 metal-2 VDD VSS Input 48 .
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