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dsPIC30F Programmer’s Reference Manual

High Performance Digital Signal Controllers

 2003 Microchip Technology Inc.

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DS70030E

Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

• •

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPIC, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

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Table of Contents
PAGE
SECTION 1. INTRODUCTION 1-1
Introduction ...................................................................................................................................................... 1-2 Manual Objective ............................................................................................................................................. 1-2 Development Support ...................................................................................................................................... 1-2 Style and Symbol Conventions ........................................................................................................................ 1-3 Instruction Set Symbols ................................................................................................................................... 1-4 Related Documents .......................................................................................................................................... 1-5

SECTION 2. PROGRAMMER’S MODEL

2-1

dsPIC30F Overview ......................................................................................................................................... 2-2 Programmer’s Model ........................................................................................................................................ 2-3

SECTION 3. INSTRUCTION SET OVERVIEW

3-1

Introduction ...................................................................................................................................................... 3-2 Instruction Set Overview .................................................................................................................................. 3-2 Instruction Set Summary Tables ....................................................................................................................... 3-3

SECTION 4. INSTRUCTION SET DETAILS

4-1

Data Addressing Modes ................................................................................................................................... 4-2 Program Addressing Modes ........................................................................................................................... 4-11 Instruction Stalls ............................................................................................................................................. 4-12 Byte Operations ............................................................................................................................................. 4-13 Word Move Operations .................................................................................................................................. 4-16 Using 10-bit Literal Operands ........................................................................................................................ 4-19 Software Stack Pointer and Frame Pointer .................................................................................................... 4-20 Conditional Branch Instructions ..................................................................................................................... 4-25 Z Status Bit ..................................................................................................................................................... 4-26 Assigned Working Register Usage ................................................................................................................. 4-27 DSP Data Formats ......................................................................................................................................... 4-30 Accumulator Usage ........................................................................................................................................ 4-32 Accumulator Access ....................................................................................................................................... 4-33 DSP MAC Instructions ................................................................................................................................... 4-33 DSP Accumulator Instructions ....................................................................................................................... 4-37 Scaling Data with the FBCL Instruction .......................................................................................................... 4-37 Normalizing the Accumulator with the FBCL Instruction ................................................................................ 4-39

SECTION 5. INSTRUCTION DESCRIPTIONS

5-1

Instruction Symbols .......................................................................................................................................... 5-2 Instruction Encoding Field Descriptors Introduction ......................................................................................... 5-2 Instruction Description Example ....................................................................................................................... 5-6 Instruction Descriptions .................................................................................................................................... 5-7

SECTION 6. REFERENCE

6-1

Data Memory Map ............................................................................................................................................ 6-2 Core Special Function Register Map ................................................................................................................ 6-3 Program Memory Map ..................................................................................................................................... 6-6 Instruction Bit Map ........................................................................................................................................... 6-7 Instruction Set Summary Table ........................................................................................................................ 6-9

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NOTES:

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1
Introduction

Section 1. Introduction
HIGHLIGHTS
This section of the manual contains the following topics: 1.1 1.2 1.3 1.4 1.5 1.6 Introduction .................................................................................................................... 1-2 Manual Objective ........................................................................................................... 1-2 Development Support .................................................................................................... 1-2 Style and Symbol Conventions ...................................................................................... 1-3 Instruction Set Symbols ................................................................................................. 1-4 Related Documents ....................................................................................................... 1-5

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dsPIC30F Programmer’s Reference Manual
1.1 Introduction
Microchip Technology’s focus is on products that meet the needs of the embedded control market. We are a leading supplier of: • • • • • 8-bit general purpose microcontrollers (PICmicro® MCUs) dsPIC30F 16-bit microcontrollers Speciality and standard non-volatile memory devices Security devices (KEELOQ®) Application specific standard products

Please request a Microchip Product Line Card for a listing of all the interesting products that we have to offer. This literature can be obtained from your local sales office, or downloaded from the Microchip web site (www.microchip.com).

1.2

Manual Objective
PICmicro and dsPIC30F devices are grouped by the size of their Instruction Word and Data Path. The current device families are: 1. 2. 3. 4. 5. Base-Line: Mid-Range: High-End: Enhanced: dsPIC30F: 12-bit Instruction Word length, 8-bit Data Path 14-bit Instruction Word length, 8-bit Data Path 16-bit Instruction Word length, 8-bit Data Path 16-bit Instruction Word length, 8-bit Data Path 24-bit Instruction Word length, 16-bit Data Path

This manual is a software developer’s reference for the dsPIC30F 16-bit MCU family of devices. This manual describes the Instruction Set in detail and also provides general information to assist the user in developing software for the dsPIC30F MCU family. This manual does not include detailed information about the core, peripherals, system integration or device-specific information. The user should refer to the dsPIC30F MCU Family Reference Manual for information about the core, peripherals and system integration. For device specific information, the user should refer to the data sheet. The information that can be found in the data sheet includes: • • • • Device memory map Device pinout and packaging details Device electrical specifications List of peripherals included on the device.

Code examples are given throughout this manual. These examples are valid for any device in the dsPIC30F MCU family.

1.3

Development Support
Microchip offers a wide range of development tools that allow users to efficiently develop and debug application code. Microchip’s development tools can be broken down into four categories: 1. 2. 3. 4. Code generation Hardware/Software debug Device programmer Product evaluation boards

Information about the latest tools, product briefs and user guides can be obtained from the Microchip web site (www.microchip.com) or from your local Microchip Sales Office. Microchip offers other reference tools to speed the development cycle. These include: • • • • • Application Notes Reference Designs Microchip web site Local Sales Offices with Field Application Support Corporate Support Line

The Microchip web site lists other sites that may be useful references.

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Section 1. Introduction

1
1.4 Style and Symbol Conventions

Introduction

Throughout this document, certain style and font format conventions are used. Most format conventions imply a distinction should be made for the emphasized text. The MCU industry has many symbols and non-conventional word definitions/abbreviations. Table 1-1 provides a description for many of the conventions contained in this document. Table 1-1: Document Conventions Description To force a bit/register to a value of logic ‘1’. To force a bit/register to a value of logic ‘0’. 1) To force a register/bit to its default state. 2) A condition in which the device places itself after a device RESET occurs. Some bits will be forced to ‘0’ (such as interrupt enable bits), while others will be forced to ‘1’ (such as the I/O data direction bits). Designates the number ‘nnnn’ in the hexadecimal number system. These conventions are used in the code examples. For example, 0x013F or 0xA800. Used to specify a range or the concatenation of registers/bits/pins. One example is ACCAU:ACCAH:ACCAL, which is the concatenation of three registers to form the 40-bit accumulator. Concatenation order (left-right) usually specifies a positional relationship (MSb to LSb, higher to lower). Specifies bit(s) locations in a particular register. One example is SR<IPL2:IPL0> (or IPL<2:0>), which specifies the register and associated bits or bit positions. Indicates the Least Significant or Most Significant bit in a field. Indicates the Least/Most Significant Byte or Word in a field of bits.

Symbol or Term set clear RESET

0xnnnn

: (colon)

<>

MSb, MSbit, LSb, LSbit MSByte, MSWord, LSByte, LSWord Courier Font

Used for code examples, binary numbers and for Instruction Mnemonics in the text. Times Font Used for equations and variables. Times, Bold Font, Used in explanatory text for items called out from a Italics graphic/equation/example. Note: A Note presents information that we wish to re-emphasize, either to help you avoid a common pitfall, or make you aware of operating differences between some device family members. In most instances, a Note is used in a shaded box (as illustrated below), however when referenced to a table, a Note will stand-alone and immediately follow the associated table (as illustrated below Table 1-2). Note: This is a Note in a shaded note box.

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5 Instruction Set Symbols The Summary Tables in Section 3-2 and Section 6. Table 1-2:Symbols Used in Instruction Summary Tables and Descriptions Symbol Description Optional field or operation The location addressed by text The contents of text The literal defined by text “a” must be in the set of [b.5. c. “Instruction Descriptions” for the specific instruction range. 0:1023 in Word mode) 14-bit literal (0:16383) 16-bit literal (0:65535) 23-bit literal (0:8388607) Signed 4-bit literal (-8:7) Signed 6-bit literal (-32:31) (range is limited to -16:16) Signed 10-bit literal (-512:511) Signed 16-bit literal (-32768:32767) Top-of-Stack Base working register Destination working register (direct and indirect addressing) Working register divide pair (dividend. {} [text] (text) #text a ∈ [b. d] Register bit field Optional label name Accumulator A or Accumulator B Accumulator Write Back 4-bit wide bit position (0:7 in Byte mode. c. . Refer to Section 5.dsPIC30F Programmer’s Reference Manual 1.4 utilize the symbols shown in Table 1-2. 0:15 in Word mode) Absolute address. divisor) Working register multiplier pair (same source register) Working register multiplier pair (different source registers) Both source and destination working register (direct addressing) Destination working register (direct addressing) Source working register (direct addressing) Default working register (assigned to W0) Source working register (direct and indirect addressing) Source Addressing mode and working register for X data bus pre-fetch Destination working register for X data bus pre-fetch Source Addressing mode and working register for Y data bus pre-fetch Destination working register for Y data bus pre-fetch The range of each symbol is instruction dependent. and the instruction descriptions in Section 5. Wn Wm*Wm Wm*Wn Wn Wnd Wns WREG Ws Wx Wxd Wy Wyd Note: DS70030E-page 1-4 Advance Information  2003 Microchip Technology Inc. d] <n:m> {label:} Acc AWB bit4 Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 Slit4 Slit6 Slit10 Slit16 TOS Wb Wd Wm. label or expression (resolved by the linker) File register address 1-bit literal (0:1) 4-bit literal (0:15) 5-bit literal (0:31) 8-bit literal (0:255) 10-bit literal (0:255 in Byte mode.

2 Third Party Documentation There are several documents available from third party sources around the world. 1.  2003 Microchip Technology Inc.microchip. The details of device operation are provided in this document. Microchip does not review these documents for technical accuracy. Please check the Microchip web site (www. peripherals and system integration features. such as pinout and packaging details. dsPIC30F Data Sheets The data sheets contain device specific information.com) for a list of available device data sheets. These lists contain the most common documentation. memory sizes and available peripherals.1 Microchip Documentation The following dsPIC30F documentation is available from Microchip at the time of this writing. However. 3.6. electrical specifications. Please refer to the Microchip web site (www. programming and designing with dsPIC30F MCUs. offer additional documentation which can aid in your development with dsPIC30F MCUs. 1. as well as other sources. dsPIC30F MCU Family Reference Manual (DS70046) The dsPIC30F Family Reference Manual provides information about the dsPIC30F architecture.6. dsPIC30F High Performance 16-Bit Digital Signal Controller Family Overview (DS70043) This document provides a summary of the available dsPIC30F family variants. they may be a helpful source for understanding the operation of Microchip dsPIC30F devices. including device pinouts.Section 1. Introduction 1 1. along with numerous code examples.com) for the latest published technical documentation. Please check the Microchip web site (www.com) for third party documentation related to the dsPIC30F. 1.microchip. but other documents may also be available.microchip. and memory maps. 2. Advance Information DS70030E-page 1-5 .6 Related Documents Introduction Microchip. Many of these documents provide application specific information that gives actual examples of using.

dsPIC30F Programmer’s Reference Manual NOTES: DS70030E-page 1-6 Advance Information  2003 Microchip Technology Inc. .

....................1 2..... 2-2 Programmer’s Model. Advance Information DS70030E-page 2-1 . It contains the following major topics: 2............................................................................................ 2-3 2 Programmer’s Model  2003 Microchip Technology Inc........................................... Programmer’s Model HIGHLIGHTS This section of the manual contains overview information about the dsPIC30F devices........2 dsPIC30F Overview ......Section 2...................................

17-bit by 17-bit multiplier. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two working registers. Register Direct. . Overhead free circular buffers (modulo addressing) are supported in both X and Y address spaces. a working register (data) read. up to 16-bits right. referred to as X and Y data memory. For most instructions. The program counter (PC) is 23-bits wide and addresses up to 4M x 24 bits of user program memory space. The 16th working register (W15) operates as a software stack pointer for interrupts and calls. The DSP dual source class of instructions operates through the X and Y AGUs. The core has a 24-bit instruction word. the dsPIC30F is capable of executing a data (or program data) memory read. The DSP engine features a high speed. 3-operand instructions can be supported. As many as 7 Addressing modes are supported for each instruction. The X AGU also supports bit-reverse addressing. The program to data space mapping feature lets any instruction access program space as if it were data space. including support for DSP. or up to 16-bits left. Furthermore. As a result. The core supports Inherent (no operand). which accesses the entire memory map as one linear data space. defined by the 8-bit Program Space Visibility Page (PSVPAG) register. Each of the working registers can act as a data. which is useful for storing data coefficients. A single cycle instruction pre-fetch mechanism is used to help maintain throughput and provides predictable execution. Each instruction is associated with a predefined Addressing mode group. 16-bit working registers. Relative. Register Indirect and Register Offset Addressing modes. with a variable length opcode field. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. the X AGU circular addressing can be used with any of the MCU class of instructions. The modulo addressing removes the software boundary checking overhead for DSP algorithms. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. in a single cycle. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operate solely through the X memory AGU. The dsPIC30F instruction set has two classes of instructions: the MCU class of instructions and the DSP class of instructions. The instruction set includes many Addressing modes and was designed for optimum C compiler efficiency. DS70030E-page 2-2 Advance Information  2003 Microchip Technology Inc. The dsPIC30F has sixteen. This requires that the data space be split for these instructions and linear for all others.dsPIC30F Programmer’s Reference Manual 2. Literal. which splits the data address space into two parts. two 40-bit saturating accumulators and a 40-bit bi-directional barrel shifter. The X and Y data space boundary is arbitrary and device specific. a 40-bit ALU. both of which are interruptible. and overhead free program loop constructs are supported using the DO and REPEAT instructions. allowing A+B=C operations to be executed in a single cycle. a data memory write and a program (instruction) memory read per instruction cycle. The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks. Each interrupt source can be assigned to one of seven priority levels. depending upon its functional requirements. The majority of instructions execute in a single cycle. address or offset register. The barrel shifter is capable of shifting a 40-bit value.1 dsPIC30F Overview The dsPIC30F core is a 16-bit (data) modified Harvard architecture with an enhanced instruction set. Memory Direct. This is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. to greatly simplify input or output data reordering for radix-2 FFT algorithms. The dsPIC30F has a vectored exception scheme with up to 8 sources of non-maskable traps and 54 interrupt sources.

address or offset registers. the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses. file register instructions operate on a specific memory address contained in the instruction opcode. which target the working register array. 2. or as addresses that point to a memory location. a default working register (WREG) is used for these file register instructions. only affect the Least Significant Byte of the target register.2.1 Working Register Array The 16 working (W) registers can function as data. if a stack frame pointer and the LNK and ULNK instructions are not used. W14 can be used by any instruction in the same manner as all other W registers. used by a function to allocate memory for local variables. Byte instructions. All registers in the programmer’s model are memory mapped and can be manipulated directly by the instruction set. A description of each register is provided in Table 2-1. The function of a W register is determined by the instruction that accesses it.2. Table 2-1: Programmer’s Model Register Descriptions Description 40-bit DSP Accumulators CPU Core Configuration register DO Loop Count register DO Loop End Address register DO Loop Start Address register 23-bit Program Counter Program Space Visibility Page Address register Repeat Loop Count register Stack Pointer Limit Value register ALU and DSP Engine Status register Table Memory Page Address register Working register array Register ACCA.2 Default Working Register (WREG) The dsPIC30F instruction set can be divided into two instruction types: working register instructions and file register instructions.2 Programmer’s Model The programmer’s model diagram for the dsPIC30F is shown in Figure 2-1. Since the working registers are memory mapped.  2003 Microchip Technology Inc.3 “Software Stack Frame Pointer” for detailed information about the Frame Pointer. Working register W0 is assigned to be the WREG.Section 2. The working register instructions use the working register array as data values.W15 2 Programmer’s Model 2. ACCB CORCON DCOUNT DOEND DOSTART PC PSVPAG RCOUNT SPLIM SR TBLPAG W0 .3 Software Stack Frame Pointer A frame is a user defined section of memory in the stack. See Section 4. The WREG assignment is not programmable.7. W14 has been assigned for use as a stack frame pointer with the link (LNK) and unlink (ULNK) instructions. 2. However. Advance Information DS70030E-page 2-3 . File register instructions that also utilize a working register do not specify the working register that is to be used for the instruction. In contrast.2. Instead. Programmer’s Model 2.

S Shadow Legend SPLIM* 39 DSP Accumulators 22 ACCA ACCB 0 31 Program Counter 7 TABPAG TBLPAG T PSVPAG mpsm^d =M Program Space Visibility Page Address 15 RCOUNT 15 DCOUNT 22 DOSTART 22 DOEND 15 CORCON =0 =`mr=Core Control Register ==0 DO Loop End Address ==0 DO Loop Start Address 0 al=iççé=`çìåíÉê 0 REPEAT Loop Counter =0 Data Table Page Address OA OB SA SB OAB SAB DA SRH DC IPL2 IPL1 IPL0 RA SRL N OV Z C Status Register DS70030E-page 2-4 Advance Information  2003 Microchip Technology Inc.dsPIC30F Programmer’s Reference Manual Figure 2-1: Programmer’s Model Diagram 15 W0 / WREG DIV and MUL Result Registers W1 W2 W3 W4 MAC Operand Registers W5 W6 W7 W8 MAC Address Registers W9 W10 W11 W12/MAC Offset W13/MAC Write Back W14/Frame Pointer W15*/Stack Pointer * W15 & SPLIM not shadowed Stack Pointer Limit Register 15 0 Working Registers DO Shadow 0 PUSH. .

Advance Information DS70030E-page 2-5 . Instructions are addressed in the 4M x 24-bit user program memory space by PC<22:1>.4 Software Stack Pointer W15 serves as a dedicated software stack pointer.7. W15 can be referenced by any instruction in the same manner as all other W registers.12 “Accumulator Usage” for details on using ACCA and ACCB.1 “Software Stack Pointer” for detailed information about the stack pointer. exception processing and returns. It is used to prevent the stack pointer from overflowing and accessing memory beyond the user allocated region of stack memory. 2.2. the PC increments by 2. Refer to the dsPIC30F MCU Family Reference Manual for details on program space visibility.32) • AccxH (bits 31 . This region is not available for user code execution and the PC can not access this area. This simplifies reading. 2. where PC<0> is always set to ‘0’ to maintain instruction word alignment and provide compatibility with data space addressing. Refer to the dsPIC30F MCU Family Reference Manual for details on accessing the configuration data.2. This means that during normal instruction execution. utilized by DSP instructions to perform mathematical and shifting operations.9 PSVPAG Register Program space visibility allows the user to map a 32 Kbyte section of the program memory space into the upper 32 Kbytes of data address space.0) Refer to Section 4.2. Refer to Section 4. Program memory located at 0x80000000 and above is utilized for device configuration data. Each accumulator is composed of 3 memory mapped registers: • AccxU (bits 39 . one may access this region of memory using Table instructions.6 Accumulator A. Accumulator B Accumulator A (ACCA) and Accumulator B (ACCB) are 40-bit wide registers.2.2. Unit ID and Device ID. This feature allows transparent access of constant data through dsPIC30F instructions that operate on data memory. writing and manipulating the stack pointer. Refer to Section 4. 2 Programmer’s Model 2.Section 2.2. Table instructions are used to transfer data between program memory space and data memory space.5 Stack Pointer Limit Register (SPLIM) The SPLIM is a 16-bit register associated with the stack pointer.  2003 Microchip Technology Inc. Unit ID and Device ID.16) • AccxL (bits 15 .7 Program Counter The Program Counter (PC) is 23-bits wide. However. Programmer’s Model 2. and will be automatically modified by function calls.5 “Stack Pointer Overflow” for detailed information about the SPLIM. 2. 2.7. The PSVPAG register selects the 32 Kbyte region of program memory space that is mapped to the data address space. Refer to the dsPIC30F MCU Family Reference Manual for details on accessing program memory with the Table instructions. However.8 TBLPAG Register The TBLPAG register is used to hold the upper 8 bits of a program memory address during table read and write operations.

11 DCOUNT Register The 14-bit DCOUNT register contains the loop counter for hardware DO loops. When a DO instruction is executed. When looping is activated. This mechanism allows for zero overhead looping. DOEND is loaded with the address specified by the expression in the DO instruction.2. or the contents of Wn for the ”REPEAT Wn” instruction. 2.Expr” instruction. or the 14 Least Significant bits of Ws for the “DO Ws. Note 1: If a REPEAT loop is executing and gets interrupted.2.13 DOEND Register The DOEND register contains the ending address for a hardware DO loop.2.2. DS70030E-page 2-6 Advance Information  2003 Microchip Technology Inc. Note 1: DOEND has a shadow register. When looping is activated and the instruction stored at the DOEND address is executed. DCOUNT is loaded with the loop count of the instruction.Expr” instruction.16 “Shadow Registers” for information on shadowing. 2: Refer to the dsPIC30F Family Reference Manual for complete details about REPEAT loops. This location in memory is the start of the DO loop. program execution continues with the instruction stored at the DOSTART address after the last instruction in the DO loop is executed. either “lit14” for the ”REPEAT #lit14“ instruction. See Section 2. The REPEAT loop will be executed RCOUNT+1 times.12 DOSTART Register The DOSTART register contains the starting address for a hardware DO loop. 2: Refer to the dsPIC30F Family Reference Manual for complete details about DO loops. RCOUNT may be cleared by the Interrupt Service Routine to break out of the REPEAT loop when the foreground code is re-entered. See Section 2. 2: Refer to the dsPIC30F Family Reference Manual for complete details about DO loops. 2. Note 1: DCOUNT contains a shadow register.10 RCOUNT Register The 14-bit RCOUNT register contains the loop counter for the REPEAT instruction. 2.16 “Shadow Registers” for information on shadowing. When a REPEAT instruction is executed. 2: Refer to the dsPIC30F Family Reference Manual for complete details about DO loops.2. This location in memory specifies the last instruction in the DO loop. either “lit14” for the “DO #lit14. Note 1: DOSTART has a shadow register. RCOUNT is loaded with the repeat count of the instruction.2. program execution will continue from the DO loop start address (stored in the DOSTART register).16 “Shadow Registers” for information on shadowing. The DO loop will be executed DCOUNT+1 times. When a DO instruction is executed. DOSTART is loaded with the address of the instruction following the DO instruction.dsPIC30F Programmer’s Reference Manual 2. When a DO instruction is executed. See Section 2. .2.

If a DO loop must be terminated prematurely. The Z status bit is a special zero status bit that is useful for extended precision arithmetic. Since the RA flag is also read only. and the conditional Branch instructions use the state of individual status bits to determine the flow of program execution. OV. Note 1: All MCU bits are shadowed during execution of the PUSH.S instruction and they are restored on execution of the POP. IPL<2:0>.2 Loop Status Bits The DO Active and REPEAT Active (DA. This action will disable looping once program execution returns from the Interrupt Service Routine. Zero.S instruction. maintains status information for instructions which have most recently been executed.2. CPB.8 “Conditional Branch Instructions”. zero. Z.2. respectively.14. The DO instructions affect the DA flag. should be used. CORCON<11>. They indicate when an operation has resulted in a carry. The DA flag is read only. the EDT bit. Overflow. which indicates that a DO loop is active. 2. The Z bit functions like a normal Z flag for all instructions except those that use a carry or borrow input (ADDC. nor may looping be terminated by writing a ‘0’ to DA. N and DC) bits are used to show the immediate status of the MCU ALU. When a subtract operation is performed. loop operations and DSP operations. and it is cleared when the instruction being repeated completes execution for the last time. RA) bits are used to indicate when looping is active.9 “Z Status Bit” for usage of the Z status bit. See Section 4. Math.1 MCU ALU Status Bits The MCU operation status bits are either affected or used by the majority of instructions in the instruction set. the Status register contains the CPU Interrupt Priority Level bits. Rotate/Shift and Bit instructions modify the MCU status bits after execution. the C flag is used as a Borrow flag. because the restored RA will be ‘0’. Additionally. except the DC flag (which is not in the SRL). the Interrupt Service Routine may clear the RA flag of the SRL.2. 2. Advance Information DS70030E-page 2-7 . The RA flag is set to ‘1’ when the instruction being repeated begins execution.14 Status Register The 16-bit Status register. Negative and Digit Carry (C. Most of the Logic. Operation status bits exist for MCU operations. SUBB and SUBBR). All conditional Branch instructions are listed in Section 4. the RA flag indicates that a REPEAT instruction is being executed. 2 Programmer’s Model  2003 Microchip Technology Inc. Likewise. and it is cleared when the last instruction of the loop completes final execution. Programmer’s Model 2. This means that looping may not be initiated by writing a ‘1’ to DA. which resides on the stack. 2: All MCU bits.1 “Software Stack Pointer”). The Carry.14. which are used for interrupt processing.7. and it is only affected by the REPEAT instructions. shown in Register 2-1. it may not be directly cleared.Section 2. overflow. However. negative result and digit carry. are stacked during exception processing (see Section 4. The DA flag is set to ‘1’ when the first instruction of the DO loop is executed. if a REPEAT or its target instruction is interrupted.

while traps have a fixed priority level between 8 and 15. Since the SRL is stacked during exception processing. the OA and OB bits are logically ORed together to form the OAB flag. while the Saturate AB and Overflow AB (SAB. which utilizes both accumulators. . This condition can only occur when the processor is in Super Saturation mode. when checking for saturation. If required. INTCON1<15>. IPL3. However. once the SA or SB is set to ‘1’. The SA and SB bits are active. For convenience. This bit is only set when a hardware trap is activated and it is cleared after the trap is serviced. OA. and the SA and SB bits are logically ORed to form the SAB flag. CORCON<3>. Likewise. a single check of OAB may be performed. regardless of subsequent DSP operations. the original IPL is always restored after the exception is serviced. all exceptions at priority Level 1 and above may interrupt the processor. Saturate B.14. SAB may be examined instead of checking both the SA and SB bits. It indicates that the operation has generated a number which cannot be represented with the lower 31 bits of the accumulator. OB) bits provide individual accumulator status.4 Interrupt Priority Level Status Bits The three IPL bits of the SRL. it is recommended that the bits be cleared with the BCLR instruction.dsPIC30F Programmer’s Reference Manual 2.2. set the CPU’s Interrupt Priority Level (IPL) which is used for exception processing. The interrupt level of a pending exception must always be greater than the CPU’s IPL for the CPU to process the exception. If the IPL is ‘7’. Overflow A and Overflow B (SA. Note that clearing the SAB flag will clear both the SA and SB bits. 2. OAB) bits provide combined accumulator status. DS70030E-page 2-8 Advance Information  2003 Microchip Technology Inc. The fourth Interrupt Priority Level bit. The SA and SB bits are used to indicate when an operation has generated an overflow out of the Most Significant bit of the respective accumulator. only hardware traps may interrupt the processor. When an exception is serviced. Instead of interrogating the OA and the OB bits independently for arithmetic overflows. The CPU’s IPL identifies the lowest level exception which may interrupt the processor.3 DSP ALU Status Bits The high byte of the Status Register (SRH) is used by the DSP class of instructions. When required. SB. Namely. one may also prevent exceptions from nesting by setting the NSTDIS bit. The SAB and OAB bits provide the software developer efficiency in checking the register for saturation or overflow. These cumulative status bits provide efficient overflow and saturation checking when an algorithm is implemented. Exceptions consist of interrupts and hardware traps. The OA and OB bits are used to indicate when an operation has generated an overflow into the guard bits (bits 32 through 39) of the respective accumulator. or if saturation is disabled. which will disable all exceptions of equal and lower priority.14. and it is modified when data passes through one of the adders. The SRH provides status information about overflow and saturation for both accumulators. one may modify the lower three bits of the IPL in an Interrupt ServiceRoutine to control which exceptions may preempt the exception processing.2. Interrupts have a user defined priority level between 0 and 7. The Saturate A. Note: Refer to the dsPIC30F Family Reference Manual for complete details on exception processing. SR<7:5>. and the IPL3 bit. the IPL is automatically set to the priority level of the exception being serviced. regardless of the Saturation mode (Disabled. since the IPL field is read/write. it can only be cleared manually by software. is a special IPL bit that may only be read or cleared by the user. Normal or Super) and may be considered “sticky”. This means that if the IPL is ‘0’.

CORCON<10:8>.S/PUSH.  2003 Microchip Technology Inc.16 Shadow Registers A shadow register is used as a temporary holding register and can transfer its contents to or from the associated host register upon some event. up to one level of DO loop nesting is possible.W3 DO Yes Yes Yes — — POP.2. Since all shadow registers are one register deep. the ability to nest DO loops without additional overhead is provided. which sets the following mode: • • • • • • Program Space not Mapped to Data Space (PSV = 0) ACCA and ACCB Saturation Disabled (SATA = 0. N. which indicates if a trap exception is being processed.S — — — Yes Yes Since the DCOUNT.S instruction. 2. Z and C bits W0 .2. Programmer’s Model 2. Shadow register usage is shown in Table 2-2. Advance Information DS70030E-page 2-9 . with support provided by the DO Loop Nesting Level Status bits in the CORCON. Additional shadowing may be performed in software using the software stack. Some of the registers in the programmer’s model have a shadow register.15 Core Control Register The 16-bit CPU Core Control Register (CORCON). IF = 0) 2 Programmer’s Model In addition to setting CPU modes. Table 2-2: Automatic Shadow Register Usage Location DCOUNT DOSTART DOEND Status Register DC. OV. SATB = 0) Data Space Write Saturation Enabled (SATDW = 1) Accumulator Saturation mode set to normal (ACCSAT = 0) Accumulator Rounding mode set to unbiased (RND = 0) DSP Multiplier mode set to signed fractional (US = 0.Section 2. This register provides the ability to: • • • • • • map program space into data space set the ACCA and ACCB saturation enable set the Data Space Write Saturation mode set the Accumulator Saturation and Rounding modes set the Multiplier mode for DSP operations terminate DO loops prematurely On device RESET. which is utilized during the execution of a DO. shown in Register 2-2. is used to set the configuration of the dsPIC30F CPU. the CORCON is set to 0x0020. the CORCON contains status information about the DO loop nesting level (DL<2:0>) and the IPL<3> status bit. DOSTART and DOEND registers are shadowed. POP. Note: All shadow registers are one register deep and are not directly accessible.S or PUSH. Further nesting of DO loops is possible in software.

it must be cleared manually by software. . 3: Clearing this bit will clear SA and SB. 2: Once this bit is set. but not set. User interrupts disabled. 2: Once this bit is set. 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. but not set. bit 11 OAB: OA || OB Combined Accumulator Overflow bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed SAB: SA || SB Combined Accumulator bit 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulators A or B are saturated Note 1: This bit may be read or cleared.dsPIC30F Programmer’s Reference Manual Register 2-1: SR. bit 8 bit 7-5 DS70030E-page 2-10 Advance Information  2003 Microchip Technology Inc. DC: MCU ALU Half Carry bit 1 = A carry-out from the Most Significant bit of the lower nibble occurred 0 = No carry-out from the Most Significant bit of the lower nibble occurred IPL<2:0>: Interrupt Priority Level bits 111 = CPU Interrupt Priority Level is 7 (15). it must be cleared manually by software. it must be cleared manually by software. bit 10 bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress Note: This bit is read only. bit 14 bit 13 bit 12 SB: Accumulator B Saturation bit 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated Note 1: This bit may be read or cleared. if IPL<3> = 1. The value in parentheses indicates the IPL. 2: Once this bit is set. but not set. Status Register R/C-0 SA R/C-0 SB R-0 OAB R/C-0 SAB R-0 DA R/W-0 DC bit 8 High Byte (SRH): R-0 R-0 OA OB bit 15 Low Byte (SRL): R/W-0 R/W-0 IPL<2:0> bit 7 bit 15 R/W-0 R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 OA: Accumulator A Overflow bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed OB: Accumulator B Overflow bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed SA: Accumulator A Saturation bit 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated Note 1: This bit may be read or cleared.

Section 2. bit 3 bit 2 bit 1 2 Programmer’s Model bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit occurred 0 = No carry-out from the Most Significant bit occurred Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set C = Clearable bit 0 = bit is cleared  2003 Microchip Technology Inc. Advance Information DS70030E-page 2-11 .9 “Z Status Bit” for operation with ADDC. Status Register (Continued) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = The result of the operation was negative 0 = The result of the operation was not negative OV: MCU ALU Overflow bit 1 = Overflow occurred 0 = No overflow occurred Z: MCU ALU Zero bit 1 = The result of the operation was zero 0 = The result of the operation was not zero Note: Refer to Section 4. CPB. SUBB and SUBBR instructions. Programmer’s Model Register 2-1: bit 4 SR.

.dsPIC30F Programmer’s Reference Manual Register 2-2: High Byte: U — bit 15 CORCON. 2: The first two levels of DO loop nesting are handled by hardware. Core Control Register U — U — R/W-0 US R(0)/W-0 EDT R-0 R-0 DL<2:0> R/W-0 bit 8 Low Byte: R/W-0 SATA bit 7 bit 15-13 Unused bit 12 US: Unsigned or Signed Multiplier Mode Select bit 1 = Unsigned mode enabled for DSP multiply operations 0 = Signed mode enabled for DSP multiply operations EDT: Early DO Loop Termination Control bit 1 = Terminate executing DO loop at end of current iteration 0 = No effect Note: bit 10-8 This bit will always read ‘0’. but not set. bit 7 SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (Super Saturation) 0 = 1. DL<2:0>: DO Loop Nesting Level Status bits 111 = DO looping is nested at 7 levels 110 = DO looping is nested at 6 levels 110 = DO looping is nested at 5 levels 110 = DO looping is nested at 4 levels 011 = DO looping is nested at 3 levels 010 = DO looping is nested at 2 levels 001 = DO looping is active. Core Control Register (Continued) R/W-0 SATB R/W-1 SATDW R/W-0 ACCSAT R/C-0 IPL3 R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 bit 11 bit 6 bit 5 bit 4 bit 3 Register 2-2: DS70030E-page 2-12 Advance Information  2003 Microchip Technology Inc. 2: This bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space CORCON. but not nested (just 1 level) 000 = DO looping is not active Note 1: DL<2:1> are read only.31 saturation (Normal Saturation) IPL3: Interrupt Priority Level 3 Status bit 1 = CPU Interrupt Priority Level is 8 or greater (trap exception activated) 0 = CPU Interrupt Priority Level is 7 or less (no trap exception activated) Note 1: This bit may be read or cleared.

Programmer’s Model bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply operations 0 = Fractional mode enabled for DSP multiply operations Legend: R = Readable bit -n = Value at POR W = Writable bit 1 = bit is set C = Clearable bit 0 = bit is cleared x = bit is unknown U = Unimplemented bit. Advance Information DS70030E-page 2-13 .Section 2. read as ‘0’ bit 0 2 Programmer’s Model  2003 Microchip Technology Inc.

.dsPIC30F Programmer’s Reference Manual NOTES: DS70030E-page 2-14 Advance Information  2003 Microchip Technology Inc.

......................................................... 3-2 Instruction Set Summary Tables ..................................1 3.........Section 3............................................................ Instruction Set Overview HIGHLIGHTS This section of the manual contains the following major topics: 3...... 3-2 Instruction Set Overview .........................2 3.... 3-3 3 Instruction Set Overview  2003 Microchip Technology Inc........................ Advance Information DS70030E-page 3-1 ..................................3 Introduction .................................................

will incur a one or two cycle delay. “Reference”. with the following exceptions: • Instructions DO. These tables define the syntax. which should be executed 18 consecutive times as the target of a REPEAT instruction. a composite alphabetized instruction set table is provided in Section 6. See the dsPIC30F Family Reference Manual for details. which supports traditional microcontroller applications and a class of instructions.2. RETLW and RETURN are a special case of an instruction that changes the program counter. which require different instruction variants. Additionally. only the first execution of the target instruction is subject to the delay. description. using Program Space Visibility. most instructions execute in a single cycle. “Instruction Set Overview”. Table 1-2 defines the symbols used in the instruction summary tables. • Instructions that change the program counter also require 2 cycles to execute. which can be grouped into the ten functional categories shown in Table 3-1. TBLWTH and TBLWTL require 2 cycles to execute. Storage requirements are represented in 24-bit instruction words and execution requirements are represented in instruction cycles. These execute in 3 cycles. which skip over a 2-word instruction. which supports math intensive applications.D. TBLRDL.dsPIC30F Programmer’s Reference Manual 3. SKIP instructions. However. TBLRDH. • The RETFIE.1 Multi-Cycle Instructions As the instruction summary tables show. For instance.1 Introduction The dsPIC30F instruction set provides a broad suite of instructions. with 2 cycles executed as a NOP.D. Since almost all of the functionality of the PICmicro® MCU instruction set has been maintained. Table 3-1: dsPIC30F Instruction Groups Functional Group Move Instructions Math Instructions Logic Instructions Rotate/Shift Instructions Bit Instructions Compare/Skip Instructions Program Flow Instructions Shadow/Stack Instructions Control Instructions DSP Instructions Summary Table Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Page # 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-10 3-10 Most instructions have several different Addressing modes and execution flows. storage and execution requirements for each instruction. • Instructions DIV. DS70030E-page 3-2 Advance Information  2003 Microchip Technology Inc. require 3 instruction cycles to execute. Note: Instructions which access program memory as data. PUSH. Table 3-2 through Table 3-11. with the extra cycle executed as a NOP.U and DIVF are single cycle instructions. . 3.S.2 Instruction Set Overview The dsPIC30F instruction set contains 84 instructions. unless an exception is pending and then they execute in 2 cycles. 3. MOV. when the target instruction of a REPEAT loop accesses program memory as data. there are six unique ADD instructions and each instruction variant has its own instruction encoding. POP. this hybrid instruction set allows a friendly DSP migration path for users already familiar with the PICmicro microcontroller. Instruction format descriptions and specific instruction operation are provided in Section 3. DIV.D.

Wd Ws.Wnd #lit16. the destination of the instruction is the file register f. listed in Table 3-8. which are Program Flow Instructions.WREG} is not specified.B MOV MOV MOV MOV MOV. the destination of the instruction is WREG.Wnd Wns.3 Instruction Set Summary Tables Table 3-2: EXCH MOV MOV MOV MOV MOV.Wnd [Ws+Slit10]. DO and GOTO instructions. almost all instructions consume one instruction word (24-bits).f #lit8. These instructions require two words of memory because their opcodes embed large literal operands. with the exception of the CALL. Instruction Set Overview 3.Wd Words Cycles Page # 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2 2 2 5-115 5-145 5-146 5-147 5-148 5-149 5-150 5-151 5-152 5-153 5-155 5-157 5-249 5-250 5-252 5-254 5-256 Move f to destination Move WREG to f Move f to Wnd Move Wns to f Move 8-bit literal to Wnd Move 16-bit literal to Wnd Move [Ws + signed 10-bit offset] to Wnd Move Wns to [Wd + signed 10-bit offset] Move Ws to Wd Move double Ws to Wnd:Wnd+1 Move double Wns:Wns+1 to Wd Wn = byte or nibble swap Wn Read high program word to Wd Read low program word to Wd Write Ws to high program word Write Ws to low program word 3 Instruction Set Overview When the optional {.f f.WREG} operand is specified.  2003 Microchip Technology Inc.Wnd f {.D SWAP TBLRDH TBLRDL TBLWTH TBLWTL Note: Move Instructions Description Swap Wns and Wnd (see Note) Assembly Syntax Wns. When {.Wnd Wns.Wd Ws.[Wd+Slit10] Ws. 3.WREG} WREG.Wd Ws.2 Multi-Word Instructions As defined by Subsection Table 3-2: “Move Instructions” . Advance Information DS70030E-page 3-3 .Wd Wn Ws.2.Wnd Wns.Section 3.Wd Ws.D MOV.

WREG} INC Ws.Wnd} = sign(Wb) * unsign(Ws) 1 1 5-174 MUL.Ws.Wnd} = sign(Wb) * unsign(lit5) 1 1 5-172 MUL. .Ws.#lit5.Wd Wd = lit5 – Wb 1 1 5-246 SUBR Wb. such that they are executed 18 consecutive times.Wd Wd = Wb – Ws – (C) 1 1 5-239 SUBBR f {. Wn Unsigned 16/16-bit integer divide 1 18(2) 5-103 DIV.WREG} operand is specified. Wn Signed 16/16-bit fractional divide 1 18(2) 5-105 (1) Destination = f + 1 1 1 5-124 INC f {.Wd Wd = Wb – lit5 – (C) 1 1 5-238 SUBB Wb.Ws. 2: The divide instructions must be preceded with a "REPEAT #17" instruction.US Wb.Wn Wn = lit10 + Wn + (C) 1 1 5-15 ADDC Wb.WREG}(1) Destination = f + WREG + (C) 1 1 5-14 ADDC #lit10.Ws.WREG}(1) Destination = f – WREG – (C) 1 1 5-236 SUBB #lit10.Wd Wd = Wb + lit5 + (C) 1 1 5-16 ADDC Wb.Ws.WREG} is not specified.Wnd {Wnd+1.U Wm.UU Wb.#lit5. the destination of the instruction is the file register f. Wn Signed 16/16-bit integer divide 1 18(2) 5-101 DIV.Ws.Wn Wn = Wn – lit10 – (C) 1 1 5-237 SUBB Wb.Wnd} = unsign(Wb) * unsign(lit5) 1 1 5-178 MUL.Wd Wd = lit5 – Wb – (C) SUBBR Wb.#lit5.Wnd} = unsign(Wb) * sign(Ws) 1 1 5-176 MUL.Wnd} = sign(Wb) * sign(Ws) 1 1 5-170 MUL.Wd Wd = Wb + Ws + (C) 1 1 5-17 DAW.Wnd {Wnd+1.Ws.Wnd Wnd = sign-extended Ws 1 1 5-220 SUB f {. Wn Signed 32/16-bit integer divide 1 18(2) 5-101 DIV.SS Wb. DS70030E-page 3-4 Advance Information  2003 Microchip Technology Inc.Wd Wd = Ws + 2 1 1 5-127 MUL f W3:W2 = f * WREG 1 1 5-169 MUL.B Wn Wn = decimal adjust Wn 1 1 5-95 DEC f {.#lit5.Wn Wn = Wn – lit10 1 1 5-231 SUB Wb.Wd Wd = Ws – 1 1 1 5-97 Destination = f – 2 1 1 5-98 DEC2 f {.WREG}(1) Destination = f – WREG 1 1 5-230 SUB #lit10.SU Wb.Ws.S Wm.Wd Wd = Ws – 2 1 1 5-99 DIV. Wn Unsigned 32/16-bit integer divide 1 18(2) 5-103 DIVF Wm.Wd Wd = Wb – Ws 1 1 5-233 SUBB f {.UU Wb.Wd Wd = Ws – Wb 1 1 5-247 ZE Ws.WREG} Destination = f + WREG 1 1 5-7 ADD #lit10.SD Wm.Wd Wd = Ws + 1 1 1 5-125 INC2 f {.#lit5.#lit5. When {.#lit5.dsPIC30F Programmer’s Reference Manual Table 3-3: Math Instructions Description (1) Assembly Syntax Words Cycles Page # ADD f {.Wd Wd = Wb + Ws 1 1 5-10 ADDC f {.WREG}(1) DEC2 Ws.Wnd {Wnd+1.UD Wm.Wn Wn = lit10 + Wn 1 1 5-8 ADD Wb.Wnd} = unsign(Wb) * unsign(Ws) 1 1 5-179 SE Ws.#lit5.WREG}(1) Destination = WREG – f – (C) 1 1 5-241 1 1 5-242 SUBBR Wb. the destination of the instruction is WREG.WREG}(1) Destination = f – 1 1 1 5-96 DEC Ws.Wnd Wnd = zero-extended Ws 1 1 5-264 Note 1: When the optional {.WREG}(1) Destination = WREG – f 1 1 5-245 SUBR Wb.Wnd {Wnd+1.Wnd {Wnd+1.Wnd {Wnd+1.Wd Wd = Wb – lit5 1 1 5-232 SUB Wb.Wd Wd = Wb + lit5 1 1 5-9 ADD Wb.Wd Wd = Ws – Wb – (C) 1 1 5-243 SUBR f {.Ws.Ws.WREG}(1) Destination = f + 2 1 1 5-126 INC2 Ws.SU Wb.

WREG} #lit10. When {.XOR.Wn Wb.Wd (see Note) Words Cycles Page # 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5-19 5-20 5-21 5-22 5-75 5-75 5-76 5-80 5-81 5-128 5-129 5-130 5-131 5-181 5-182 5-221 5-221 5-222 5-259 5-260 5-261 5-262 Destination = f .IOR.Ws. Ws f = 0x0000 WREG = 0x0000 Wd = 0x0000 Destination = f Wd = Ws Destination = f .  2003 Microchip Technology Inc. the destination of the instruction is the file register f.#lit5. lit5 Wd = Wb . Wn Wd = Wb .WREG} #lit10.Wn Wb. WREG Wn = lit10 .WREG}(see Note) Ws. WREG Wn = lit10 .XOR.#lit5.Ws. Wn Wd = Wb . Wn Wd = Wb .Section 3.XOR.Wd f {.WREG}(see Note) #lit10. Instruction Set Overview Table 3-4: AND AND AND AND CLR CLR CLR COM COM IOR IOR IOR IOR NEG NEG SETM SETM SETM XOR XOR XOR XOR Note: Logic Instructions Description (see Note) Assembly Syntax f {. lit5 Wd = Wb .Wd Wb.WREG} is not specified. the destination of the instruction is WREG.AND.XOR. Ws Destination = f + 1 Wd = Ws + 1 f = 0xFFFF WREG = 0xFFFF Wd = 0xFFFF Destination = f .IOR.Wn Wb.Wd f WREG Wd f {. Advance Information DS70030E-page 3-5 .Wd f {.IOR. WREG Wn = lit10 .WREG}(see Note) Ws. lit5 Wd = Wb .Wd Wb.IOR.#lit5.Wd f WREG Wd f {. Ws 3 Instruction Set Overview When the optional {.Wd Wb.Ws.WREG} operand is specified.AND.AND.AND.

the destination of the instruction is the file register f.Wd Wb.#lit4.Wd Wb.WREG}(see Note) Ws. . When {.Wd f {.dsPIC30F Programmer’s Reference Manual Table 3-5: ASR ASR ASR ASR LSR LSR LSR LSR RLC RLC RLNC RLNC RRC RRC RRNC RRNC SL SL SL SL Note: Rotate/Shift Instructions Description (see Note) Assembly Syntax f {.WREG} Ws.Wns.Wnd Wb.Wd f {.WREG} Ws.#lit4.WREG} operand is specified.Wd Wb.Wns.Wnd Wb.Wd f {. the destination of the instruction is WREG.Wd f {.WREG}(see Note) Ws.Wnd Wb.WREG} Ws. DS70030E-page 3-6 Advance Information  2003 Microchip Technology Inc.WREG} Ws.WREG} is not specified.Wnd f {.Wnd (see Note) (see Note) (see Note) Words Cycles Page # 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5-24 5-25 5-27 5-28 5-136 5-137 5-139 5-140 5-204 5-205 5-207 5-208 5-210 5-211 5-213 5-214 5-225 5-226 5-228 5-229 Destination = arithmetic right shift f Wd = arithmetic right shift Ws Wnd = arithmetic right shift Wb by lit4 Wnd = arithmetic right shift Wb by Wns Destination = logical right shift f Wd = logical right shift Ws Wnd = logical right shift Wb by lit4 Wnd = logical right shift Wb by Wns Destination = rotate left through Carry f Wd = rotate left through Carry Ws Destination = rotate left (no Carry) f Wd = rotate left (no Carry) Ws Destination = rotate right through Carry f Wd = rotate right through Carry Ws Destination = rotate right (no Carry) f Wd = rotate right (no Carry) Ws Destination = left shift f Wd = left shift Ws Wnd = left shift Wb by lit4 Wnd = left shift Wb by Wns When the optional {.Wnd f {.WREG}(see Note) Ws.Wns.#lit4.

Wnd Ws.Wnd Assembly Syntax 3 Instruction Set Overview  2003 Microchip Technology Inc.#bit4 Ws. Instruction Set Overview Table 3-6: BCLR BCLR BSET BSET BSW.C BTST.Section 3.C BTST.#bit4 f.#bit4 f.Z BTSTS BTSTS.Z BTST.#bit4 Ws.Wnd Ws.C BTSTS.#bit4 Ws.#bit4 Ws.Z FBCL FF1L FF1R Bit Instructions Description Bit clear f Bit clear Ws Bit set f Bit set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit toggle f Bit toggle Ws Bit test f Bit test Ws to C Bit test Ws to Z Bit test Ws<Wb> to C Bit test Ws<Wb> to Z Bit test f then set f Bit test Ws to C then set Ws Bit test Ws to Z then set Ws Find bit change from left (MSb) side Find first one from left (MSb) side Find first one from right (LSb) side Words Cycles Page # 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5-29 5-30 5-54 5-55 5-56 5-56 5-58 5-59 5-67 5-68 5-68 5-69 5-69 5-71 5-72 5-72 5-116 5-118 5-120 f.Z BTG BTG BTST BTST.#bit4 Ws.#bit4 Ws.#bit4 Ws.#bit4 Ws.C BSW.Wb Ws.#bit4 Ws. Advance Information DS70030E-page 3-7 .Wb f.#bit4 Ws.Wb Ws.Wb f.

Ws Wb. skip if > Compare (Wb – Wn). skip if clear Bit test f. Wn Wb.#bit4 f. skip if = Compare (Wb – Wn). skip if clear Bit test Ws.#lit5 Wb. Wn Assembly Syntax Conditional skip instructions execute in 1 cycle if the skip is not taken. skip if set Bit test Ws. skip if < Compare (Wb – Wn).Ws f Ws f Wb.#bit4 Ws.#bit4 Ws. DS70030E-page 3-8 Advance Information  2003 Microchip Technology Inc.#lit5 Wb.dsPIC30F Programmer’s Reference Manual Table 3-7: BTSC BTSC BTSS BTSS CP CP CP CP0 CP0 CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE Note: Compare/Skip Instructions Description Bit test f. skip if set Compare (f – WREG) Compare (Wb – lit5) Compare (Wb – Ws) Compare (f – 0x0000) Compare (Ws – 0x0000) Compare with Borrow (f – WREG – C) Compare with Borrow (Wb – lit5 – C) Compare with Borrow (Wb – Ws – C) Compare (Wb – Wn). 2 cycles if the skip is taken over a one-word instruction and 3 cycles if the skip is taken over a two-word instruction. . Wn Wb.#bit4 f Wb. Wn Wb. skip if ≠ Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Cycles(see Note) 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 1 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) Page # 5-60 5-62 5-64 5-65 5-82 5-83 5-84 5-85 5-86 5-87 5-88 5-89 5-91 5-92 5-93 5-94 f.

Expr LTU.Expr GEU.Expr GE.Wn Program Flow Instructions Description Branch unconditionally Computed branch Branch if Carry (no Borrow) Branch if greater than or equal Branch if unsigned greater than or equal Branch if greater than Branch if unsigned greater than Branch if less than or equal Branch if unsigned less than or equal Branch if less than Branch if unsigned less than Branch if Negative Branch if not Carry (Borrow) Branch if not Negative Branch if not Overflow Branch if not Zero Branch if Accumulator A Overflow Branch if Accumulator B Overflow Branch if Overflow Branch if Accumulator A Saturate Branch if Accumulator B Saturate Branch if Zero Call subroutine Call indirect subroutine Do code through PC+Expr.Expr NZ.Expr NC. 2: RETURN instructions execute in 3 cycles.Expr GTU.  2003 Microchip Technology Inc. but if an exception is pending.Expr NN.Expr LEU.Expr N.Expr LE.Section 3.Expr Z.Expr Wn.Expr SA.Expr OB. (lit14+1) times Do code through PC+Expr. they execute in 2 cycles.Expr OV.Expr Expr Wn Expr Wn #lit14 Wn 5-31 5-32 5-33 5-35 5-33 5-37 5-38 5-39 5-40 5-41 5-44 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-73 5-74 5-107 5-109 5-122 5-123 5-196 5-196 5-197 5-198 (2) 1 (2)(1) 1 (2)(1) 1 (2) 1 (2) (1) 1 (2)(1) (1) 1 (2)(1) 1 (2)(1) 1 (2) (1) 1 (2)(1) 1 (2)(1) 1 (2) 1 (2) (1) 1 (2)(1) (1) 3 Instruction Set Overview 1 (2)(1) 1 (2)(1) 1 (2) 2 2 2 2 2 2 2 2 1 1 3 (2) 3 (2)(2) 3 (2) (2) (1) 5-201 5-202 5-203 Note 1: Conditional branch instructions execute in 1 cycle if the branch is not taken.Expr GT. Instruction Set Overview Table 3-8: BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA CALL CALL DO DO GOTO GOTO RCALL RCALL REPEAT REPEAT RETFIE RETLW RETURN #lit10. Advance Information DS70030E-page 3-9 . (Wn+1) times Go to address Go to address indirectly Relative call Computed call Repeat next instruction (lit14+1) times Repeat next instruction (Wn+1) times Return from interrupt enable Return with lit10 in Wn Return from subroutine Words Cycles Page # 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 1 1 1 1 1 1 1 1 2 2 1 (2)(1) 1 (2)(1) 1 (2)(1) 1 (2) (1) Assembly Syntax Expr Wn C. or 2 cycles if the branch is taken.Expr LT.Expr NOV.Expr OA.Expr Expr Wn #lit14.Expr SB.

Wxd Wm*Wm.Wxd.Wy.Acc.Wd Acc.Wxd Ws.Wx.Acc.D POP.Wx.Acc. .Wx.#Slit4.AWB Acc Acc.AWB DS70030E-page 3-10 Advance Information  2003 Microchip Technology Inc.#Slit4. Wyd.Wy.Wx.Wy.Wx.#Slit6 Acc.Wxd.Wx.Acc.Wxd.Acc.AWB Wm*Wm.Wxd.Wxd. Wyd.Wxd.AWB Wm*Wm.Wy.#Slit4.Wy.Wy.Wyd Square to Acc Wm*Wn.D PUSH.Wxd.Wy.Wyd Multiply Wn by Wm to Acc Wm*Wm.Wxd.#Slit4.Acc.Wyd.N MSC NEG SAC SAC.Wy.S ULNK f Ws Wns Shadow/Stack Instructions Description Link frame pointer Pop TOS to f Pop TOS to Wd Double pop from TOS to Wnd:Wnd+1 Pop shadow registers Push f to TOS Push Ws to TOS Push double Wns:Wns+1 to TOS Push shadow registers Unlink frame pointer Words Cycles Page # 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 5-135 5-186 5-187 5-188 5-189 5-190 5-191 5-192 5-193 5-258 #lit14 f Wd Wnd Assembly Syntax Table 3-10: CLRWDT DISI NOP NOPR PWRSAV RESET #lit1 Control Instructions Description Clear Watchdog Timer #lit14 Disable interrupts for (lit14+1) instruction cycles No operation No operation Enter Power Saving mode lit1 Software device RESET Words Cycles Page # 1 1 1 1 1 1 1 1 1 1 1 1 5-79 5-100 5-184 5-185 5-194 5-200 Assembly Syntax Table 3-11: ADD ADD CLR ED EDAC LAC MAC MAC MPY MPY MPY.dsPIC30F Programmer’s Reference Manual Table 3-9: LNK POP POP POP.S PUSH PUSH PUSH.Wyd -(Multiply Wn by Wm) to Acc Wm*Wn.Wx.Wy.Wyd Square and accumulate Move Wx to Wxd and Wy to Wyd Wm*Wn.R SFTAC SFTAC SUB Acc DSP Instructions Description Add accumulators 16-bit signed add to Acc Clear Acc Euclidean distance (no accumulate) Euclidean distance Load Acc Multiply and accumulate Words Cycles Page # 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5-11 5-12 5-77 5-111 5-113 5-133 5-141 5-143 5-159 5-161 5-163 5-165 5-167 5-183 5-216 5-218 5-223 5-224 5-235 Assembly Syntax Ws.Wy.Acc.Acc Wm*Wn.Wyd.Wx.Wd Acc.Wx.Acc.Wn Acc Multiply and subtract from Acc Negate Acc Store Acc Store rounded Acc Arithmetic shift Acc by Slit6 Arithmetic shift Acc by (Wn) Subtract accumulators MOVSAC Acc.Acc Acc.Wx.

.................... 4-26 Assigned Working Register Usage ....................................................17 Data Addressing Modes............4 4..................................................................1 4............ Advance Information DS70030E-page 4-1 ..............................15 4.............................................................................................................10 4.......9 4.................................... 4-16 Using 10-bit Literal Operands ................13 4.....3 4......................... 4-11 Instruction Stalls.................................................................................. 4-33 DSP MAC Instructions ..................................................................................................................................................................................................................................14 4.. 4-19 Software Stack Pointer and Frame Pointer..................................................8 4............................... 4-37 Scaling Data with the FBCL Instruction ..........................................Section 4.................................2 4........................... 4-2 Program Addressing Modes .... 4-37 Normalizing the Accumulator with the FBCL Instruction..................................................16 4......5 4.................12 4....... Instruction Set Details HIGHLIGHTS This section of the manual contains the following major topics: 4...................... 4-25 Z Status Bit................... 4-20 Conditional Branch Instructions ........................................................................................... 4-33 DSP Accumulator Instructions ....................... 4-12 Byte Operations .......................................................................................................................................... 4-39 4 Instruction Set Details  2003 Microchip Technology Inc.........11 4............................................................................... 4-13 Word Move Operations .......................... 4-27 DSP Data Formats ....................................... 4-32 Accumulator Access .......................................................... 4-30 Accumulator Usage.............6 4................................7 4...............................

The address range of each mode is summarized in Table 4-1. register direct or register indirect addressing. when both the file register and WREG are specified in the instruction. which support file register addressing. and store the contents of any working register to any location in data memory. It should be noted that file register addressing supports both byte and word accesses of data memory.2. and also move data between the working registers and the entire 64K data space. Table 4-1: dsPIC30F Addressing Modes Address Range 0x0000 .1 File Register Addressing File register addressing is used by instructions which use a predetermined data address as an operand for the instruction. the operation results are stored in WREG and the contents of the file register are unchanged. “Instruction Set Overview”. along with several forms of immediate addressing. Examples of file register addressing are shown in Example 4-1. Data accesses may be performed using file register. Immediate addressing does not access data memory. .dsPIC30F Programmer’s Reference Manual 4. with the exception of the MOV instruction. which accesses all 64K of memory as words. This allows one to load data from any location in data memory to any working register.2 “Default Working Register (WREG)”). File register addressing provides the ability to operate on data stored in the lower 8K of data memory (Near RAM). Note: Instructions which support file register addressing use ‘f’ as an operand in the instruction summary tables of Section 3. which is called the Near RAM. the MOV instruction provides access to all 64 Kbytes of memory using file register addressing. DS70030E-page 4-2 Advance Information  2003 Microchip Technology Inc. In these cases. but provides the ability to use a constant value as an instruction operand.0xFFFF N/A (constant value) The address range for the File Register MOV is 0x0000 . and immediate addressing allows a fixed value to be used by the instruction. the instruction is effectively a read-modify-write instruction. (see Note) Addressing Mode File Register Register Direct Register Indirect Immediate Note: 0x0000 . The majority of instructions that support file register addressing provide access to the lower 8 Kbytes of data memory. W0:W15.1 Data Addressing Modes The dsPIC30F supports three native Addressing modes for accessing data memory. However. If only one operand is supplied in the instruction.0xFFFE. However.0x1FFF 0x0000 . WREG is an implied operand and the operation results are stored back to the file register. using the contents of the working registers as an effective address. Most instructions. perform an operation on the specified file register and the default working register WREG (see Section 2. Register direct addressing is used to access the 16 memory mapped working registers.0x001F (working register array W0:W15) 4.1. Sample instructions which show the interaction between the file register and WREG are shown in Example 4-2. Register indirect addressing is used to efficiently operate on data stored in the entire 64K data space.

Section 4. Advance Information DS70030E-page 4-3 . AND 0x1000 with WREG. Instruction Set Details Example 4-1: DEC File Register Addressing 0x1000 . W0 . decrement data stored at 0x1000 _ÉÑçêÉ=fåëíêìÅíáçåW Data Memory 0x1000 = 0x5555 ^ÑíÉê=fåëíêìÅíáçåW Data Memory 0x1000 = 0x5554 MOV 0x27FE. store to WREG _ÉÑçêÉ=fåëíêìÅíáçåW W0 (WREG) = 0x332C Data Memory 0x1000 = 0x5555 ^ÑíÉê=fåëíêìÅíáçåW W0 (WREG) = 0x1104 Data Memory 0x1000 = 0x5555 4 Instruction Set Details  2003 Microchip Technology Inc. AND 0x1000 with WREG. WREG . move data stored at 0x27FE to W0 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x5555 Data Memory 0x27FE = 0x1234 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x1234 Data Memory 0x27FE = 0x1234 Example 4-2: AND File Register Addressing and WREG 0x1000 . store to 0x1000 _ÉÑçêÉ=fåëíêìÅíáçåW W0 (WREG) = 0x332C Data Memory 0x1000 = 0x5555 ^ÑíÉê=fåëíêìÅíáçåW W0 (WREG) = 0x332C Data Memory 0x1000 = 0x1104 AND 0x1000.

Wns and Wnd in the summary tables of Section 3. Shift left W6 by W7. Exchange W2 and W3 Example 4-3: EXCH _ÉÑçêÉ=fåëíêìÅíáçåW W2 = 0x3499 W3 = 0x003D ^ÑíÉê=fåëíêìÅíáçåW W2 = 0x003D W3 = 0x3499 IOR #0x44.1. . W3 . so this Addressing mode is useful only when data already resides in the working register core. “Instruction Set Overview”. Since variants of the DO and REPEAT instruction support register direct addressing. Register Direct Addressing W2. “Instruction Set Overview”. and it supports both byte and word accesses. use the symbols Wb. Another feature of register direct addressing is that it provides the ability for dynamic flow control. Sample instructions which utilize register direct addressing are shown in Example 4-3. Instructions which use register indirect addressing. Instructions which employ register direct addressing use the contents of the specified working register as data to execute the instruction. use the symbols Wd and Ws in the summary tables of Section 3. Wn.2 Register Direct Addressing Register direct addressing is used to access the contents of the 16 working registers (W0:W15). The Register Direct Addressing mode is fully orthogonal. W8 . Inclusive-OR 0x44 and W0 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x9C2E ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x9C6E SL W6. W0 . Note: Instructions which must use register direct addressing. W7.dsPIC30F Programmer’s Reference Manual 4. register direct addressing may also be used when register indirect addressing may be used. and store to W8 _ÉÑçêÉ=fåëíêìÅíáçåW W6 = 0x000C W7 = 0x0008 W8 = 0x1234 ^ÑíÉê=fåëíêìÅíáçåW W6 = 0x000C W7 = 0x0008 W8 = 0x0C00 DS70030E-page 4-4 Advance Information  2003 Microchip Technology Inc. Commonly. one may generate flexible looping constructs using these instructions. which allows any working register to be specified for any instruction which uses register direct addressing.

in Word mode. and pre/post-increments add 2 to the EA. Note: The MOV with offset instructions (pages page 151 and page 152) provides a literal addressing offset ability to be used with indirect addressing. This mode does not scale for Word mode instructions. Wn is pre-decremented to form the EA. Table 4-2: Indirect Mode No Modification Pre-Increment Pre-Decrement Post-Increment Indirect Addressing Modes Syntax [Wn] [++Wn] [--Wn] [Wn++] Function (Byte Instruction) EA = [Wn] EA = [Wn+=1] EA = [Wn-=1] EA = [Wn]+= 1 Function (Word Instruction) EA = [Wn] EA = [Wn+=2] EA = [Wn-=2] EA = [Wn]+= 2 Description The contents of Wn forms the EA. This Addressing mode is powerful. then Wn is post-incremented. Example 4-6 shows how these instructions may be used to move data to and from the working register array. and this allows the following updates to be made to the working register: post-increment. then Wn is post-decremented. The contents of Wn forms the EA. that the EA will point to the next adjacent word in memory. Wn and Wb are not modified. 4 Instruction Set Details  2003 Microchip Technology Inc. This mode uses the contents of a second working register to form the EA by adding the two specified working registers. Wn is pre-incremented to form the EA. Example 4-5 shows how register offset indirect addressing may be used to access data memory. Advance Information DS70030E-page 4-5 . because it also allows one to modify the contents of the working register. Since all EAs must be given as byte addresses. register indirect addressing allows for the efficient processing of data that is stored sequentially in memory. the contents of the working register become a pointer to the location in data memory which is to be accessed by the instruction. The modes of indirect addressing supported by the dsPIC30F are shown in Table 4-2. pre/post-decrements subtract 2 from the EA stored in the working register. Note that neither of the working registers used to form the EA are modified. Table 4-2 also shows that the Register Offset mode addresses data which is offset from a base EA stored in a working register. Example 4-4 shows how indirect addressing may be used to update the EA. The contents of Wn forms he EA. post-decrement. The sum of Wn and Wb forms the EA. by incrementing or decrementing the EA. pre-increment and pre-decrement. In these instructions. support is provided for Word mode instructions by scaling the EA update by 2. the EA is formed by adding the contents of a working register to a signed 10-bit literal. but offers the complete offset range of 64 Kbytes. Essentially. This feature ensures that after an EA modification is made.1. Post-Decrement [Wn--] EA = [Wn]-= 1 EA = [Wn]-= 2 Register Offset [Wn+Wb] EA = [Wn+Wb] EA = [Wn+Wb] Table 4-2 shows that four Addressing modes modify the EA used in the instruction.3 Register Indirect Addressing Register indirect addressing is used to access any location in data memory by treating the contents of a working register as an effective address (EA) to data memory.Section 4. By modifying the EA in the same cycle that an operation is being performed. Namely. Instruction Set Details 4. either before or after the data access is made.

pre-dec W5. [--W5]. [++W8] .dsPIC30F Programmer’s Reference Manual Example 4-4: MOV. post-dec W13 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x2300 W13 = 0x2708 Data Memory 0x2300 = 0x7783 Data Memory 0x2708 = 0x904E ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x2301 W13 = 0x2707 Data Memory 0x2300 = 0x7783 Data Memory 0x2708 = 0x9083 ADD W1.B Indirect Addressing with Effective Address Update [W0++]. byte move [W0] to [W13] . pre-inc W8 . store in [W8] _ÉÑçêÉ=fåëíêìÅíáçåW W1 = W5 = W8 = Data Data W1 = W5 = W8 = Data Data 0x0800 0x2200 0x2400 Memory 0x21FE = 0x7783 Memory 0x2402 = 0xAACC 0x0800 0x21FE 0x2402 Memory 0x21FE = 0x7783 Memory 0x2402 = 0x7F83 ^ÑíÉê=fåëíêìÅíáçåW DS70030E-page 4-6 Advance Information  2003 Microchip Technology Inc. . [W13--] . post-inc W0. add W1 to [W5].

B Indirect Addressing with Register Offset [W0+W1]. A .Section 4. (sign-extend and zero-backfill) _ÉÑçêÉ=fåëíêìÅíáçåW W0 = W8 = ACCA Data W0 = W8 = ACCA Data 0x2344 0x0008 = 0x00 7877 9321 Memory 0x234C = 0xE290 0x2344 0x0008 = 0xFF E290 0000 Memory 0x234C = 0xE290 ^ÑíÉê=fåëíêìÅíáçåW Example 4-6: MOV Move with Literal Offset Instructions [W0+0x20]. Instruction Set Details Example 4-5: MOV. move [W0+0x20] to W1 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x1200 W1 = 0x01FE Data Memory 0x1220 = 0xFD27 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x1200 W1 = 0xFD27 Data Memory 0x1220 = 0xFD27 4 Instruction Set Details MOV W4. Advance Information DS70030E-page 4-7 . [W8-0x300] . W1 . [W7++] . load ACCA with [W0+W8] . move W4 to [W8-0x300] _ÉÑçêÉ=fåëíêìÅíáçåW W4 = 0x3411 W8 = 0x2944 Data Memory 0x2644 = 0xCB98 ^ÑíÉê=fåëíêìÅíáçåW W4 = 0x3411 W8 = 0x2944 Data Memory 0x2644 = 0x3411  2003 Microchip Technology Inc. byte move [W0+W1] to W7. post-inc W7 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = W1 = W7 = Data Data W0 = W1 = W7 = Data Data 0x2300 0x01FE 0x1000 Memory 0x24FE = 0x7783 Memory 0x1000 = 0x11DC 0x2300 0x01FE 0x1001 Memory 0x24FE = 0x7783 Memory 0x1000 = 0x1183 ^ÑíÉê=fåëíêìÅíáçåW LAC [W0+W8].

.14 “DSP MAC Instructions”. The majority of instructions which use indirect addressing support the No Modify.1. Post-Increment and Post-Decrement Addressing modes. the Addressing modes offered by the DSP MAC instructions provide greater range in the size of the effective address update which may be made. not every instruction which supports indirect addressing supports all modes shown in Table 4-2. Both of these Addressing modes are powerful features of the dsPIC30F architecture. As is described later in Section 4. Since DSP algorithms frequently demand a broader range of address updates. “Instruction Set Overview”. Table 4-3: DSP MAC Indirect Addressing Modes Addressing Mode Indirect with no modification Indirect with Post-Increment by 2 Indirect with Post-Increment by 4 Indirect with Post-Increment by 6 Indirect with Post-Decrement by 2 Indirect with Post-Decrement by 4 Indirect with Post-Decrement by 6 Indirect with Register Offset Note: X Memory EA = [Wx] EA = [Wx]+= 2 EA = [Wx]+= 4 EA = [Wx]+= 6 EA = [Wx]-= 2 EA = [Wx]-= 4 EA = [Wx]-= 6 EA = [W9 + W12] Y Memory EA = [Wy] EA = [Wy]+= 2 EA = [Wy]+= 4 EA = [Wy]+= 6 EA = [Wy]-= 2 EA = [Wy]-= 4 EA = [Wy]-= 6 EA = [W11 + W12] As described in Section 4. Table 4-3 shows that both X and Y pre-fetches support PostIncrement and Post-Decrement Addressing modes. Similarly. 4. and only W10 and W11 may be used to access Y Memory. only W8 and W9 may be used to access X Memory. are also capable of using the Register Offset Addressing mode.dsPIC30F Programmer’s Reference Manual 4. Pre-Decrement. which can be exploited by any instruction that uses indirect addressing. Due to operation encoding and functional considerations. which can improve the performance of certain algorithms.3. no provisions are made for odd sized EA updates. Modulo buffers remove the need for software to perform address boundary checks. Bit-Reversed addressing allows one to access the elements of a buffer in a non-linear fashion. the DSP MAC class of instructions are capable of performing two fetches from memory using effective addressing. 4. and several accumulator based DSP instructions. DS70030E-page 4-8 Advance Information  2003 Microchip Technology Inc.14 “DSP MAC Instructions”. 4 and 6 bytes. Modulo (or circular) addressing provides an automated means to support circular data buffers in X and/or Y memory. which are commonly used to implement DSP algorithms. Note: Instructions which use register indirect addressing use the operand symbols Wd and Ws in the summary tables of Section 3.1.1 Register Indirect Addressing and the Instruction Set The Addressing modes presented in Table 4-2 demonstrate the Indirect Addressing mode capability of the dsPIC30F.3 Modulo and Bit-Reversed Addressing Modes The dsPIC30F provides support for two special Register Indirect Addressing modes.3. Since DSP instructions only execute in Word mode. The MOV instructions. Pre-Increment. with updates of 2. This Addressing mode simplifies data re-ordering for radix-2 FFT algorithms and provides a significant reduction in FFT processing time.2 DSP MAC Indirect Addressing Modes A special class of Indirect Addressing modes is utilized by the DSP MAC instructions.1. Refer to the dsPIC30F MCU Family Reference Manual for details on using Modulo and Bit-Reversed addressing.3.

LNK. BTSTS. #lit4 and #Slit4). AND. 4-bit (#bit4. IOR. Constants may be signed or unsigned and the symbols #Slit4. Instruction Set Details 4. Constants of size 1-bit (#lit1). SUBB. Advance Information DS70030E-page 4-9 . BTST. SAC.Z ASR. the instruction encoding contains a predefined constant operand.SU. ADDC. 6-bit (#Slit6). CP. The size of the immediate operand which may be used varies with the instruction type. BTSS. CPB. This Addressing mode may be used independently. DO. ADDC. BTST. BTST. SUB. SAC. LSR. All other immediate constants are unsigned. Table 4-4 shows the usage of each immediate operand in the instruction set. but it is more frequently combined with the File Register. which is used by the instruction. XOR MOV DISI. BSET. RETLW. SUBBR.Z. SUBR. 14-bit (#lit14) and 16-bit (#lit16) may be used. REPEAT MOV Immediate Operands in the Instruction Set Instruction Usage 4 Instruction Set Details  2003 Microchip Technology Inc.Section 4.C. 10-bit (#lit10 and #Slit10). CP. LAC. #Slit6 and #Slit10 designate a signed constant.R ADD.UU. SL ADD. 5-bit (#lit5). BTSC. MUL. MUL. BTSTS. XOR SFTAC MOV. BTG. SUBB. BTSTS. Table 4-4: Operand #lit1 #bit4 #lit4 #Slit4 #lit5 #Slit6 #lit8 #lit10 #Slit10 #lit14 #lit16 PWRSAV BCLR.B ADD.4 Immediate Addressing In immediate addressing. 8-bit (#lit8). CPB. IOR.1. SUB.C. AND. Direct and Indirect Addressing modes.

Enter IDLE mode ADD. [W1++] . 4 and 6) Indirect Post-Decrement (2. Post-increment W1 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0xFFFF W1 = 0x0890 Data Memory 0x0890 = 0x0032 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0xFFFF W1 = 0x0892 Data Memory 0x0890 = 0xFFFE 4. . 4 and 6) Register Offset DS70030E-page 4-10 Advance Information  2003 Microchip Technology Inc. Several examples of immediate addressing are shown in Example 4-7.dsPIC30F Programmer’s Reference Manual The syntax for immediate addressing requires that the number sign (#) must immediately precede the constant operand value. Add 0x10 to W0 (byte mode) _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x12A9 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x12B9 XOR W0. Example 4-7: PWRSAV #1 Immediate Addressing .B #0x10. If an out-of-range constant is used with an instruction. The "#" symbol indicates to the assembler that the quantity is a constant. Figure 4-1: Data Addressing Mode Tree Immediate File Register Basic Direct Indirect No Modification Pre-Increment Pre-Decrement Post-Increment Post-Decrement Data Addressing Modes Literal Offset Register Offset Direct DSP MAC No Modification Post-Increment (2. the assembler will generate an error. #1. Store the result to [W1] . Exclusive-OR W0 and 0x1 . W0 .1.5 Data Addressing Mode Tree The Data Addressing modes of the dsPIC30F are summarized in Figure 4-1.

and it may be loaded in several ways. When DO looping is active. Table 4-5 summarizes the instructions which modify the PC of the dsPIC30F. CALL and GOTO. which is stored in the interrupt vector table. The change to the PC may be from an immediate value encoded in the instruction. Expr(1) (Branch Conditionally) CALL Expr(1) (Call Subroutine) CALL Wn (Call Subroutine Indirect) GOTO Expr(1) (Unconditional Jump) GOTO Wn (Unconditional Indirect Jump) RCALL Expr(1) (Relative Call) RCALL Wn (Computed Relative Call) Exception Handling PC = Target REPEAT instruction (REPEAT Looping) PC = DOEND address (DO Looping) (1) 4 Instruction Set Details Note 1: For BRA. When required. or expression. the Expr may be a label. the PC is loaded with the address of the exception handler.  2003 Microchip Technology Inc. 3: After an exception is processed. the PC is loaded with the address stored in the DOSTART register. See Section 5. which is resolved by the linker to a 16-bit or 23-bit value (Slit16 or lit23).Section 4.2 Program Addressing Modes The dsPIC30F has a 23-bit Program Counter (PC). the software stack is used to return scope to the foreground process from where the change in program flow occurred. it is recommended that RCALL be used instead of CALL. Several methods may be used to modify the PC in a non-sequential manner. RETURN or RETLW will pop the top-of-stack back into the PC. each instruction word consumes two locations in program memory. the PC is loaded with PC+2. This means that during serial execution. and both absolute and relative changes may be made to the PC. after the instruction at the DOEND address is executed. 2: After CALL or RCALL is executed. When performing function calls. The PC addresses the 24-bit wide program memory to fetch instructions for execution. absolute address. since RCALL only consumes 1 word of program memory. Table 4-5: Methods of Modifying Program Flow PC Modification PC = PC + 2 PC = PC + 2*Slit16 PC = PC + 2 (condition false) PC = PC + 2*Slit16 (condition true) PC = lit23 PC = Wn PC = lit23 PC = Wn PC = PC + 2*Slit16 PC = PC + 2*Wn Software Stack Usage None None None PC+4 is pushed on the stack(2) PC+2 is pushed on the stack(2) None None PC+2 is pushed on the stack(2) PC+2 is pushed on the stack(2) PC = address of the exception handler PC+2 is pushed on the (read from vector table) stack(3) PC not modified (if REPEAT active) PC = DOSTART (if DO active) None None Condition/Instruction Sequential Execution BRA Expr (Branch Unconditionally) BRA Condition. RETFIE will pop the top-of-stack back into the PC. or a dynamic value contained in a working register. “Instruction Descriptions” for details. For exception handling. For byte compatibility with the Table Read and Table Write instructions. Instruction Set Details 4. Advance Information DS70030E-page 4-11 .

W MOV. W1. W3 Destination Address Mode Using Wn Direct Indirect Indirect Indirect Indirect with pre/post-modification Direct Direct Indirect Indirect Indirect with pre/post-modification Indirect with pre/post-modification Note 1: When stalls are detected. a set of rules are applied to decide whether or not to stall the instruction by one cycle. W3 W0. An example of a RAW dependency would be a write operation that modifies W5. 4. W1. W2 [W2].dsPIC30F Programmer’s Reference Manual 4.W MOV. W3 W0.W MOV. W2 [W2++]. [W2++] W2.W ADD. DS70030E-page 4-12 Advance Information  2003 Microchip Technology Inc.W MOV.W MOV. W3 W0. [W2++] [W2].W ADD. followed by a read operation that uses W5 as an address pointer. W1. W3(2) W0. W1.W MOV. the core determines if any address register dependency is imminent across an instruction boundary. ’Read After Write’ (RAW) dependencies occur across instruction boundaries and are detected by the hardware. [W2] W2. the X data space read and write accesses are partially pipelined.W ADD.3.1 RAW Dependency Detection During the instruction pre-decode. W1. W1. the contents of W2 = the mapped address of W2 (0x0004). W3 W0. W1. W1. [W2](2) [W2].W ADD.W MOV.W ADD.W MOV. [W2] [W2++]. W3(2) W0. Table 4-6 lists various RAW conditions which cause an instruction execution stall. A consequence of this pipelining is that address register data dependencies may arise between successive read and write operations using common registers. W3 W0. W3 W0. W1.W ADD.W Examples (Wn = W2) W0. W2 W2.W MOV. W3 W0. [W2](2) [W2++]. one cycle is added to the instruction execution time.W ADD. [W2] [W2]. . When a match between the destination and source registers is identified.W MOV. This problem is resolved by stalling the instruction execution for one instruction cycle. 2: For these examples.W ADD. The stall detection logic compares the W register (if any) used for the destination EA of the instruction currently being executed with the W register to be used by the source EA (if any) of the pre-fetched instruction. [W2++] [W2++]. The contents of W5 will not be valid for the read operation until the earlier write completes. W1. which allows the write to complete before the next read is started. W3 W0. Table 4-6: Raw Dependency Rules (Detection By Hardware) Source Address Mode Using Wn Direct Direct Indirect Indirect with pre/post-modification Direct Indirect Indirect with pre/post-modification Indirect Indirect with pre/post-modification Indirect Indirect with pre/post-modification Stall Required ? No Stall No Stall No Stall No Stall No Stall Stall(1) Stall(1) Stall(1) Stall(1) Stall(1) Stall(1) ADD.W ADD.W ADD.3 Instruction Stalls In order to maximize the data space EA calculation and operand fetch time.W MOV. W1.

the following rules apply: • all direct working register references use the Least Significant Byte of the 16-bit working register and leave the Most Significant Byte unchanged • all indirect working register references use the data byte specified by the 16-bit address stored in the working register • all file register references use the data byte specified by the byte address • the Status Register is updated to reflect the result of the byte operation It should be noted that data addresses are always represented as byte addresses.B W0 W0 4 Instruction Set Details  2003 Microchip Technology Inc. most of the base instructions may operate in either Byte mode or Word mode. For example. 4. higher address (as shown in Figure 4-2). which means that words are stored with the Least Significant Byte at the lower address.b CLR.3.3. the second cycle of the instruction will initiate a stall. Example 4-8 shows sample byte move operations and Example 4-9 shows sample byte math operations. the last cycle of the previous instruction will initiate a stall. loop exit and also during loop processing. 4. just like any other instruction.B” instruction extension to specify a byte instruction. Stalls may occur on loop entry. the native data format is little-endian. Note: Instructions which operate in Byte mode must use the “. the following two instructions are valid forms of a byte clear operation: CLR.Section 4.4 Instruction Stalls and DO/REPEAT Loops Instructions operating in a DO or REPEAT loop are subject to instruction stalls. GOTO.2 Instruction Stalls and Exceptions In order to maintain deterministic operation. Instruction Set Details 4. 4. just like any other instruction. 4. even if they occur immediately prior to exception processing. be subject to an instruction stall if the source read of the subsequent instruction uses W15.3. RETFIE and RETURN instructions are never subject to an instruction stall because they do not perform write operations to the working registers. instruction stalls are allowed to happen. therefore. and the Most Significant Byte at the adjacent. Should a data dependency be detected in the instruction immediately before the PSV data access. Additionally. When these instructions operate in Byte mode. Advance Information DS70030E-page 4-13 .5 Instruction Stalls and PSV Instructions operating in PSV address space are subject to instruction stalls.b” or “. Note: Refer to the dsPIC30F Family Reference Manual for more detailed information about RAW instruction stalls. Should a data dependency be detected in the instruction immediately following the PSV data access.3 Instruction Stalls and Instructions that Change Program Flow CALL and RCALL write to the stack using W15 and may.4 Byte Operations Since the dsPIC30F data memory is byte addressable.3.

then post-inc W1 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x1234 W1 = 0x1001 Data Memory 0x1000 = 0x5555 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x1234 W1 = 0x1002 Data Memory 0x1000 = 0x3455 DS70030E-page 4-14 Advance Information  2003 Microchip Technology Inc.B 0x1000.B W0.B Sample Byte Move Operations #0x30. move the byte at 0x1000 to W0 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x5555 Data Memory 0x1000 = 0x1234 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x5534 Data Memory 0x1000 = 0x1234 MOV.B W0. byte move W0 to [W1]. . [W1++] . move the literal byte 0x30 to W0 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x5555 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x5530 MOV. W0 . byte move W0 to address 0x1001 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x1234 Data Memory 0x1000 = 0x5555 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x1234 Data Memory 0x1000 = 0x3455 MOV.dsPIC30F Programmer’s Reference Manual Example 4-8: MOV. W0 . 0x1001 .

store to [W2] .B W0. W1. byte subtract literal 0x10 from W0 . Advance Information DS70030E-page 4-15 . #0x10. W1 . and post-inc W2 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = W1 = W2 = Data W0 = W1 = W2 = Data 0x1234 0x5678 0x1000 Memory 0x1000 = 0x5555 0x1234 0x5678 0x1001 Memory 0x1000 = 0x55AC ^ÑíÉê=fåëíêìÅíáçåW 4 Instruction Set Details  2003 Microchip Technology Inc.B W0. byte add W0 and W1. then post-dec W6 _ÉÑçêÉ=fåëíêìÅíáçåW W6 = 0x1001 Data Memory 0x1000 = 0x5555 ^ÑíÉê=fåëíêìÅíáçåW W6 = 0x1000 Data Memory 0x1000 = 0x0055 SUB.Section 4. [W2++] . Instruction Set Details Example 4-9: CLR.B Sample Byte Math Operations [W6--] . and store to W1 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x1234 W1 = 0xFFFF ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x1234 W1 = 0xFF24 ADD. byte clear [W6].

all double-words must be word aligned. they may be specified with an optional “. Example 4-10 contains several legal word move operations. Likewise. the Least Significant address bit must be ‘0’.byte stored at 0x1003 b3:b2 . Figure 4-2 shows how bytes and words may be aligned in data memory.dsPIC30F Programmer’s Reference Manual 4.W” extension. If a word move is made to or from an odd address.5 Word Move Operations Even though the dsPIC30F data space is byte addressable. . When an exception is generated due to a misaligned access.w CLR. if desired.byte stored at 0x1000 b1 . This means that for all source and destination operands. all move operations made in Word mode must be word aligned. If the illegal access occurs from a data read. the operation will be allowed to complete. Example 4-11 contains several illegal word move operations. the following instructions are valid forms of a word clear operation: CLR CLR. the exception is taken after the instruction executes.word stored at 0x1005:1004 (b2 is LSB) b7:b4 . However. but the Least Significant bit of the source address will be cleared to force word alignment. Figure 4-2: Data Alignment in Memory 0x1001 0x1003 0x1005 0x1007 0x1009 0x100B b1 b3 b5 b7 b0 b2 b4 b6 b8 Legend: b0 . For example. If the illegal access occurs during a data write.byte stored at 0x100A 0x1000 0x1002 0x1004 0x1006 0x1008 0x100A Note: Instructions which operate in Word mode are not required to use an instruction extension.W W0 W0 W0 DS70030E-page 4-16 Advance Information  2003 Microchip Technology Inc. the write will be inhibited.w” or “. an address error exception is generated.double-word stored at 0x1009:0x1006 (b4 is LSB) b8 .

W0 . W0 W0 = 0x5555 _ÉÑçêÉ=fåëíêìÅíáçåW ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x0030 MOV 0x1000. word move [W0] to [W1]. [W1++] . move the literal word 0x30 to W0 #0x30. Advance Information DS70030E-page 4-17 . Instruction Set Details Example 4-10: MOV Legal Word Move Operations . then post-inc W1 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = W1 = Data Data W0 = W1 = Data Data 0x1234 0x1000 Memory 0x1000 = 0x5555 Memory 0x1234 = 0xAAAA 0x1234 0x1002 Memory 0x1000 = 0xAAAA Memory 0x1234 = 0xAAAA ^ÑíÉê=fåëíêìÅíáçåW 4 Instruction Set Details  2003 Microchip Technology Inc.Section 4. move the word at 0x1000 to W0 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x5555 Data Memory 0x1000 = 0x1234 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x1234 Data Memory 0x1000 = 0x1234 MOV [W0]. .

. 0x1001 . . move the word at 0x1001 to W0 0x1001.dsPIC30F Programmer’s Reference Manual Example 4-11: MOV Illegal Word Move Operations . W0 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x5555 Data Memory 0x1000 = 0x1234 Data Memory 0x1002 = 0x5678 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x1234 Data Memory 0x1000 = 0x1234 Data Memory 0x1002 = 0x5678 ^aaobpp=boolo=qo^m=dbkbo^qba EëçìêÅÉ=~ÇÇêÉëë=áë=ãáë~äáÖåÉÇI=ëç=MOV=áë=éÉêÑçêãÉÇF MOV W0. word move [W0] to [W1]. [W1++] . then post-inc W1 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = W1 = Data Data Data W0 = W1 = Data Data Data 0x1235 0x1000 Memory 0x1000 = 0x1234 Memory 0x1234 = 0xAAAA Memory 0x1236 = 0xBBBB 0x1235 0x1002 Memory 0x1000 = 0xAAAA Memory 0x1234 = 0xAAAA Memory 0x1236 = 0xBBBB ^ÑíÉê=fåëíêìÅíáçåW ^aaobpp=boolo=qo^m=dbkbo^qba EëçìêÅÉ=~ÇÇêÉëë=áë=ãáë~äáÖåÉÇI=ëç=MOV=áë=éÉêÑçêãÉÇF DS70030E-page 4-18 Advance Information  2003 Microchip Technology Inc. move W0 to the word at 0x1001 _ÉÑçêÉ=fåëíêìÅíáçåW W0 = 0x1234 Data Memory 0x1000 = 0x5555 Data Memory 0x1002 = 0x6666 ^ÑíÉê=fåëíêìÅíáçåW W0 = 0x1234 Data Memory 0x1000 = 0x5555 Data Memory 0x1002 = 0x6666 ^aaobpp=boolo=qo^m=dbkbo^qba= EÇÉëíáå~íáçå=~ÇÇêÉëë=áë=ãáë~äáÖåÉÇI=ëç=MOV=áë=åçí=éÉêÑçêãÉÇF MOV [W0].

Illegal syntax for byte mode add 15 to W0 add 127 to W0 ERROR. add 128 (or -128) to W0 ERROR. RETLW. since the Most Significant bit of the byte is set.e.. W0 #0xF.B ADD. Example 4-12 shows how positive and negative literals are used in Byte mode for the ADD instruction. ADDC.B ADD. . Illegal syntax for byte mode add 255 (or -1) to W0 ERROR.B ADD. .. #-10).. . . For byte instructions.Section 4. When operating in Byte mode. .B ADD.B ADD. So when 10-bit literals are used in Byte mode. Instructions which employ 10-bit literals in Byte and Word mode are: ADD. Illegal syntax for byte mode Byte Mode kkkk kkkk 0000 0000 0000 0001 0000 0010 0111 1111 1000 0000 1111 1111 N/A N/A N/A Note: Using a literal value greater than 127 in Byte mode is functionally identical to using the equivalent negative two’s complement value. . 4 Instruction Set Details  2003 Microchip Technology Inc. W0 . W0 #0x3FF..B ADD. Table 4-7: Literal Value 0 1 2 127 128 255 256 512 1023 Example 4-12: ADD. SUB.. W0 #0x7F. SUBB and XOR. AND. IOR. Instruction Set Details 4. the range of the operand must be reduced to 8-bits or the assembler will generate an error. a 10-bit literal is too large to use.B 10-bit Literal Coding Word Mode kk kkkk kkkk 00 0000 0000 00 0000 0001 00 0000 0010 00 0111 1111 00 1000 0000 00 1111 1111 01 0000 0000 10 0000 0000 11 1111 1111 Using 10-bit Literals For Byte Operands #0x80. W0 #0x380. the Assembler will accept either a positive or negative literal value (i.6 Using 10-bit Literal Operands Several instructions which support Byte and Word mode have 10-bit operands.. W0 #0x100. W0 #0xFF. Table 4-7 shows that the range of a 10-bit literal is 0:1023 in Word mode and 0:255 in Byte mode.. Advance Information DS70030E-page 4-19 .

as shown in Figure 4-3. the Most Significant 7 bits of the PC are zero-extended before the push is made. working from lower addresses towards higher addresses. the contents of W0 can be pushed onto the top-of-stack (TOS) by PUSH W0 This syntax is equivalent to MOV W0.7 4. with W15 used as the destination pointer. program flow may resume from the correct location. During exception processing.7. it is initialized to 0x0800. When the PC is pushed onto the stack. The user may reprogram the SP during initialization to any location within data space. It pre-decrements for a stack pop (read) and post-increments for a stack push (write). This ensures that the SP will point to valid RAM in all dsPIC30F devices and permits stack availability for exceptions. This allows the primary Status Register contents and CPU Interrupt Priority Level to be automatically preserved during interrupts.dsPIC30F Programmer’s Reference Manual 4. When PC<22:16> is pushed. . Note: In order to protect against misaligned stack accesses. which may occur before the SP is set by the user software.[W15++] The contents of the TOS can be returned to W0 by POP W0 This syntax is equivalent to MOV [--W15]. The software stack is manipulated using the PUSH and POP instructions. The PUSH and POP instructions are the equivalent of a MOV instruction. DS70030E-page 4-20 Advance Information  2003 Microchip Technology Inc. such that when the subroutine completes execution.1 Software Stack Pointer and Frame Pointer Software Stack Pointer The dsPIC30F features a software stack which facilitates function calls and exception handling. the PC is pushed onto the stack. For example. then PC<22:16> is pushed. the upper nine bits of the second pushed word contains the SRL and IPL<3>. CORCON<3>. the Most Significant 7 bits of the PC are concatenated with the lower byte of the Status Register (SRL) and IPL<3>. Figure 4-3: 0x0000 Stack Operation for CALL Instruction 15 Stack Grows Towards Higher Address 0 PC<15:0> 0x0 PC<22:16> Top-of-Stack W15 (before CALL) W15 (after CALL) 0xFFFE Note: For exceptions. PC<15:0> is pushed onto the first available stack word. The SP always points to the first available free word (top-of-stack) and fills the software stack.W0 During any CALL instruction. W15<0> is always clear. W15 is the default Stack Pointer (SP) and after any RESET.

7. W1 W0 W1 W3 Figure 4-4: Stack Pointer Before The First PUSH 0x0000 0x0800 <TOS> W15 (SP) 0xFFFE W0 = 0x5A5A W1 = 0x3636 W15 = 0x0800 Figure 4-5: Stack Pointer After "PUSH W0" Instruction 4 0x0000 Instruction Set Details 0x0800 0x0802 5A5A <TOS> W15 (SP) 0xFFFE W0 = 0x5A5A W1 = 0x3636 W15 = 0x0802  2003 Microchip Technology Inc. Furthermore. . . Load W0 Load W1 Push W0 Push W1 Pop TOS with 0x5A5A with 0x3636 to TOS (see Figure 4-5) to TOS (see Figure 4-6) to W3 (see Figure 4-7) #0x5A5A. respectively. Example 4-13: MOV MOV PUSH PUSH POP Stack Pointer Usage . the example loads 0x5A5A and 0x3636 to W0 and W1. W15 is automatically updated to point to the next available stack location. the final TOS is 0x0802. The stack is pushed for the first time in Figure 4-5 and the value contained in W0 is copied to TOS. . the contents of W1 are pushed onto the stack. Instruction Set Details 4. W0 #0x3636. and the new TOS becomes 0x0804. Advance Information DS70030E-page 4-21 . The SP is decremented during the POP operation. and the new TOS is 0x0802. In Figure 4-7.Section 4. Note that the SP has the initialized value of 0x0800.2 Stack Pointer Example Figure 4-4 through Figure 4-7 show how the software stack is modified for the code snippet shown in Example 4-13. . Figure 4-4 shows the software stack before the first PUSH has executed. which copies the last pushed value (W1) to W3. In Figure 4-6. the stack is popped. and at the end of the example.

the new TOS. the ULNK instruction is used to remove the stack frame created by the LNK instruction. The LNK and ULNK instructions must always be used together to avoid stack overflow. The LNK instruction is used to create a stack frame. W14 is the default Stack Frame Pointer (FP) and it is initialized to 0x0000 on any RESET. . W14 may be used like any other working register. 4.7. DS70030E-page 4-22 Advance Information  2003 Microchip Technology Inc. After the function completes execution.3 Software Stack Frame Pointer A stack frame is a user defined section of memory residing in the software stack. remain unchanged (0x3636).dsPIC30F Programmer’s Reference Manual Figure 4-6: Stack Pointer After "PUSH W1" Instruction 0x0000 0x0800 0x0802 0x0804 5A5A 3636 <TOS> W15 (SP) 0xFFFE W0 = 0x5A5A W1 = 0x3636 W15 = 0x0804 Figure 4-7: Stack Pointer After "POP W3" Instruction 0x0000 0x0800 0x0802 0x0804 5A5A <TOS> W15 (SP) 0xFFFE W0 = 0x5A5A W1 = 0x3636 W3 = 0x3636 W15 = 0x0802 Note: The contents of 0x802. such that the stack may be used to store temporary variables utilized by the called function. It is used during a call sequence to adjust the SP. The link (LNK) and unlink (ULNK) instructions provide stack frame functionality. It is used to allocate memory for temporary variables which a function uses and one stack frame may be created for each function. If the stack frame pointer is not used.

The ULNK instruction returns the stack back to the state shown in Figure 4-9. allocate 4 bytes for local variables . Advance Information DS70030E-page 4-23 ...Section 4. which reserves memory for two words of temporary data (Figure 4-10). . . the literal 4 is added to the stack pointer address in W15. W1 and W2) are pushed on the stack. A RETURN instruction will return to the code that called the subroutine. Here.4 Stack Frame Pointer Example Figure 4-8 through Figure 4-10 show how a stack frame is created and removed for the code snippet shown in Example 4-14. Function "COMPUTE" then uses the "LNK #4" instruction to push the calling routine’s frame pointer value onto the stack and the new frame pointer will be set to point to the current stack pointer. [W14+n] will access the temporary variables used by the routine and [W14-n] is used to access the parameters. Stack FP.. At the end of the function. Example 4-14: TASKA: .. . Instruction Set Details 4.. the FP is used to access the function parameters and temporary (local) variables. . The calling code is responsible for removing the parameters from the stack. Return to TASKA 4 Instruction Set Details Figure 4-8: Stack at the Beginning of Example 4-14 0x0000 0x0800 Frame of TASKA <TOS> W14 (FP) W15 (SP) 0xFFFE  2003 Microchip Technology Inc. Free allocated memory. the ULNK instruction is used to copy the frame pointer address to the stack pointer and then pop the calling subroutine’s frame pointer back to the W14 register. Push parameter 1 Push parameter 2 Push parameter 3 Call COMPUTE function Pop parameter 3 Pop parameter 2 Pop parameter 1 COMPUTE: LNK #4 . before any registers are pushed to the stack. ULNK RETURN . After the "CALL COMPUTE" instruction is executed. Inside the function "COMPUTE". Then. the PC changes to the address of "COMPUTE" and the return address of the function "TASKA" is placed on the stack (Figure 4-9)..7. W15 points to the first free stack location (TOS) and W14 points to a portion of stack memory allocated for the routine that is currently executing. Before calling the function "COMPUTE". restore original FP . . Frame Pointer Usage W0 W1 W2 COMPUTE W2 W1 W0 . the parameters of the function (W0. . Figure 4-8 shows the stack condition at the beginning of the example. The RETURN and POP instructions restore the stack to the state shown in Figure 4-8. PUSH PUSH PUSH CALL POP POP POP .

6 Stack Pointer Underflow The stack is initialized to 0x0800 during RESET.dsPIC30F Programmer’s Reference Manual Figure 4-9: Stack After "CALL COMPUTE" Executes 0x0000 0x0800 Frame of TASKA Parameter 1 Parameter 2 Parameter 3 PC<15:0> 0:PC<22:16> <TOS> W14 (FP) W15 (SP) 0xFFFE Figure 4-10: Stack After "LNK #4" Executes 0x0000 0x0800 Frame of TASKA Parameter 1 Parameter 2 Parameter 3 PC<15:0> 0:PC<22:16> FP of TASKA Temp Word 1 Temp Word 2 <TOS> 0xFFFE W14 (FP) W15 (SP) 4. DS70030E-page 4-24 Advance Information  2003 Microchip Technology Inc. because all stack operations must be word aligned. in general. All effective addresses generated using W15 as a source or destination are compared against the value in SPLIM. after which time it can only be disabled by a device RESET. SPLIM is a 16-bit register. but SPLIM<0> is fixed to ‘0’. a stack error trap will also occur if the W15 effective address calculation wraps over the end of data space (0xFFFF).7. . Should the effective address be greater than the contents of SPLIM. reserved for core and peripheral special function registers. Note: Locations in data space between 0x0000 and 0x07FF are.5 Stack Pointer Overflow There is a stack limit register (SPLIM) associated with the stack pointer that is reset to 0x0000.7. A stack error trap will be initiated should the stack pointer address ever be less than 0x0800. Refer to the dsPIC30F Family Reference Manual for more information on the stack error trap. then a stack error trap is generated. 4. The stack overflow check will not be enabled until a word write to SPLIM occurs. If stack overflow checking has been enabled.

but they may be employed effectively after any operation that modifies the Status Register. If the result of the Status Register test is true. CPSGT. while in other cases. perform a subtract operation (minuend subtrahend). compare instructions just update the flags in the Status Register. CPSNE) do not modify the Status Register. based on the contents of the Status Register. Instead.Section 4. SA and SB condition mnemonics. Expr. a complex logic operation is performed (as in BRA GT). Instruction Set Details 4.8 Conditional Branch Instructions Conditional branch instructions are used to direct program flow. OB. It is worth noting that both signed and unsigned conditional tests are supported. just a single bit is tested (as in BRA C). CP0 and CPB. If the result of the Status Register test is false. Expr. Table 4-8: Condition Mnemonic(1) C GE GEU(2) GT GTU LE LEU LT LTU(3) N NC NN NOV NZ OA OB OV SA SB Z Conditional Branch Instructions Description Carry (not Borrow) Signed greater than or equal Unsigned greater than or equal Signed greater than Unsigned greater than Signed less than or equal Unsigned less than or equal Signed less than Unsigned less than Negative Not Carry (Borrow) Not Negative Not Overflow Not Zero Accumulator A overflow Accumulator B overflow Overflow Accumulator A saturate Accumulator B saturate Zero C (N&&OV) || (N&&OV) C (Z&&N&&OV) || (Z&&N&&OV) C&&Z Z || (N&&OV) || (N&&OV) C || Z (N&&OV) || (N&&OV) C N C N OV Z OA OB OV SA SB Z Status Test 4 Instruction Set Details Note 1: Instructions are of the form: BRA mnemonic. Note: The “Compare and Skip” instructions (CPSEQ. 2: GEU is identical to C and will reverse assemble to BRA C. This table identifies the condition in the Status Register which must be true for the branch to be taken. CPSLT.  2003 Microchip Technology Inc. the branch is taken. and that support is provided for DSP algorithms with the OA. These instructions are generally used in conjunction with a Compare class instruction. the branch is not taken. In some cases. Expr. The conditional branch instructions supported by the dsPIC30F devices are shown in Table 4-8. 3: LTU is identical to NC and will reverse assemble to BRA NC. Advance Information DS70030E-page 4-25 . such that an ensuing conditional branch instruction may change program flow by testing the contents of the updated Status Register. The compare instructions CP. but do not actually store the result of the subtraction.

It shows how the Z bit is affected for a 32-bit addition implemented with an ADD/ADDC instruction sequence. regardless of the result of subsequent ADDC. If the result of one of these instructions is non-zero. W2. SUBB or SUBBR instructions. A sequence of instructions working on multi-precision data (starting with an instruction with no carry/borrow input) will automatically logically AND the successive results of the zero test. the Z bit can only be cleared and never set. W3. SUBB and SUBBR instructions.C=1) ^ÑíÉê=POJÄáí=^ÇÇáíáçåW _ÉÑçêÉ=POJÄáí=^ÇÇáíáçå=EòÉêç=êÉëìäí=Ñçê=iptçêÇ=~åÇ=jptçêÇFW W0 W1 W2 W3 W4 W5 SR W0 W1 W2 W3 W4 W5 SR = = = = = = = = = = = = = = 0xB76E 0xFB7B 0x4892 0x0484 0x0000 0x0000 0x0000 0xB76E 0xFB7B 0x4892 0x0485 0x0000 0x0000 0x0103 (DC. If the result of the ADDC. SUBB or SUBBR operations. CPB. CPB. . Add LSWord and store to W4 ADDC W1. Example 4-15: ’Z’ Status bit Operation for 32-bit Addition .C=1) ^ÑíÉê=POJÄáí=^ÇÇáíáçåW DS70030E-page 4-26 Advance Information  2003 Microchip Technology Inc. Add MSWord and store to W5 _ÉÑçêÉ=POJÄáí=^ÇÇáíáçå=EòÉêç=êÉëìäí=Ñçê=jptçêÇFW W0 W1 W2 W3 W4 W5 SR W0 W1 W2 W3 W4 W5 SR = = = = = = = = = = = = = = 0x2342 0xFFF0 0x39AA 0x0010 0x0000 0x0000 0x0000 0x2342 0xFFF0 0x39AA 0x0010 0x5CEC 0x0000 0x0201 (DC. and the second example generates a zero result for both the LSWord and MSWord. CPB. Store the result in W5:W4 ADD W0. except those that use the carry/borrow input (ADDC. W4 . Add two doubles (W0:W1 and W2:W3) .dsPIC30F Programmer’s Reference Manual 4. W5 . CPB. Example 4-15 shows how the Z bit operates for a 32-bit addition. CPB. The first example generates a zero result for only the MSWord. This allows the Z bit to be used for performing a simple zero check on the result of a series of extended precision operations. All results must be zero for the Z flag to remain set at the end of the sequence of operations. For the ADDC.9 Z Status Bit The Z status bit is a special zero status bit that is useful for extended precision arithmetic. SUBB or SUBBR instruction is non-zero. SUBB and SUBBR). The Z bit functions like a normal Z flag for all instructions. the Z bit will be cleared and remain cleared for all subsequent ADDC.Z. the Z bit will be cleared and will remain cleared.

1 Implied DSP Operands To assist instruction encoding and maintain uniformity among the DSP class of instructions. a stable run-time environment and backwards compatibility with earlier Microchip processor cores. some working registers have pre-assigned functionality. RCALL. ED.10 Assigned Working Register Usage The 16 working registers of the dsPIC30F provide a large register set for efficient code generation and algorithm implementation. Advance Information DS70030E-page 4-27 . Instruction Set Details 4. RETLW. POP. EDAC.15 “DSP Accumulator Instructions”).15 “DSP Accumulator Instructions”) are not required to follow the working register assignments in Table 4-9 and may freely use any working register when required. For all DSP instructions which have pre-fetch ability. MAC. with details provided in subsections Section 4.10. they may still be used as generic operands in any instruction.10. LNK.1 “Implied DSP Operands”.3 “PICmicro® Microcontroller Compatibility”. extreme care must be taken such that the run-time environment is not corrupted. The DSP Accumulator class of instructions (described in Section 4. Even though W14 and W15 have this implied usage. some working registers have a pre-assigned usage. If W14 and W15 must be used for other purposes (it is strongly advised that they remain reserved for the Frame and Stack pointer). MPY.  2003 Microchip Technology Inc. Table 4-9 summarizes these working register assignments.10. Divide Quotient Divide Remainder “MUL f” Product Least Significant Word “MUL f” Product Most Significant Word MAC Operand MAC Operand MAC Operand MAC Operand MAC Pre-fetch Address (X Memory) MAC Pre-fetch Address (X Memory) MAC Pre-fetch Address (Y Memory) MAC Pre-fetch Address (Y Memory) MAC Pre-fetch Offset MAC Write Back Destination Frame Pointer Stack Pointer Register W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 4. which utilize working registers and have pre-fetch ability (described in Section 4. MPY.10. with the exceptions outlined in Section 4.1 “Implied DSP Operands” through Section 4. The affected instructions are CLR. Table 4-9: Special Working Register Assignments Special Assignment Default WREG.Section 4. W14 is the implied frame pointer (used by the LNK and ULNK instructions) and W15 is the implied stack pointer (used by the CALL.10. MOVSAC. TRAP and ULNK instructions). 4. RETFIE. the following 10 register assignments must be adhered to: • • • • W4-W7 are used for arithmetic operands W8-W11 are used for pre-fetch addresses (pointers) W12 is used for the pre-fetch register offset index W13 is used for the accumulator write back destination 4 Instruction Set Details These restrictions only apply to the DSP MAC class of instructions. RETURN.2 Implied Frame and Stack Pointer To accommodate software stack usage. PUSH. In an effort to maintain an instruction set that provides advanced capability.N and MSC.

. . “WREG” must be used to specify the default working register.3. The dsPIC30F has a 17-bit x 17-bit multiplier. . Additionally. the dsPIC30F has matched the functionality of the PICmicro instruction sets as closely as possible. store in WREG clear the WREG LS Byte decrement RAM100. DS70030E-page 4-28 Advance Information  2003 Microchip Technology Inc. The PICmicro families only provide one 8-bit working register. As shown in the detailed instruction descriptions in Section 5.3 4.10. RAM100 WREG RAM100 4. When “MUL{. This means that when “MUL{. 16-bit working registers. Example 4-16: ADD ASR CLR. The default working register is set to W0. the 16-bit product is stored in W2.1 PICmicro® Microcontroller Compatibility Default Working Register WREG To ease the migration path for users of the Microchip PICmicro families. . WREG WREG RAM100.3.B} f” instruction (described on page 5-169).10. Example 4-16 shows several instructions which use WREG.dsPIC30F Programmer’s Reference Manual 4. Supporting the legacy MULWF instruction has been accomplished by mapping the PRODH:PRODL registers to the working register pair W3:W2. “Instruction Descriptions”. . which may place the result into any two successive working registers (starting with an even register).2 PRODH:PRODL Register Pair Another significant difference between the Microchip PICmicro and dsPIC30F architectures is the multiplier. or an accumulator. the syntax used by the dsPIC30F assembler to specify the default working register is similar to that used by the PICmicro assembler. add RAM100 and WREG. store in WREG move WREG to RAM100 set all bits in the WREG XOR RAM100 and WREG. the multiply generates a 32-bit product which is stored in W3:W2.10. the dsPIC30F instruction set has designated one working register to be the default working register for all legacy file register instructions. the dsPIC30F still supports the legacy file register multiply instruction (MULWF) with the “MUL{.B} f” is executed in Word mode. Despite this architectural difference. One major difference between the dsPIC30F and the PICmicro processors is the number of working registers provided. Examples of this instruction are shown in Example 4-17. . WREG WREG. and W3 is unaffected. where W3 has the Most Significant Word of the product and W2 has the Least Significant Word of the product. store in RAM100 shift RAM100 right. store in RAM100 RAM100 RAM100. and it is used by all instructions which use file register addressing. To accommodate for the one working register of the PICmicro MCU.B} f” is executed in Byte mode.B DEC MOV SETM XOR Using the Default Working Register WREG . Some PICmicro families support an 8-bit x 8-bit multiplier. which places the multiply product in the PRODH:PRODL register pair. while the dsPIC30F provides sixteen. .

Instruction Set Details Example 4-17: MUL. (0x100)*WREG (word mode). store to W3:W2 _ÉÑçêÉ=fåëíêìÅíáçåW W0 (WREG) = 0x7705 W2 = 0x1235 W3 = 0x1000 Data Memory 0x0100 = 0x1255 ^ÑíÉê=fåëíêìÅíáçåW W0 (WREG) = 0x7705 W2 = 0xDEA9 W3 = 0x0885 Data Memory 0x0100 = 0x1255 4 Instruction Set Details  2003 Microchip Technology Inc.B Unsigned f and WREG Multiply (Legacy MULWF Instruction) .Section 4. store to W2 0x100 _ÉÑçêÉ=fåëíêìÅíáçåW W0 (WREG) = 0x7705 W2 = 0x1235 W3 = 0x1000 Data Memory 0x0100 = 0x1255 ^ÑíÉê=fåëíêìÅíáçåW W0 (WREG) = 0x7705 W2 = 0x01A9 W3 = 0x1000 Data Memory 0x0100 = 0x1255 MUL 0x100 . (0x100)*WREG (byte mode). Advance Information DS70030E-page 4-29 .

dsPIC30F Programmer’s Reference Manual 4. the range of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1.6566x10-10.657 x 10-10 Register Size 16-bit 32-bit 40-bit -1. data format selection is made by the IF bit.5 x 0.483.483. where 1 is the number of bits used to represent the integer portion of the number.g. the data range is -32768 (0x8000) to 32767 (0x7FFF). The accumulators then support an integer range of -5.1 DSP Data Formats Integer and Fractional Data The dsPIC30F devices support both integer and fractional data types. This mode is enabled when the ACCSAT bit (CORCON<4>). multiplying two 16-bit integers produces a 32-bit integer result.31 format. In Fractional mode. This is required because of the implied radix point used by dsPIC30F fractions.147.25). is set to ‘1’ and it expands the accumulators to 40-bits. Table 4-10 identifies the range and precision of integers and fractions on the dsPIC30F devices for 16-bit.0 and it has a precision of 3. justified with a 1. but has no other effect on the computation (e. Namely. Super Saturation mode expands the dynamic range of the accumulators by using the 8 bits of the Upper Accumulator register (ACCxU) as guard bits. 9.0 to (1.31 fractional format.648 to 2.147. As in Integer mode.0 (0x8000) to 0.052 x 10-5 4. The only difference is how the result is interpreted by the user. .755. Fractional data is represented as a two’s complement number. It should be noted that. multiplies performed by DSP operations are different. the guard bits of the accumulator do not modify the location of the radix point and the 40-bit accumulators use a 9. with the exception of DSP multiplies.498x1011 (0x7F FFFF FFFF).648 (0x8000 0000) to 2. This feature reduces the resolution of the DSP multiplier to 2-30.01518x10-5. ‘1’ for Integer mode). and the radix point is implied to lie just after the sign bit. For a 32-bit integer. the dsPIC30F ALU operates identically on integer and fractional data. Table 4-10: dsPIC30F Data Ranges Integer Range -32768 to 32767 -2. For a 16-bit fraction. and it must be set accordingly (‘0’ for Fractional mode.483.647 (0x7FFF FFFF). the 1.647 -549. where the Most Significant bit is defined as a sign bit.498x1011 (0x80 0000 0000) to 5. Note that all fractional operation results are stored in the 40-bit accumulator. 32-bit and 40-bit registers.31 radix point. For a 16-bit integer.15 data range is -1.65661x10-10) (0x7F FFFF FFFF).483.31 fractions have a range of -256.0 to (256. and they are useful for implementing DSP algorithms. The range of an N-bit two’s complement fraction with this implied radix point is -1. the guard bits merely increase the dynamic range of the accumulator.15 values generates a 2. and 15 is the number of bits used to represent the fractional portion. where the Most Significant bit is defined as a sign bit.813.657 x 10-10 DS70030E-page 4-30 Advance Information  2003 Microchip Technology Inc.5 = 0.30 result. CORCON<0>. the data range is -2.0 (0x80 0000 0000) to (256.147.0 – 2-31) 4. This format is commonly referred to as 1.888 to 549.15 (or Q15) format. However. multiplying two 1. 0. the 32-bit accumulators use a 1. In Normal Saturation mode. Since the dsPIC30F devices use 1. However. Integer data is inherently represented as a signed two’s complement value. a DSP multiply in Fractional mode also includes a left shift of one bit to keep the radix point properly aligned.11 4.0 to (1.0 – 2-31) -256.11.999969482 (0x7FFF). including 0.755.0 – 4.. In Integer mode.887 Fraction Range -1. an addition of two integers will yield the same result (binary number) as the addition of two fractional numbers.31 format for the accumulators. including 0.813.0 to (1 – 21-N). which enhances the precision to 4. In these instructions.147.0 – 2-15) Fraction Resolution 3. Guard bits are used if the value stored in the accumulator overflows beyond the 32nd bit. Generally speaking.

. .5 + . 20 0xC002 = -215 + 214 + 21= -32768 + 16384 + 2 = -16382 1. This is shown in Figure 4-11 for a positive value and in Figure 4-12 for a negative value. the binary exponent starts at 0 for the Most Significant bit. . . Advance Information DS70030E-page 4-31 .499938965  2003 Microchip Technology Inc.500030518 Figure 4-12: Integer: Different Representations of 0xC002 4 Instruction Set Details 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 -215 214 213 212 . . Both integer and fractional data treat the Most Significant bit as a sign bit. For an N-bit fraction. Likewise.15 Fractional: 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 -20 . .5 + 0. . . Instruction Set Details 4. To go from an N-bit integer to a fraction. Converting between integer and fractional representations can be performed using simple division and multiplication. 2-1 2-2 2-3 .11.000030518 = 0. and the binary exponent decreases by one as the bit position advances towards the Least Significant bit. to convert an N-bit fraction to an integer. multiply the fractional value by 2N-1. divide the integer value by 2N-1. The binary exponent for an N-bit integer starts at (N-1) for the Most Significant bit. . . .15 Fractional: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 -20 . . . . 2-15 Implied Radix Point 0xC002 = -20 + 2-1 + 2-14 = -1. .0 + 0.2 Integer and Fractional Data Representation Having a working knowledge of how integer and fractional data are represented on the dsPIC30F is fundamental to working with the device. .000061035 = -0. and ends at 0 for the Least Significant bit. and ends at (1-N) for the Least Significant bit. . . .Section 4. . 2-15 Implied Radix Point 0x4001 = 2-1 + 2-15 = 0. 2-1 2-2 2-3 . Figure 4-11: Integer: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Different Representations of 0x4001 -215 214 213 212 . 20 0x4001 = 214 + 20 = 16384 + 1 = 16385 1.

Item A in Figure 4-13 shows that each 40-bit accumulator (ACCA and ACCB) consists of an 8-bit Upper register (ACCxU). ACCxH is used as a destination register for loading the accumulator (with the LAC instruction). MAC. Figure 4-13. Figure 4-13: Accumulator Alignment and Usage A) 39 ACCxU 32 31 30 ACCxH ACCxL 16 15 0 . For instance. etc. the result is stored in ACCxH:ACCxL.R instruction). ACCxL is zero backfilled and ACCxU is sign-extended to represent the sign of the value loaded in ACCxH.11. .31 math. DSP operations (such as ADD. MSC.12 Accumulator Usage Accumulators A and B are utilized by DSP instructions to perform mathematical and shifting operations. and the sign of the result is extended through ACCxU. Since the accumulators are 40-bits wide and the X and Y data paths are only 16-bits.dsPIC30F Programmer’s Reference Manual 4. the method to load and store the accumulators must be understood. When Normal (31-bit) Saturation is enabled. all registers of the accumulator may be used (Item D in Figure 4-13) and the results of DSP operations are stored in ACCxU:ACCxH:ACCxL. The benefit of ACCxU is that it increases the dynamic range of the accumulator. When Super Saturation is enabled. during accumulator loads. In reality.) utilize solely ACCxH:ACCxL (Item C in Figure 4-13) and ACCxU is only used to maintain the sign of the value stored in ACCxH:ACCxL.1 “Integer and Fractional Data”. To address the bus alignment requirement and provide the ability for 1. Implied Radix Point (between bits 31 and 30) B) C) D) A) B) C) D) 40-bit Accumulator consists of ACCxU:ACCxH:ACCxL Load and Store operations Operations in Normal Saturation mode Operations in Super Saturation mode DS70030E-page 4-32 Advance Information  2003 Microchip Technology Inc. as described in Section 4. Refer to Table 4-10 to see the range of values which may be stored in the accumulator when in Normal and Super Saturation modes. where the upper and lower portions of the accumulator are shaded. This is represented by Item B. and also as a source register for storing the accumulator (with the SAC. a 16-bit High register (ACCxH) and a 16-bit Low register (ACCxL). when a MPY instruction is executed.

LAC. This mode is the Register Offset Addressing mode and utilizes W12. However.N MSC DSP MAC Instructions Description Clear accumulator Euclidean distance (no accumulate) Euclidean distance Multiply and accumulate Square and accumulate Move from X and Y bus Multiply to accumulator Square to accumulator Negative multiply to accumulator Multiply and subtract Accumulator WB? Yes No No Yes No Yes No No No Yes 4 Instruction Set Details 4. and one read must occur from the Y data bus using W10 or W11.14 DSP MAC Instructions The DSP Multiply and Accumulate (MAC) operations are a special suite of instructions which provide the most efficient use of the dsPIC30F architecture. In this mode. This feature allows them to be accessed with file register or indirect addressing.14. “Instruction Descriptions”. plus the 16-bit signed value stored in W12.  2003 Microchip Technology Inc.14. Note: For convenience. ACCAU and ACCBU are sign-extended to 16-bits. or efficiently process complex numbers. The DSP MAC instructions. and in the Y-space with W11.R be used to load and store the accumulators.13 Accumulator Access The six registers of Accumulator A and Accumulator B are memory mapped like any other special function register. Table 4-11: Instruction CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY. Instruction Set Details 4. shifting and rounding capabilities. 4.1 MAC Pre-Fetches Pre-Fetches (or data reads) are made using the effective address stored in the working register. using any instruction which supports such addressing. One read must occur from the X data bus using W8 or W9. Advance Information DS70030E-page 4-33 . utilize both the X and Y data paths of the CPU core. SAC and SAC. one special Addressing mode exists for the MAC class of instructions. Allowable destination registers for both pre-fetches are W4-W7.R instruction details are provided in Section 5. shown in Table 4.Section 4. This feature is called Accumulator Write Back (WB) and it provides flexibility for the software developer. while storing out the rounded contents of the alternate accumulator. SAC and SAC. For instance. it is recommended that the DSP instructions LAC. since they provide sign-extension. which enables these instructions to perform the following operations all in one cycle: • two reads from data memory using pre-fetch working registers (MAC Pre-fetches) • two updates to pre-fetch working registers (MAC Pre-fetch Register Updates) • one mathematical operation with an accumulator (MAC Operations) In addition. the Accumulator WB may be used to run two algorithms concurrently. As shown in Table 4-3. The two pre-fetches from data memory must be specified using the working registers assignments shown in Table 4-9. among other things. the pre-fetch is made using the effective address of the specified working register. four of the ten DSP MAC instructions are also capable of performing an operation with one accumulator. Register Offset Addressing may only be used in the X space with W9. This provides the flexibility to access these registers using either Byte or Word mode (when file register or indirect addressing is used).

dsPIC30F Programmer’s Reference Manual
4.14.2 MAC Pre-Fetch Register Updates
After the MAC pre-fetches are made, the effective address stored in each pre-fetch working register may be modified. This feature enables efficient single cycle processing for data stored sequentially in X and Y memory. Since all DSP instructions execute in Word mode, only even numbered updates may be made to the effective address stored in the working register. Allowable address modifications to each pre-fetch register are -6, -4, -2, 0 (no update), +2, +4 and +6. This means that effective address updates may be made up to 3 words in either direction. When the Register Offset Addressing mode is used, no update is made to the base pre-fetch register (W9 or W11), or the offset register (W12).

4.14.3

MAC Operations
The mathematical operations performed by the MAC class of DSP instructions center around multiplying the contents of two working registers and either adding or storing the result to either Accumulator A or Accumulator B. This is the operation of the MAC, MPY, MPY.N and MSC instructions. Table 4-9 shows that W4-W7 must be used for data source operands in the MAC class of instructions. W4-W7 may be combined in any fashion, and when the same working register is specified for both operands, a square or square and accumulate operation is performed. For the ED and EDAC instructions, the same multiplicand operand must be specified by the instruction, because this is the definition of the Euclidean Distance operation. Another unique feature about this instruction is that the values pre-fetched from X and Y memory are not actually stored in W4-W7. Instead, only the difference of the pre-fetched data words is stored in W4-W7. The two remaining MAC class instructions, CLR and MOVSAC, are useful for initiating or completing a series of MAC or EDAC instructions and do not use the multiplier. CLR has the ability to clear Accumulator A or B, pre-fetch two values from data memory and store the contents of the other accumulator. Similarly, MOVSAC has the ability to pre-fetch two values from data memory and store the contents of either accumulator.

4.14.4

MAC Write Back
The write back ability of the MAC class of DSP instructions facilitates efficient processing of algorithms. This feature allows one mathematical operation to be performed with one accumulator, and the rounded contents of the other accumulator to be stored in the same cycle. As indicated in Table 4-9, register W13 is assigned for performing the write back, and two Addressing modes are supported: Direct and Indirect with Post-increment. The CLR, MOVSAC and MSC instructions support accumulator write back, while the ED, EDAC, MPY and MPY.N instructions do not support accumulator write back. The MAC instruction, which multiplies two working registers which are not the same, also supports accumulator write back. However, the square and accumulate MAC instruction does not support accumulator write back (see Table 4.14).

4.14.5

MAC Syntax
The syntax of the MAC class of instructions can have several formats, which depend on the instruction type and the operation it is performing, with respect to pre-fetches and accumulator write back. With the exception of the CLR and MOVSAC instructions, all MAC class instructions must specify a target accumulator along with two multiplicands, as shown in Example 4-18.

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Section 4. Instruction Set Details
Example 4-18: Base MAC Syntax

; MAC with no prefetch MAC W4*W5, A

Multiply W4*W5, Accumulate to ACCA

; MAC with no prefetch MAC W7*W7, B

Multiply W7*W7, Accumulate to ACCB If a pre-fetch is used in the instruction, the assembler is capable of discriminating the X or Y data pre-fetch based on the register used for the effective address. [W8] or [W9] specifies the X pre-fetch and [W10] or [W11] specifies the Y pre-fetch. Brackets around the working register are required in the syntax, and they designate that indirect addressing is used to perform the pre-fetch. When address modification is used, it must be specified using a minus-equals or plus-equals “C”- like syntax (i.e., “[W8]-=2” or “[W8]+=6”). When Register Offset Addressing is used for the pre-fetch, W12 is placed inside the brackets ([W9+W12] for X pre-fetches and [W11+W12] for Y pre-fetches). Each pre-fetch operation must also specify a pre-fetch destination register (W4-W7). In the instruction syntax, the destination register appears before the pre-fetch register. Legal forms of pre-fetch are shown in Example 4-19. Example 4-19: MAC Pre-Fetch Syntax

; MAC with X only prefetch MAC W5*W6, A, [W8]+=2, W5

ACCA=ACCA+W5*W6 X([W8]+=2)→ W5
; MAC with Y only prefetch MAC W5*W5, B, [W11+W12], W5

4
ACCA=ACCA+W5*W5 Y([W11+W12])→ W5

Instruction Set Details

; MAC with X/Y prefetch MAC W6*W7, B, [W9], W6,

[W10]+=4, W7

ACCB=ACCB+W6*W7 X([W9])→ W6 Y([W10]+=4)→ W7

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dsPIC30F Programmer’s Reference Manual
If an accumulator write back is used in the instruction, it is specified last. The write back must use the W13 register, and allowable forms for the write back are “W13” for direct addressing and “[W13]+=2” for indirect addressing with post-increment. By definition, the accumulator not used in the mathematical operation is stored, so the write back accumulator is not specified in the instruction. Legal forms of accumulator write back (WB) are shown in Example 4-20. Example 4-20: MAC Accumulator WB Syntax

; CLR with direct WB of ACCB CLR A, W13

0 → ACCA ACCB → W13

; MAC with indirect WB of ACCB MAC W4*W5, A [W13]+=2

ACCA=ACCA+W4*W5 ACCB → [W13]+=2

; MAC with Y prefetch, direct WB of ACCA MAC W4*W5, B, [W10]+=2, W4, W13

ACCB=ACCB+W4*W5 Y([W10]+=2)→ W4 ACCA → W13 Putting it all together, an MSC instruction which performs two pre-fetches and a write back is shown in Example 4-21. Example 4-21: MSC Instruction with Two Pre-Fetches and Accumulator Write Back

; MSC with X/Y prefetch, indirect WB of ACCA MSC W6*W7, B, [W8]+=2, W6, [W10]-=6, W7 [W13]+=2 ACCB=ACCB-W6*W7 X([W8]+=2)→W6 Y([W10]-=6)→W7 ACCA→[W13]+=2

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Section 4. Instruction Set Details
4.15 DSP Accumulator Instructions
The DSP Accumulator instructions do not have pre-fetch or accumulator WB ability, but they do provide the ability to add, negate, shift, load and store the contents of either 40-bit accumulator. In addition, the ADD and SUB instructions allow the two accumulators to be added or subtracted from each other. DSP Accumulator instructions are shown in Table 4-12 and instruction details are provided in Section 5. “Instruction Descriptions”. Table 4-12: Instruction ADD ADD LAC NEG SAC SAC.R SFTAC SFTAC SUB DSP Accumulator Instructions Description Add accumulators 16-bit signed accumulator add Load accumulator Negate accumulator Store accumulator Store rounded accumulator Arithmetic shift accumulator by Literal Arithmetic shift accumulator by (Wn) Subtract accumulators Accumulator WB? No No No No No No No No No

4.16

Scaling Data with the FBCL Instruction
To minimize quantization errors that are associated with data processing using DSP instructions, it is important to utilize the complete numerical result of the operations. This may require scaling data up to avoid underflow (i.e., when processing data from a 12-bit ADC), or scaling data down to avoid overflow (i.e., when sending data to a 10-bit DAC). The scaling, which must be performed to minimize quantization error, depends on the dynamic range of the input data which is operated on, and the required dynamic range of the output data. At times, these conditions may be known beforehand and fixed scaling may be employed. In other cases, scaling conditions may not be fixed or known, and then dynamic scaling must be used to process data. The FBCL instruction (Find First Bit Change Left) can efficiently be used to perform dynamic scaling, because it determines the exponent of a value. A fixed point or integer value’s exponent represents the amount which the value may be shifted before overflowing. This information is valuable, because it may be used to bring the data value to “full scale”, meaning that it’s numeric representation utilizes all the bits of the register it is stored in. The FBCL instruction determines the exponent of a word by detecting the first bit change starting from the value’s sign bit and working towards the LSB. Since the dsPICTM device’s barrel shifter uses negative values to specify a left shift, the FBCL instruction returns the negated exponent of a value. If the value is being scaled up, this allows the ensuing shift to be performed immediately with the value returned by FBCL. Additionally, since the FBCL instruction only operates on signed quantities, FBCL produces results in the range of -15:0. When the FBCL instruction returns ‘0’, it indicates that the value is already at full scale. When the instruction returns -15, it indicates that the value cannot be scaled (as is the case with 0x0 and 0xFFFF). Table 4-13 shows word data with various dynamic ranges, their exponents, and the value after scaling each data to maximize the dynamic range. Example 4-22 shows how the FBCL instruction may be used for block processing.

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dsPIC30F Programmer’s Reference Manual
Table 4-13: Word Value 0x0001 0x0002 0x0004 0x0100 0x01FF 0x0806 0x2007 0x4800 0x7000 0x8000 0x900A 0xE001 0xFF07 Note: Scaling Examples Exponent 14 13 12 6 6 3 1 0 0 0 0 2 7 Full Scale Value (Word Value << Exponent) 0x4000 0x4000 0x4000 0x4000 0x7FC0 0x4030 0x400E 0x4800 0x7000 0x8000 0x900A 0x8004 0x8380

For the word values 0x0000 and 0xFFFF, the FBCL instruction returns -15.

As a practical example, assume that block processing is performed on a sequence of data with very low dynamic range stored in 1.15 fractional format. To minimize quantization errors, the data may be scaled up to prevent any quantization loss which may occur as it is processed. The FBCL instruction can be executed on the sample with the largest magnitude to determine the optimal scaling value for processing the data. Note that scaling the data up is performed by left shifting the data. This is demonstrated with the code snippet below. Example 4-22: Scaling with FBCL

; assume W0 contains the largest absolute value of the data block ; assume W4 points to the beginning of the data block ; assume the block of data contains BLOCK_SIZE words ; determine the exponent to use for scaling FBCL W0, W2 ; store exponent in W2 ; scale DO LAC SFTAC SCALE: SAC the entire data block before processing #(BLOCK_SIZE-1), SCALE [W4], A ; move the next data sample to ACCA A, W2 ; shift ACCA by W2 bits A, [W4++] ; store scaled input (overwrite original)

; now process the data ; (processing block goes here)

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Section 4. Instruction Set Details
4.17 Normalizing the Accumulator with the FBCL Instruction
The process of scaling a quantized value for its maximum dynamic range is known as normalization (the data in the third column in Table 4-13 contains normalized data). Accumulator normalization is a technique used to ensure that the accumulator is properly aligned before storing data from the accumulator, and the FBCL instruction facilitates this function. The two 40-bit accumulators each have 8 guard bits from the AccU register, which expands the dynamic range of the accumulators from 1.31 to 9.31, when operating in Super Saturation mode (see Section 4.11.1 “Integer and Fractional Data”). However, even in Super Saturation mode, the Store Rounded Accumulator (SAC.R) instruction only stores 16-bit data (in 1.15 format) from AccH, as described in Section 4.12 “Accumulator Usage”. Under certain conditions, this may pose a problem. Proper data alignment for storing the contents of the accumulator may be achieved by scaling the accumulator down if AccU is in use, or scaling the accumulator up if all of the AccH bits are not being used. To perform such scaling, the FBCL instruction must operate on the AccU byte and it must operate on the AccH word. If a shift is required, the ALU’s 40-bit shifter is employed, using the SFTAC instruction to perform the scaling. Example 4-23 contains a code snippet for accumulator normalization. Example 4-23: Normalizing with FBCL

; assume an operation in ACCA has just completed (SR intact) ; assume the processor is in super saturation mode ; assume ACCAH is defined to be the address of ACCAH (0x24) MOV #ACCAH, W5 BRA OA, FBCL_GUARD FBCL_HI: FBCL [W5], W0 BRA SHIFT_ACC FBCL_GUARD: FBCL [++W5], W0 ADD.B W0, #15, W0 SHIFT_ACC: SFTAC A, W0 ; W5 points to ACCAH ; if overflow we right shift ; extract exponent for left shift ; branch to the shift ; extract exponent for right shift ; adjust the sign for right shift ; shift ACCA to normalize

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NOTES:

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Section 5. Instruction Descriptions
HIGHLIGHTS
This section of the manual contains the following major topics: 5.1 5.2 5.3 5.4 Instruction Symbols........................................................................................................ 5-2 Instruction Encoding Field Descriptors Introduction....................................................... 5-2 Instruction Description Example .................................................................................... 5-6 Instruction Descriptions.................................................................................................. 5-7

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dsPIC30F Programmer’s Reference Manual
5.1 5.2 Instruction Symbols
All symbols used in Section 5.4 “Instruction Descriptions” are shown in Table 1-2.

Instruction Encoding Field Descriptors Introduction
All instruction encoding field descriptors used in Section 5.4 “Instruction Descriptions” are shown in Table 5.2 through Table 5-12. Table 5-1: Instruction Encoding Field Descriptors
Field A aa B bbbb D dddd f ffff ffff ffff fff ffff ffff ffff ffff ffff ffff ffff ggg hhh iiii jjjj k kkkk kkkk kkkk kkkk kkkk kkkk mm mmm nnnn nnnn nnnn nnn0 nnn nnnn nnnn nnnn nnnn nnnn ppp qqq rrrr ssss tttt vvvv W wwww xx xxxx xxxx xxxx xxxx yy z Description Accumulator selection bit: 0=ACCA; 1=ACCB Accumulator Write Back mode (see Table 5-12) Byte mode selection bit: 0=word operation; 1=byte operation 4-bit bit position select: 0000=LSB; 1111=MSB Destination address bit: 0=result stored in WREG; 1=result stored in file register Wd destination register select: 0000=W0; 1111=W15 13-bit register file address (0x0000 to 0x1FFF) 15-bit register file word address (implied 0 LSB) (0x0000 to 0xFFFE) 16-bit register file byte address (0x0000 to 0xFFFF) Register Offset Addressing mode for Ws source register (see Table 5-4) Register Offset Addressing mode for Wd destination register (see Table 5-5) Pre-Fetch X Operation (see Table 5-6) Pre-Fetch Y Operation (see Table 5-8) 1-bit literal field, constant data or expression 4-bit literal field, constant data or expression 6-bit literal field, constant data or expression 8-bit literal field, constant data or expression 10-bit literal field, constant data or expression 14-bit literal field, constant data or expression 16-bit literal field, constant data or expression Multiplier source select with same working registers (see Table 5-10) Multiplier source select with different working registers (see Table 5-11) 23-bit program address for CALL and GOTO instructions 16-bit program offset field for relative branch/call instructions Addressing mode for Ws source register (see Table 5-2) Addressing mode for Wd destination register (see Table 5-3) Barrel shift count Ws source register select: 0000=W0; 1111=W15 Dividend select, Most Significant Word Dividend select, Least Significant Word Double-Word mode selection bit: 0=word operation; 1=double-word operation Wb base register select: 0000=W0; 1111=W15 Pre-Fetch X Destination (see Table 5-7) 16-bit unused field (don’t care) Pre-Fetch Y Destination (see Table 5-9) Bit test destination: 0=C flag bit; 1=Z flag bit

kk kkkk kk kkkk kk kkkk kkkk kkkk kkkk kkkk

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Section 5. Instruction Descriptions
Table 5-2: ppp 000 001 010 011 100 101 11x Table 5-3: qqq 000 001 010 011 100 101 11x Table 5-4: ggg 000 001 010 011 100 101 11x Table 5-5: hhh 000 001 010 011 100 101 11x Register Direct Indirect Indirect with Post-Decrement Indirect with Post-Increment Indirect with Pre-Decrement Indirect with Pre-Increment Indirect with Register Offset Register Direct Indirect Indirect with Post-Decrement Indirect with Post-Increment Indirect with Pre-Decrement Indirect with Pre-Increment Indirect with Register Offset Register Direct Indirect Indirect with Post-Decrement Indirect with Post-Increment Indirect with Pre-Decrement Indirect with Pre-Increment Register Direct Indirect Indirect with Post-Decrement Indirect with Post-Increment Indirect with Pre-Decrement Indirect with Pre-Increment Unused Addressing Modes for Wd Destination Register Addressing Mode Destination Operand Wd [Wd] [Wd--] [Wd++] [--Wd] [++Wd] Addressing Modes for Ws Source Register Addressing Mode Ws [Ws] [Ws--] [Ws++] [--Ws] [++Ws] Source Operand

Unused (an attempt to use this Addressing mode will force a RESET instruction) Offset Addressing Modes for Ws Source Register (with Register Offset) Addressing Mode Ws [Ws] [Ws--] [Ws++] [--Ws] [++Ws] [Ws+Wb] Source Operand

Offset Addressing Modes for Wd Destination Register (with Register Offset) Addressing Mode Wd [Wd] [Wd--] [Wd++] [--Wd] [++Wd] [Wd+Wb] Source Operand

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Table 5-6: iiii 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 5-7: xx 00 01 10 11 Table 5-8: jjjj 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Wyd=[W10] Wyd=[W10], W10 = W10 + 2 Wyd=[W10], W10 = W10 + 4 Wyd=[W10], W10 = W10 + 6 No Pre-fetch for Y Data Space Wyd=[W10], W10 = W10 – 6 Wyd=[W10], W10 = W10 – 4 Wyd=[W10], W10 = W10 – 2 Wyd=[W11] Wyd=[W11], W11 = W11 + 2 Wyd=[W11], W11 = W11 + 4 Wyd=[W11], W11 = W11 + 6 Wyd=[W11+W12] Wyd=[W11], W11 = W11 – 6 Wyd=[W11], W11 = W11 – 4 Wyd=[W11], W11 = W11 – 2 W4 W5 W6 W7 Y Data Space Pre-Fetch Operation Operation Wxd=[W8] Wxd=[W8], W8 = W8 + 2 Wxd=[W8], W8 = W8 + 4 Wxd=[W8], W8 = W8 + 6 No Pre-fetch for X Data Space Wxd=[W8], W8 = W8 – 6 Wxd=[W8], W8 = W8 – 4 Wxd=[W8], W8 = W8 – 2 Wxd=[W9] Wxd=[W9], W9 = W9 + 2 Wxd=[W9], W9 = W9 + 4 Wxd=[W9], W9 = W9 + 6 Wxd=[W9+W12] Wxd=[W9], W9 = W9 – 6 Wxd=[W9], W9 = W9 – 4 Wxd=[W9], W9 = W9 – 2 X Data Space Pre-Fetch Destination Wxd X Data Space Pre-Fetch Operation Operation

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Section 5. Instruction Descriptions
Table 5-9: yy 00 01 10 11 W4 W5 W6 W7 Y Data Space Pre-Fetch Destination Wyd

Table 5-10: MAC or MPY Source Operands (Same Working Register) mm 00 01 10 11 Table 5-11: mmm 000 001 010 011 100 101 110 111 Table 5-12: aa 00 01 10 11 W4 * W5 W4 * W6 W4 * W7 Invalid W5 * W6 W5 * W7 W6 * W7 Invalid MAC Accumulator Write Back Selection Write Back Selection W13 = Other Accumulator (Direct Addressing) [W13]+=2 = Other Accumulator (Indirect Addressing with Post-Increment) No Write Back Invalid W4 * W4 W5 * W5 W6 * W6 W7 * W7 MAC or MPY Source Operands (Different Working Register) Multiplicands Multiplicands

5
Instruction Descriptions

 2003 Microchip Technology Inc.

Advance Information

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dsPIC30F Programmer’s Reference Manual
5.3 Instruction Description Example
The example description below is for the fictitious instruction FOO. The following example instruction was created to demonstrate how the table fields (syntax, operands, operation, etc.) are used to describe the instructions presented in Section 5.4 “Instruction Descriptions”.

FOO
Syntax:

The Header field summarizes what the instruction does The Syntax field consists of an optional label, the instruction mnemonic, any optional extensions which exist for the instruction, and the operands for the instruction. Most instructions support more than one operand variant to support the various dsPIC30F Addressing modes. In these circumstances, all possible instruction operands are listed beneath each other (as in the case of op2a, op2b and op2c above). Optional operands are enclosed in braces. The Operands field describes the set of values which each of the operands may take. Operands may be accumulator registers, file registers, literal constants (signed or unsigned), or working registers. The Operation field summarizes the operation performed by the instruction. The Status Affected field describes which bits of the Status Register are affected by the instruction. Status bits are listed by bit position in descending order. The Encoding field shows how the instruction is bit encoded. Individual bit fields are explained in the Description field, and complete encoding details are provided in Table 5.2. The Description field describes in detail the operation performed by the instruction. A key for the encoding bits is also provided. The Words field contains the number of program words that are used to store the instruction in memory. The Cycles field contains the number of instruction cycles that are required to execute the instruction. The Examples field contains examples which demonstrate how the instruction operates. “Before” and “After” register snapshots are provided, which allow the user to clearly understand what operation the instruction performs.

Operands:

Operation: Status Affected:

Encoding:

Description:

Words:

Cycles:

Examples:

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1 for byte). Add WREG to RAM100 (Byte mode) Before Instruction WREG CC80 RAM100 FFC0 SR 0000 After Instruction WREG CC80 RAM100 FF40 SR 0005 (OV. OV. Note 1: The extension . If WREG is specified. 8191] (f) + (WREG) → destination designated by D DC. The ‘f’ bits select the address of the file register. Words: Cycles: Example 1 1 1 ADD. Add RAM200 to WREG (Word mode) Before Instruction WREG CC80 RAM200 FFC0 SR 0000 After Instruction WREG CC40 RAM200 FFC0 SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. but it is not required. WREG . If WREG is not specified.. You may use a . the result is stored in WREG. C 1011 0100 0BDf ffff ffff ffff Add the contents of the default working register WREG to the contents of the file register and place the result in the destination register..WREG} f ∈ [0 . The optional WREG operand determines the destination register.B in the instruction denotes a byte operation rather than a word operation. Advance Information DS70030E-page 5-7 . The ‘D’ bit selects the destination (0 for WREG.B} f {. C=1) Example 2 ADD RAM200. 2: The WREG is set to working register W0. N.Section 5. Z. The ‘B’ bit selects byte or word operation (0 for word. Instruction Descriptions 5. 1 for file register). the result is stored in the file register.4 Instruction Descriptions ADD Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Add f to WREG ADD{.W extension to denote a word operation.B RAM100 .

Wn lit10 ∈ [0 . . The ‘d’ bits select the address of the working register. The ‘k’ bits specify the literal operand. Add 255 to W1 (Word mode) Before Instruction W1 12C0 SR 0000 After Instruction W1 13BF SR 0000 DS70030E-page 5-8 Advance Information  2003 Microchip Technology Inc.. Z.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode. N. W15] lit10 + (Wn) → Wn DC. The ‘B’ bit selects byte or word operation (0 for word.B in the instruction denotes a byte operation rather than a word operation. the literal must be specified as an unsigned value [0:255]. See Section 4. Add -1 to W7 (Byte mode) Before Instruction W7 12C0 SR 0000 After Instruction W7 12BF SR 0009 (N. 1 for byte).. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 ADD.B #0xFF.C=1) Example 2 ADD #0xFF.dsPIC30F Programmer’s Reference Manual ADD Syntax: Operands: {label:} Add Literal to Wn ADD{. 255] for byte operation lit10 ∈ [0 . Note 1: The extension . W1 . OV. 1023] for word operation Wn ∈ [W0 . C 1011 0000 0Bkk kkkk kkkk dddd Add the 10-bit unsigned literal operand to the contents of the working register Wn and place the result back into the working register Wn....W extension to denote a word operation. W7 .B} #lit10. 2: For byte operations. You may use a .. but it is not required.

Store the result in [--W4] Before Instruction W3 6006 W4 1000 Data 0FFE DDEE Data 1000 DDEE SR 0000 After Instruction W3 6006 W4 0FFE Data 0FFE 600C Data 1000 DDEE SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.. Add W3 and 6 (Word mode) . You may use a .. Z.Section 5.W extension to denote a word operation. #0x6. OV. Store the result in W7 Before Instruction W0 2290 W7 12C0 SR 0000 Example 2 ADD After Instruction W0 2290 W7 12AF SR 0008 (N=1) W3. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 ADD. The ‘w’ bits select the address of the base register. [--W4] . Add W0 and 31 (Byte mode) . Note: The extension .B in the instruction denotes a byte operation rather than a word operation. The ‘q’ bits select the destination Address mode. but it is not required. W15] lit5 ∈ [0 . C 0100 0www wBqq qddd d11k kkkk Add the contents of the base register Wb to the 5-bit unsigned short literal operand and place the result in the destination register Wd. The ‘k’ bits provide the literal operand.B W0. #0x1F. a five-bit integer number.B} Wb. Instruction Descriptions ADD Syntax: {label:} Add Wb to Short Literal ADD{.. Either register direct or indirect addressing may be used for Wd. #lit5. Advance Information DS70030E-page 5-9 . W15] (Wb) + lit5 → Wd DC. 31] Wd ∈ [W0 . N.. The ‘B’ bit selects byte or word operation (0 for word.. W7 . 1 for byte). Register direct addressing must be used for Wb.. The ‘d’ bits select the address of the destination register. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 .

Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 ADD. Ws. [Ws--]. Register direct addressing must be used for Wb. [++Ws]. N. The ‘q’ bits select the destination Address mode.B} Wb. (Byte mode) Before Instruction W5 AB00 W6 0030 W7 FFFF SR 0000 Example 2 ADD After Instruction W5 AB00 W6 0030 W7 FF30 SR 0000 W5. The ‘d’ bits select the address of the destination register.. The ‘B’ bit selects byte or word operation (0 for word. C 0100 0www wBqq qddd dppp ssss Add the contents of the source register Ws and the contents of the base register Wb and place the result in the destination register Wd. Z. The ‘w’ bits select the address of the base register...B in the instruction denotes a byte operation rather than a word operation. W7 . Either register direct or indirect addressing may be used for Ws and Wd. W15] (Wb) + (Ws) → Wd DC. Add W5 to W6. W6. W15] Ws ∈ [W0 .B W5. Note: The extension . [Ws++]. The ‘s’ bits select the address of the source register. W7 .W extension to denote a word operation. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . store result in W7 . (Word mode) Before Instruction W5 AB00 W6 0030 W7 FFFF SR 0000 After Instruction W5 AB00 W6 0030 W7 AB30 SR 0008 (N=1) DS70030E-page 5-10 Advance Information  2003 Microchip Technology Inc. [--Ws]. .. but it is not required. The ‘p’ bits select the source Address mode. 1 for byte). W6. [Ws]. Add W5 to W6. You may use a .dsPIC30F Programmer’s Reference Manual ADD Syntax: {label:} Add Wb to Ws ADD{. store result in W7 . OV. W15] Wd ∈ [W0 ...

SB. SA. (ACCSAT=1. Add ACCA to ACCB . OAB. Instruction Descriptions ADD Syntax: Operands: Operation: {label:} Acc ∈ [A. OB. OAB=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 ADD A . The ‘A’ bit specifies the destination accumulator.Section 5. Assume Super Saturation mode enabled . SAB 1100 1011 A000 0000 0000 0000 Add the contents of Accumulator A to the contents of Accumulator B and place the result in the selected accumulator.B] Add Accumulators ADD Acc If (Acc = A): (ACCA) + (ACCB) → ACCA Else: (ACCA) + (ACCB) → ACCB OA. Advance Information DS70030E-page 5-11 . SATB=1) Before Instruction ACCA 00 E111 2222 ACCB 00 7654 3210 SR 0000 After Instruction ACCA 00 E111 2222 ACCB 01 5765 5432 SR 4800 (OB. Add ACCB to ACCA Before Instruction ACCA 00 0022 3300 ACCB 00 1833 4558 SR 0000 Example 2 ADD B After Instruction ACCA 00 1855 7858 ACCB 00 1833 4558 SR 0000 . This instruction performs a 40-bit addition. SATA=1.

A .} Acc Operands: Ws ∈ [W0 . SB. W15] Wb ∈ [W0 ... The source operand may specify the direct contents of a working register or an effective address. #2. The value added to the accumulator may also be shifted by a 4-bit signed literal before the addition is made. [Ws]. The ‘w’ bits specify the offset register Wb.dsPIC30F Programmer’s Reference Manual ADD Syntax: {label:} 16-Bit Signed Add to Accumulator ADD Ws.. {#Slit4.B] ShiftSlit4(Extend(Ws)) + (Acc) → Acc 1100 1001 Awww wrrr rggg ssss Operation: Status Affected: OA.. The ‘r’ bits encode the optional shift. SAB Encoding: Description: Add a 16-bit value specified by the source working register to the Most Significant word of the selected accumulator. OAB. [--Ws]. The contents of the source register are not affected by Slit4. Note: Positive values of operand Slit4 represent an arithmetic shift right and negative values of operand Slit4 represent an arithmetic shift left. +7] Acc ∈ [A. The ‘g’ bits select the source Address mode. SA. The value specified is added to the Most Significant Word of the accumulator. Words: Cycles: Example 1 1 1 ADD W0.. . The ‘s’ bits specify the source register Ws. Add W0 right-shifted by 2 to ACCA Before Instruction W0 8000 ACCA 00 7000 0000 SR 0000 After Instruction W0 8000 ACCA 00 5000 0000 SR 0000 DS70030E-page 5-12 Advance Information  2003 Microchip Technology Inc.. [Ws--]. OB. [++Ws]. W15] Slit4 ∈ [-8 . by sign-extending and zero backfilling the source operand prior to the operation. The ‘A’ bit specifies the destination accumulator. [Ws+Wb]. [Ws++].

Section 5. Advance Information DS70030E-page 5-13 . A . Post-increment W5 W5 ACCA Data 2000 SR Before Instruction 2000 00 0067 2345 5000 0000 W5 ACCA Data 2000 SR After Instruction 2002 00 5067 2345 5000 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Instruction Descriptions Example 2 ADD [W5++]. Add the effective value of W5 to ACCA .

The ‘B’ bit selects byte or word operation (0 for word. . SUBB and SUBBR. The ‘f’ bits select the address of the file register. 8191] (f) + (WREG) + (C) → destination designated by D DC. the result is stored in WREG.B in the instruction denotes a byte operation rather than a word operation.. the contents of the file register and the Carry bit and place the result in the destination register. (Byte mode) Before After Instruction Instruction WREG CC60 WREG CC60 RAM100 8006 RAM100 8067 SR 0001 (C=1) SR 0000 Example 2 ADDC RAM200. The optional WREG operand determines the destination register. OV=1) DS70030E-page 5-14 Advance Information  2003 Microchip Technology Inc. (Word mode) Before After Instruction Instruction WREG 5600 WREG 8A01 RAM200 3400 RAM200 3400 SR 0001 (C=1) SR 000C (N. If WREG is specified. 3: The Z flag is “sticky” for ADDC.WREG} f ∈ [0 . the result is stored in the file register.. Note 1: The extension .B RAM100 .dsPIC30F Programmer’s Reference Manual ADDC Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Add f to WREG with Carry ADDC{. CPB. If WREG is not specified.W extension to denote a word operation. These instructions can only clear Z. 2: The WREG is set to working register W0. OV. 1 for byte). 1 for file register). N. The ‘D’ bit selects the destination (0 for WREG. You may use a . WREG . C 1011 0100 1BDf ffff ffff ffff Add the contents of the default working register WREG. Words: Cycles: Example 1 1 1 ADDC. Z.B} f {. Add WREG and C bit to RAM100 . but it is not required. Add RAM200 and C bit to the WREG .

2: For byte operations..C=1) Example 2 ADDC #0xFF.. W7 . the contents of the working register Wn and the Carry bit and place the result back into the working register Wn.W extension to denote a word operation. SUBB and SUBBR.B #0xFF.. W15] lit10 + (Wn) + (C) → Wn DC.. The ‘B’ bit selects byte or word operation (0 for word. the literal must be specified as an unsigned value [0:255]..7 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode. 1023] for word operation Wn ∈ [W0 . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 ADDC. N. Note 1: The extension .. The ‘k’ bits specify the literal operand. These instructions can only clear Z.Section 5. You may use a . W1 . The ‘d’ bits select the address of the working register. 255] for byte operation lit10 ∈ [0 . Advance Information DS70030E-page 5-15 . OV. but it is not required. Add -1 and C bit to W7 (Byte mode) Before Instruction W7 12C0 SR 0000 (C=0) After Instruction W7 12BF SR 0009 (N. Z. See Section 2. C 1011 0000 1Bkk kkkk kkkk dddd Add the 10-bit unsigned literal operand. 1 for byte). CPB. Add 255 and C bit to W1 (Word mode) Before Instruction W1 12C0 SR 0001 (C=1) After Instruction W1 13C0 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. 3: The Z flag is “sticky” for ADDC. Wn lit10 ∈ [0 . Instruction Descriptions ADDC Syntax: Operands: {label:} Add Literal to Wn with Carry ADDC{.B} #lit10.B in the instruction denotes a byte operation rather than a word operation.

OV.W extension to denote a word operation. the 5-bit unsigned short literal operand and the Carry bit and place the result in the destination register Wd.dsPIC30F Programmer’s Reference Manual ADDC Syntax: {label:} Add Wb to Short Literal with Carry ADDC{. #0x6.. 1 for byte)..B in the instruction denotes a byte operation rather than a word operation.B W0. #lit5. 2: The Z flag is “sticky” for ADDC. N.. Store the result in [--W4] Before Instruction W3 6006 W4 1000 Data 0FFE DDEE Data 1000 DDEE SR 0001 (C=1) After Instruction W3 6006 W4 0FFE Data 0FFE 600D Data 1000 DDEE SR 0000  2003 Microchip Technology Inc. Note 1: The extension . [--W4] .. W15] lit5 ∈ [0 . Add W3. The ‘q’ bits select the destination Address mode. C 0100 1www wBqq qddd d11k kkkk Add the contents of the base register Wb. DS70030E-page 5-16 Advance Information . SUBB and SUBBR. Register direct or indirect addressing may be used for Wd. These instructions can only clear Z. The ‘k’ bits provide the literal operand. The ‘d’ bits select the address of the destination register. Add W0. [W7] . W15] (Wb) + lit5 + (C) → Wd DC. Store the result in [W7] Before Instruction W0 CC80 W7 12C0 Data 12C0 B000 SR 0000 (C=0) Example 2 ADDC After Instruction W0 CC80 W7 12C0 Data 12C0 B09F SR 0008 (N=1) W3.B} Wb. 6 and C bit (Word mode) .. Z. The ‘B’ bit selects byte or word operation (0 for word. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 ADDC. but it is not required. a five-bit integer number. 31] Wd ∈ [W0 . 31 and C bit (Byte mode) . #0x1F. CPB. The ‘w’ bits select the address of the base register. You may use a . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 .. Register direct addressing must be used for Wb.

. 2: The Z flag is “sticky” for ADDC. These instructions can only clear Z. Z. [Ws].Section 5.. Note 1: The extension . W15] Wd ∈ [W0 . Advance Information DS70030E-page 5-17 . The ‘w’ bits select the address of the base register. the contents of the base register Wb and the Carry bit and place the result in the destination register Wd. [--Ws].B} Wb. C 0100 1www wBqq qddd dppp ssss Add the contents of the source register Ws. Instruction Descriptions ADDC Syntax: {label:} Add Wb to Ws with Carry ADDC{. The ‘p’ bits select the source Address mode. [Ws--].B in the instruction denotes a byte operation rather than a word operation. [Ws++]. You may use a . W2 Before After Instruction Instruction W0 CC20 W0 CC20 W1 0800 W1 0801 W2 1000 W2 1001 Data 0800 AB25 Data 0800 AB25 Data 1000 FFFF Data 1000 FF46 SR 0001 (C=1) SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.. W15] (Wb) + (Ws) + (C) → Wd DC. OV. [++Ws]. Store the result in [W2] . The ‘q’ bits select the destination Address mode.. The ‘s’ bits select the address of the source register. N. 1 for byte).. W15] Ws ∈ [W0 .B W0. but it is not required. Ws. Either register direct or indirect addressing may be used for Ws and Wd.[W2++] . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . Post-increment W1. Register direct addressing must be used for Wb. The ‘B’ bit selects byte or word operation (0 for word. [W1] and C bit (Byte mode) .. CPB. The ‘d’ bits select the address of the destination register.[W1++].W extension to denote a word operation. SUBB and SUBBR. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 ADDC. Add W0.

.dsPIC30F Programmer’s Reference Manual Example 2 ADDC W3. Post-increment W1.[W2++]. Store the result in [W1] . W2 Before After Instruction Instruction W1 1000 W1 1002 W2 2000 W2 2002 W3 0180 W3 0180 Data 1000 8000 Data 1000 2681 Data 2000 2500 Data 2000 2500 SR 0001 (C=1) SR 0000 DS70030E-page 5-18 Advance Information  2003 Microchip Technology Inc. [W2] and C bit (Word mode) .[W1++] . Add W3.

1 for file register). 8191] (f). but it is not required.B RAM100 . AND RAM200 to WREG (Word mode) RAM200. Note 1: The extension . 1 for byte).W extension to denote a word operation. Instruction Descriptions AND Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} AND f and WREG AND{. the result is stored in WREG. WREG Before Instruction WREG CC80 RAM200 12C0 SR 0000 After Instruction WREG 0080 RAM200 12C0 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. You may use a . Advance Information DS70030E-page 5-19 . The optional WREG operand determines the destination register.B in the instruction denotes a byte operation rather than a word operation.WREG} f ∈ [0 .AND.Section 5. The ‘B’ bit selects byte or word operation (0 for word.B} f {. AND WREG to RAM100 (Byte mode) Before Instruction WREG CC80 RAM100 FFC0 SR 0000 Example 2 AND After Instruction WREG CC80 RAM100 FF80 SR 0008 (N=1) . Words: Cycles: Example 1 1 1 AND. If WREG is not specified. If WREG is specified. the result is stored in the file register. Z 1011 0110 0BDf ffff ffff ffff Compute the logical AND operation of the contents of the default working register WREG and the contents of the file register and place the result in the destination register. The ‘f’ bits select the address of the file register.(WREG) → destination designated by D N. The ‘D’ bit selects the destination (0 for WREG.. 2: The WREG is set to working register W0..

255] for byte operation lit10 ∈ [0 .6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode.(Wn) → Wn N.. but it is not required. W7 .dsPIC30F Programmer’s Reference Manual AND Syntax: Operands: {label:} AND Literal and Wd AND{.. Wn lit10 ∈ [0 .. AND 0x333 to W1 (Word mode) Before Instruction W1 12D0 SR 0000 After Instruction W1 0210 SR 0000 DS70030E-page 5-20 Advance Information  2003 Microchip Technology Inc.AND. . You may use a . The ‘B’ bit selects byte or word operation (0 for word. The ‘k’ bits specify the literal operand. See Section 4. Register direct addressing must be used for Wn. W15] lit10.W extension to denote a word operation. AND 0x83 to W7 (Byte mode) Before Instruction W7 12C0 SR 0000 Example 2 AND #0x333. 2: For byte operations. W1 After Instruction W7 1280 SR 0008 (N=1) .B} #lit10. 1023] for word operation Wn ∈ [W0 . 1 for byte). Note 1: The extension ..B in the instruction denotes a byte operation rather than a word operation.B #0x83. Z 1011 0010 0Bkk kkkk kkkk dddd Compute the logical AND operation of the 10-bit literal operand and the contents of the working register Wn and place the result back into the working register Wn.. the literal must be specified as an unsigned value [0:255]. The ‘d’ bits select the address of the working register. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 AND..

The ‘q’ bits select the destination Address mode.B} Wb.B W0.AND.[W1++] .. You may use a .W1 . #lit5. but it is not required.. 1 for byte).. AND W0 and 0x1F (Word mode) .B in the instruction denotes a byte operation rather than a word operation.. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 AND. W15] lit5 ∈ [0 . The ‘k’ bits provide the literal operand. W15] (Wb). Store to W1 5 Instruction Descriptions Before Instruction W0 6723 W1 7878 SR 0000 After Instruction W0 6723 W1 0003 SR 0000  2003 Microchip Technology Inc. The ‘w’ bits select the address of the base register. a five-bit integer number. Note: The extension . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . Register direct addressing must be used for Wb..W extension to denote a word operation. The ‘B’ bit selects byte or word operation (0 for word. Either register direct or indirect addressing may be used for Wd.Section 5. AND W0 and 0x3 (Byte mode) . Instruction Descriptions AND Syntax: {label:} AND Wb and Short Literal AND{.lit5 → Wd N.. Post-increment W1 Before Instruction W0 23A5 W1 2211 Data 2210 9999 SR 0000 Example 2 AND After Instruction W0 23A5 W1 2212 Data 2210 0199 SR 0000 W0. Advance Information DS70030E-page 5-21 .#0x3. Z 0110 0www wBqq qddd d11k kkkk Compute the logical AND operation of the contents of the base register Wb and the 5-bit literal and place the result in the destination register Wd. 31] Wd ∈ [W0 .#0x1F. The ‘d’ bits select the address of the destination register. Store to [W1] .

Ws. [Ws]..B in the instruction denotes a byte operation rather than a word operation. The ‘w’ bits select the address of the base register. W15] Ws ∈ [W0 . 1 for byte).. Register direct addressing must be used for Wb. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . Post-increment W2 Before Instruction W0 AA55 W1 2211 W2 1001 Data 1000 FFFF SR 0000 After Instruction W0 AA55 W1 2211 W2 1002 Data 1000 11FF SR 0000 DS70030E-page 5-22 Advance Information  2003 Microchip Technology Inc.... The ‘p’ bits select the source Address mode.(Ws) → Wd N. Z 0110 0www wBqq qddd dppp ssss Compute the logical AND operation of the contents of the source register Ws and the contents of the base register Wb and place the result in the destination register Wd. W15] (Wb).AND. AND W0 and W1.dsPIC30F Programmer’s Reference Manual AND Syntax: {label:} And Wb and Ws AND{. The ‘B’ bit selects byte or word operation (0 for word. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 AND. The ‘q’ bits select the destination Address mode. [--Ws]. You may use a .W extension to denote a word operation.B W0. W15] Wd ∈ [W0 .B} Wb. Either register direct or indirect addressing may be used for Ws and Wd. [Ws++]. The ‘d’ bits select the address of the destination register. store to [W2] (Byte mode) .. [Ws--]. . Note: The extension . [++Ws]. and . The ‘s’ bits select the address of the source register. W1 [W2++] . but it is not required.

[W1++]. AND W0 and [W1]. Post-increment W1 Before Instruction W0 AA55 W1 1000 W2 55AA Data 1000 2634 SR 0000 After Instruction W0 AA55 W1 1002 W2 2214 Data 1000 2634 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. store to W2 (Word mode) . Instruction Descriptions Example 2 AND W0. and . W2 . Advance Information DS70030E-page 5-23 .Section 5.

the result is sign-extended. Note 1: The extension . You may use a . If WREG is specified. The ‘B’ bit selects byte or word operation (0 for word. Z.dsPIC30F Programmer’s Reference Manual ASR Syntax: Operands: Operation: {label:} Arithmetic Shift Right f ASR{. the result is stored in WREG. If WREG is not specified.WREG} f ∈ [0 . but it is not required. 2: The WREG is set to working register W0. ASR RAM400 and store to WREG . The ‘f’ bits select the address of the file register. 1 for file register). the result is stored in the file register. . WREG . The Least Significant bit of the file register is shifted into the Carry bit of the Status Register.B in the instruction denotes a byte operation rather than a word operation. 8191] For byte operation: (f<7>) → Dest<7> (f<7>) → Dest<6> (f<6:1>) → Dest<5:0> (f<0>) → C For word operation: (f<15>) → Dest<15> (f<15>) → Dest<14> (f<14:1>) → Dest<13:0> (f<0>) → C C Status Affected: Encoding: Description: N. Words: Cycles: Example 1 1 1 ASR. The ‘D’ bit selects the destination (0 for WREG.. The optional WREG operand determines the destination register.W extension to denote a word operation. 1 for byte). C 1101 0101 1BDf ffff ffff ffff Shift the contents of the file register one bit to the right and place the result in the destination register.B RAM400. After the shift is performed. C=1) DS70030E-page 5-24 Advance Information  2003 Microchip Technology Inc.B} f {. ASR RAM200 (Word mode) Before Instruction RAM200 8009 SR 0000 After Instruction RAM200 C004 SR 0009 (N.. (Byte mode) Before Instruction WREG 0600 RAM400 0823 SR 0000 Example 2 ASR RAM200 After Instruction WREG 0611 RAM400 0823 SR 0001 (C=1) .

The ‘p’ bits select the source Address mode. but it is not required.. 1 for byte). Either register direct or indirect addressing may be used for Ws and Wd. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 . After the shift is performed. The ‘s’ bits select the address of the source register. Words: Cycles: 1 1 5 Instruction Descriptions  2003 Microchip Technology Inc. [Ws].. W15] Wd ∈ [W0 .. You may use a .W extension to denote a word operation. Z. [Ws--]. [--Ws]. The ‘d’ bits select the address of the destination register. The ‘q’ bits select the destination Address mode. [++Ws].. C 1101 0001 1Bqq qddd dppp ssss Shift the contents of the source register Ws one bit to the right and place the result in the destination register Wd.B} Ws. The ‘B’ bit selects byte or word operation (0 for word. W15] For byte operation: (Ws<7>) → Wd<7> (Ws<7>) → Wd<6> (Ws<6:1>) → Wd<5:0> (Ws<0>) → C For word operation: (Ws<15>) → Wd<15> (Ws<15>) → Wd<14> (Ws<14:1>) → Wd<13:0> (Ws<0>) → C C Status Affected: Encoding: Description: N.B in the instruction denotes a byte operation rather than a word operation.Section 5. The Least Significant bit of Ws is shifted into the Carry bit of the Status Register. Advance Information DS70030E-page 5-25 . Instruction Descriptions ASR Syntax: {label:} Arithmetic Shift Right Ws ASR{. Note: The extension . [Ws++]. the result is sign-extended.

C=1) DS70030E-page 5-26 Advance Information  2003 Microchip Technology Inc. ASR W12 and store to W13 (Word mode) Before Instruction W12 AB01 W13 0322 SR 0000 After Instruction W12 AB01 W13 D580 SR 0009 (N. . Post-increment W0 and W1 Before Instruction W0 0600 W1 0801 Data 600 2366 Data 800 FFC0 SR 0000 After Instruction W0 0601 W1 0802 Data 600 2366 Data 800 33C0 SR 0000 Example 2 ASR W12. [W1++] .dsPIC30F Programmer’s Reference Manual Example 1 ASR.B [W0++]. W13 . ASR [W0] and store to [W1] (Byte mode) .

ASR W0 by 15 and store to W1 Before Instruction W0 70FF W1 CC26 SR 0000 After Instruction W0 70FF W1 0000 SR 0002 (Z=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. The ‘w’ bits select the address of the base register. the result is sign-extended. #0x6. The ‘d’ bits select the address of the destination register. ASR W0 by 4 and store to W1 Before Instruction W0 060F W1 1234 SR 0000 Example 2 ASR W0. #lit4. Z 1101 1110 1www wddd d100 kkkk Arithmetic shift right the contents of the source register Wb by the 4-bit unsigned literal and store the result in the destination register Wnd. After the shift is performed. ASR W0 by 6 and store to W1 Before Instruction W0 80FF W1 0060 SR 0000 Example 3 ASR W0. W1 After Instruction W0 80FF W1 FE03 SR 0008 (N=1) .. #0xF. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 ASR 1 1 W0. Direct addressing must be used for Wb and Wnd. W1 . #0x4... W15] lit4<3:0> → Shift_Val Wb<15> → Wnd<15:15-Shift_Val+1> Wb<15:Shift_Val> → Wnd<15-Shift_Val:0> N. Wnd Wb ∈ [W0 .15] Wnd ∈ [W0 .Section 5.. W15] lit4 ∈ [0. W1 After Instruction W0 060F W1 0060 SR 0000 .. Advance Information DS70030E-page 5-27 . The ‘k’ bits provide the literal operand. Note: This instruction operates in Word mode only.. Instruction Descriptions ASR Syntax: Operands: {label:} Arithmetic Shift Right by Short Literal ASR Wb.

The ‘s’ bits select the address of the source register.. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 ASR W0. The ‘w’ bits select the address of the base register. Note 1: This instruction operates in Word mode only. Wns and Wnd.dsPIC30F Programmer’s Reference Manual ASR Syntax: Operands: {label:} Arithmetic Shift Right by Wns ASR Wb. ASR W11 by W12 and store to W13 Before Instruction W11 8765 W12 88E4 W13 A5A5 SR 0000 After Instruction W11 8765 W12 88E4 W13 F876 SR 0008 (N=1) DS70030E-page 5-28 Advance Information  2003 Microchip Technology Inc. W15] Wns ∈ [W0 . After the shift is performed. W5. W6 . Wns. 2: If Wns is greater than 15... Z 1101 1110 1www wddd d000 ssss Arithmetic shift right the contents of the source register Wb by the 4 Least Significant bits of Wns (up to 15 positions) and store the result in the destination register Wnd. W13 After Instruction W0 6688 W5 000A W6 0019 SR 0000 .W15] Wnd ∈ [W0 .. ASR W0 by W5 and store to W6 Before Instruction W0 6688 W5 000A W6 FF00 SR 0000 Example 3 ASR W11. Direct addressing must be used for Wb. . ASR W0 by W5 and store to W6 Before Instruction W0 80FF W5 0004 W6 2633 SR 0000 Example 2 ASR W0.. W12. and Wnd = 0xFFFF if Wb is negative. the result is sign-extended. W6 After Instruction W0 80FF W5 0004 W6 F80F SR 0000 . Wnd Wb ∈ [W0 . The ‘d’ bits select the address of the destination register. Wnd = 0x0 if Wb is positive.. W5. W15] Wns<3:0> → Shift_Val Wb<15> → Wnd<15:15-Shift_Val+1> Wb<15:Shift_Val> → Wnd<15-Shift_Val:0> N.

B 0x800.. 8191] for byte operation f ∈ [0 . but it is not required. 7] for byte operation bit4 ∈ [0 .B in the instruction denotes a byte operation rather than a word operation.. ‘bit4’ must be between 0 and 7. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations... 15] for byte operation 0 → f<bit4> None 1010 1001 bbbf ffff ffff fffb Clear the bit in the file register f specified by ‘bit4’. 3: When this instruction operates in Byte mode. Clear bit 7 in 0x800 Before Instruction Data 0800 66EF SR 0000 Example 2 BCLR After Instruction Data 0800 666F SR 0000 . The ‘b’ bits select value bit4 of the bit position to be cleared. Instruction Descriptions BCLR Syntax: Operands: {label:} Bit Clear f BCLR{. Advance Information DS70030E-page 5-29 . 8190] (even only) for word operation bit4 ∈ [0 . Clear bit 10 in 0x400 0x400. You may use a ..Section 5. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BCLR.B} f. #0xA Before Instruction Data 0400 AA55 SR 0000 After Instruction Data 0400 A855 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.W extension to denote a word operation. #bit4 f ∈ [0 .. The ‘f’ bits select the address of the file register. bit 15 for word operations). Note 1: The extension .. 2: When this instruction operates in Word mode.. #0x7 . the file register address must be word aligned.

Clear bit 0 in [W0] . W15] bit4 ∈ [0 . #0x2 . bit 15 for word operations). The ‘B’ bit selects byte or word operation (0 for word.. 15] for word operation 0 → Ws<bit4> None 1010 0001 bbbb 0B00 0ppp ssss Clear the bit in register Ws specified by ‘bit4’. 3: When this instruction operates in Byte mode.. the source register address must be word aligned.. [Ws].B in the instruction denotes a byte operation rather than a word operation. but it is not required. #bit4 Operands: Ws ∈ [W0 . The ‘b’ bits select value bit4 of the bit position to be cleared.. Note 1: The extension . The ‘p’ bits select the source Address mode. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations. [--Ws].B} Ws. [Ws--]. [Ws++]. [++Ws]. Register direct or indirect addressing may be used for Ws. 7] for byte operation bit4 ∈ [0 . You may use a . 2: When this instruction operates in Word mode.B W2. #0x0 After Instruction W2 F230 SR 0000 . .. 1 for byte). Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BCLR. Post-increment W0 Before Instruction W0 2300 Data 2300 5607 SR 0000 After Instruction W0 2302 Data 2300 5606 SR 0000 DS70030E-page 5-30 Advance Information  2003 Microchip Technology Inc. Clear bit 3 in W2 Before Instruction W2 F234 SR 0000 Example 2 BCLR [W0++].W extension to denote a word operation.. ‘bit4’ must be between 0 and 7. The ‘s’ bits select the address of the source/destination register.dsPIC30F Programmer’s Reference Manual BCLR Syntax: {label:} Bit Clear in Ws BCLR{.

. where Slit16 ∈ [-32768 . . The offset of the branch is the 2’s complement number ‘2*Slit16’. . . (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 0111 nnnn nnnn nnnn nnnn The program will branch unconditionally. The ‘n’ bits are a signed literal that specifies the number of program words offset from (PC+2). . . which supports branches up to 32K instructions forward or backward. . . . . . . After the branch is taken. . . . since the PC will have incremented to fetch the next instruction. . . +32767]. Branch to THERE+0x2 002000 HERE: 002002 002004 002006 002008 00200A THERE: 00200C PC SR Example 3 Before Instruction 00 2000 0000 BRA 0x1366 . . absolute address or expression. . Instruction Descriptions BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Branch Unconditionally BRA Expr Expr may be a label. . . . THERE+0x2 . Advance Information DS70030E-page 5-31 . absolute address or expression.Section 5. After Instruction PC 00 200A SR 0000 . .. . . Branch to THERE PC SR Example 2 Before Instruction 00 2000 0000 BRA . . . . . . . . Branch to 0x1366 5 Instruction Descriptions 002000 HERE: 002002 002004 PC SR Before Instruction 00 2000 0000 After Instruction PC 00 1366 SR 0000  2003 Microchip Technology Inc. the new address will be (PC+2) + 2*Slit16. Expr is resolved by the linker to a Slit16. Words: Cycles: Example 1 1 2 002000 HERE: 002002 002004 002006 002008 00200A THERE: 00200C BRA . After Instruction PC 00 200C SR 0000 . . relative to the next PC. THERE . . . . . . The Slit16 value is resolved by the linker from the supplied label. .

. . . . . . Words: Cycles: Example 1 1 2 002000 HERE: 002002 ... 002106 002108 TABLE7: 00210A BRA . . .. . . since the PC will have incremented to fetch the next instruction. Branch forward 2*W7 PC W7 SR Before Instruction 00 2000 0084 0000 After Instruction PC 00 2108 W7 0084 SR 0000 DS70030E-page 5-32 Advance Information  2003 Microchip Technology Inc. . relative to the next PC.. The offset of the branch is the sign-extended 17-bit value (2*Wn). which supports branches up to 32K instructions forward or backward. W15] (PC+2) + (2*Wn) → PC NOP → Instruction Register None 0000 0001 0110 0000 0000 ssss The program will branch unconditionally.. . . The ‘s’ bits select the address of the source register. . . the new PC will be (PC+2)+2*Wn. W7 . . .dsPIC30F Programmer’s Reference Manual BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Computed Branch BRA Wn Wn ∈ [W0 . . After this instruction executes. . .

.. .... The Slit16 value is resolved by the linker from the supplied label.. Otherwise. . . . branch to CARRY . . .. . absolute address or expression. Otherwise. +32767]. . . . then the program will branch relative to the next PC. CARRY . The offset of the branch is the 2’s complement number ‘2*Slit16’. . If C is set. Expr Expr may be a label.Section 5.. . where Slit16 ∈ [-32768 . . . which supports branches up to 32K instructions forward or backward.. Instruction Descriptions BRA C Syntax: Operands: Operation: {label:} Branch if Carry BRA C. Expr is resolved by the linker to a Slit16. . with a NOP executed in the second cycle. continue 5 Instruction Descriptions After Instruction 00 2002 0000 PC SR Before Instruction 00 2000 0000 PC SR  2003 Microchip Technology Inc.. the new address will be (PC+2) + 2*Slit16.. CARRY . GOTO THERE . .. The instruction then becomes a two-cycle instruction.. since the PC will have incremented to fetch the next instruction. continue CARRY: THERE: PC SR Before Instruction 00 2000 0001 (C=1) PC SR After Instruction 00 2008 0001 (C=1) Example 2 002000 002002 002004 002006 002008 00200A 00200C 00200E HERE: NO_C: CARRY: THERE: BRA C. . branch to CARRY .. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 002002 002004 002006 002008 00200A 00200C 00200E HERE: NO_C: BRA C.... .. . If C is set. . Condition = C If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 0001 nnnn nnnn nnnn nnnn If the Carry flag bit is ‘1’. If the branch is taken. Advance Information DS70030E-page 5-33 . GOTO THERE . absolute address or expression. . The ‘n’ bits are a 16-bit signed literal that specify the offset from (PC+2) in instruction words. .

. ..... ... . .dsPIC30F Programmer’s Reference Manual Example 3 006230 006232 006234 006236 006238 00623A 00623C 00623E HERE: NO_C: BRA C. continue CARRY: THERE: PC SR Example 4 Before Instruction 00 6230 0001 (C=1) PC SR After Instruction 00 6238 0001 (C=1) 006230 START: 006232 006234 CARRY: 006236 006238 00623A 00623C HERE: 00623E . CARRY . branch to CARRY . .. Otherwise... CARRY .... . branch to CARRY . ... . continue PC SR Before Instruction 00 623C 0001 (C=1) PC SR After Instruction 00 6234 0001 (C=1) DS70030E-page 5-34 Advance Information  2003 Microchip Technology Inc.... GOTO THERE . .. If C is set... ...... . Otherwise.. BRA C... .. If C is set.

LOOP . The ‘n’ bits are a 16-bit signed literal that specify the offset from (PC+2) in instruction words. . Otherwise. GE. where Slit16 ∈ [-32768 . After Instruction PC 00 7600 SR 0000 007600 LOOP: 007602 007604 007606 007608 HERE: 00760A NO_GE: . . Note: The assembler will convert the specified label into the offset to be used. . +32767].. with a NOP executed in the second cycle. If GE. The instruction then becomes a two-cycle instruction.. . . . The Slit16 value is resolved by the linker from the supplied label. Expr Expr may be a label. then the program will branch relative to the next PC. BRA . Instruction Descriptions BRA GE Syntax: Operands: {label:} Branch if Signed Greater Than or Equal BRA GE. . . .. . continue 5 Instruction Descriptions PC SR Before Instruction 00 7608 0008 (N=1) After Instruction PC 00 760A SR 0008 (N=1)  2003 Microchip Technology Inc. absolute address or expression. continue PC SR Example 2 Before Instruction 00 7608 0000 .. . Otherwise. absolute address or expression. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 007600 LOOP: 007602 007604 007606 007608 HERE: 00760A NO_GE: . branch to LOOP . branch to LOOP . If GE. . . the new address will be (PC+2) + 2*Slit16. . which supports branches up to 32K instructions forward or backward. . . . Advance Information DS70030E-page 5-35 . . .Section 5.. . Condition = (N&&OV)||(!N&&!OV) If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 1101 nnnn nnnn nnnn nnnn If the logical expression (N&&OV)||(!N&&!OV) is true. . BRA . GE. LOOP .. If the branch is taken. . The offset of the branch is the 2’s complement number ‘2*Slit16’. Expr is resolved by the linker to a Slit16. . since the PC will have incremented to fetch the next instruction. . .

Expr Expr may be a label. Slit16. . . branch .. . . The instruction then becomes a two-cycle instruction. +32767] program words. . the new address will be (PC+2) + 2*Slit16. . absolute address or expression. . continue PC SR Before Instruction 00 2000 0001 (C=1) PC SR After Instruction 00 200C 0001 (C=1) DS70030E-page 5-36 Advance Information  2003 Microchip Technology Inc. . Note: This instruction is identical to the BRA C. . The ‘n’ bits are a 16-bit signed literal that specify the offset from (PC+2) in instruction words. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_GEU: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA GEU. The offset of the branch is the 2’s complement number ‘2*Slit16’. . Expr is resolved by the linker to a Slit16 offset that supports an offset range of [-32768 .dsPIC30F Programmer’s Reference Manual BRA GEU Syntax: Operands: {label:} Branch if Unsigned Greater Than or Equal BRA GEU. If the branch is taken. .. since the PC will have incremented to fetch the next instruction.. . . GOTO THERE . Condition = C If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 0001 nnnn nnnn nnnn nnnn If the Carry flag is ‘1’. . with a NOP executed in the second cycle. Expr (Branch if Carry) instruction and has the same encoding. absolute address or expression. If C is set. . . Otherwise. which supports branches up to 32K instructions forward or backward. then the program will branch relative to the next PC. The Slit16 value is resolved by the linker from the supplied label. It will reverse assemble as BRA C.. BYPASS . to BYPASS . . .

Condition = (!Z&&N&&OV)||(!Z&&!N&&!OV) If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 1100 nnnn nnnn nnnn nnnn If the logical expression (!Z&&N&&OV)||(!Z&&!N&&!OV) is true. .. Otherwise. . . . Expr Expr may be a label. . branch to BYPASS . Instruction Descriptions BRA GT Syntax: Operands: {label:} Branch if Signed Greater Than BRA GT. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_GT: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA GT.. . absolute address or expression. The offset of the branch is the 2’s complement number ‘2*Slit16’.Section 5. If GT. continue PC SR Before Instruction 00 2000 0001 (C=1) PC SR After Instruction 00 200C 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.. . . The ‘n’ bits are a 16-bit signed literal that specify the offset from (PC+2) in instruction words. . . . . the new address will be (PC+2) + 2*Slit16. +32767]. The Slit16 value is resolved by the linker from the supplied label. Advance Information DS70030E-page 5-37 . with a NOP executed in the second cycle. Expr is resolved by the linker to a Slit16. . . where Slit16 ∈ [-32768 . The instruction then becomes a two-cycle instruction. . then the program will branch relative to the next PC. which supports branches up to 32K instructions forward or backward. . GOTO THERE . since the PC will have incremented to fetch the next instruction. absolute address or expression. . If the branch is taken. BYPASS ..

. . If the branch is taken. . the new address will be (PC+2) + 2*Slit16. The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). .. Expr Expr may be a label. . The Slit16 value is resolved by the linker from the supplied label.dsPIC30F Programmer’s Reference Manual BRA GTU Syntax: Operands: {label:} Branch if Unsigned Greater Than BRA GTU. BYPASS . . which supports branches up to 32K instructions forward or backward. . then the program will branch relative to the next PC. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_GTU: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA GTU. . . branch to BYPASS .. . GOTO THERE . . . absolute address or expression. +32767]. . . Condition = (C&&!Z) If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 1110 nnnn nnnn nnnn nnnn If the logical expression (C&&!Z) is true. . with a NOP executed in the second cycle. The offset of the branch is the 2’s complement number ‘2*Slit16’. If GTU. Expr is resolved by the linker to a Slit16. The instruction then becomes a two-cycle instruction. where Slit16 ∈ [-32768 . Otherwise. . continue PC SR Before Instruction 00 2000 0001 (C=1) PC SR After Instruction 00 200C 0001 (C=1) DS70030E-page 5-38 Advance Information  2003 Microchip Technology Inc. since the PC will have incremented to fetch the next instruction. .. . absolute address or expression..

. . The instruction then becomes a two-cycle instruction. Expr is resolved by the linker to a Slit16. . . branch to BYPASS . absolute address or expression. since the PC will have incremented to fetch the next instruction. Advance Information DS70030E-page 5-39 . Expr Expr may be a label. Otherwise.Section 5. where Slit16 ∈ [-32768 . then the program will branch relative to the next PC. +32767]. . Condition = Z||(N&&!OV)||(!N&&OV) If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 0100 nnnn nnnn nnnn nnnn If the logical expression (Z||(N&&!OV)||(!N&&OV)) is true. The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). . . . GOTO THERE . . . the new address will be (PC+2) + 2*Slit16. If the branch is taken. The Slit16 value is resolved by the linker from the supplied label. . BYPASS . . . . continue PC SR Before Instruction 00 2000 0001 (C=1) PC SR After Instruction 00 2002 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.. . Instruction Descriptions BRA LE Syntax: Operands: {label:} Branch if Signed Less Than or Equal BRA LE. with a NOP executed in the second cycle... Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_LE: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA LE. . If LE. absolute address or expression.. The offset of the branch is the 2’s complement number ‘2*Slit16’. . which supports branches up to 32K instructions forward or backward.

. absolute address or expression. . . The Slit16 value is resolved by the linker from the supplied label. Expr is resolved by the linker to a Slit16. which supports branches up to 32K instructions forward or backward. Condition = !C||Z If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 0110 nnnn nnnn nnnn nnnn If the logical expression (!C||Z) is true.. where Slit16 ∈ [-32768 . then the program will branch relative to the next PC.. . . . GOTO THERE . The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2).dsPIC30F Programmer’s Reference Manual BRA LEU Syntax: Operands: {label:} Branch if Unsigned Less Than or Equal BRA LEU. . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_LEU: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA LEU. since the PC will have incremented to fetch the next instruction. continue PC SR Before Instruction 00 2000 0001 (C=1) PC SR After Instruction 00 200C 0001 (C=1) DS70030E-page 5-40 Advance Information  2003 Microchip Technology Inc. If LEU. the new address will be (PC+2) + 2*Slit16. The offset of the branch is the 2’s complement number ‘2*Slit16’. BYPASS . Otherwise. .. . . . . Expr Expr may be a label. . . . absolute address or expression.. with a NOP executed in the second cycle. +32767]. . . If the branch is taken. branch to BYPASS . . The instruction then becomes a two-cycle instruction.

. The offset of the branch is the 2’s complement number ‘2*Slit16’. . +32767]. GOTO THERE . . . . where Slit16 ∈ [-32768 . absolute address or expression. with a NOP executed in the second cycle... Condition = (N&&!OV)||(!N&&OV) If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 0101 nnnn nnnn nnnn nnnn If the logical expression ( (N&&!OV)||(!N&&OV) ) is true. Otherwise. BYPASS . Expr Expr may be a label.Section 5. . If the branch is taken. . . The instruction then becomes a two-cycle instruction. If LT. The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). . then the program will branch relative to the next PC. continue PC SR Before Instruction 00 2000 0001 (C=1) After Instruction PC 00 2002 SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. . . Advance Information DS70030E-page 5-41 .. Expr is resolved by the linker to a Slit16. the new address will be (PC+2) + 2*Slit16. Instruction Descriptions BRA LT Syntax: Operands: {label:} Branch if Signed Less Than BRA LT. since the PC will have incremented to fetch the next instruction.. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_LT: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA LT. . . . . absolute address or expression. branch to BYPASS . . which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label. .

. absolute address or expression. Expr Expr may be a label. BYPASS . . . the new address will be (PC+2) + 2*Slit16. . If the branch is taken. since the PC will have incremented to fetch the next instruction. branch to BYPASS .. It will reverse assemble as BRA NC. . .. . where Slit16 ∈ [-32768 . . which supports branches up to 32K instructions forward or backward. then the program will branch relative to the next PC. Condition = !C If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 1001 nnnn nnnn nnnn nnnn If the Carry flag is ‘0’. absolute address or expression. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_LTU: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA LTU. The Slit16 value is resolved by the linker from the supplied label. . . Expr is resolved by the linker to a Slit16.. If LTU. Expr (Branch if Not Carry) instruction and has the same encoding. +32767]. Otherwise. . . GOTO THERE . . with a NOP executed in the second cycle. Slit16. . continue PC SR Before Instruction 00 2000 0001 (C=1) PC SR After Instruction 00 2002 0001 (C=1) DS70030E-page 5-42 Advance Information  2003 Microchip Technology Inc. The instruction then becomes a two-cycle instruction. The offset of the branch is the 2’s complement number ‘2*Slit16’. .. . .dsPIC30F Programmer’s Reference Manual BRA LTU Syntax: Operands: {label:} Branch if Unsigned Less Than BRA LTU. . The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). Note: This instruction is identical to the BRA NC.

GOTO THERE . Otherwise. . The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). If the branch is taken. continue PC SR Before Instruction 00 2000 0008 (N=1) PC SR After Instruction 00 200C 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. .. Expr is resolved by the linker to a Slit16. Expr Expr may be a label. which supports branches up to 32K instructions forward or backward. . since the PC will have incremented to fetch the next instruction. . +32767]. then the program will branch relative to the next PC. . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_N: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA N. The Slit16 value is resolved by the linker from the supplied label. Instruction Descriptions BRA N Syntax: Operands: {label:} Branch if Negative BRA N. . . Condition = N If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register. . The offset of the branch is the 2’s complement number ‘2*Slit16’. . . .Section 5.. absolute address or expression. . None 0011 0011 nnnn nnnn nnnn nnnn If the Negative flag is ‘1’. . . The instruction then becomes a two-cycle instruction.. . where Slit16 ∈ [-32768 . If N. .. BYPASS . . absolute address or expression. with a NOP executed in the second cycle. branch to BYPASS . Advance Information DS70030E-page 5-43 . the new address will be (PC+2) + 2*Slit16.

. . The instruction then becomes a two-cycle instruction.. Expr Expr may be a label. . . . then the program will branch relative to the next PC. GOTO THERE .dsPIC30F Programmer’s Reference Manual BRA NC Syntax: Operands: {label:} Branch if Not Carry BRA NC. . . branch to BYPASS . . Otherwise. since the PC will have incremented to fetch the next instruction. . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_NC: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA NC. absolute address or expression. . . The offset of the branch is the 2’s complement number ‘2*Slit16’. . where Slit16 ∈ [-32768 .. BYPASS . with a NOP executed in the second cycle. . . . If NC. the new address will be (PC+2) + 2*Slit16. Expr is resolved by the linker to a Slit16. The Slit16 value is resolved by the linker from the supplied label. +32767]. . If the branch is taken. . absolute address or expression. which supports branches up to 32K instructions forward or backward. continue PC SR Before Instruction 00 2000 0001 (C=1) PC SR After Instruction 00 2002 0001 (C=1) DS70030E-page 5-44 Advance Information  2003 Microchip Technology Inc. Condition = !C If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 1001 nnnn nnnn nnnn nnnn If the Carry flag is ‘0’. The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2).. ..

. If the branch is taken. The Slit16 value is resolved by the linker from the supplied label.. where Slit16 ∈ [-32768 . . .. Instruction Descriptions BRA NN Syntax: Operands: {label:} Branch if Not Negative BRA NN. branch to BYPASS . . Otherwise. .. . Condition = !N If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 1011 nnnn nnnn nnnn nnnn If the Negative flag is ‘0’. continue PC SR Before Instruction 00 2000 0000 PC SR After Instruction 00 200C 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.Section 5.. The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). GOTO THERE . Advance Information DS70030E-page 5-45 . absolute address or expression. . absolute address or expression. then the program will branch relative to the next PC. the new address will be (PC+2) + 2*Slit16. . . with a NOP executed in the second cycle. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_NN: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA NN. The offset of the branch is the 2’s complement number ‘2*Slit16’. Expr Expr may be a label. . since the PC will have incremented to fetch the next instruction. Expr is resolved by the linker to a Slit16. . . If NN. The instruction then becomes a two-cycle instruction. . . BYPASS . . which supports branches up to 32K instructions forward or backward. . . +32767].

. . absolute address or expression.. . +32767]. which supports branches up to 32K instructions forward or backward. continue PC SR Before Instruction 00 2000 0008 (N=1) PC SR After Instruction 00 200C 0008 (N=1) DS70030E-page 5-46 Advance Information  2003 Microchip Technology Inc. then the program will branch relative to the next PC. . . . The offset of the branch is the 2’s complement number ‘2*Slit16’. . GOTO THERE . . Condition = !OV If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 1000 nnnn nnnn nnnn nnnn If the Overflow flag is ‘0’. . . Otherwise. . . . Expr Expr may be a label. Expr is resolved by the linker to a Slit16. BYPASS . If the branch is taken. . The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). . . If NOV..dsPIC30F Programmer’s Reference Manual BRA NOV Syntax: Operands: {label:} Branch if Not Overflow BRA NOV. with a NOP executed in the second cycle. The Slit16 value is resolved by the linker from the supplied label. .. the new address will be (PC+2) + 2*Slit16. where Slit16 ∈ [-32768 . . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_NOV: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA NOV. The instruction then becomes a two-cycle instruction. since the PC will have incremented to fetch the next instruction. branch to BYPASS . absolute address or expression. .

. The offset of the branch is the 2’s complement number ‘2*Slit16’. . . Condition = !Z If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 1010 nnnn nnnn nnnn nnnn If the Z flag is ‘0’. since the PC will have incremented to fetch the next instruction. .. Instruction Descriptions BRA NZ Syntax: Operands: {label:} Branch if Not Zero BRA NZ. . the new address will be (PC+2) + 2*Slit16. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_NZ: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA NZ.. branch to BYPASS . If NZ. . . GOTO THERE . then the program will branch relative to the next PC. .Section 5. The instruction then becomes a two-cycle instruction. absolute address or expression. . The Slit16 value is resolved by the linker from the supplied label. continue PC SR Before Instruction 00 2000 0002 (Z=1) PC SR After Instruction 00 2002 0002 (Z=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. +32767]. where Slit16 ∈ [-32768 . . . absolute address or expression. .. BYPASS . If the branch is taken. Expr is resolved by the linker to a Slit16. . with a NOP executed in the second cycle. Advance Information DS70030E-page 5-47 . . . The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). Otherwise. Expr Expr may be a label. which supports branches up to 32K instructions forward or backward.. . .

. . since the PC will have incremented to fetch the next instruction. Otherwise.. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_OA: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA OA. The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). the new address will be (PC+2) + 2*Slit16. absolute address or expression. . continue PC SR Before Instruction 00 2000 8800 (OA. which supports branches up to 32K instructions forward or backward.dsPIC30F Programmer’s Reference Manual BRA OA Syntax: Operands: {label:} Branch if Overflow Accumulator A BRA OA. . . The Slit16 value is resolved by the linker from the supplied label. branch to BYPASS . . Expr Expr may be a label. absolute address or expression. BYPASS . . . The instruction then becomes a two-cycle instruction.. OAB=1) DS70030E-page 5-48 Advance Information  2003 Microchip Technology Inc. then the program will branch relative to the next PC.. . If the branch is taken. If OA. . The offset of the branch is the 2’s complement number ‘2*Slit16’. OAB=1) PC SR After Instruction 00 200C 8800 (OA. +32767]. Condition = OA If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0000 1100 nnnn nnnn nnnn nnnn If the Overflow Accumulator A flag is ‘1’. . Expr is resolved by the linker to a Slit16.. . Note: The assembler will convert the specified label into the offset to be used. . . with a NOP executed in the second cycle. . . GOTO THERE . where Slit16 ∈ [-32768 . . .

If the branch is taken. .. The instruction then becomes a two-cycle instruction. . . continue PC SR Before Instruction 00 2000 8800 (OA. absolute address or expression. absolute address or expression. The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). with a NOP executed in the second cycle. Condition = OB If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0000 1101 nnnn nnnn nnnn nnnn If the Overflow Accumulator B flag is ‘1’. The offset of the branch is the 2’s complement number ‘2*Slit16’. .. which supports branches up to 32K instructions forward or backward. . . branch to BYPASS . Instruction Descriptions BRA OB Syntax: Operands: {label:} Branch if Overflow Accumulator B BRA OB. GOTO THERE . . Advance Information DS70030E-page 5-49 . then the program will branch relative to the next PC. OAB=1) PC SR After Instruction 00 2002 8800 (OA. . the new address will be (PC+2) + 2*Slit16. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_OB: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA OB. +32767]. where Slit16 ∈ [-32768 . . . OAB=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. . . . .. BYPASS . .. . Otherwise. The Slit16 value is resolved by the linker from the supplied label. .Section 5. since the PC will have incremented to fetch the next instruction. Expr Expr may be a label. If OB. Expr is resolved by the linker to a Slit16.

Condition = OV If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 0000 nnnn nnnn nnnn nnnn If the Overflow flag is ‘1’.dsPIC30F Programmer’s Reference Manual BRA OV Syntax: Operands: {label:} Branch if Overflow BRA OV. with a NOP executed in the second cycle. . . The instruction then becomes a two-cycle instruction. The Slit16 value is resolved by the linker from the supplied label. . . The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). the new address will be (PC+2) + 2*Slit16.. . Expr is resolved by the linker to a Slit16. absolute address or expression. .. . Expr Expr may be a label. . The offset of the branch is the 2’s complement number ‘2*Slit16’. . then the program will branch relative to the next PC. . absolute address or expression. . branch to BYPASS . continue PC SR Before Instruction 00 2000 0002 (Z=1) PC SR After Instruction 00 2002 0002 (Z=1) DS70030E-page 5-50 Advance Information  2003 Microchip Technology Inc. +32767]. where Slit16 ∈ [-32768 . . . since the PC will have incremented to fetch the next instruction. .. Otherwise. which supports branches up to 32K instructions forward or backward. If the branch is taken. GOTO THERE . . . . . If OV.. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_OV 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA OV. BYPASS .

. Expr Expr may be a label. GOTO THERE . . . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_SA: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA SA.. . branch to BYPASS . then the program will branch relative to the next PC. Condition = SA If (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0000 1110 nnnn nnnn nnnn nnnn If the Saturation Accumulator A flag is ‘1’. . Advance Information DS70030E-page 5-51 . The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). which supports branches up to 32K instructions forward or backward. .. The Slit16 value is resolved by the linker from the supplied label. . SAB=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. where Slit16 ∈ [-32768 . Instruction Descriptions BRA SA Syntax: Operands: {label:} Branch if Saturation Accumulator A BRA SA. Otherwise. . absolute address or expression. . . absolute address or expression. . . . If SA. .Section 5. BYPASS . If the branch is taken. since the PC will have incremented to fetch the next instruction. +32767]. . the new address will be (PC+2) + 2*Slit16. . with a NOP executed in the second cycle. Expr is resolved by the linker to a Slit16. The instruction then becomes a two-cycle instruction. . . SAB=1) PC SR After Instruction 00 200C 2400 (SA. continue PC SR Before Instruction 00 2000 2400 (SA.. The offset of the branch is the 2’s complement number ‘2*Slit16’.

The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). . which supports branches up to 32K instructions forward or backward. . Expr Expr may be a label. Otherwise. then the program will branch relative to the next PC. . If the branch is taken. . BYPASS . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 if branch taken) 002000 HERE: 002002 NO_SB: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA SB. . . . . absolute address or expression.. The instruction then becomes a two-cycle instruction. branch to BYPASS . . since the PC will have incremented to fetch the next instruction. Expr is resolved by the linker to a Slit16. continue PC SR Before Instruction 00 2000 0000 PC SR After Instruction 00 2002 0000 DS70030E-page 5-52 Advance Information  2003 Microchip Technology Inc.. the new address will be (PC+2) + 2*Slit16. GOTO THERE . Condition = SB if (Condition) (PC+2) + 2*Slit16→ PC NOP → Instruction Register None 0000 1111 nnnn nnnn nnnn nnnn If the Saturation Accumulator B flag is ‘1’. . . where Slit16 ∈ [-32768 .dsPIC30F Programmer’s Reference Manual BRA SB Syntax: Operands: {label:} Branch if Saturation Accumulator B BRA SB. . with a NOP executed in the second cycle. The Slit16 value is resolved by the linker from the supplied label. absolute address or expression. .. .. If SB. . +32767]. . . The offset of the branch is the 2’s complement number ‘2*Slit16’. .

absolute address or expression. . 1 1 (2 if branch taken) 002000 HERE: 002002 NO_Z: 002004 002006 002008 00200A 00200C BYPASS: 00200E BRA Z. which supports branches up to 32K instructions forward or backward.. The Slit16 value is resolved by the linker from the supplied label. The offset of the branch is the 2’s complement number ‘2*Slit16’. The instruction then becomes a two-cycle instruction.. . . absolute address or expression. . . . Expr Operation: Status Affected: Encoding: Description: Expr may be a label. Condition = Z if (Condition) (PC+2) + 2*Slit16 → PC NOP → Instruction Register None 0011 0010 nnnn nnnn nnnn nnnn If the Zero flag is ‘1’. with a NOP executed in the second cycle. If Z. .. the new address will be (PC+2) + 2*Slit16. branch to BYPASS . since the PC will have incremented to fetch the next instruction. Expr is resolved by the linker to a Slit16. Otherwise. Advance Information DS70030E-page 5-53 . . BYPASS . . where Slit16 ∈ [-32768 . continue Words: Cycles: Example 1 PC SR Before Instruction 00 2000 0002 (Z=1) PC SR After Instruction 00 200C 0002 (Z=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. . then the program will branch relative to the next PC.Section 5. Instruction Descriptions BRA Z Syntax: Operands: {label:} Branch if Zero BRA Z. GOTO THERE . . The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+2). .. . If the branch is taken. . . . . +32767].

8191] for byte operation f ∈ [0 . You may use a . 8190] (even only) for word operation bit4 ∈ [0 . Set bit 3 in 0x601 Before Instruction Data 0600 F234 SR 0000 Example 2 BSET After Instruction Data 0600 FA34 SR 0000 .. 7] for byte operation bit4 ∈ [0 . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BSET. ‘bit4’ must be between 0 and 7. #0x3 ... . Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations... 3: When this instruction operates in Byte mode.. #0xF Before Instruction Data 0444 5604 SR 0000 After Instruction Data 0444 D604 SR 0000 DS70030E-page 5-54 Advance Information  2003 Microchip Technology Inc. The ‘b’ bits select value bit4 of the bit position to be set.B} f.. Set bit 15 in 0x444 0x444. bit 15 for word operations). The ‘f’ bits select the address of the file register.. Note 1: The extension . 15] for word operation 1 → f<bit4> None 1010 1000 bbbf ffff ffff fffb Set the bit in the file register f specified by ‘bit4’. but it is not required.B in the instruction denotes a byte operation rather than a word operation. #bit4 f ∈ [0 .dsPIC30F Programmer’s Reference Manual BSET Syntax: Operands: {label:} Bit Set f BSET{.B 0x601. the file register address must be word aligned. 2: When this instruction operates in Word mode.W extension to denote a word operation.

The ‘B’ bit selects byte or word operation (0 for word. 1 for byte). [++Ws]. W15] bit4 ∈ [0 . #0x7 . Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations. The ‘b’ bits select value bit4 of the bit position to be cleared.B in the instruction denotes a byte operation rather than a word operation.W extension to denote a word operation. 3: When this instruction operates in Byte mode. Post-increment W4 Before Instruction W4 6700 Data 6700 1734 SR 0000 After Instruction W4 6702 Data 6700 1735 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. bit 15 for word operations). Register direct or indirect addressing may be used for Ws. the source register address must be word aligned.. but it is not required. [Ws++].Section 5. Instruction Descriptions BSET Syntax: {label:} Bit Set in Ws BSET{. Set bit 7 in W3 Before Instruction W3 0026 SR 0000 Example 2 BSET [W4++]. #0x0 After Instruction W3 00A6 SR 0000 . The ‘p’ bits select the source Address mode. Note 1: The extension . ‘bit4’ must be between 0 and 7. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BSET. 2: When this instruction operates in Word mode. You may use a . Set bit 0 in [W4] .B} Ws. [Ws--]... #bit4 Operands: Ws ∈ [W0 .. 15] for word operation 1 → Ws<bit4> None 1010 0000 bbbb 0B00 0ppp ssss Set the bit in register Ws specified by ‘bit4’.. 7] for byte operation bit4 ∈ [0 . [--Ws]. Advance Information DS70030E-page 5-55 .. The ‘s’ bits select the address of the source/destination register. [Ws].B W3.

or indirect addressing may be used for Ws... W3 . [Ws].Z Ws.C W2. The ‘p’ bits select the source Address mode. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the working register. [Ws++].Z W2.Z” operation is assumed. of the C bit Before Instruction W2 F234 W3 111F SR 0002 (Z=1. C=0) After Instruction W2 E234 W3 0550 SR 0002 (Z=1.dsPIC30F Programmer’s Reference Manual BSW Syntax: {label:} Bit Write in Ws BSW.Z” operation (default): Z → Ws<(Wb)> None 1010 1101 Zwww w000 0ppp ssss The (Wb) bit in register Ws is written with the value of the C or Z flag from the Status register.C BSW. Only the four Least Significant bits of Wb are used to determine the destination bit number. Note: This instruction only operates in Word mode. [++Ws]. The ‘Z’ bit selects the C or Z flag as source. [--Ws]. [Ws--]. W3 . C=0) After Instruction W2 7234 W3 111F SR 0002 (Z=1. Set bit W3 in W2 to the value . If no extension is provided. W15] Wb ∈ [W0 . The ‘w’ bits select the address of the bit select register. Set bit W3 in W2 to the complement . Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BSW. the “.. The ‘s’ bits select the address of the source register. of the Z bit Before Instruction W2 E235 W3 0550 SR 0002 (Z=1..C” operation: C → Ws<(Wb)> For “. C=0) Example 2 BSW. W15] For “. Wb Operands: Operation: Ws ∈ [W0 . C=0) DS70030E-page 5-56 Advance Information  2003 Microchip Technology Inc. . and either register direct. Register direct addressing must be used for Wb.

Post-decrement W1 Before After Instruction Instruction W1 1000 W1 0FFE W5 888B W5 888B Data 1000 C4DD Data 1000 CCDD SR 0001 (C=1) SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. W5 . complement of the Z bit . Set bit W6 in [W0++] to the value .Section 5. Instruction Descriptions Example 3 BSW. Set bit W5 in [W1] to the .C [++W0]. of the C bit Before After Instruction Instruction W0 1000 W0 1002 W6 34A3 W6 34A3 Data 1002 2380 Data 1002 2388 SR 0001 (Z=0. C=1) Example 4 BSW [W1--]. W6 . Advance Information DS70030E-page 5-57 . C=1) SR 0001 (Z=0.

Note 1: The extension . You may use a . but it is not required. For the bit4 operand. The ‘b’ bits select value bit4. 3: When this instruction operates in Byte mode.B 0x1001.. ‘bit4’ must be between 0 and 7. 8190] (even only) for word operation bit4 ∈ [0 . The ‘f’ bits select the address of the file register. #bit4 f ∈ [0 .. 7] for byte operation bit4 ∈ [0 . the file register address must be word aligned. the bit position to toggle. .B in the instruction denotes a byte operation rather than a word operation. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BTG. bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operation.dsPIC30F Programmer’s Reference Manual BTG Syntax: Operands: {label:} Bit Toggle f BTG{. Toggle bit 8 in RAM660 0x1660... bit 15 for word operation) of the byte. 15] for word operation (f)<bit4> → (f)<bit4> None 1010 1010 bbbf ffff ffff fffb Bit ‘bit4’ in file register f is toggled (complemented). #0x8 Before Instruction Data 1660 5606 SR 0000 After Instruction Data 1660 5706 SR 0000 DS70030E-page 5-58 Advance Information  2003 Microchip Technology Inc.. 2: When this instruction operates in Word mode.B} f.. 8191] for byte operation f ∈ [0 .W extension to denote a word operation.. #0x4 . Toggle bit 4 in 0x1001 Before Instruction Data 1000 F234 SR 0000 Example 2 BTG After Instruction Data 1000 E234 SR 0000 ..

. [Ws]. #0x0 After Instruction W2 F235 SR 0000 . Register direct or indirect addressing may be used for Ws.W extension to denote a word operation. #0x0 .B} Ws. For the bit4 operand. Post-increment W0 Before Instruction W0 2300 Data 2300 5606 SR 0000 After Instruction W0 2302 Data 2300 5607 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations. You may use a . W15] bit4 ∈ [0 . [Ws--]. the source register address must be word aligned. Note 1: The extension . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 BTG 1 1 W2. the bit position to test. Advance Information DS70030E-page 5-59 . 2: When this instruction operates in Word mode. 1 for byte). 15] for word operation (Ws)<bit4> → Ws<bit4> None 1010 0010 bbbb 0B00 0ppp ssss Bit ‘bit4’ in register Ws is toggled (complemented). Toggle bit 0 in W2 Before Instruction W2 F234 SR 0000 Example 2 BTG [W0++]. Toggle bit 0 in [W0] ... The ‘B’ bit selects byte or word operation (0 for word.. #bit4 Operands: Ws ∈ [W0 . bit 15 for word operations). Instruction Descriptions BTG Syntax: {label:} Bit Toggle in Ws BTG{. 3: When this instruction operates in Byte mode. The ‘p’ bits select the source Address mode. The ‘s’ bits select the address of the source/destination register. [Ws++]. [--Ws]. The ‘b’ bits select value bit4.. but it is not required.. 7] for byte operation bit4 ∈ [0 . [++Ws]. ‘bit4’ must be between 0 and 7.B in the instruction denotes a byte operation rather than a word operation.Section 5.

Skip if Clear BTSC{. 8190] (even only) for word operation bit4 ∈ [0 . . If the tested bit is ‘1’.B} f.dsPIC30F Programmer’s Reference Manual BTSC Syntax: Operands: {label:} Bit Test f.. skip the GOTO PC Data 1200 SR Before Instruction 00 2000 264F 0000 After Instruction PC 00 2002 Data 1200 264F SR 0000 DS70030E-page 5-60 Advance Information  2003 Microchip Technology Inc. . If the tested bit is ‘0’. .B GOTO . ‘bit4’ must be between 0 and 7. but it is not required.B in the instruction denotes a byte operation rather than a word operation. the bit position to test. In either case. the next instruction is executed as normal. #2 . the contents of the file register are not changed. 2: When this instruction operates in Word mode. bit 15 for word operations). .. . . 3: When this instruction operates in Byte mode. BYPASS . You may use a . Note 1: The extension . . . 0x1201.. #bit4 f ∈ [0 . 7] for byte operation bit4 ∈ [0 . . the file register address must be word aligned. a NOP is executed instead. If bit 2 of 0x1201 is 0.W extension to denote a word operation. .. The ‘b’ bits select value bit4. For the bit4 operand. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 or 3) 002000 HERE: 002002 002004 002006 002008 BYPASS: 00200A BTSC.. .. 8191] for byte operation f ∈ [0 . .. bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations. the next instruction (fetched during the current instruction execution) is discarded and on the next cycle. The ‘f’ bits select the address of the file register. 15] for word operation Test (f)<bit4>.. skip if clear None 1010 1111 bbbf ffff ffff fffb Bit ‘bit4’ in the file register is tested.

. Advance Information DS70030E-page 5-61 . . . BYPASS . . .Section 5. Instruction Descriptions Example 2 002000 HERE: 002002 002004 002006 002008 BYPASS: 00200A BTSC GOTO . . . . . If bit 14 of 0x804 is 0. 0x804. . . #14 . skip the GOTO PC Data 0804 SR Before Instruction 00 2000 2647 0000 After Instruction PC 00 2004 Data 0804 2647 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.

. skip if clear None 1010 0111 bbbb 0000 0ppp ssss Bit ‘bit4’ in Ws is tested. . For the bit4 operand. [--Ws]. . The ‘b’ bits select value bit4. the next instruction is executed as normal. . [Ws++]. Either register direct or indirect addressing may be used for Ws. bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the word. . The ‘p’ bits select the source Address mode. . In either case. skip the GOTO PC W0 SR Before Instruction 00 2000 264F 0000 After Instruction PC 00 2002 W0 264F SR 0000 DS70030E-page 5-62 Advance Information  2003 Microchip Technology Inc.dsPIC30F Programmer’s Reference Manual BTSC Syntax: {label:} Bit Test Ws. The ‘s’ bits select the address of the source register. . [++Ws]. . Words: Cycles: Example 1 1 1 (2 or 3 if the next instruction is skipped) 002000 HERE: 002002 002004 002006 002008 BYPASS: 00200A BTSC GOTO . W0. Note: This instruction operates in Word mode only.. the contents of Ws are not changed. 15] Test (Ws)<bit4>. #bit4 Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 . a NOP is executed instead. . . W15] bit4 ∈ [0 . #0x0 BYPASS . . If the tested bit is ‘0’.. [Ws]. . [Ws--].. If the tested bit is ‘1’. . If bit 0 of W0 is 0. the bit position to test. Skip if Clear BTSC Ws.. the next instruction (fetched during the current instruction execution) is discarded and on the next cycle.

#0xF BYPASS . . . . . . . . Advance Information DS70030E-page 5-63 . Post-increment W6 003400 HERE: 003402 003404 003406 003408 BYPASS: 00340A [W6++]. Instruction Descriptions Example 2 002000 HERE: 002002 002004 002006 002008 BYPASS: 00200A BTSC GOTO . . . . . . . #0xC BYPASS PC W6 Data 1800 SR Before Instruction 00 3400 1800 1000 0000 PC W6 Data 1800 SR After Instruction 00 3402 1802 1000 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. . . . . . skip the GOTO PC W6 SR Example 3 Before Instruction 00 2000 264F 0000 BTSC GOTO . If bit 12 of [W6] is 0. . . . . skip the GOTO . . W6.Section 5. . If bit 15 of W6 is 0. PC W6 SR After Instruction 00 2004 264F 0000 .

If the tested bit is ‘1’. .W extension to denote a word operation. the contents of the file register are not changed. 15] for word operation Test (f)<bit4>. 0x1401. but it is not required. . After Instruction 00 7104 0280 0000 007100 HERE: 007102 007104 007106 BYPASS: 0x890. . #0x9 . For the bit4 operand. BYPASS . . the next instruction (fetched during the current instruction execution) is discarded and on the next cycle. bit 15 for word operation). the file register address must be word aligned. #bit4 f ∈ [0 ..B} f. 8190] (even only) for word operation bit4 ∈ [0 . If bit 1 of 0x1401 is 1. You may use a . the next instruction is executed as normal. The ‘f’ bits select the address of the file register. 8191] for byte operation f ∈ [0 . .B CLR . If bit 9 of 0x890 is 1. don’t clear WREG PC Data 1400 SR Example 2 Before Instruction 00 7100 0280 0000 PC Data 1400 SR BTSS GOTO . the bit position to test.dsPIC30F Programmer’s Reference Manual BTSS Syntax: Operands: {label:} Bit Test f.. . ‘bit4’ must be between 0 and 7. In either case. WREG .. 7] for byte operation bit4 ∈ [0 . .B in the instruction denotes a byte operation rather than a word operation. bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operation. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 (2 or 3 if the next instruction is skipped) 007100 HERE: 007102 007104 BTSS.. The ‘b’ bits select value bit4.. . Skip if Set BTSS{. 3: When this instruction operates in Byte mode. 2: When this instruction operates in Word mode... If the tested bit is ‘0’. Note 1: The extension . skip the GOTO PC Data 0890 SR Before Instruction 00 7100 00FE 0000 PC Data 0890 SR After Instruction 00 7102 00FE 0000 DS70030E-page 5-64 Advance Information  2003 Microchip Technology Inc. skip if set None 1010 1110 bbbf ffff ffff fffb Bit ‘bit4’ in the file register f is tested. #0x1 . a NOP is executed instead..

Words: Cycles: Example 1 1 1 (2 or 3 if the next instruction is skipped) 002000 HERE: 002002 002004 002006 002008 BYPASS: 00200A BTSS GOTO . the bit position to test. [--Ws]. Note: This instruction operates in Word mode only. skip the GOTO PC W0 SR Before Instruction 00 2000 264F 0000 After Instruction PC 00 2004 W0 264F SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Advance Information DS70030E-page 5-65 . 15] Test (Ws)<bit4>. For the bit4 operand. Skip if Set BTSS Ws. bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the word. . . The ‘p’ bits select the source Address mode.. . . #0x0 BYPASS . . Instruction Descriptions BTSS Syntax: {label:} Bit Test Ws. [Ws++]. The ‘b’ bits select the value bit4. . . [Ws--]. [++Ws]. . the contents of Ws are not changed. . [Ws]. None 1010 0110 bbbb 0000 0ppp ssss Bit ‘bit4’ in Ws is tested. skip if set. . a NOP is executed instead. The ‘s’ bits select the address of the source register. If the tested bit is ‘1’. W0. the next instruction (fetched during the current instruction execution) is discarded and on the next cycle. If the tested bit is ‘0’. In either case. . If bit 0 of W0 is 1. .. W15] bit4 ∈ [0 . Either register direct or indirect addressing may be used for Ws. the next instruction is executed as normal. #bit4 Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 .Section 5...

. Post-increment W6 003400 HERE: 003402 003404 003406 003408 BYPASS: 00340A [W6++]. . . W6. . . . . . . . skip the GOTO PC W6 SR Example 3 Before Instruction 00 2000 264F 0000 BTSS GOTO . skip the GOTO . . PC W6 SR After Instruction 00 2002 264F 0000 . If bit 15 of W6 is 1. . . . . . . . 0xC BYPASS PC W6 Data 1800 SR Before Instruction 00 3400 1800 1000 0000 PC W6 Data 1800 SR After Instruction 00 3404 1802 1000 0000 DS70030E-page 5-66 Advance Information  2003 Microchip Technology Inc. . #0xF BYPASS . .dsPIC30F Programmer’s Reference Manual Example 2 002000 HERE: 002002 002004 002006 002008 BYPASS: 00200A BTSS GOTO . . . If bit 12 of [W6] is 1. . . .

15] for word operation (f)<bit4> → Z Z 1010 1011 bbbf ffff ffff fffb Bit ‘bit4’ in file register f is tested and the complement of the tested bit is stored to the Z flag in the Status Register.. The ‘f’ bits select the address of the file register.. 3: When this instruction operates in Byte mode.Section 5. #0x7 Before After Instruction Instruction Data 1302 F7FF Data 1302 F7FF SR 0002 (Z=1) SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. #bit4 f ∈ [0 . Note 1: The extension .. the file register address must be word aligned. For the bit4 operand. bit 3 in 0x1201 Before Instruction Data 1200 F7FF SR 0000 Example 2 BTST After Instruction Data 1200 F7FF SR 0002 (Z=1) . Advance Information DS70030E-page 5-67 . You may use a . The contents of the file register are not changed. 7] for byte operation bit4 ∈ [0 .... The ‘b’ bits select value bit4. 8190] (even only) for word operation bit4 ∈ [0 . Set Z = complement of . bit 7 in 0x1302 0x1302. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BTST.W extension to denote a word operation. bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operation.B 0x1201.. Instruction Descriptions BTST Syntax: Operands: {label:} Bit Test f BTST{. the bit position to be tested. Set Z = complement of . 8191] for byte operation f ∈ [0 .B} f. #0x3 . ‘bit4’ must be between 0 and 7.. bit 15 for word operation). but it is not required.B in the instruction denotes a byte operation rather than a word operation. 2: When this instruction operates in Word mode.

Z Ws. [--Ws].C BTST. In either case. . the complement of the tested bit is stored to the Zero flag in the Status register. the value of the tested bit is stored to the Carry flag in the Status register. Set Z = complement of bit 7 in W0 Before Instruction W0 F234 SR 0000 After Instruction W0 F234 SR 0002 (Z=1) DS70030E-page 5-68 Advance Information  2003 Microchip Technology Inc.C” option of the instruction is specified. the bit position to test. W15] bit4 ∈ [0 .Z” operation is assumed.. [Ws--]. The ‘b’ bits select value bit4. The ‘p’ bits select the source Address mode. [Ws]. #0x3 .. #0x7 . Either register direct or indirect addressing may be used for Ws.C [W0++]. 15] For “. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BTST. For the bit4 operand. #bit4 Operands: Operation: Ws ∈ [W0 . The ‘s’ bits select the address of the source register..C” operation: (Ws)<bit4> → C For “.Z” operation (default): (Ws)<bit4> → Z Z or C 1010 0011 bbbb Z000 0ppp ssss Bit ‘bit4’ in register Ws is tested. [Ws++]. The ‘Z’ bit selects the C or Z flag as destination. the “.dsPIC30F Programmer’s Reference Manual BTST Syntax: {label:} Bit Test in Ws BTST. the contents of Ws are not changed.. bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the word. Post-increment W0 Before After Instruction Instruction W0 1200 W0 1202 Data 1200 FFF7 Data 1200 FFF7 SR 0001 (C=1) SR 0000 Example 2 BTST.Z W0. If the “.Z” option of the instruction is specified. If no extension is provided. Note: This instruction only operates in Word mode. If the “. Set C = bit 3 in [W0] . [++Ws].

Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BTST. The ‘s’ bits select the address of the source register. the value of the tested bit is stored to the Carry flag in the Status register.C BTST.Z Ws. Instruction Descriptions BTST Syntax: {label:} Bit Test in Ws BTST. [Ws]. The ‘w’ bits select the address of the bit select register.C W2. the contents of Ws are not changed... Only the four Least Significant bits of Wb are used to determine the bit number.Z” operation is assumed. [Ws++]. If the “. The ‘p’ bits select the source Address mode. If no extension is provided..Z” operation (default): (Ws)<(Wb)> → Z Z or C 1010 0101 Zwww w000 0ppp ssss The (Wb) bit in register Ws is tested. [Ws--]. Register direct or indirect addressing may be used for Ws. Wb Operands: Operation: Ws ∈ [W0 .Section 5. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the working register. In either case. The ‘Z’ bit selects the C or Z flag as destination. the complement of the tested bit is stored to the Zero flag in the Status register. Advance Information DS70030E-page 5-69 . the “. [++Ws]. W15] For “. W3 . If the “.. Note: This instruction only operates in Word mode.C” option of the instruction is specified. W15] Wb ∈ [W0 . [--Ws]. Set C = bit W3 of W2 Before Instruction W2 F234 W3 2368 SR 0001 (C=1) After Instruction W2 F234 W3 2368 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.Z” option of the instruction is specified.C” operation: (Ws)<(Wb)> → C For “.

W1 . bit W1 in [W0].Z [W0++]. . Set Z = complement of .dsPIC30F Programmer’s Reference Manual Example 2 BTST. Post-increment W0 Before Instruction W0 1200 W1 CCC0 Data 1200 6243 SR 0002 (Z=1) After Instruction W0 1202 W1 CCC0 Data 1200 6243 SR 0000 DS70030E-page 5-70 Advance Information  2003 Microchip Technology Inc. .

W extension to denote a word operation. 8191] for byte operation f ∈ [0 . then set bit 3 of 0x1201 = 1 Before Instruction Data 1200 F7FF SR 0000 Example 2 BTSTS After Instruction Data 1200 FFFF SR 0002 (Z=1) . the bit position to test/set. #0x3 . The tested bit is then set to “1” in the file register. Set Z = complement of bit 15 in 0x808.B in the instruction denotes a byte operation rather than a word operation. 15] for word operation (f)<bit4> → Z 1 → (f)<bit4> Z 1010 1100 bbbf ffff ffff fffb Bit ‘bit4’ in file register f is tested and the complement of the tested bit is stored to the Zero flag in the Status register. .. Set Z = complement of bit 3 in 0x1201. #15 Before After Instruction Instruction RAM300 8050 RAM300 8050 SR 0002 (Z=1) SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. 3: When this instruction operates in Byte mode. Note 1: The extension . The ‘b’ bits select value bit4. #bit4 f ∈ [0 . 7] for byte operation bit4 ∈ [0 . bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations. the file register address must be word aligned. ...B} f.. bit 15 for word operations)..Section 5.. Instruction Descriptions BTSTS Syntax: Operands: {label:} Bit Test/Set f BTSTS{. 2: When this instruction operates in Word mode..B 0x1201. You may use a . Advance Information DS70030E-page 5-71 . For the bit4 operand.. The ‘f’ bits select the address of the file register. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BTSTS. but it is not required. ‘bit4’ must be between 0 and 7. 8190] (even only) for word operation bit4 ∈ [0 . then set bit 15 of 0x808 = 1 0x808.

If the “. #bit4 Operands: Operation: Ws ∈ [W0 .Z” operation (default): (Ws)<bit4> → Z 1 → Ws<bit4> Z or C 1010 0100 bbbb Z000 0ppp ssss Bit ‘bit4’ in register Ws is tested. In both cases. #0x7 Before Instruction W0 F234 SR 0000 After Instruction W0 F2BC SR 0002 (Z=1) DS70030E-page 5-72 Advance Information  2003 Microchip Technology Inc. Note: This instruction only operates in Word mode.. Set bit 3 in [W0] = 1 . the tested bit in Ws is set to “1”. The ‘Z’ bit selects the C or Z flag as destination. If no extension is provided. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 BTSTS.. Post-increment W0 Before Instruction W0 1200 Data 1200 FFF7 SR 0001 (C=1) Example 2 BTSTS. If the “. [--Ws].C” operation: (Ws)<bit4> → C 1 → Ws<bit4> For “..Z” option of the instruction is specified. and set bit 7 in W0 = 1 W0. [++Ws]. W15] bit4 ∈ [0 . the bit position to test/set. 15] For “. Set C = bit 3 in [W0] .C” option of the instruction is specified.Z After Instruction W0 1202 Data 1200 FFFF SR 0000 . the value of the tested bit is stored to the Carry flag in the Status register. The ‘p’ bits select the source Address mode. [Ws]. The ‘s’ bits select the address of the source register. . The ‘b’ bits select the value bit4.dsPIC30F Programmer’s Reference Manual BTSTS Syntax: {label:} Bit Test/Set in Ws BTSTS. Set Z = complement of bit 7 . #0x3 .C [W0++]. [Ws--]. the “. the complement of the tested bit is stored to the Zero flag in the Status register..C BTSTS.Z Ws.Z” operation is assumed. [Ws++]. in W0.

the 24-bit return address (PC+4) is pushed onto the stack. PC W15 Data A268 Data A26A SR _G66 W0. Before the call is made.. INC . 077A28 _G66: 077A2A 077A2C W6.. 8388606]. After the return address is stacked. Call _FIR subroutine .. call routine _G66 .. Note: The linker will resolve the specified expression into the lit23 to be used. Expr is resolved by the linker to a lit23. W2 . routine start 072000 072004 . W1 #0x400. Instruction Descriptions CALL Syntax: Operands: Operation: {label:} Call Subroutine CALL Expr Status Affected: Encoding: 1st word 2nd word Description: Expr may be a label or expression (but not a literal). .. 026844 _FIR: 026846 CALL MOV .Section 5. The ‘n’ bits form the target address.. where lit23 ∈ [0 ... [W7++] PC W15 Data 9004 Data 9006 SR Before Instruction 07 2000 9004 FFFF FFFF 0000 PC W15 Data 9004 Data 9006 SR After Instruction 07 7A28 9008 2004 0007 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.. the 23-bit value ‘lit23’ is loaded into the PC.. Advance Information DS70030E-page 5-73 . MOV .. . W1 After Instruction 02 6844 A26C 6004 0002 0000 . (PC)+4 → PC (PC<15:0>) → (TOS) (W15)+2 → W15 (PC<23:16>) → (TOS) (W15)+2 → W15 lit23 → PC NOP → Instruction Register None 0000 0010 nnnn nnnn nnnn nnn0 0000 0000 0000 0000 0nnn nnnn Direct subroutine call over the entire 4 Mbyte instruction program memory range.. Words: Cycles: Example 1 2 2 026000 026004 . _FIR subroutine start PC W15 Data A268 Data A26A SR Example 2 Before Instruction 02 6000 A268 FFFF FFFF 0000 CALL MOV . _FIR W0.

001600 _BOOT: 001602 . Status Affected: Encoding: Description: Words: Cycles: Example 1 1 2 001002 001004 . 004200 004202 . MOV #0x400.. . .. W2 MOV #0x300.. Wn<0> is ignored. . Wn<15:1> is loaded into PC<15:1> and PC<22:16> is cleared...dsPIC30F Programmer’s Reference Manual CALL Syntax: Operands: Operation: {label:} Call Indirect Subroutine CALL Wn Wn ∈ [W0 .. . W3 After Instruction 00 1600 1600 6F04 1004 0000 0000 . Since PC<0> is always ‘0’. Before the call is made. 005500 _TEST: 005502 . Call BOOT subroutine indirectly . PC W0 W15 Data 6F00 Data 6F02 SR W7 W1. W15] (PC)+2 → PC (PC<15:0>) → TOS (W15)+2 → W15 (PC<23:16>) → TOS (W15)+2 → W15 0 → PC<22:16> (Wn<15:1>) → PC<15:1> NOP → Instruction Register None 0000 0001 0000 0000 0000 ssss Indirect subroutine call over the first 32K instructions of program memory. CALL W0 ... Call TEST subroutine indirectly . using W0 ... INC DEC . W6 . After the return address is stacked.. _TEST starts here . the 24-bit return address (PC+2) is pushed onto the stack. _BOOT starts here PC W0 W15 Data 6F00 Data 6F02 SR Example 2 Before Instruction 00 1002 1600 6F00 FFFF FFFF 0000 CALL . PC W7 W15 Data 6F00 Data 6F02 SR Before Instruction 00 4200 5500 6F00 FFFF FFFF 0000 PC W7 W15 Data 6F00 Data 6F02 SR After Instruction 00 5500 5500 6F04 4202 0000 0000 DS70030E-page 5-74 Advance Information  2003 Microchip Technology Inc.... W2 W1. The ‘s’ bits select the address of the source register. using W7 .

Clear RAM200 (Byte mode) Before Instruction RAM200 8009 SR 0000 Example 2 CLR WREG After Instruction RAM200 8000 SR 0000 . the specified file register f is cleared. The ‘B’ bit selects byte or word operation (0 for word.B} f WREG Operands: Operation: Status Affected: Encoding: Description: f ∈ [0 . 1 for byte). Clear WREG (Word mode) Before Instruction WREG 0600 SR 0000 After Instruction WREG 0000 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. but it is not required. the WREG is cleared. The ‘f’ bits select the address of the file register. The ‘D’ bit selects the destination (0 for WREG. You may use a .B in the instruction denotes a byte operation rather than a word operation..Section 5.B RAM200 . Instruction Descriptions CLR Syntax: {label:} Clear f or WREG CLR{. Note 1: The extension . 8191] 0 → destination designated by D None 1110 1111 0BDf ffff ffff ffff Clear the contents of a file register or the default working register WREG. Words: Cycles: Example 1 1 1 CLR. If WREG is specified.. Otherwise. 2: The WREG is set to working register W0.W extension to denote a word operation. 1 for file register). Advance Information DS70030E-page 5-75 .

Note: The extension . The ‘q’ bits select the destination Address mode. The ‘d’ bits select the address of the destination register. W15] 0 → Wd None 1110 1011 0Bqq qddd d000 0000 Clear the contents of register Wd.B in the instruction denotes a byte operation rather than a word operation. Clear W2 (Byte mode) Before Instruction W2 3333 SR 0000 Example 2 CLR [W0++] After Instruction W2 3300 SR 0000 . Clear [W0] .B W2 .W extension to denote a word operation. The ‘B’ bits selects byte or word operation (0 for word. but it is not required. .. You may use a ..B} Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Status Affected: Encoding: Description: Wd ∈ [W0 . Either register direct or indirect addressing may be used for Wd.dsPIC30F Programmer’s Reference Manual CLR Syntax: {label:} Clear Wd CLR{. Words: Cycles: Example 1 1 1 CLR. 1 for byte). Post-increment W0 Before Instruction W0 2300 Data 2300 5607 SR 0000 After Instruction W0 2302 Data 2300 0000 SR 0000 DS70030E-page 5-76 Advance Information  2003 Microchip Technology Inc.

Operand AWB specifies the optional register direct or indirect store of the convergently rounded contents of the “other” accumulator.14.14.[W11+W12]. W7] AWB ∈ [W13. [W8]+=2.[W9+W12]. 4.[Wy]-=ky.Wyd} {. The ‘y’ bits select the pre-fetch Wyd destination. SB). Wxd ∈ [W4 . W9].. -2. The ‘j’ bits select the Wy pre-fetch operation.Wyd} Operands: Acc ∈ [A. The ‘i’ bits select the Wx pre-fetch operation.[Wx]-=kx.[Wx]+=kx.Wyd} {.4 “MAC Write Back”.Wxd} {. Instruction Descriptions CLR Syntax: {label:} CLR Clear Accumulator.Section 5. Operands Wx. Store ACCB to W13 W4 W8 W13 ACCA ACCB Data 2000 SR Before Instruction F001 2000 C623 00 0067 2345 00 5420 3BDD 1221 0000 W4 W8 W13 ACCA ACCB Data 2000 SR After Instruction 1221 2002 5420 00 0000 0000 00 5420 3BDD 1221 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.Wxd} {..AWB} {. post-inc W8 . SA or OB. W4. The ‘x’ bits select the pre-fetch Wxd destination. Clear ACCA .[Wy]+=ky. Words: Cycles: Example 1 CLR 1 1 A. The ‘A’ bit selects the other accumulator used for write back. SB 1100 0011 A0xx yyii iijj jjaa Operation: Status Affected: Encoding: Description: Clear all 40 bits of the specified accumulator. -2.[Wy]. Advance Information DS70030E-page 5-77 . 2. 4.Wxd} {. Wyd ∈ [W4 . (Wx)+/-kx→Wx ([Wy])→ Wyd. The ‘a’ bits select the accumulator write back destination. -4. as described in Section 4.[Wx].B] Wx ∈ [W8.. Wxd. W7] Wy ∈ [W10. 2.1 “MAC Pre-Fetches”. SA.Wxd} {. Pre-Fetch Operands Acc {. as described in Section 4. kx ∈ [-6.Wyd} {. Load W4 with [W8]. [W13]+=2] 0 → Acc(A or B) ([Wx])→ Wxd. Wy and Wyd specify optional pre-fetch operations which support indirect and register offset addressing. optionally pre-fetch operands in preparation for a MAC type instruction and optionally store the non-specified accumulator results. 6]. W13 .. W11]. ky ∈ [-6. OB. 6]. -4. (Wy)+/-ky→Wy (Acc(B or A)) rounded → AWB OA. This instruction clears the respective overflow and saturate flags (either OA.

W7. . . [W13]+=2 . W6. . Clear ACCB Load W6 with [W8] Load W7 with [W10] Save ACCA to [W13] Post-inc W8.W10.dsPIC30F Programmer’s Reference Manual Example 2 CLR B. [W10]+=2.W13 W6 W7 W8 W10 W13 ACCA ACCB Data 2000 Data 3000 Data 4000 SR Before Instruction F001 C783 2000 3000 4000 00 0067 2345 00 5420 ABDD 1221 FF80 FFC3 0000 W6 W7 W8 W10 W13 ACCA ACCB Data 2000 Data 3000 Data 4000 SR After Instruction 1221 FF80 2002 3002 4002 00 0067 2345 00 0000 0000 1221 FF80 0067 0000 DS70030E-page 5-78 Advance Information  2003 Microchip Technology Inc. . . [W8]+=2.

Instruction Descriptions CLRWDT Syntax: Operands: Operation: {label:} None Clear Watchdog Timer CLRWDT 0 → WDT count register 0 → WDT prescaler A count 0 → WDT prescaler B count None 1111 1110 0110 0000 0000 0000 Clear the contents of the Watchdog Timer count register and the prescaler count registers. 1 1 CLRWDT . The Watchdog Prescaler A and Prescaler B settings.Section 5. set by configuration fuses in the FWDT. Clear Watchdog Timer Status Affected: Encoding: Description: Words: Cycles: Example 1 Before Instruction SR 0000 After Instruction SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. are not changed. Advance Information DS70030E-page 5-79 .

the result is stored in the file register. If WREG is specified. Z 1110 1110 1BDf ffff ffff ffff Compute the 1’s complement of the contents of the file register and place the result in the destination register. The ‘D’ bit selects the destination (0 for WREG. 8191] (f) → destination designated by D N. COM RAM400 and store to WREG .B in the instruction denotes a byte operation rather than a word operation. 2: The WREG is set to working register W0.dsPIC30F Programmer’s Reference Manual COM Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Complement f COM{. You may use a .. COM RAM200 (Byte mode) Before Instruction RAM200 80FF SR 0000 Example 2 COM After Instruction RAM200 8000 SR 0002 (Z) . 1 for byte).B} f {. (Word mode) RAM400.b RAM200 . the result is stored in WREG. Note 1: The extension . The optional WREG operand determines the destination register. 1 for file register). The ‘f’ bits select the address of the file register. If WREG is not specified. The ‘B’ bit selects byte or word operation (0 for word..W extension to denote a word operation. WREG Before Instruction WREG 1211 RAM400 0823 SR 0000 After Instruction WREG F7DC RAM400 0823 SR 0008 (N=1) DS70030E-page 5-80 Advance Information  2003 Microchip Technology Inc. .WREG} f ∈ [0 . but it is not required. Words: Cycles: Example 1 1 1 COM.

B 1 1 [W0++]. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 . Post-increment W1 Before Instruction W0 D004 W1 1000 Data 1000 ABA9 SR 0000 After Instruction W0 D004 W1 1002 Data 1000 2FFB SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. COM W0 and store to [W1] (Word mode) .. Z 1110 1010 1Bqq qddd dppp ssss Compute the 1’s complement of the contents of the source register Ws and place the result in the destination register Wd.B} Ws. [--Ws]. but it is not required. COM [W0] and store to [W1] (Byte mode) .W extension to denote a word operation. The ‘p’ bits select the source Address mode. Post-increment W0. W1 Before Instruction W0 2301 W1 2400 Data 2300 5607 Data 2400 ABCD SR 0000 Example 2 COM W0. W15] Wd ∈ [W0 . [Ws++]. W15] (Ws) → Wd N. [W1++] After Instruction W0 2302 W1 2401 Data 2300 5607 Data 2400 ABA9 SR 0008 (N=1) . Advance Information DS70030E-page 5-81 . [++Ws]. Either register direct or indirect addressing may be used for both Ws and Wd. The ‘s’ bits select the address of the source register. [Ws--]. The ‘B’ bit selects byte or word operation (0 for word.. 1 for byte). [Ws].. The ‘q’ bits select the destination Address mode.Section 5.B in the instruction denotes a byte operation rather than a word operation. [W1++] . The ‘d’ bits select the address of the destination register. You may use a . Words: Cycles: Example 1 COM.. Note: The extension . Instruction Descriptions COM Syntax: {label:} Complement Ws COM{.

C 1110 0011 0B0f ffff ffff ffff Compute (f) – (WREG) and update the Status register. The ‘B’ bit selects byte or word operation (0 for word. You may use a . Z. Words: Cycles: Example 1 1 1 CP.8191] (f) – (WREG) DC.B} f f ∈ [0 . This instruction is equivalent to the SUBWF instruction. . but it is not required..dsPIC30F Programmer’s Reference Manual CP Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Compare f with WREG. Compare RAM400 with WREG (Byte mode) Before Instruction WREG 8823 RAM400 0823 SR 0000 Example 2 CP 0x1200 After Instruction WREG 8823 RAM400 0823 SR 0002 (Z=1) .B RAM400 .B in the instruction denotes a byte operation rather than a word operation. Note 1: The extension . 1 for byte). The ‘f’ bits select the address of the file register. N. OV. Set Status Flags CP{..W extension to denote a word operation. 2: The WREG is set to working register W0. but the result of the subtraction is not stored. Compare (0x1200) with WREG (Word mode) Before Instruction WREG 2377 Data 1200 2277 SR 0000 After Instruction WREG 2377 Data 1200 2277 SR 0008 (N=1) DS70030E-page 5-82 Advance Information  2003 Microchip Technology Inc.

#0x12 After Instruction W4 7711 SR 0008 (N=1) .B W4. 1 for byte). Compare W4 with 0x12 (Byte mode) Before Instruction W4 7711 SR 0000 Example 2 CP W4. but it is not required. #lit5 Wb ∈ [W0 .. Advance Information DS70030E-page 5-83 .B in the instruction denotes a byte operation rather than a word operation. You may use a . Note: The extension . This instruction is equivalent to the SUB instruction. 31] (Wb) – lit5 DC. Compare W4 with 0x12 (Word mode) Before Instruction W4 7713 SR 0000 After Instruction W4 7713 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Set Status Flags CP{.. The ‘w’ bits select the address of the Wb base register.Section 5. #0x12 . W15] lit5 ∈ [0 .. but the result of the subtraction is not stored. Words: Cycles: Example 1 1 1 CP. Instruction Descriptions CP Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Compare Wb with lit5. OV. Register direct addressing must be used for Wb. Z. N.. The ‘k’ bits provide the literal operand.B} Wb. C 1110 0001 0www wB00 011k kkkk Compute (Wb) – lit5. a five-bit integer number. and update the Status register.W extension to denote a word operation. The ‘B’ bit selects byte or word operation (0 for word.

but the result of the subtraction is not stored. Ws [Ws] [Ws++] [Ws--] [++Ws] [--Ws] Operands: Operation: Status Affected: Encoding: Description: Wb ∈ [W0 . The ‘w’ bits select the address of the Wb source register.dsPIC30F Programmer’s Reference Manual CP Syntax: {label:} Compare Wb with Ws. C 1110 0001 0www wB00 0ppp ssss Compute (Wb) – (Ws). ..B} Wb. but it is not required. This instruction is equivalent to the SUB instruction. [W1++] . OV.. N. Z. Note: The extension . Words: Cycles: Example 1 1 1 CP. Register direct addressing must be used for Wb. Register direct or indirect addressing may be used for Ws. You may use a . and update the Status register.B W0.. The ‘B’ bit selects byte or word operation (0 for word. Set Status Flags CP{. W15] (Wb) – (Ws) DC. The ‘p’ bits select the source Address mode. Compare [W1] with W0 (Byte mode) . W6 After Instruction W0 ABA9 W1 2001 Data 2000 D004 SR 0008 (N=1) . Post-increment W1 Before Instruction W0 ABA9 W1 2000 Data 2000 D004 SR 0000 Example 2 CP W5.W extension to denote a word operation.. Compare W6 with W5 (Word mode) Before Instruction W5 2334 W6 8001 SR 0000 After Instruction W5 2334 W6 8001 SR 000C (N. The ‘s’ bits select the address of the Ws source register.B in the instruction denotes a byte operation rather than a word operation. W15] Ws ∈ [W0 . 1 for byte).OV=1) DS70030E-page 5-84 Advance Information  2003 Microchip Technology Inc.

N.B} f f ∈ [0 . Instruction Descriptions CP0 Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Compare f with 0x0. The result of the subtraction is not stored. C 1110 0010 0B0f ffff ffff ffff Compute (f) – 0x0 and update the Status register. Words: Cycles: Example 1 1 1 CP0.W extension to denote a word operation. Set Status Flags CP0{. The ‘B’ bit selects byte or word operation (0 for word.Section 5. Advance Information DS70030E-page 5-85 .B in the instruction denotes a byte operation rather than a word operation.. OV.B RAM100 . You may use a . Compare (0x1FFE) with 0x0 (Word mode) Before Instruction Data 1FFE 0001 SR 0000 After Instruction Data 1FFE 0001 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. 1 for byte). Compare RAM100 with 0x0 (Byte mode) Before Instruction RAM100 44C3 SR 0000 Example 2 CP0 0x1FFE After Instruction RAM100 44C3 SR 0008 (N=1) . Z. The ‘f’ bits select the address of the file register. 8191] (f) – 0x0 DC. but it is not required.. Note: The extension .

The result of the subtraction is not stored. Compare [--W5] with 0 (Word mode) Before Instruction W5 2400 Data 23FE 9000 SR 0000 After Instruction W5 23FE Data 23FE 9000 SR 0008 (N=1) DS70030E-page 5-86 Advance Information  2003 Microchip Technology Inc. N.B [W4--] . OV. W15] (Ws) – 0x0000 DC. but it is not required. The ‘s’ bits select the address of the Ws source register. The ‘p’ bits select the source Address mode. Register direct or indirect addressing may be used for Ws. Words: Cycles: Example 1 1 1 CP0. Compare [W4] with 0 (Byte mode) . 1 for byte).B in the instruction denotes a byte operation rather than a word operation. . Note: The extension . You may use a ... Post-decrement W4 Before Instruction W4 1001 Data 1000 0034 SR 0000 Example 2 CP0 [--W5] After Instruction W4 1000 Data 1000 0034 SR 0002 (Z=1) .B} Ws [Ws] [Ws++] [Ws--] [++Ws] [--Ws] Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 . Z. Set Status Flags CP0{. C 1110 0000 0000 0B00 0ppp ssss Compute (Ws) – 0x0000 and update the Status register.W extension to denote a word operation. The ‘B’ bit selects byte or word operation (0 for word.dsPIC30F Programmer’s Reference Manual CP0 Syntax: {label:} Compare Ws with 0x0.

C 1110 0011 1B0f ffff ffff ffff Compute (f) – (WREG) – (C).Section 5. Z. These instructions can only clear Z. SUBB and SUBBR.. This instruction is equivalent to the SUBB instruction. but the result of the subtraction is not stored. Note 1: The extension .. Words: Cycles: Example 1 1 1 CPB. The ‘B’ bit selects byte or word operation (0 for word. The ‘f’ bits select the address of the file register. Compare RAM400 with WREG using C (Byte mode) Before Instruction WREG 8823 RAM400 0823 SR 0000 Example 2 CPB 0x1200 After Instruction WREG 8823 RAM400 0823 SR 0008 (N=1) .B} f f ∈ [0 . Set Status Flags {label:} CPB{.B RAM400 .8191] (f) – (WREG) – (C) DC. but it is not required. and update the Status register.W extension to denote a word operation. OV. Advance Information DS70030E-page 5-87 . Instruction Descriptions CPB Syntax: Operands: Operation: Status Affected: Encoding: Description: Compare f with WREG using Borrow. 3: The Z flag is “sticky” for ADDC. You may use a . CPB.B in the instruction denotes a byte operation rather than a word operation. 1 for byte). Compare (0x1200) with WREG using C (Word mode) Before After Instruction Instruction WREG 2377 WREG 2377 Data 1200 2377 Data 1200 2377 SR 0001 (C=1) SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. 2: The WREG is set to working register W0. N.

B in the instruction denotes a byte operation rather than a word operation. Note 1: The extension . OV.. Compare W4 with 0x12 using C (Byte mode) Before Instruction W4 7711 SR 0000 Example 3 CPB W12.B} Wb. The ‘w’ bits select the address of the Wb source register. These instructions can only clear Z. 31] (Wb) – lit5 – (C) DC. #lit5 Wb ∈ [W0 ..dsPIC30F Programmer’s Reference Manual CPB Syntax: Operands: Operation: Status Affected: Encoding: Description: Compare Wb with lit5 using Borrow. . CPB. 1 for byte). Compare W4 with 0x12 using C (Byte mode) Before Instruction W4 7711 SR 0001 (C=1) Example 2 CPB. Compare W12 with 0x1F using C (Word mode) Before Instruction W12 0020 SR 0002 (Z=1) Example 4 CPB W12. but it is not required. C 1110 0001 1www wB00 011k kkkk Compute (Wb) – lit5 – (C). #0x12 . W15] lit5 ∈ [0 . You may use a . but the result of the subtraction is not stored. The ‘k’ bits provide the literal operand. #0x1F After Instruction W12 0020 SR 0003 (Z.. Words: Cycles: Example 1 1 1 CPB. Z.W extension to denote a word operation.B W4. 2: The Z flag is “sticky” for ADDC. The ‘B’ bit selects byte or word operation (0 for word. #0x1F After Instruction W4 7711 SR 0008 (N=1) . #0x12 After Instruction W4 7711 SR 0008 (N=1) . SUBB and SUBBR. C=1) .. a five bit integer number. This instruction is equivalent to the SUBB instruction. N. and update the Status register. Set Status Flags {label:} CPB{. Compare W12 with 0x1F using C (Word mode) Before Instruction W12 0020 SR 0003 (Z. C=1) After Instruction W12 0020 SR 0001 (C=1) DS70030E-page 5-88 Advance Information  2003 Microchip Technology Inc.B W4. Register direct addressing must be used for Wb.

Compare [W1] with W0 using C (Byte mode) .B in the instruction denotes a byte operation rather than a word operation. The ‘w’ bits select the address of the Wb source register. N. Post-increment W1 Before After Instruction Instruction W0 ABA9 W0 ABA9 W1 1000 W1 1001 Data 1000 D0A9 Data 1000 D0A9 SR 0002 (Z=1) SR 0008 (N=1) Example 2 CPB. Words: Cycles: Example 1 1 1 CPB. Set Status Flags CPB{.. but the result of the subtraction is not stored. Z. You may use a . Advance Information DS70030E-page 5-89 . and update the Status register. 1 for byte).B} Wb. Register direct or indirect addressing may be used for Ws. [W1++] . Ws [Ws] [Ws++] [Ws--] [++Ws] [--Ws] Operands: Operation: Status Affected: Encoding: Description: Wb ∈ [W0 .B W0. These instructions can only clear Z. Post-increment W1 Before After Instruction Instruction W0 ABA9 W0 ABA9 W1 1000 W1 1001 Data 1000 D0A9 Data 1000 D0A9 SR 0001 (C=1) SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.Section 5. The ‘s’ bits select the address of the Ws source register. This instruction is equivalent to the SUBB instruction.B W0. W15] Ws ∈ [W0 . Register direct addressing must be used for Wb.. 2: The Z flag is “sticky” for ADDC.. The ‘B’ bit selects byte or word operation (0 for word. Instruction Descriptions CPB Syntax: {label:} Compare Ws with Wb using Borrow.W extension to denote a word operation. OV. W15] (Wb) – (Ws) – (C) DC. Note 1: The extension . but it is not required. C 1110 0001 1www wB00 0ppp ssss Compute (Wb) – (Ws) – (C). Compare [W1] with W0 using C (Byte mode) . SUBB and SUBBR.. The ‘p’ bits select the source Address mode. [W1++] . CPB.

Compare W5 with W4 using C (Word mode) Before Instruction W4 4000 W5 3000 SR 0001 (C=1) After Instruction W4 4000 W5 3000 SR 0001 (C=1) DS70030E-page 5-90 Advance Information  2003 Microchip Technology Inc. .dsPIC30F Programmer’s Reference Manual Example 3 CPB W4. W5 .

..B in the instruction denotes a byte operation rather than a word operation. W1 002002 GOTO BYPASS 002004 . If W4 = W8 (Word mode). 002006 . the next instruction is executed as normal. but it is not required.. The ‘s’ bits select the address of the Ws source register. skip the GOTO PC W0 W1 SR Example 2 Before Instruction 00 2000 1001 1000 0000 CPSEQ CALL . 00200A .Section 5. Skip if Equal (Wb = Wn) CPSEQ{.W extension to denote a word operation. . . .. If W0 = W1 (Byte mode).B} Wb. but do not store the result. . You may use a . The ‘B’ bit selects byte or word operation (0 for word...B W0. Note: The extension . .. . Instruction Descriptions CPSEQ Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Compare Wb with Wn. Wn Wb ∈ [W0 . . . . the next instruction (fetched during the current instruction execution) is discarded and on the next cycle. a NOP is executed instead. . 002008 BYPASS:. . W15] Wn ∈ [W0 . W8 _FIR PC W0 W1 SR After Instruction 00 2002 1001 1000 0000 018000 HERE: 018002 018006 018008 . W4. .. W15] (Wb) – (Wn) Skip if (Wb) = (Wn) None 1110 0111 1www wB00 0000 ssss Compare the contents of Wb with the contents of Wn by performing the subtraction (Wb) – (Wn). If (Wb) = (Wn). 1 for byte). The ‘w’ bits select the address of the Wb source register. Words: Cycles: Example 1 1 1 (2 or 3 if skip taken) 002000 HERE: CPSEQ. Advance Information DS70030E-page 5-91 . If (Wb) ≠ (Wn). skip the subroutine call PC W4 W8 SR Before Instruction 01 8000 3344 3344 0002 (Z=1) PC W4 W8 SR After Instruction 01 8006 3344 3344 0002 (Z=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.

You may use a . The ‘w’ bits select the address of the Wb source register. . W1 . the next instruction is executed as normal. the next instruction (fetched during the current instruction execution) is discarded and on the next cycle.dsPIC30F Programmer’s Reference Manual CPSGT Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Signed Compare Wb with Wn. If (Wb) > (Wn). If W0 > W1 (Byte mode). . C=1) 018000 HERE: 018002 018006 018008 W4. but it is not required. . but do not store the result. W0. . C=1) CPSGT CALL .. . PC W0 W1 SR After Instruction 00 2006 00FF 26FE 0009 (N. W15] Wn ∈ [W0 .. skip the subroutine call PC W4 W5 SR Before Instruction 01 8000 2600 2600 0004 (OV=1) PC W4 W5 SR After Instruction 01 8002 2600 2600 0004 (OV=1) DS70030E-page 5-92 Advance Information  2003 Microchip Technology Inc. . If W4 > W5 (Word mode). ... . _FIR . Words: Cycles: Example 1 1 1 (2 or 3 if skip taken) 002000 HERE: 002002 002006 002008 00200A BYPASS 00200C CPSGT. The ‘s’ bits select the address of the Ws source register. . skip the GOTO PC W0 W1 SR Example 2 Before Instruction 00 2000 00FF 26FE 0009 (N.B} Wb.B in the instruction denotes a byte operation rather than a word operation. W5 .. Note: The extension . Wn Wb ∈ [W0 .. a NOP is executed instead.B GOTO . Otherwise. 1 for byte). .W extension to denote a word operation. .. W15] (Wb) – (Wn) Skip if (Wb) > (Wn) None 1110 0110 0www wB00 0000 ssss Compare the contents of Wb with the contents of Wn by performing the subtraction (Wb) – (Wn).. . Skip if Greater Than (Wb > Wn) CPSGT{. BYPASS . . The ‘B’ bit selects byte or word operation (0 for word.

W9 . Wn Wb ∈ [W0 . If (Wb) < (Wn). . 1 for byte). If W8 < W9 (Byte mode). . . but do not store the result. The ‘B’ bit selects byte or word operation (0 for word. . BYPASS .Section 5. . the next instruction (fetched during the current instruction execution) is discarded and on the next cycle. The ‘s’ bits select the address of the Ws source register. Note: The extension .B in the instruction denotes a byte operation rather than a word operation. Otherwise.. W6 . W15] (Wb) – (Wn) Skip if (Wb) < (Wn) None 1110 0110 1www wB00 0000 ssss Compare the contents of Wb with the contents of Wn by performing the subtraction (Wb) – (Wn). The ‘w’ bits select the address of the Wb source register. . . but it is not required. the next instruction is executed as normal. . skip the subroutine call PC W3 W6 SR Before Instruction 01 8000 2600 3000 0000 PC W3 W6 SR After Instruction 01 8006 2600 3000 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. . Words: Cycles: Example 1 1 1 (2 or 3 if skip taken) 002000 HERE: 002002 002006 002008 00200A BYPASS: 00200C CPSLT. If W3 < W6 (Word mode). PC W8 W9 SR After Instruction 00 2002 00FF 26FE 0008 (N=1) 018000 HERE: 018002 018006 018008 W3.. a NOP is executed instead. . skip the GOTO PC W8 W9 SR Example 2 Before Instruction 00 2000 00FF 26FE 0008 (N=1) CPSLT CALL . . W8.W extension to denote a word operation. You may use a . .B GOTO . Advance Information DS70030E-page 5-93 . . . Instruction Descriptions CPSLT Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Signed Compare Wb with Wn. W15] Wn ∈ [W0 . _FIR . .. Skip if Less Than (Wb < Wn) CPSLT{. .B} Wb..

skip the GOTO PC W2 W3 SR Example 2 Before Instruction 00 2000 00FF 26FE 0001 (C=1) CPSNE CALL .. W15] Wn ∈ [W0 . W15] (Wb) – (Wn) Skip if (Wb) ≠ (Wn) None 1110 0111 0www wB00 0000 ssss Compare the contents of Wb with the contents of Wn by performing the subtraction (Wb) – (Wn)... . If W0 != W8 (Word mode). .. .. BYPASS .. . a NOP is executed instead. W8 _FIR PC W2 W3 SR After Instruction 00 2006 00FF 26FE 0001 (C=1) 018000 HERE: 018002 018006 018008 .B in the instruction denotes a byte operation rather than a word operation. The ‘B’ bit selects byte or word operation (0 for word. . Note: The extension . . . . Otherwise. The ‘w’ bits select the address of the Wb source register. . . but do not store the result. the next instruction (fetched during the current instruction execution) is discarded and on the next cycle.B} Wb. W2. If W2 != W3 (Byte mode). . . but it is not required. Wn Wb ∈ [W0 . Skip if Not Equal (Wb ≠ Wn) CPSNE{. W3 . If (Wb) ≠ (Wn). You may use a ..B GOTO . skip the subroutine call PC W0 W8 SR Before Instruction 01 8000 3000 3000 0000 PC W0 W8 SR After Instruction 01 8002 3000 3000 0000 DS70030E-page 5-94 Advance Information  2003 Microchip Technology Inc.W extension to denote a word operation. 1 for byte). Words: Cycles: Example 1 1 1 (2 or 3 if skip taken) 002000 HERE: 002002 002006 002008 00200A BYPASS: 00200C CPSNE.dsPIC30F Programmer’s Reference Manual CPSNE Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Signed Compare Wb with Wn. .. W0. The ‘s’ bits select the address of the Ws source register. . the next instruction is executed as normal.

. Decimal adjust W0 Before Instruction W0 771A SR 0002 (DC=1) Example 2 DAW. Words: Cycles: Example 1 1 1 DAW.B extension must be included with the opcode. 2: This instruction operates in Byte mode only and the .B Wn Wn ∈ [W0 . W15] If (Wn<3:0> > 9) or (DC = 1) (Wn<3:0>) + 6 → Wn<3:0> Else (Wn<3:0>) → Wn<3:0> If (Wn<7:4> > 9) or (C = 1) (Wn<7:4>) + 6 → Wn<7:4> Else (Wn<7:4>) → Wn<7:4> Status Affected: Encoding: Description: C 1111 1101 0100 0000 0000 ssss Adjust the Least Significant Byte in Wn to produce a binary coded decimal (BCD) result.B Syntax: Operands: Operation: {label:} Decimal Adjust Wn DAW. and the Carry flag is used to indicate any decimal rollover.B W3 After Instruction W0 7720 SR 0002 (DC=1) . The Most Significant Byte of Wn is not changed. Advance Information DS70030E-page 5-95 . Decimal adjust W3 Before Instruction W3 77AA SR 0000 After Instruction W3 7710 SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.Section 5. The ‘s’ bits select the address of the source/destination register.. Register direct addressing must be used for Wn. Note 1: This instruction is used to correct the data format after two packed BCD bytes have been added.B W0 . Instruction Descriptions DAW.

C=1) . the result is stored in the file register. Decrement (0x200) (Byte mode) Before Instruction Data 200 80FF SR 0000 Example 2 DEC After Instruction Data 200 80FE SR 0009 (N. C 1110 1101 0BDf ffff ffff ffff Subtract one from the contents of the file register and place the result in the destination register. You may use a . The ‘D’ bit selects the destination (0 for WREG. but it is not required.W extension to denote a word operation. 8191] (f) – 1 → destination designated by D DC. N.WREG} f ∈ [0 . The ‘B’ bit selects byte or word operation (0 for word. Z. If WREG is not specified. If WREG is specified. Note 1: The extension . The optional WREG operand determines the destination register..B in the instruction denotes a byte operation rather than a word operation.B} f {.dsPIC30F Programmer’s Reference Manual DEC Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Decrement f DEC{. Decrement RAM400 and store to WREG .. OV. (Word mode) RAM400. . 2: The WREG is set to working register W0. Words: Cycles: Example 1 1 1 DEC. 1 for byte). the result is stored in WREG.B 0x200 . The ‘f’ bits select the address of the file register. 1 for file register). WREG Before Instruction WREG 1211 RAM400 0823 SR 0000 After Instruction WREG 0822 RAM400 0823 SR 0000 DS70030E-page 5-96 Advance Information  2003 Microchip Technology Inc.

[W8++] . W15] Wd ∈ [W0 . The ‘s’ bits select the address of the source register. Post-increment W6 Before Instruction W5 D004 W6 2000 Data 2000 ABA9 SR 0000 After Instruction W5 D004 W6 2002 Data 2000 D003 SR 0009 (N. N. W8 Before Instruction W7 2301 W8 2400 Data 2300 5607 Data 2400 ABCD SR 0000 Example 2 DEC W5. [Ws--]. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 . [Ws++]. Advance Information DS70030E-page 5-97 .. C 1110 1001 0Bqq qddd dppp ssss Subtract one from the contents of the source register Ws and place the result in the destination register Wd... Instruction Descriptions DEC Syntax: {label:} Decrement Ws DEC{.W extension to denote a word operation. [--Ws]. The ‘q’ bits select the destination Address mode. but it is not required. Z. Words: Cycles: Example 1 1 1 DEC.B in the instruction denotes a byte operation rather than a word operation. 1 for byte).B} Ws. Post-increment W7. The ‘B’ bit selects byte or word operation (0 for word. Decrement W5 and store to [W6] (Word mode) . DEC [W7] and store to [W8] (Byte mode) . OV.. Note: The extension . [++Ws]. The ‘d’ bits select the address of the destination register. You may use a .B [W7++]. Either register direct or indirect addressing may be used by Ws and Wd. C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. [Ws]. [W6++] After Instruction W7 2302 W8 2401 Data 2300 5607 Data 2400 AB55 SR 0000 . The ‘p’ bits select the source Address mode. W15] (Ws) – 1 → Wd DC.Section 5.

dsPIC30F Programmer’s Reference Manual DEC2 Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Decrement f by 2 DEC2{..B in the instruction denotes a byte operation rather than a word operation. 8191] (f) – 2 → destination designated by D DC. If WREG is specified. . 1 for file register). Words: Cycles: Example 1 1 1 DEC2. Note: The extension . Decrement RAM400 by 2 and . If WREG is not specified. but it is not required. C 1110 1101 1BDf ffff ffff ffff Subtract two from the contents of the file register and place the result in the destination register. WREG Before Instruction WREG 1211 RAM400 0823 SR 0000 After Instruction WREG 0821 RAM400 0823 SR 0000 DS70030E-page 5-98 Advance Information  2003 Microchip Technology Inc. The ‘D’ bit selects the destination (0 for WREG. 1 for byte). OV.B} f {.W extension to denote a word operation.. Z. The ‘f’ bits select the address of the file register. the result is stored in the file register.B 0x200 . the result is stored in WREG. The ‘B’ bit selects byte or word operation (0 for word. N. The optional WREG operand determines the destination register. C=1) . You may use a .WREG} f ∈ [0 . Decrement (0x200) by 2 (Byte mode) Before Instruction Data 200 80FF SR 0000 Example 2 DEC2 After Instruction Data 200 80FD SR 0009 (N. store to WREG (Word mode) RAM400.

W extension to denote a word operation. Note: The extension . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 . The ‘B’ bit selects byte or word operation (0 for word. DEC [W7] by 2. Post-decrement W7. Either register direct or indirect addressing may be used by Ws and Wd. C 1110 1001 1Bqq qddd dppp ssss Subtract two from the contents of the source register Ws and place the result in the destination register Wd. [Ws++]. Post-increment W6 Before Instruction W5 D004 W6 1000 Data 1000 ABA9 SR 0000 After Instruction W5 D004 W6 1002 Data 1000 D002 SR 0009 (N. [W8--]. [Ws]. [--Ws]. [W6++] . W8 Before Instruction W7 2301 W8 2400 Data 2300 0107 Data 2400 ABCD SR 0000 Example 2 DEC2 After Instruction W7 2300 W8 23FF Data 2300 0107 Data 2400 ABFF SR 0008 (N=1) W5..B} Ws.B in the instruction denotes a byte operation rather than a word operation. Z. The ‘s’ bits select the address of the source register. W15] Wd ∈ [W0 . C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. 1 for byte). The ‘p’ bits select the source Address mode. [Ws--]. DEC W5 by 2. but it is not required... store to [W6] (Word mode) . The ‘q’ bits select the destination Address mode. store to [W8] (Byte mode) . Words: Cycles: Example 1 1 1 DEC2.Section 5. N. Instruction Descriptions DEC2 Syntax: {label:} Decrement Ws by 2 DEC2{. [++Ws]. The ‘d’ bits select the address of the destination register. You may use a . W15] (Ws) – 2 → Wd DC. Advance Information DS70030E-page 5-99 . OV..B [W7--].

The lit14 value is written to the DISICNT register. Note: This instruction does not prevent priority 7 interrupts and traps from running.. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 002000 HERE: 002002 002004 DISI . This instruction can be used before executing time critical code. and the DISI flag (INTCON2<14>) is set to ‘1’. #100 . to limit the effects of interrupts. . See the dsPIC30F Data Sheet for details.. . now execute time critical code PC DISICNT INTCON2 SR Before Instruction 00 2000 0000 0000 0000 PC DISICNT INTCON2 SR After Instruction 00 2002 0100 4000 (DISI=1) 0000 DS70030E-page 5-100 Advance Information  2003 Microchip Technology Inc. . Disable interrupts for 101 cycles . 16383] lit14 → DISICNT 1 → DISI Disable interrupts for (lit14+1) cycles None 1111 1100 00kk kkkk kkkk kkkk Disable interrupts of priority 0 through priority 6 for (lit14+1) instruction cycles after the instruction executes.dsPIC30F Programmer’s Reference Manual DISI Syntax: Operands: Operation: {label:} Disable Interrupts Temporarily DISI #lit14 lit14 ∈ [0 .

D in the instruction denotes a double-word (32-bit) dividend rather than a word dividend. only one type of overflow may occur (0x8000 / 0xFFFF = +32768 or 0x00008000). W4 . These bits are clear for the word operation. 1 for 32-bit). Wn Wm..S{W} DIV. The OV flag will be set if the divide operation resulted in an overflow and cleared otherwise. Instruction Descriptions DIV. The ‘v’ bits select the Least Significant Word of the dividend. In the default word operation. In the double operation. Wm+1:Wm is first copied to W1:W0. W14] for double operation Wn ∈ [W2 .. but it is not required. 2: Unexpected results will occur if the quotient can not be represented in 16 bits. Note 1: The extension .SD). and the 16-bit remainder is stored in W1. W15] For word operation (default): Wm → W0 If (Wm<15> = 1): 0xFFFF → W1 Else: 0x0 → W1 W1:W0 / Wn → W0 Remainder → W1 For double operation (DIV. Wm is first copied to W0 and sign-extended through W1 to perform the operation. The ‘t’ bits select the Most Significant Word of the dividend for the double operation. The C flag is used to implement the divide algorithm and its final value should not be used. 5 Instruction Descriptions  2003 Microchip Technology Inc.SD Wm. W2. The Z flag will be set if the remainder is 0 and cleared otherwise. The ‘s’ bits select the divisor register. W15] for word operation Wm ∈ [W0.SD): Wm+1:Wm → W1:W0 W1:W0 / Wn → W0 Remainder → W1 Operation: Status Affected: Encoding: Description: N.. OV.Section 5. the OV status bit will be set and the quotient and remainder should not be used.S Syntax: {label:} Signed Integer Divide DIV.W extension to denote a word operation. 3: Dividing by zero will initiate an arithmetic error trap during the first cycle of execution.. signed integer divide. For the word operation (DIV. The ‘W’ bit selects the dividend size (0 for 16-bit.S).. Wn Operands: Wm ∈ [W0 . When this occurs for the double operation (DIV. which allows the OV status bit to interpret the result. Z. where the dividend is stored in Wm (for a 16-bit by 16-bit divide) or Wm+1:Wm (for a 32-bit by 16-bit divide) and the divisor is stored in Wn. The 16-bit quotient of the divide operation is stored in W0.. C 1101 1000 0ttt tvvv vW00 ssss Iterative. The N flag will be set if the remainder is negative and cleared otherwise. 4: This instruction is interruptible on each instruction cycle boundary. Advance Information DS70030E-page 5-101 . You may use a . This instruction must be executed 18 times using the REPEAT instruction (with an iteration count of 17) to generate the correct quotient and remainder.

W4 .SD 18 times . remainder to W1 Before Instruction W0 2500 W1 FF42 W12 2200 SR 0000 After Instruction W0 FA6B W1 EF00 W12 2200 SR 0008 (N=1) DS70030E-page 5-102 Advance Information  2003 Microchip Technology Inc. Divide W3 by W4 .S 18 times . Execute DIV.dsPIC30F Programmer’s Reference Manual DIV. Execute DIV.SD #17 W0. remainder to W1 Before Instruction W0 5555 W1 1234 W3 3000 W4 0027 SR 0000 Example 2 REPEAT DIV. Store quotient to W0. . Store quotient to W0. Divide W1:W0 by W12 .S Words: Cycles: Example 1 1 Signed Integer Divide 18 (plus 1 for REPEAT execution) REPEAT #17 DIV. W12 After Instruction W0 013B W1 0003 W3 3000 W4 0027 SR 0000 .S W3.

The Z flag will be set if the remainder is 0 and cleared otherwise. When an overflow occurs. and the 16-bit remainder is stored in W1. In the word operation. where the dividend is stored in Wm (for a 16-bit by 16-bit divide).UD Wm. the OV status bit will be set and the quotient and remainder should not be used. Wm is first copied to W0 and W1 is cleared to perform the divide.. 1 for 32-bit).D in the instruction denotes a double-word (32-bit) dividend rather than a word dividend. W15] for word operation Wm ∈ [W0. Instruction Descriptions DIV. Wn Operands: Wm ∈ [W0 .U Syntax: {label:} Unsigned Integer Divide DIV.. 2: Unexpected results will occur if the quotient can not be represented in 16 bits.. W14] for double operation Wn ∈ [W2 . These bits are clear for the word operation. The OV flag will be set if the divide operation resulted in an overflow and cleared otherwise.. unsigned integer divide.Section 5. C 1101 1000 1ttt tvvv vW00 ssss Iterative. The ‘v’ bits select the Least Significant Word of the dividend. The 16-bit quotient of the divide operation is stored in W0.UD). 4: This instruction is interruptible on each instruction cycle boundary.. but it is not required. The ‘s’ bits select the divisor register. You may use a . The ‘t’ bits select the Most Significant Word of the dividend for the double operation. Wn Wm. The N flag will always be cleared. This instruction must be executed 18 times using the REPEAT instruction (with an iteration count of 17) to generate the correct quotient and remainder.U{W} DIV. OV. The C flag is used to implement the divide algorithm and its final value should not be used. 5 Instruction Descriptions Words: Cycles: 1 18 (plus 1 for REPEAT execution)  2003 Microchip Technology Inc. The ‘W’ bit selects the dividend size (0 for 16-bit.UD): Wm+1:Wm → W1:W0 W1:W0 / Wns → W0 Remainder → W1 Operation: Status Affected: Encoding: Description: N. Wm+1:Wm is first copied to W1:W0. Z. W2. or Wm+1:Wm (for a 32-bit by 16-bit divide) and the divisor is stored in Wn. 3: Dividing by zero will initiate an arithmetic error trap during the first cycle of execution. Note 1: The extension . W4 . This may only occur for the double operation (DIV. Advance Information DS70030E-page 5-103 . In the double operation.. W15] For word operation (default): Wm → W0 0x0 → W1 W1:W0 / Wn → W0 Remainder → W1 For double operation (DIV.W extension to denote a word operation.

remainder to W1 Before Instruction W0 5555 W1 1234 W10 2500 W11 0042 W12 2200 SR 0000 After Instruction W0 01F2 W1 0100 W10 2500 W11 0042 W12 2200 SR 0000 DS70030E-page 5-104 Advance Information  2003 Microchip Technology Inc. Divide W2 by W4 .U 18 times . Execute DIV. .UD #17 W10.UD 18 times . W4 . W12 After Instruction W0 0040 W1 0000 W2 8000 W4 0200 SR 0002 (Z=1) . Store quotient to W0. Divide W11:W10 by W12 . Execute DIV.U W2. Store quotient to W0.dsPIC30F Programmer’s Reference Manual Example 1 REPEAT #17 DIV. remainder to W1 Before Instruction W0 5555 W1 1234 W2 8000 W4 0200 SR 0000 Example 2 REPEAT DIV.

Wm must be less than or equal to Wn. The C flag is used to implement the divide algorithm and its final value should not be used. To perform the operation. Store quotient to W0. W0 is first cleared and Wm is copied to W1.0. The Z flag will be set if the remainder is 0 and cleared otherwise. W15] 0x0 → W0 Wm → W1 W1:W0 / Wn → W0 Remainder → W1 N. Execute DIVF 18 times . 2: Dividing by zero will initiate an arithmetic error trap during the first cycle of execution. W15] Wn ∈ [W2 . signed fractional 16-bit by 16-bit divide. Z. the OV status bit will be set and the quotient and remainder should not be used. The sign of the remainder will be the same as the sign of the dividend. The ‘s’ bits select the divisor register.. The ‘t’ bits select the dividend register. When this occurs. unexpected results will occur because the fractional result will be greater than 1. OV. The 16-bit quotient of the divide operation is stored in W0. Instruction Descriptions DIVF Syntax: Operands: Operation: {label:} Fractional Divide DIVF Wm.. If Wm is greater than Wn. where the dividend is stored in Wm and the divisor is stored in Wn. and the 16-bit remainder is stored in W1.Section 5.. This instruction must be executed 18 times using the REPEAT instruction (with an iteration count of 17) to generate the correct quotient and remainder. C 1101 1001 0ttt t000 0000 ssss Iterative. Advance Information DS70030E-page 5-105 . Wn Wm ∈ [W0 .. 3: This instruction is interruptible on each instruction cycle boundary. Divide W8 by W9 . The N flag will be set if the remainder is negative and cleared otherwise. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 18 (plus 1 for REPEAT execution) REPEAT DIVF #17 W8. Note 1: For the fractional divide to be effective. remainder to W1 Before Instruction W0 8000 W1 1234 W8 1000 W9 4000 SR 0000 After Instruction W0 2000 W1 0000 W8 1000 W9 4000 SR 0002 (Z=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. The OV flag will be set if the divide operation resulted in an overflow and cleared otherwise. W9 .

W9 . remainder to W1 Before Instruction W0 8002 W1 8001 SR 0000 After Instruction W0 7FFE W1 8002 SR 0008 (N=1) DS70030E-page 5-106 Advance Information  2003 Microchip Technology Inc. Divide W8 by W9 . . Store quotient to W0. remainder to W1 Before Instruction W0 8000 W1 1234 W8 1000 W9 8000 SR 0000 Example 3 REPEAT #17 DIVF W0. Divide W0 by W1 . W1 After Instruction W0 F000 W1 0000 W8 1000 W9 8000 SR 0002 (Z=1) . Execute DIVF 18 times .dsPIC30F Programmer’s Reference Manual Example 2 REPEAT #17 DIVF W8. Store quotient to W0. Execute DIVF 18 times .

which is executed (lit14+1) times. 16383] Expr may be an absolute address. Using a loop size of -2. When this instruction executes.. DL<2:0> (CORCON<8:10>). DOSTART and DOEND are first pushed into their respective shadow registers. Unexpected results may occur if these offsets are used. The very last two instructions of the DO loop can NOT be: • an instruction which changes program control flow • a DO or REPEAT instruction Unexpected results may occur if any of these instructions are used. Advance Information DS70030E-page 5-107 . 1. The DO level count. The 14-bit count value (lit14) supports a maximum loop count value of 16384. 2: The linker will convert the specified expression into the offset to be used. 5 Instruction Descriptions Words: Cycles: 2 2  2003 Microchip Technology Inc. See the dsPIC30F Family Reference Manual for details. and the 16-bit offset value (Slit16) supports offsets of 32K instruction words in both directions. After the DO loop completes execution. Push DO shadows (DCOUNT. where Slit16 ∈ [-32768 . The ‘n’ bits are a signed literal that specifies the number of instructions offset from the PC to the last instruction executed in the loop. -1 or 0 is invalid. +32767]. label or expression. Using a loop count of 0 will result in the loop being executed one time. Expr lit14 ∈ [0 . 3. Special Features. 2. Expr is resolved by the linker to a Slit16. and then updated with the new DO loop parameters specified by the instruction.. Nesting up to an additional 5 levels may be provided in software by the user. The DO loop begins at the address following the DO instruction. DOSTART and DOEND registers are restored.. the pushed DCOUNT.Section 5.. DOEND. DCOUNT. and DL<2:0> is decremented. The ‘k’ bits specify the loop count. Instruction Descriptions DO Syntax: Operands: {label:} Initialize Hardware Loop Literal DO #lit14. is then incremented. Note 1: The DO instruction is interruptible and supports 1 level of hardware nesting. and ends at the address 2*Slit16 instruction words away. Restrictions: The following features and restrictions apply to the DO instruction. DOSTART) (lit14) → DCOUNT (PC)+4 → PC (PC) → DOSTART (PC) + (2*Slit16) → DOEND Increment DL<2:0> (CORCON<10:8>) DA 0000 0000 1000 0000 00kk nnnn kkkk nnnn kkkk nnnn kkkk nnnn Operation: Status Affected: Encoding: Description: Initiate a no overhead hardware DO loop.

01C010 CALL _FIR88 01C014 END12: NOP . . . Last instruction in loop PC DCOUNT DOSTART DOEND CORCON SR Example 2 Before Instruction 00 2000 0000 FF FFFF FF FFFF 0000 0001 (C=1) PC DCOUNT DOSTART DOEND CORCON SR After Instruction 00 2004 0005 00 2004 00 200A 0100 (DL=1) 0201 (DA. . Call the FIR88 subroutine . END12 01C004 DEC W1. . 01C00E . C=1) . W2 01C006 . . . . W4 . . END6 ADD W1. Last instruction in loop . . First instruction in loop . N=1) DS70030E-page 5-108 Advance Information  2003 Microchip Technology Inc. W3. SUB W2. Initiate DO loop (5 reps) . . . 01C008 . . . 01C00C . .dsPIC30F Programmer’s Reference Manual Example 1 002000 LOOP6: 002004 002006 002008 00200A END6: 00200C DO #5. First instruction in loop 01C000 LOOP12: DO #0x160. 01C00A . . W3 . W2. . Init DO loop (352 reps) . . . . (Required NOP filler) PC DCOUNT DOSTART DOEND CORCON SR Before Instruction 01 C000 0000 FF FFFF FF FFFF 0000 0008 (N=1) PC DCOUNT DOSTART DOEND CORCON SR After Instruction 01 C004 0160 01 C004 01 C014 0100 (DL=1) 0208 (DA.

Push Shadows (DCOUNT. 2: The linker will convert the specified expression into the offset to be used. Expr is resolved by the linker to a Slit16. 2. Note 1: The DO instruction is interruptible and supports 1 level of nesting. The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC+4).Section 5. is then incremented. The ‘s’ bits specify the register Wn that contains the loop count. +32767]. DOSTART) (Wn) → DCOUNT (PC)+4 → PC (PC) → DOSTART (PC) + (2*Slit16) → DOEND Increment DL<2:0> (CORCON<10:8>) DA 0000 1000 0000 1000 nnnn 0000 nnnn 0000 nnnn ssss nnnn Operation: Status Affected: Encoding: Description: 0000 Initiate a no overhead hardware DO loop. After the DO loop completes execution. Expr Wn ∈ [W0 . which is executed (Wn+1) times.. and the 16-bit offset value (Slit16) supports offsets of 32K instruction words in both directions. DOSTART and DOEND are first pushed into their respective shadow registers.. and DL<2:0> is decremented. Nesting up to an additional 5 levels may be provided in software by the user. Special Features. DOSTART and DOEND registers are restored. Instruction Descriptions DO Syntax: Operands: {label:} Initialize Hardware Loop Wn DO Wn. the pushed DCOUNT. When this instruction executes. 3. See the dsPIC30F Family Reference Manual for details. where Slit16 ∈ [-32768 . DL<2:0> (CORCON<8:10>). 1. -1 or 0 is invalid. and ends at the address 2*Slit16 instruction words away. The DO loop begins at the address following the DO instruction. label or expression. DOEND.. Advance Information DS70030E-page 5-109 .. Using an offset of -2. W15] Expr may be an absolute address. Restrictions: The following features and restrictions apply to the DO instruction. which is the last instruction executed in the loop. 5 Instruction Descriptions Words: Cycles: 2 2  2003 Microchip Technology Inc. The lower 14 bits of Wn support a maximum count value of 16384. The very last two instructions of the DO loop can NOT be: • an instruction which changes program control flow • a DO or REPEAT instruction Unexpected results may occur if these last instructions are used. DCOUNT. Unexpected results may occur if these offsets are used. Using a loop count of 0 will result in the loop being executed one time. The DO level count. and then updated with the new DO loop parameters specified by the instruction.

. . . . . Last instruction in loop . . Initiate DO loop (W7 reps) . First instruction in loop 002000 LOOPA: 002004 002006 002008 00200A 002010 ENDA: W1. . . END6 . W3 . .dsPIC30F Programmer’s Reference Manual Example 1 002000 LOOP6: 002004 002006 002008 00200A 00200C 00200E 002010 END6: DO ADD . . W2. . W3. . First instruction in loop #6 W2. REPEAT SUB NOP W0. (Required NOP filler) PC W0 DCOUNT DOSTART DOEND CORCON SR Example 2 Before Instruction 00 2000 0012 0000 FF FFFF FF FFFF 0000 0000 DO SWAP . Last instruction in loop PC W7 DCOUNT DOSTART DOEND CORCON SR Before Instruction 00 2000 E00F 0000 FF FFFF FF FFFF 0000 0000 PC W7 DCOUNT DOSTART DOEND CORCON SR After Instruction 00 2004 E00F 200F 00 2004 00 2010 0100 (DL=1) 0080 (DA=1) DS70030E-page 5-110 Advance Information  2003 Microchip Technology Inc. [W2++] . . MOV PC W0 DCOUNT DOSTART DOEND CORCON SR W7. . . ENDA W0 After Instruction 00 2004 0012 0012 00 2004 00 2010 0100 (DL=1) 0080 (DA=1) . . . W4 . Initiate DO loop (W0 reps) W1.

W4. 2. 4. The results of [Wx] – [Wy] are stored in Wxd. -2. [W11+W12]. W9]. Wxd [W9+W12]. [Wy]. The ‘x’ bits select the pre-fetch difference Wxd destination. [Wx]. W7*W7] Wx ∈ [W8. A..1 “MAC Pre-Fetches”. Operands: Acc ∈ [A. which may be the same as Wm. W11]. The ‘A’ bit selects the accumulator for the result. kx ∈ [-6. . [W8]+=2. 4. Operands Wx. W6*W6. The ‘i’ bits select the Wx pre-fetch operation. Acc. [Wx]+=kx.Section 5. -4. 2. 6] Wy ∈ [W10. OAB 1111 00mm A1xx 00ii iijj jj11 Operation: Status Affected: Encoding: Description: Compute the square of Wm. ky ∈ [-6. -4. -2. [Wy]+=ky. . [Wy]-=ky.B] Wm*Wm ∈ [W4*W4. W7] (Wm)*(Wm) → Acc(A or B) ([Wx]–[Wy])→ Wxd (Wx)+kx→Wx (Wy)+ky→Wy OA. [Wx]-=kx. W5*W5. OB. Wxd and Wyd specify the pre-fetch operations which support indirect and register offset addressing as described in Section 4. The results of Wm*Wm are sign-extended to 40-bits and stored in the specified accumulator. Instruction Descriptions ED Syntax: {label:} ED Euclidean Distance (No Accumulate) Wm*Wm. and optionally compute the difference of the pre-fetch values specified by [Wx] and [Wy].. . [W10]-=2. Advance Information DS70030E-page 5-111 . The ‘j’ bits select the Wy pre-fetch operation. The ‘m’ bits select the operand register Wm for the square. Words: Cycles: Example 1 ED 1 1 W4*W4. Square W4 to ACCA [W8]-[W10] to W4 Post-increment W8 Post-decrement W10 W4 W8 W10 ACCA Data 1100 Data 2300 SR Before Instruction 009A 1100 2300 00 3D0A 0000 007F 0028 0000 W4 W8 W10 ACCA Data 1100 Data 2300 SR After Instruction 0057 1102 22FE 00 0000 5CA4 007F 0028 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. 6] Wxd ∈ [W4 .14.

B.dsPIC30F Programmer’s Reference Manual Example 2 ED W5*W5. Square W5 to ACCB . W5 . [W11+W12]. [W9]+=2. Post-increment W9 W5 W9 W11 W12 ACCB Data 1200 Data 2508 SR Before Instruction 43C2 1200 2500 0008 00 28E3 F14C 6A7C 2B3D 0000 W5 W9 W11 W12 ACCB Data 1200 Data 2508 SR After Instruction 3F3F 1202 2500 0008 00 11EF 1F04 6A7C 2B3D 0000 DS70030E-page 5-112 Advance Information  2003 Microchip Technology Inc. [W11+W12]-[W9] to W5 . .

W11]. Wxd [W9+W12]. W9]. Acc. 4. W4 . [Wx]+=kx. and also the difference of the pre-fetch values specified by [Wx] and [Wy]. . W5*W5.. 4. Square W4 and add to ACCA [W10]-[W8] to W4 Post-increment W8 Post-decrement W10 W4 W8 W10 ACCA Data 1100 Data 2300 SR Before Instruction 009A 1100 2300 00 3D0A 3D0A 007F 0028 0000 W4 W8 W10 ACCA Data 1100 Data 2300 SR After Instruction 0057 1102 22FE 00 3D0A 99AE 007F 0028 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. which may be the same as Wm. OAB. Words: Cycles: Example 1 EDAC 1 1 W4*W4. [Wy]-=ky. Instruction Descriptions EDAC Syntax: {label:} EDAC Euclidean Distance Wm*Wm. 6] Wxd ∈ [W4 . The ‘m’ bits select the operand register Wm for the square. The results of [Wx] – [Wy] are stored in Wxd. Operands Wx. The ‘i’ bits select the Wx pre-fetch operation. A. OB. -2. . -4. 6] Wy ∈ [W10. [Wx]. The ‘x’ bits select the pre-fetch difference Wxd destination. [W11+W12]. Operands: Acc ∈ [A. The ‘A’ bit selects the accumulator for the result. W7] (Acc(A or B)) + (Wm)*(Wm) → Acc(A or B) ([Wx]–[Wy])→ Wxd (Wx)+kx→Wx (Wy)+ky→Wy OA. ky ∈ [-6. The ‘j’ bits select the Wy pre-fetch operation. W7*W7] Wx ∈ [W8. [Wy]. kx ∈ [-6. SB. Wxd and Wyd specify the pre-fetch operations which support indirect and register offset addressing as described in Section 4.1 “MAC Pre-Fetches”. SAB 1111 00mm A1xx 00ii iijj jj10 Operation: Status Affected: Encoding: Description: Compute the square of Wm. Advance Information DS70030E-page 5-113 . 2. 2. The results of Wm*Wm are sign-extended to 40-bits and added to the specified accumulator. [Wx]-=kx. [Wy]+=ky. [W8]+=2.B] Wm*Wm ∈ [W4*W4. W6*W6. -4. [w10]-=2.. . SA.Section 5. . -2.14.

dsPIC30F Programmer’s Reference Manual Example 2 EDAC W5*W5. . [W11+W12]. B. . . [w9]+=2. W5 . . Square W5 and add to ACCB [W9]-[W11+W12] to W5 Post-increment W9 W5 W9 W11 W12 ACCB Data 1200 Data 2508 SR Before Instruction 43C2 1200 2500 0008 00 28E3 F14C 6A7C 2B3D 0000 W5 W9 W11 W12 ACCB Data 1200 Data 2508 SR After Instruction 3F3F 1202 2500 0008 00 3AD3 1050 6A7C 2B3D 0000 DS70030E-page 5-114 Advance Information  2003 Microchip Technology Inc.

Exchange the contents of W1 and W9 W1 W9 SR Example 2 EXCH Before Instruction 55FF A3A3 0000 W4. W15] (Wns) ↔ (Wnd) None 1111 1101 0000 0ddd d000 ssss Exchange the word contents of two working registers.. W5 After Instruction W1 A3A3 W9 55FF SR 0000 . W9 . Note: This instruction only executes in Word mode. W15] Wnd ∈ [W0 . Words: Cycles: Example 1 1 1 EXCH W1. Advance Information DS70030E-page 5-115 . The ‘s’ bits select the address of the second register. Exchange the contents of W4 and W5 W4 W5 SR Before Instruction ABCD 4321 0000 After Instruction W4 4321 W5 ABCD SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Register direct addressing must be used for Wns and Wnd. The ‘d’ bits select the address of the first register.. Instruction Descriptions EXCH Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Exchange Wns and Wnd EXCH Wns.Section 5. Wnd Wns ∈ [W0 ...

W15] Wnd ∈ [W0 . If a bit change is not found. The ‘s’ bits select the address of the source register. Find 1st bit change from left in W1 . The bit number result is sign-extended to 16-bits and placed in Wnd.dsPIC30F Programmer’s Reference Manual FBCL Syntax: {label:} Find First Bit Change from Left FBCL Ws.. Wnd Operands: Operation: Ws ∈ [W0 . starting from the Most Significant bit after the sign bit of Ws and working towards the Least Significant bit of the word operand. W15] Max_Shift = 15 Sign = (Ws) & 0x8000 Temp = (Ws) << 1 Shift = 0 While ( (Shift < Max_Shift) && ( (Temp & 0x8000) == Sign) ) Temp = Temp << 1 Shift = Shift + 1 -Shift → (Wnd) C 1101 1111 0000 0ddd dppp ssss Status Affected: Encoding: Description: Find the first occurrence of a one (for a positive value). Words: Cycles: Example 1 1 1 FBCL W1.. This bit ordering allows for the immediate use of Wd with the SFTAC instruction for scaling values up. The next Most Significant bit after the sign bit is allocated bit number 0 and the Least Significant bit is allocated bit number -14. [Ws++]. The ‘d’ bits select the address of the destination register. or zero (for a negative value). Note: This instruction operates in Word mode only. [--Ws]. [Ws]. W9 . The ‘p’ bits select the source Address mode. . [++Ws]. When a bit change is found.. a result of -15 is returned and the C flag is set. and store result to W9 Before Instruction W1 55FF W9 FFFF SR 0000 After Instruction W1 55FF W9 0000 SR 0000 DS70030E-page 5-116 Advance Information  2003 Microchip Technology Inc. [Ws--]. the C flag is cleared..

W9 . W9 After Instruction W1 FFFF W9 FFF1 SR 0001 (C=1) . Advance Information DS70030E-page 5-117 . and store result to W9 Before Instruction W1 FFFF W9 BBBB SR 0000 Example 3 FBCL [W1++]. Find 1st bit change from left in [W1] . Find 1st bit change from left in W1 .Section 5. and store result to W9 . Instruction Descriptions Example 2 FBCL W1. Post-increment W1 Before Instruction W1 2000 W9 BBBB Data 2000 FF0A SR 0000 After Instruction W1 2002 W9 FFF9 Data 2000 FF0A SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.

Wnd Operands: Operation: Ws ∈ [W0 . W15] Max_Shift = 17 Temp = (Ws) Shift = 1 While ( (Shift < Max_Shift) && !(Temp & 0x8000) ) Temp = Temp << 1 Shift = Shift + 1 If (Shift == Max_Shift) 0 → (Wnd) Else Shift → (Wnd) C 1100 1111 1000 0ddd dppp ssss Status Affected: Encoding: Description: Finds the first occurrence of a ‘1’ starting from the Most Significant bit of Ws and working towards the Least Significant bit of the word operand.. Note: This instruction operates in Word mode only. [Ws++]. W5 . [Ws]. [Ws--]. Find the 1st one from the left in W2 . The ‘s’ bits select the address of the source register.. [--Ws]. W15] Wnd ∈ [W0 .. and store result to W5 Before Instruction W2 000A W5 BBBB SR 0000 After Instruction W2 000A W5 000D SR 0000 DS70030E-page 5-118 Advance Information  2003 Microchip Technology Inc. The ‘d’ bits select the address of the destination register. the C flag is cleared. Bit numbering begins with the Most Significant bit (allocated number 1) and advances to the Least Significant bit (allocated number 16). A result of zero indicates a ‘1’ was not found. [++Ws]. Words: Cycles: Example 1 1 1 FF1L W2. The bit number result is zero-extended to 16-bits and placed in Wnd. and the C flag will be set. . If a ‘1’ is found..dsPIC30F Programmer’s Reference Manual FF1L Syntax: {label:} Find First One from Left FF1L Ws. The ‘p’ bits select the source Address mode.

and store the result to W5 . W5 .Section 5. Instruction Descriptions Example 2 FF1L [W2++]. Find the 1st one from the left in [W2] . Post-increment W2 Before Instruction W2 2000 W5 BBBB Data 2000 0000 SR 0000 After Instruction W2 2002 W5 0000 Data 2000 0000 SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Advance Information DS70030E-page 5-119 .

[Ws]. . Find the 1st one from the right in W1 . W15] Wnd ∈ [W0 . W15] Max_Shift = 17 Temp = (Ws) Shift = 1 While ( (Shift < Max_Shift) && !(Temp & 0x1) ) Temp = Temp >> 1 Shift = Shift + 1 If (Shift == Max_Shift) 0 → (Wnd) Else Shift → (Wnd) C 1100 1111 0000 0ddd dppp ssss Status Affected: Encoding: Description: Finds the first occurrence of a ‘1’ starting from the Least Significant bit of Ws and working towards the Most Significant bit of the word operand. W9 . [Ws--]. A result of zero indicates a ‘1’ was not found. Note: This instruction operates in Word mode only.dsPIC30F Programmer’s Reference Manual FF1R Syntax: {label:} Find First One from Right FF1R Ws. [--Ws]. The ‘d’ bits select the address of the destination register. The ‘s’ bits select the address of the source register. If a ‘1’ is found.. Wnd Operands: Operation: Ws ∈ [W0 .. Words: Cycles: Example 1 1 1 FF1R W1. the C flag is cleared. The bit number result is zero-extended to 16-bits and placed in Wnd. [++Ws]. and store the result to W9 Before Instruction W1 000A W9 BBBB SR 0000 After Instruction W1 000A W9 0002 SR 0000 DS70030E-page 5-120 Advance Information  2003 Microchip Technology Inc. [Ws++].. and the C flag will be set.. Bit numbering begins with the Least Significant bit (allocated number 1) and advances to the Most Significant bit (allocated number 16). The ‘p’ bits select the source Address mode.

Post-increment W1 Before Instruction W1 2000 W9 BBBB Data 2000 8000 SR 0000 After Instruction W1 2002 W9 0010 Data 2000 8000 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.Section 5. Instruction Descriptions Example 2 FF1R [W1++]. W9 . and store the result to W9 . Find the 1st one from the right in [W1] . Advance Information DS70030E-page 5-121 .

Jump to _THERE #0x400. Expr is resolved by the linker to a lit23. . 027844 _THERE: MOV 027846 . ..dsPIC30F Programmer’s Reference Manual GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word 2nd word Description: 0000 0000 {label:} Unconditional Jump GOTO Expr Expr may be label or expression (but not a literal).... Since the PC must always reside on an even address boundary. lit23<0> is ignored.. . The ‘n’ bits form the target address.. Words: Cycles: Example 1 2 2 026000 GOTO 026004 MOV .. . 026000 026004 _code+2 .. W2 . lit23 → PC NOP → Instruction Register None 0100 0000 nnnn 0000 nnnn 0000 nnnn 0nnn nnn0 nnnn Unconditional jump to anywhere within the 4M instruction word program memory range. resumes here PC SR Example 2 Before Instruction 02 6000 0000 . W1 . PC SR After Instruction 02 7844 0000 . Jump to _code+2 PC SR Before Instruction 02 6000 0000 PC SR After Instruction 00 0102 0000 DS70030E-page 5-122 Advance Information  2003 Microchip Technology Inc.. GOTO . The PC is loaded with the 23-bit literal specified in the instruction. 8388606]. .. Note: The linker will resolve the specified expression into the lit23 to be used. start of code 000100 _code: .. Code execution . _THERE W0... where lit23 ∈ [0 ..

Section 5. Instruction Descriptions

GOTO
Syntax: Operands: Operation: {label:}

Unconditional Indirect Jump GOTO Wn

Wn ∈ [W0 ... W15] 0 → PC<22:16> (Wn<15:1>) → PC<15:1> 0 → PC<0> NOP → Instruction Register None 0000 0001 0100 0000 0000 ssss

Status Affected: Encoding: Description:

Unconditional indirect jump within the first 32K words of program memory. Zero is loaded into PC<22:16> and the value specified in (Wn) is loaded into PC<15:1>. Since the PC must always reside on an even address boundary, Wn<0> is ignored. The ‘s’ bits select the address of the source register.

Words: Cycles: Example 1

1 2
006000 GOTO 006002 MOV . ... . ... 007844 _THERE: MOV 007846 ... W4 W0, W1 ; Jump unconditionally ; to 16-bit value in W4

#0x400, W2

; Code execution ; resumes here

W4 PC SR

Before Instruction 7844 00 6000 0000

W4 PC SR

After Instruction 7844 00 7844 0000

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INC
Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:}

Increment f INC{.B} f {,WREG}

f ∈ [0 ... 8191] (f) + 1 → destination designated by D DC, N, OV, Z, C 1110 1100 0BDf ffff ffff ffff

Add one to the contents of the file register and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register. The ‘B’ bit selects byte or word operation (0 for word, 1 for byte). The ‘D’ bit selects the destination (0 for WREG, 1 for file register). The ‘f’ bits select the address of the file register. Note 1: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .W extension to denote a word operation, but it is not required. 2: The WREG is set to working register W0.

Words: Cycles: Example 1

1 1
INC.B 0x1000 ; Increment 0x1000 (Byte mode)

Before Instruction Data 1000 8FFF SR 0000 Example 2
INC

After Instruction Data 1000 8F00 SR 0101 (DC, C=1)
; Increment 0x1000 and store to WREG ; (Word mode)

0x1000, WREG

Before Instruction WREG ABCD Data 1000 8FFF SR 0000

After Instruction WREG 9000 Data 1000 8FFF SR 0108 (DC, N=1)

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Section 5. Instruction Descriptions

INC
Syntax: {label:}

Increment Ws INC{.B} Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws], Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd]

Operands: Operation: Status Affected: Encoding: Description:

Ws ∈ [W0 ... W15] Wd ∈ [W0 ... W15] (Ws) + 1 → Wd DC, N, OV, Z, C 1110 1000 0Bqq qddd dppp ssss

Add one to the contents of the source register Ws and place the result in the destination register Wd. Register direct or indirect addressing may be used for Ws and Wd. The ‘B’ bit selects byte or word operation (0 for word, 1 for byte). The ‘q’ bits select the destination Address mode. The ‘d’ bits select the address of the destination register. The ‘p’ bits select the source Address mode. The ‘s’ bits select the address of the source register. Note: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .W extension to denote a word operation, but it is not required.

Words: Cycles: Example 1

1 1
INC.B W1, [++W2] ; Pre-increment W2 ; Increment W1 and store to W2 ; (Byte mode)

Before Instruction W1 FF7F W2 2000 Data 2000 ABCD SR 0000 Example 2
INC W1, W2

After Instruction W1 FF7F W2 2001 Data 2000 80CD SR 010C (DC, N, OV=1)
; Increment W1 and store to W2 ; (Word mode)

Before Instruction W1 FF7F W2 2000 SR 0000

After Instruction W1 FF7F W2 FF80 SR 0108 (DC, N=1)

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INC2
Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:}

Increment f by 2 INC2{.B} f {,WREG}

f ∈ [0 ... 8191] (f) + 2 → destination designated by D DC, N, OV, Z, C 1110 1100 1BDf ffff ffff ffff

Add two to the contents of the file register and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register. The ‘B’ bit selects byte or word operation (0 for word, 1 for byte). The ‘D’ bit selects the destination (0 for WREG, 1 for file register). The ‘f’ bits select the address of the file register. Note: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .W extension to denote a word operation, but it is not required.

Words: Cycles: Example 1

1 1
INC2.B 0x1000 ; Increment 0x1000 by 2 ; (Byte mode)

Before Instruction Data 1000 8FFF SR 0000 Example 2
INC2

After Instruction Data 1000 8F01 SR 0101 (DC, C=1)
; Increment 0x1000 by 2 and store to WREG ; (Word mode)

0x1000, WREG

Before Instruction WREG ABCD Data 1000 8FFF SR 0000

After Instruction WREG 9001 Data 1000 8FFF SR 0108 (DC, N=1)

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Section 5. Instruction Descriptions

INC2
Syntax: {label:}

Increment Ws by 2 INC2{.B} Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws], Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd]

Operands: Operation: Status Affected: Encoding: Description:

Ws ∈ [W0 ... W15] Wd ∈ [W0 ... W15] (Ws) + 2 → Wd DC, N, OV, Z, C 1110 1000 1Bqq qddd dppp ssss

Add two to the contents of the source register Ws and place the result in the destination register Wd. Register direct or indirect addressing may be used for Ws and Wd. The ‘B’ bit selects byte or word operation (0 for word, 1 for byte). The ‘q’ bits select the destination Address mode. The ‘d’ bits select the address of the destination register. The ‘p’ bits select the source Address mode. The ‘s’ bits select the address of the source register. Note: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .W extension to denote a word operation, but it is not required.

Words: Cycles: Example 1

1 1
INC2.B W1, [++W2] ; Pre-increment W2 ; Increment by 2 and store to W1 ; (Byte mode)

Before Instruction W1 FF7F W2 2000 Data 2000 ABCD SR 0000 Example 2
INC2 W1, W2

After Instruction W1 FF7F W2 2001 Data 2000 81CD SR 010C (DC, N, OV=1)
; Increment W1 by 2 and store to W2 ; (word mode)

Before Instruction W1 FF7F W2 2000 SR 0000

After Instruction W1 FF7F W2 FF81 SR 0108 (DC, N=1)

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IOR
{label:} Operands: Operation: Status Affected: Encoding: Description:

Inclusive OR f and WREG IOR{.B} f {,WREG}

f ∈ [0 ... 8191] (f).IOR.(WREG) → destination designated by D N, Z 1011 0111 0BDf ffff ffff ffff

Compute the logical inclusive OR operation of the contents of the working register WREG and the contents of the file register and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register. The ‘B’ bit selects byte or word operation (0 for word, 1 for byte). The ‘D’ bit selects the destination (0 for WREG, 1 for file register). The ‘f’ bits select the address of the file register. Note 1: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .W extension to denote a word operation, but it is not required. 2: The WREG is set to working register W0.

Words: Cycles: Example 1

1 1
IOR.B 0x1000 ; IOR WREG to (0x1000) (Byte mode) ; (Byte mode)

Before Instruction WREG 1234 Data 1000 FF00 SR 0000 Example 2
IOR

After Instruction WREG 1234 Data 1000 FF34 SR 0000
; IOR (0x1000) to WREG ; (Word mode)

0x1000, WREG

Before After Instruction Instruction WREG 1234 WREG 1FBF Data 1000 0FAB Data 1000 0FAB SR 0008 (N=1) SR 0000

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Section 5. Instruction Descriptions

IOR
Syntax: Operands: {label:}

Inclusive OR Literal and Wn IOR{.B} #lit10, Wn

lit10 ∈ [0 ... 255] for byte operation lit10 ∈ [0 ... 1023] for word operation Wn ∈ [W0 ... W15] lit10.IOR.(Wn) → Wn N, Z 1011 0011 0Bkk kkkk kkkk dddd

Operation: Status Affected: Encoding: Description:

Compute the logical inclusive OR operation of the 10-bit literal operand and the contents of the working register Wn and place the result back into the working register Wn. The ‘B’ bit selects byte or word operation (0 for word, 1 for byte). The ‘k’ bits specify the literal operand. The ‘d’ bits select the address of the working register. Note 1: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .W extension to denote a word operation, but it is not required. 2: For byte operations, the literal must be specified as an unsigned value [0:255]. See Section 4.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode.

Words: Cycles: Example 1

1 1
IOR.B #0xAA, W9 ; IOR 0xAA to W9 ; (Byte mode)

Before Instruction W9 1234 SR 0000 Example 2
IOR #0x2AA, W4

After Instruction W9 12BE SR 0008 (N=1)
; IOR 0x2AA to W4 ; (Word mode)

Before Instruction W4 A34D SR 0000

After Instruction W4 A3EF SR 0008 (N=1)

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Advance Information

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#0x0.dsPIC30F Programmer’s Reference Manual IOR Syntax: {label:} Inclusive OR Wb and Short Literal IOR{. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 .. 1 for byte). You may use a .IOR.B W1. The ‘q’ bits select the destination Address mode. #lit5.B in the instruction denotes a byte operation rather than a word operation. . The ‘w’ bits select the address of the base register. IOR W1 and 0x5 (Byte mode) . W15] (Wb). Post-increment W9 Before Instruction W1 AAAA W9 2000 Data 2000 0000 SR 0000 Example 2 IOR After Instruction W1 AAAA W9 2001 Data 2000 00AF SR 0008 (N=1) . W9 Before Instruction W1 0000 W9 A34D SR 0000 After Instruction W1 0000 W9 0000 SR 0002 (Z=1) DS70030E-page 5-130 Advance Information  2003 Microchip Technology Inc. a five-bit integer number. The ‘B’ bit selects byte or word operation (0 for word... IOR W1 with 0x0 (Word mode) .. #0x5.W extension to denote a word operation. Z 0111 0www wBqq qddd d11k kkkk Operation: Status Affected: Encoding: Description: Compute the logical inclusive OR operation of the contents of the base register Wb and the 5-bit literal operand and place the result in the destination register Wd. Store to [W9] . 31] Wd ∈ [W0 . The ‘k’ bits provide the literal operand. Words: Cycles: Example 1 1 1 IOR. The ‘d’ bits select the address of the destination register.lit5 → Wd N. [W9++] .. Either register direct or indirect addressing may be used for Wd.. but it is not required.B} Wb. W15] lit5 ∈ [0 . Store to W9 W1. Note: The extension . Register direct addressing must be used for Wb.

The ‘w’ bits select the address of the base register. Register direct addressing must be used for Wb. The ‘q’ bits select the destination Address mode. The ‘s’ bits select the address of the source register. W15] Wd ∈ [W0 . [Ws++].B W1.(Ws) → Wd N. Advance Information DS70030E-page 5-131 .. The ‘B’ bit selects byte or word operation (0 for word. [Ws].IOR. Store result to [W9] . You may use a . Post-increment W5 and W9 Before Instruction W1 AAAA W5 2000 W9 2400 Data 2000 1155 Data 2400 0000 SR 0000 After Instruction W1 AAAA W5 2001 W9 2401 Data 2000 1155 Data 2400 00FF SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.B} Wb. Note: The extension . [Ws--]... Words: Cycles: Example 1 1 1 IOR. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . Either register direct or indirect addressing may be used for Ws and Wd. [--Ws]. but it is not required. Ws.B in the instruction denotes a byte operation rather than a word operation.. Z 0111 0www wBqq qddd dppp ssss Operation: Status Affected: Encoding: Description: Compute the logical inclusive OR operation of the contents of the source register Ws and the contents of the base register Wb and place the result in the destination register Wd. The ‘d’ bits select the address of the destination register. W15] Ws ∈ [W0 . [++Ws]. Instruction Descriptions IOR Syntax: {label:} Inclusive OR Wb and Ws IOR{. W15] (Wb). [W5++]. [W9++] ...W extension to denote a word operation. The ‘p’ bits select the source Address mode. 1 for byte). IOR W1 and [W5] (Byte mode) .Section 5.

W5. IOR W1 and W5 (Word mode) . Store the result to W9 Before Instruction W1 AAAA W5 5555 W9 A34D SR 0000 After Instruction W1 AAAA W5 5555 W9 FFFF SR 0008 (N=1) DS70030E-page 5-132 Advance Information  2003 Microchip Technology Inc. .dsPIC30F Programmer’s Reference Manual Example 2 IOR W1. W9 .

The ‘w’ bits specify the offset register Wb.. prior to shifting.Section 5. Note: If the operation moves more than sign-extension data into the upper Accumulator register (AccxU). OB. Words: Cycles: Example 1 1 1 LAC [W4++]. OAB. The ‘g’ bits select the source Address mode. OAB=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Instruction Descriptions LAC Syntax: {label:} Load Accumulator LAC Ws. [--Ws]. {#Slit4. SAB 1100 1010 Awww wrrr rggg ssss Operation: Status Affected: Encoding: Description: Read the contents of the source register. [Ws]. . B .B] ShiftSlit4(Extend(Ws)) → Acc(A or B) OA. [++Ws]. +7] Acc ∈ [A. The shift range is -8:7. SA. or causes a saturation. W15] Wb ∈ [W0 .. The data stored in the source register is assumed to be 1.. The ‘s’ bits specify the source register Ws. . the appropriate overflow and saturation bits will be set.15 fractional data and is automatically sign-extended (through bit 39) and zero-backfilled (bits [15:0]). SB. The ‘r’ bits encode the accumulator pre-shift.. [Ws--]. . W15] Slit4 ∈ [-8 . [Ws++]. optionally perform a signed 4-bit shift and store the result in the specified accumulator.} Acc Operands: Ws ∈ [W0 .. Advance Information DS70030E-page 5-133 . The ‘A’ bit specifies the destination accumulator. .. Load ACCB with [W4] << 3 Contents of [W4] do not change Post increment W4 Assume saturation disabled (SATB = 0) W4 ACCB Data 2000 SR Before Instruction 2000 00 5125 ABCD 1221 0000 W4 ACCB Data 2000 SR After Instruction 2002 FF 9108 0000 1221 4800 (OB. [Ws+Wb]. #-3. where a negative operand indicates an arithmetic left shift and a positive operand indicates an arithmetic right shift.

A . . #7. . . .dsPIC30F Programmer’s Reference Manual Example 2 LAC [--W2]. Pre-decrement W2 Load ACCA with [W2] >> 7 Contents of [W2] do not change Assume saturation disabled (SATA = 0) W2 ACCA Data 4000 Data 4002 SR Before Instruction 4002 00 5125 ABCD 9108 1221 0000 W2 ACCA Data 4000 Data 4002 SR After Instruction 4000 FF FF22 1000 9108 1221 0000 DS70030E-page 5-134 Advance Information  2003 Microchip Technology Inc. .

Allocate a stack frame of 160 bytes W14 W15 Data 2000 SR Before Instruction 2000 2000 0000 0000 W14 W15 Data 2000 SR After Instruction 2002 20A2 2000 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.. The ‘k’ bits specify the size of the stack frame. This instruction supports a maximum stack frame of 16382 bytes. Words: Cycles: Example 1 LNK 1 1 #0xA0 . Instruction Descriptions LNK Syntax: Operands: Operation: {label:} Allocate Stack Frame LNK #lit14 lit14 ∈ [0 . 16382] (W14) → (TOS) (W15) + 2 → W15 (W15) → W14 (W15) + lit14 → W15 None 1111 1010 00kk kkkk kkkk kkk0 Status Affected: Encoding: Description: This instruction allocates a stack frame of size lit14 bytes for a subroutine calling sequence. Advance Information DS70030E-page 5-135 . The stack frame is allocated by pushing the contents of the frame pointer (W14) onto the stack. lit14 must be even.. Note: Since the stack pointer can only reside on a word boundary.Section 5. storing the updated stack pointer (W15) to the frame pointer and then incrementing the stack pointer by the unsigned 14-bit literal operand.

The optional WREG operand determines the destination register. Logically shift right (0x600) by one . Z. 8191] For byte operation: 0 → Dest<7> (f<7:1>) → Dest<6:0> (f<0>) → C For word operation: 0 → Dest<15> (f<15:1>) → Dest<14:0> (f<0>) → C 0 C Status Affected: Encoding: Description: N.B 0x600 . If WREG is not specified. The ‘D’ bit selects the destination (0 for WREG. Zero is shifted into the Most Significant bit of the destination register. If WREG is specified. The Least Significant bit of the file register is shifted into the Carry bit of the Status register..B} f {. C 1101 0101 0BDf ffff ffff ffff Shift the contents of the file register one bit to the right and place the result in the destination register.WREG} f ∈ [0 . the result is stored in the file register. . 1 for byte).W extension to denote a word operation.dsPIC30F Programmer’s Reference Manual LSR Syntax: Operands: Operation: {label:} Logical Shift Right f LSR{. WREG After Instruction Data 600 557F SR 0001 (C=1) . You may use a .B in the instruction denotes a byte operation rather than a word operation.. Store to WREG . but it is not required. 2: The WREG is set to working register W0. 1 for file register). The ‘f’ bits select the address of the file register. The ‘B’ bit selects byte or word operation (0 for word. Words: Cycles: Example 1 1 1 LSR. (Byte mode) Before Instruction Data 600 55FF SR 0000 Example 2 LSR 0x600. the result is stored in WREG. (Word mode) Before Instruction Data 600 55FF WREG 0000 SR 0000 After Instruction Data 600 55FF WREG 2AFF SR 0001 (C=1) DS70030E-page 5-136 Advance Information  2003 Microchip Technology Inc. Note 1: The extension . Logically shift right (0x600) by one .

The ‘p’ bits select the source Address mode. 1 for byte). Words: Cycles: Example 1 1 1 LSR. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 . The Least Significant bit of Ws is shifted into the Carry bit of the Status register. Instruction Descriptions LSR Syntax: {label:} Logical Shift Right Ws LSR{. [--Ws].B W0. LSR W0 (Byte mode) . The ‘s’ bits select the address of the source register.W extension to denote a word operation. [Ws]. [Ws++]. Z. W15] Wd ∈ [W0 . W15] For byte operation: 0 → Wd<7> (Ws<7:1>) → Wd<6:0> (Ws<0>) → C For word operation: 0 → Wd<15> (Ws<15:1>) → Wd<14:0> (Ws<0>) → C 0 C Status Affected: Encoding: Description: N. The ‘d’ bits select the address of the destination register. Either register direct or indirect addressing may be used for Ws and Wd. Zero is shifted into the Most Significant bit of Wd. The ‘B’ bit selects byte or word operation (0 for word. W1 .. Note: The extension ..Section 5. You may use a .. [Ws--].B in the instruction denotes a byte operation rather than a word operation.. The ‘q’ bits select the destination Address mode. Store result to W1 Before Instruction W0 FF03 W1 2378 SR 0000 After Instruction W0 FF03 W1 2301 SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. C 1101 0001 0Bqq qddd dppp ssss Shift the contents of the source register Ws one bit to the right and place the result in the destination register Wd.B} Ws. [++Ws]. but it is not required. Advance Information DS70030E-page 5-137 .

dsPIC30F Programmer’s Reference Manual Example 2 LSR W0. LSR W0 (Word mode) . W1 . Store the result to W1 Before Instruction W0 8000 W1 2378 SR 0000 After Instruction W0 8000 W1 4000 SR 0000 DS70030E-page 5-138 Advance Information  2003 Microchip Technology Inc. .

Section 5. Z 1101 1110 0www wddd d100 kkkk Operation: Status Affected: Encoding: Description: Logical shift right the contents of the source register Wb by the 4-bit unsigned literal and store the result in the destination register Wnd. The ‘d’ bits select the address of the destination register.. #lit4.. Wnd Wb ∈ [W0 . The ‘k’ bits provide the literal operand. Advance Information DS70030E-page 5-139 . W5 .. 15] Wnd ∈ [W0 . Instruction Descriptions LSR Syntax: Operands: {label:} Logical Shift Right by Short Literal LSR Wb. Store result to W5 Before Instruction W4 0505 W5 F000 SR 0000 After Instruction W4 0505 W5 0282 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Direct addressing must be used for Wb and Wnd... LSR W4 by 1 . #14. Note: This instruction operates in Word mode only. Words: Cycles: Example 1 LSR 1 1 W4. W15] lit4<3:0> → Shift_Val 0 → Wnd<15:15-Shift_Val+1> Wb<15:Shift_Val> → Wnd<15-Shift_Val:0> N. #1. The ‘w’ bits select the address of the base register. W5 After Instruction W4 C800 W5 0003 SR 0000 . W15] lit4 ∈ [0 . LSR W4 by 14 .. Store result to W5 Before Instruction W4 C800 W5 1200 SR 0000 Example 2 LSR W4.

W2 . Store result to W3 Before Instruction W3 DD43 W4 000C W5 0800 SR 0000 After Instruction W3 0000 W4 000C W5 0800 SR 0002 (Z=1) DS70030E-page 5-140 Advance Information  2003 Microchip Technology Inc. Note 1: This instruction operates in Word mode only. Wns. The ‘s’ bits select the address of the source register. . Words: Cycles: Example 1 LSR 1 1 W0. The ‘d’ bits select the address of the destination register. Z 1101 1110 0www wddd d000 ssss Operation: Status Affected: Encoding: Description: Logical shift right the contents of the source register Wb by the 5 Least Significant bits of Wns (only up to 15 positions) and store the result in the destination register Wnd. W3 After Instruction W0 C00C W1 0001 W2 6006 SR 0000 .. W15] Wns ∈ [W0 . Direct addressing must be used for Wb and Wnd. Wnd Wb ∈ [W0 . W4. W15] Wns<4:0> → Shift_Val 0 → Wnd<15:15-Shift_Val+1> Wb<15:Shift_Val> → Wnd<15-Shift_Val:0> N. LSR W0 by W1 . W1. Store result to W2 Before Instruction W0 C00C W1 0001 W2 2390 SR 0000 Example 2 LSR W5. LSR W5 by W4 ...dsPIC30F Programmer’s Reference Manual LSR Syntax: Operands: {label:} Logical Shift Right by Wns LSR Wb.W15] Wnd ∈ [W0 . The ‘w’ bits select the address of the base register. Wnd will be loaded with 0x0.. 2: If Wns is greater than 15...

Acc {.. Wxd} {. OAB. Instruction Descriptions MAC Syntax: {label:} MAC Multiply and Accumulate Wm*Wn. (Wy)+ky→Wy (Acc(B or A)) rounded → AWB OA.[W11+W12]. as described in Section 4. Wyd ∈ [W4 . Note: The IF bit. W5*W7.AWB} {. SB. Wyd} {. Operands Wx. The ‘A’ bit selects the accumulator for the result. 6].Section 5. optionally pre-fetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. determines if the multiply is fractional or an integer. Wxd} {. CORCON<0>.[Wx]-=kx. [W13]+=2] (Acc(A or B)) + (Wm)*(Wn) → Acc(A or B) ([Wx])→ Wxd. W7] Wy ∈ [W10. W6*W7] Acc ∈ [A. ky ∈ [-6. Wy and Wyd specify optional pre-fetch operations. as described in Section 4.[Wx].14.1 “MAC Pre-Fetches”. Words: Cycles: 1 1 5 Instruction Descriptions  2003 Microchip Technology Inc. 2. 4. SAB 1100 0mmm A0xx yyii iijj jjaa Operation: Status Affected: Encoding: Description: Multiply the contents of two working registers.4 “MAC Write Back”. W4*W7. Wxd.[Wx]+=kx. Wyd} {.. SA. which support indirect and register offset addressing. kx ∈ [-6. 4. The 32-bit result of the signed multiply is sign-extended to 40-bits and added to the specified accumulator.[W9+W12]. W9]. (Wx)+kx→Wx ([Wy])→ Wyd. Wxd} {. Operand AWB specifies the optional store of the “other” accumulator. W5*W6. W11]. The ‘m’ bits select the operand registers Wm and Wn for the multiply. -4. -2. Wxd ∈ [W4 .[Wy]+=ky. The ‘a’ bits select the accumulator write back destination. The ‘y’ bits select the pre-fetch Wyd destination. The ‘x’ bits select the pre-fetch Wxd destination. -4. The ‘i’ bits select the Wx pre-fetch operation. Wyd} Operands: Wm*Wn ∈ [W4*W5. Advance Information DS70030E-page 5-141 . 2. W7] AWB ∈ [W13.[Wy]-=ky. -2. Wyd} {.[Wy]. OB.B] Wx ∈ [W8.. W4*W6..14. Wxd} {. 6]. The ‘j’ bits select the Wy pre-fetch operation.

Fetch [W8] to W4. [W8]-=2. W5 . Fetch [W8] to W4. Post-increment W10 by 2 . Multiply W4*W5 and add to ACCA . Write Back ACCB to W13 . CORCON = 0x00C0 (fractional multiply. Post-increment W10 by 2 . . CORCON = 0x00D0 (fractional multiply. super saturation) W4 W5 W8 W10 W13 ACCA ACCB Data 0A00 Data 1800 CORCON SR Before Instruction 1000 3000 0A00 1800 2000 23 5000 2000 00 0000 8F4C 5BBE C967 00D0 0000 W4 W5 W8 W10 W13 ACCA ACCB Data 0A00 Data 1800 CORCON SR After Instruction 5BBE C967 09FE 1802 0001 23 5600 2000 00 0000 1F4C 5BBE C967 00D0 8800 (OA. Fetch [W10] to W5. Post-decrement W8 by 2 . A. normal saturation) W4 W5 W8 W10 ACCA Data 0A00 Data 1800 CORCON SR Example 2 Before Instruction A022 B900 0A00 1800 00 1200 0000 2567 909C 00C0 0000 W4 W5 W8 W10 ACCA Data 0A00 Data 1800 CORCON SR After Instruction 2567 909C 0A06 1802 00 472D 2400 2567 909C 00C0 0000 MAC W4*W5. Multiply W4*W5 and add to ACCA . W4. W5.dsPIC30F Programmer’s Reference Manual Example 1 MAC W4*W5. W13 . Fetch [W10] to W5. W4. A. [W8]+=6. [W10]+=2. [W10]+=2. Post-increment W8 by 6 . OAB=1) DS70030E-page 5-142 Advance Information  2003 Microchip Technology Inc.

Wy and Wyd specify optional pre-fetch operations. kx ∈ [-6. W7] (Acc(A or B)) + (Wm)*(Wm) → Acc(A or B) ([Wx])→ Wxd. Wyd ∈ [W4 . The ‘i’ bits select the Wx pre-fetch operation. Wyd} {. W11]. Wxd.Section 5. W9]. SB. The ‘y’ bits select the pre-fetch Wyd destination. Acc {. Note: The IF bit. OAB. W6*W6. ky ∈ [-6. The ‘x’ bits select the pre-fetch Wxd destination. SAB 1111 00mm A0xx yyii iijj jj00 Operation: Status Affected: Encoding: Description: Square the contents of a working register.[W11+W12]. Wyd} Operands: Wm*Wm ∈ [W4*W4. CORCON<0>. W7] Wy ∈ [W10. -4. Wxd} {. 2.[Wy]+=ky. which support indirect and register offset addressing.[Wy]-=ky. 6]. Wxd ∈ [W4 . 6].. as described in Section 4. (Wx)+kx→Wx ([Wy])→ Wyd. (Wy)+ky→Wy OA. Wxd} {. The ‘A’ bit selects the accumulator for the result.1 “MAC Pre-Fetches”. The ‘m’ bits select the operand register Wm for the square. Words: Cycles: 1 1 5 Instruction Descriptions  2003 Microchip Technology Inc. -2.B] Wx ∈ [W8. W7*W7] Acc ∈ [A. optionally pre-fetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. Operands Wx. OB. Advance Information DS70030E-page 5-143 . 4. -4. Wyd} {. The 32-bit result of the signed multiply is sign-extended to 40-bits and added to the specified accumulator.14. 4.[Wx]-=kx.. Instruction Descriptions MAC Syntax: {label:} MAC Square and Accumulate Wm*Wm. determines if the multiply is fractional or an integer.[Wx].. -2.[Wx]+=kx. Wxd} {.. The ‘j’ bits select the Wy pre-fetch operation. Wxd} {. 2.[Wy]. W5*W5.[W9+W12]. Wyd} {. SA.

[W9+W12]. OAB=1) DS70030E-page 5-144 Advance Information  2003 Microchip Technology Inc. A. W7 . CORCON = 0x00C0 (fractional multiply. W4. . Fetch [W11] to W7. Post-decrement W10 by 2 . B. normal saturation) W4 W5 W9 W10 W12 ACCB Data 0C20 Data 1900 CORCON SR Example 2 Before Instruction A022 B200 0C00 1900 0020 00 2000 0000 A230 650B 00C0 0000 W4 W5 W9 W10 W12 ACCB Data 0C20 Data 1900 CORCON SR After Instruction A230 650B 0C00 18FE 0020 00 67CD 0908 A230 650B 00C0 0000 MAC W7*W7. CORCON = 0x00D0 (fractional multiply. [W10]-=2. [W11]-=2.dsPIC30F Programmer’s Reference Manual Example 1 MAC W4*W4. Fetch [W10] to W5. Post-decrement W11 by 2 . Fetch [W9+W12] to W4 . W5 . Square W4 and add to ACCB . super saturation) W7 W11 ACCA Data 2000 CORCON SR Before Instruction 76AE 2000 FE 9834 4500 23FF 00D0 0000 W7 W11 ACCA Data 2000 CORCON SR After Instruction 23FF 1FFE FF 063E 0188 23FF 00D0 8800 (OA. Square W7 and add to ACCA .

Advance Information DS70030E-page 5-145 . You may use a .B} f {. 1 for byte).B TMR0. Note 1: The extension . but it is not required.B in the instruction denotes a byte operation rather than a word operation. The ‘f’ bits select the address of the file register. the result is stored back to the file register and the only effect is to modify the status register. Z 1011 1111 1BDf ffff ffff ffff Move the contents of the specified file register to the destination register.Section 5. The ‘D’ bit selects the destination (0 for WREG. Instruction Descriptions MOV Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Move f to Destination MOV{. If WREG is specified.WREG} f ∈ [0 . Words: Cycles: Example 1 1 1 MOV. update SR based on (0x800) (Word mode) Before Instruction Data 0800 B29F SR 0000 After Instruction Data 0800 B29F SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.W extension to denote a word operation. WREG . 8191] (f) → destination designated by D N. The optional WREG operand determines the destination register. 1 for file register). move (TMR0) to WREG (Byte mode) Before Instruction WREG (W0) 9080 TMR0 2355 SR 0000 Example 2 MOV 0x800 After Instruction WREG (W0) 9055 TMR0 2355 SR 0000 .. 2: The WREG is set to working register W0. The ‘B’ bit selects byte or word operation (0 for word.. the result is stored in WREG. If WREG is not specified.

Words: Cycles: Example 1 1 1 MOV. The ‘B’ bit selects byte or word operation (0 for word.W extension to denote a word move. but it is not required. 2: The WREG is set to working register W0.B WREG. move WREG to 0x801 (Byte mode) Before Instruction WREG (W0) 98F3 Data 0800 4509 SR 0000 Example 2 MOV After Instruction WREG (W0) 98F3 Data 0800 F309 SR 0008 (N=1) . DISICNT Before Instruction WREG (W0) 00A0 DISICNT 0000 SR 0000 After Instruction WREG (W0) 00A0 DISICNT 00A0 SR 0000 DS70030E-page 5-146 Advance Information  2003 Microchip Technology Inc. 8191] (WREG) → f None 1011 0111 1B1f ffff ffff ffff Move the contents of the default working register WREG into the specified file register.. Note 1: The extension .. 0x801 . move WREG to DISICNT WREG. 1 for byte).B in the instruction denotes a byte move rather than a word move. f f ∈ [0 .dsPIC30F Programmer’s Reference Manual MOV Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Move WREG to f MOV{. The ‘f’ bits select the address of the file register.B} WREG. . You may use a .

W12 . 2: Since the file register address must be word aligned. W3 Before Instruction W3 0035 Data 27FE ABCD SR 0000 After Instruction W3 ABCD Data 27FE ABCD SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Wnd f ∈ [0 . but must be word aligned.. move (0x27FE) to W3 0x27FE. only the upper 15 bits of the file register address are encoded (bit 0 is assumed to be ‘0’). The ‘d’ bits select the address of the destination register. The file register may reside anywhere in the 32K words of data memory. Words: Cycles: Example 1 MOV 1 1 CORCON. Advance Information DS70030E-page 5-147 . The ‘f’ bits select the address of the file register. Instruction Descriptions MOV Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Move f to Wnd MOV f.Section 5. Note 1: This instruction only operates on word operands. move CORCON to W12 Before Instruction W12 78FA CORCON 00F0 SR 0000 Example 2 MOV After Instruction W12 00F0 CORCON 00F0 SR 0000 .. 65534] Wnd ∈ [W0 ... W15] (f) → Wnd None 1000 0fff ffff ffff ffff dddd Move the word contents of the specified file register to Wnd. Register direct addressing must be used for Wnd.

65534] Wns ∈ [W0 . Note 1: This instruction only operates on word operands. W15] (Wns) → f None 1000 1fff ffff ffff ffff ssss Move the word contents of the working register Wns to the specified file register. The ‘s’ bits select the address of the source register.dsPIC30F Programmer’s Reference Manual MOV Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Move Wns to f MOV Wns. .. but must be word aligned. Words: Cycles: Example 1 MOV 1 1 W4. move W4 to XMODSRT Before Instruction W4 1200 XMODSRT 1340 SR 0000 Example 2 MOV After Instruction W4 1200 XMODSRT 1200 SR 0000 . move W8 to data address 0x1222 W8. The ‘f’ bits select the address of the file register. XMDOSRT . 2: Since the file register address must be word aligned.. Register direct addressing must be used for Wn. 0x1222 Before Instruction W8 F200 Data 1222 FD88 SR 0000 After Instruction W8 F200 Data 1222 F200 SR 0000 DS70030E-page 5-148 Advance Information  2003 Microchip Technology Inc. only the upper 15 bits of the file register address are encoded (bit 0 is assumed to be ‘0’)... f f ∈ [0 . The file register may reside anywhere in the 32K words of data memory.

load W5 with #0x17 (Byte mode) Before Instruction W5 7899 SR 0000 Example 2 MOV.. W9 After Instruction W5 7817 SR 0000 . Register direct addressing must be used for Wnd.. The ‘k’ bits specify the value of the literal.. load W9 with #0xFE (Byte mode) Before Instruction W9 AB23 SR 0000 After Instruction W9 ABFE SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Note: This instruction operates in Byte mode and the .B #0x17. Advance Information DS70030E-page 5-149 .Section 5.B #0xFE. 255] Wnd ∈ [W0 .B #lit8. Instruction Descriptions MOV. W5 . The ‘d’ bits select the address of the working register. Wnd lit8 ∈ [0 . W15] lit8 → Wnd None 1011 0011 1100 kkkk kkkk dddd The unsigned 8-bit literal ‘k’ is loaded into the lower byte of Wnd.. The upper byte of Wnd is not changed.B extension must be provided.B Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Move 8-bit Literal to Wnd MOV. Words: Cycles: Example 1 1 1 MOV.

Note 1: This instruction operates only in Word mode. W2 After Instruction W13 4231 SR 0000 .. load W8 with #-1000 Before Instruction W8 23FF SR 0000 After Instruction W8 FC18 SR 0000 DS70030E-page 5-150 Advance Information  2003 Microchip Technology Inc.dsPIC30F Programmer’s Reference Manual MOV Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Move 16-bit Literal to Wnd MOV #lit16.. Wnd lit16 ∈ [-32768 . . W15] lit16 → Wnd None 0010 kkkk kkkk kkkk kkkk dddd The 16-bit literal ‘k’ is loaded into Wnd. or unsigned value [0:65535]. Words: Cycles: Example 1 MOV 1 1 #0x4231. W13 . The ‘d’ bits select the address of the working register. 2: The literal may be specified as a signed value [-32768:32767]. W8 After Instruction W2 0004 SR 0000 . 65535] Wnd ∈ [W0 .. load W13 with #0x4231 Before Instruction W13 091B SR 0000 Example 2 MOV #0x4.. The ‘k’ bits specify the value of the literal. load W2 with #0x4 Before Instruction W2 B004 SR 0000 Example 3 MOV #-1000. Register direct addressing must be used for Wnd.

Note 1: The extension . 1022] (even only) for word operation Wnd ∈ [W0 .. the range of Slit10 is not reduced as specified in Section 4. 1 for byte). You may use a ... Register indirect addressing must be used for the source. (Word mode) [W4+0x3E8]. load W2 with [W4+0x3E8] . W15] Slit10 ∈ [-512 .Section 5. W2 Before Instruction W2 9088 W4 0800 Data 0BE8 5634 SR 0000 After Instruction W2 5634 W4 0800 Data 0BE8 5634 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc... Words: Cycles: Example 1 1 1 MOV. The ‘s’ bits select the address of the source register. W15] [Ws+Slit10] → Wnd None 1001 0kkk kBkk kddd dkkk ssss Operation: Status Affected: Encoding: Description: The contents of [Ws+Slit10] are loaded into Wnd.. 2: In Byte mode. The ‘B’ bit selects byte or word operation (0 for word..6 “Using 10-bit Literal Operands”.B in the instruction denotes a byte move rather than a word move.W extension to denote a word move. 1022] and Slit10 must be even to maintain word address alignment. since the literal represents an address offset from Ws.B} [Ws+Slit10]. In Word mode. Wnd Ws ∈ [W0 .. but it is not required. The ‘d’ bits select the address of the destination register. Instruction Descriptions MOV Syntax: Operands: {label:} Move [Ws with offset] to Wnd MOV{. (Byte mode) Before Instruction W8 1008 W10 4009 Data 101A 3312 SR 0000 Example 2 MOV After Instruction W8 1008 W10 4033 Data 101A 3312 SR 0000 .. the range of Slit10 is increased to [-1024 .B [W8+0x13].. Advance Information DS70030E-page 5-151 . The ‘k’ bits specify the value of the literal. and direct addressing must be used for Wnd. load W10 with [W8+0x13] . 511] for byte operation Slit10 ∈ [-1024 . W10 .

W extension to denote a word move. Words: Cycles: Example 1 1 1 MOV. W15] (Wns) → [Wd+Slit10] None 1001 1kkk kBkk kddd dkkk ssss Operation: Status Affected: Encoding: Description: The contents of Wns are stored to [Wd+Slit10]. In Word mode.B} Wns.B in the instruction denotes a byte move rather than a word move...6 “Using 10-bit Literal Operands”. [W1-0x400] Before Instruction W1 1000 W11 8813 Data 0C00 FFEA SR 0000 After Instruction W1 1000 W11 8813 Data 0C00 8813 SR 0000 DS70030E-page 5-152 Advance Information  2003 Microchip Technology Inc. store W11 to [W1-0x400] . 511] in Byte mode Slit10 ∈ [-1024 . The ‘k’ bits specify the value of the literal. 2: In Byte mode. since the literal represents an address offset from Wd. and indirect addressing must be used for the destination.B W0. Note 1: The extension .. Register direct addressing must be used for Wns. . store W0 to [W1+0x7] .. but it is not required. The ‘s’ bits select the address of the destination register. The ‘B’ bit selects byte or word operation (0 for word.. (Word mode) W11. the range of Slit10 is increased to [-1024 .. (Byte mode) Before Instruction W0 9015 W1 1800 Data 1806 2345 SR 0000 Example 2 MOV After Instruction W0 9015 W1 1800 Data 1806 1545 SR 0000 . You may use a .. 1022] (even only) in Word mode Wd ∈ [W0 ..dsPIC30F Programmer’s Reference Manual MOV Syntax: Operands: {label:} Move Wns to [Wd with offset] MOV{. [W1+0x7] . 1022] and Slit10 must be even to maintain word address alignment. [Wd+Slit10] Wns ∈ [W0 . the range of Slit10 is not reduced as specified in Section 4.. 1 for byte). W15] Slit10 ∈ [-512 .. The ‘d’ bits select the address of the destination register.

W15] Wd ∈ [W0 . The ‘B’ bit selects byte or word operation (0 for word. W15] (Ws) → Wd None 0111 1www wBhh hddd dggg ssss Operation: Status Affected: Encoding: Description: Move the contents of the source register into the destination register. [W15++]. The ‘h’ bits select the destination Address mode. The ‘g’ bits select the source Address mode. Instruction Descriptions MOV Syntax: {label:} Move Ws to Wd MOV{. Wd [Wd] [Wd++] [Wd--] [--Wd] [++Wd] [Wd+Wb] Operands: Ws ∈ [W0 ..W extension to denote a word move.B [W0--]. The ‘w’ bits define the offset register Wb. the offset must be the same because the ‘w’ encoding bits are shared by Ws and Wd. 3: The instruction “PUSH Ws” translates to MOV Ws.. 1 for byte). You may use a . Move [W0] to W4 (Byte mode) .B in the instruction denotes a byte move rather than a word move. but it is not required. 4: The instruction “POP Wd” translates to MOV [--W15]. [Ws++].B} Ws. W4 . Post-decrement W0 Before Instruction W0 0A01 W4 2976 Data 0A00 8988 SR 0000 After Instruction W0 0A00 W4 2989 Data 0A00 8988 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. [Ws].. Wd. Note 1: The extension . The ‘d’ bits select the address of the destination register. [Ws--]. The ‘s’ bits select the address of the source register.. 2: When Register Offset Addressing mode is used for both the source and destination. [++Ws]. Advance Information DS70030E-page 5-153 . W15] Wb ∈ [W0 .Section 5. Words: Cycles: Example 1 1 1 MOV.. [--Ws].. [Ws+Wb]. Either register direct or indirect addressing may be used for Ws and Wd.

. Post-increment W6 Before Instruction W2 0800 W3 0040 W6 1228 Data 0840 9870 Data 1228 0690 SR 0000 After Instruction W2 0800 W3 0040 W6 122A Data 0840 0690 Data 1228 0690 SR 0000 DS70030E-page 5-154 Advance Information  2003 Microchip Technology Inc.dsPIC30F Programmer’s Reference Manual Example 2 MOV [W6++]. [W2+W3] . Move [W6] to [W2+W3] (Word mode) .

. Note 1: This instruction only operates on double-words.. [Ws--]. Move W2 to W6 (Double mode) Before Instruction W2 12FB W3 9877 W6 9833 W7 FCC6 SR 0000 After Instruction W2 12FB W3 9877 W6 12FB W7 9877 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. W14] For direct addressing of source: Wns → Wnd Wns+1 → Wnd+1 For indirect addressing of source: See Description None 1011 1110 0000 0ddd 0ppp ssss Operation: Status Affected: Encoding: Description: Move the double-word specified by the source to a destination working register pair (Wnd:Wnd+1).D Syntax: {label:} Double-Word Move from Source to Wnd MOV. W6 .. 3: The instruction “POP. The ‘p’ bits select the source Address mode. W4 . If indirect addressing is used for the source. Wnd.Section 5.D [--W15]. 2: Wnd must be an even working register.D Wns. W2.D W2. [Ws++].D Wnd” translates to MOV. Instruction Descriptions MOV. the contents of two successive working registers (Wns:Wns+1) are moved to Wnd:Wnd+1. The ‘d’ bits select the address of the destination register.. W14] Ws ∈ [W0 . Words: Cycles: Example 1 1 2 MOV. See Figure 4-2 for information on how double-words are aligned in memory. The ‘s’ bits select the address of the first source register. Any pre/post-increment or pre/post-decrement will adjust Ws by 4 bytes to accommodate for the double-word. If register direct addressing is used for the source. Advance Information DS70030E-page 5-155 . [Ws]. W15] Wnd ∈ [W0. W4 . W2. [++Ws]. Ws specifies the effective address for the Least Significant Word of the double-word.. [--Ws]. Wnd Operands: Wns ∈ [W0..

Move [W7] to W4 (Double mode) .D [W7--].dsPIC30F Programmer’s Reference Manual Example 2 MOV. . W4 . Post-decrement W7 Before Instruction W4 B012 W5 FD89 W7 0900 Data 0900 A319 Data 0902 9927 SR 0000 After Instruction W4 A319 W5 9927 W7 08FC Data 0900 A319 Data 0902 9927 SR 0000 DS70030E-page 5-156 Advance Information  2003 Microchip Technology Inc.

. If indirect addressing is used for the destination. 3: The instruction PUSH.. Move W10 to W0 (Double mode) Before Instruction W0 9000 W1 4322 W10 CCFB W11 0091 SR 0000 After Instruction W0 CCFB W1 0091 W10 CCFB W11 0091 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. The ‘d’ bits select the address of the destination register. W14] Wnd ∈ [W0. W15] For direct addressing of destination: Wns → Wnd Wns+1 → Wnd+1 For indirect addressing of destination: See Description None 1011 1110 10qq qddd d000 sss0 Move a double-word (Wns:Wns+1) to the specified destination..D Wns.D Ws translates to MOV. W2. the contents of Wns:Wns+1 are stored to Wnd:Wnd+1. Wnd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wns ∈ [W0. W0 . Wd specifies the effective address for the Least Significant Word of the double-word. W4 . See Figure 4-2 for information on how double-words are aligned in memory. The ‘s’ bits select the address of the source register pair.. The ‘q’ bits select the destination Address mode.. W14] Wd ∈ [W0 .. Note 1: This instruction only operates on double-words. Advance Information DS70030E-page 5-157 . If register direct addressing is used for the destination.Section 5.D Syntax: {label:} Double-Word Move from Wns to Destination MOV. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 2 MOV. [W15++].D W10. 2: Wnd must be an even working register.D Wns. Instruction Descriptions MOV. Any pre/post-increment or pre/post-decrement will adjust Wd by 4 bytes to accommodate for the double-word. W4 . W2.

dsPIC30F Programmer’s Reference Manual Example 2 MOV. Move W4 to [W6] Before Instruction W4 100A W5 CF12 W6 0804 Data 0800 A319 Data 0802 9927 SR 0000 After Instruction W4 100A W5 CF12 W6 0800 Data 0800 100A Data 0802 CF12 SR 0000 DS70030E-page 5-158 Advance Information  2003 Microchip Technology Inc. .D W4. Pre-decrement W6 (Double mode) . [--W6] .

Wxd} {. Wy and Wyd specify optional pre-fetch operations which support indirect and register offset addressing.[W9+W12]. Store B. kx ∈ [-6. -4.4 “MAC Write Back”.. Operand AWB specifies the optional store of the “other” accumulator. an accumulator must be specified to designate which accumulator to write back. The ‘a’ bits select the accumulator write back destination. Wyd ∈ [W4 .B] Wx ∈ [W8. Wyd} {. W9]. 6]. Words: Cycles: Example 1 1 1 MOVSAC . Instruction Descriptions MOVSAC Syntax: {label:} MOVSAC Pre-Fetch Operands and Store Accumulator Acc {. [W13]+=2] ([Wx])→ Wxd. Post-increment W11 by 4 ACCA to W13 W6 W7 W9 W11 W13 ACCA Data 0800 Data 1900 SR Before Instruction A022 B200 0800 1900 0020 00 3290 5968 7811 B2AF 0000 W6 W7 W9 W11 W13 ACCA Data 0800 Data 1900 SR After Instruction 7811 B2AF 0800 1904 3290 00 3290 5968 7811 B2AF 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. as described in Section 4. Wxd. 2. The ‘y’ bits select the pre-fetch Wyd destination. Fetch . Operands Wx. Advance Information DS70030E-page 5-159 . (Wx)+kx→Wx ([Wy])→ Wyd. The ‘j’ bits select the Wy pre-fetch operation.[Wy]. (Wy)+ky→Wy (Acc(B or A)) rounded → AWB None 1100 0111 A0xx yyii iijj jjaa Operation: Status Affected: Encoding: Description: Optionally pre-fetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. -2. Even though an accumulator operation is not performed in this instruction. W7] AWB ∈ [W13. Wyd} Operands: Acc ∈ [A. W7] Wy ∈ [W10. 4.1 “MAC Pre-Fetches”. as described in Section 4.Section 5. 2. W13 [W9] to W6 [W11] to W7.[Wx]-=kx. Wxd} {.[Wx]+=kx.. W7. W6. 4. The ‘A’ bit selects the other accumulator used for write back. The ‘x’ bits select the pre-fetch Wxd destination. -4. ky ∈ [-6. Fetch .[W11+W12].. Wxd ∈ [W4 .14. -2. The ‘i’ bits select the Wx pre-fetch operation. Wyd} {.[Wy]-=ky.[Wx]. Wyd} {. [W9]. 6]. Wxd} {.14.. [W11]+=4. W11].[Wy]+=ky.AWB} {. Wxd} {.

. [W9]-=2. Post-increment W13 by 2 W4 W6 W9 W11 W12 W13 ACCB Data 1200 Data 2024 Data 2300 SR Before Instruction 76AE 2000 1200 2000 0024 2300 00 9834 4500 BB00 52CE 23FF 0000 W4 W6 W9 W11 W12 W13 ACCB Data 1200 Data 2024 Data 2300 SR After Instruction BB00 52CE 11FE 2000 0024 2302 00 9834 4500 BB00 52CE 9834 0000 DS70030E-page 5-160 Advance Information  2003 Microchip Technology Inc. Post-decrement W9 by 2 [W11+W12] to W6 ACCB to [W13]. Store A. W6. [W11+W12]. W4. Fetch . [W13]+=2 [W9] to W4.dsPIC30F Programmer’s Reference Manual Example 2 MOVSAC . Fetch .

Note: The IF bit. [W13]+=2] (Wm)*(Wn) → Acc(A or B) ([Wx])→ Wxd. W7] Wy ∈ [W10. W4*W6. -4. 2.[W9+W12]. as described in Section 4. Wyd} Operands: Wm*Wn ∈ [W4*W5. Wxd. OB. 4. W9]. W5*W6. -4. 2. W7] AWB ∈ [W13. Wyd} {.[W11+W12].[Wx]-=kx. Wxd} {.[Wx]. Wxd} {. The ‘i’ bits select the Wx pre-fetch operation.[Wx]+=kx. The ‘j’ bits select the Wy pre-fetch operation. Advance Information DS70030E-page 5-161 . Wyd} {. (Wy)+ky→Wy OA. Wxd} {. Wxd} {. CORCON<0>. Words: Cycles: 1 1 5 Instruction Descriptions  2003 Microchip Technology Inc. Wyd ∈ [W4 .. SB. OAB.. Wy and Wyd specify optional pre-fetch operations which support indirect and register offset addressing. The 32-bit result of the signed multiply is sign-extended to 40-bits and stored to the specified accumulator. 6].[Wy]. Operands Wx. 6]. kx ∈ [-6. Acc {. Wyd} {. 4. W5*W7. SA. The ‘x’ bits select the pre-fetch Wxd destination. The ‘y’ bits select the pre-fetch Wyd destination.14.[Wy]-=ky. Instruction Descriptions MPY Syntax: {label:} MPY Multiply Wm by Wn to Accumulator Wm*Wn.1 “MAC Pre-Fetches”. -2. (Wx)+kx→Wx ([Wy])→ Wyd. W6*W7] Acc ∈ [A.[Wy]+=ky. The ‘m’ bits select the operand registers Wm and Wn for the multiply: The ‘A’ bit selects the accumulator for the result. W4*W7. Wxd ∈ [W4 . ky ∈ [-6. optionally pre-fetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results... determines if the multiply is fractional or an integer.Section 5.B] Wx ∈ [W8. -2. SAB 1100 0mmm A0xx yyii iijj jj11 Operation: Status Affected: Encoding: Description: Multiply the contents of two working registers. W11].

CORCON = 0x0000 (fractional multiply. no saturation) W4 W5 W6 W7 W8 W10 ACCB Data 1782 Data 23FE CORCON SR Before Instruction C000 9000 671F E3DC 1782 23FE 00 9834 4500 8FDC 0078 0000 0000 W4 W5 W6 W7 W8 W10 ACCB Data 1782 Data 23FE CORCON SR After Instruction 8FDC 0078 671F E3DC 1784 23FC FF E954 3748 8FDC 0078 0000 0000 DS70030E-page 5-162 Advance Information  2003 Microchip Technology Inc. Fetch [W10] to W5. Post-decrement W10 by 2 . no saturation) W4 W5 W6 W7 W8 W10 ACCA Data 1780 Data 2400 CORCON SR Example 2 Before Instruction C000 9000 0800 B200 1780 2400 FF F780 2087 671F E3DC 0000 0000 W4 W5 W6 W7 W8 W10 ACCA Data 1780 Data 2400 CORCON SR After Instruction C000 9000 671F E3DC 1782 23FE 00 3800 0000 671F E3DC 0000 0000 MPY W6*W7. A. Post-decrement W10 by 2 . [W8]+=2. Post-increment W8 by 2 . [W10]-=2. [W10]-=2. W4. CORCON = 0x0000 (fractional multiply. [W8]+=2. Post-increment W8 by 2 . Fetch [W10] to W7. B. Fetch [W8] to W6. W6. Multiply W6*W7 and store to ACCB . Multiply W4*W5 and store to ACCA . W5 .dsPIC30F Programmer’s Reference Manual Example 1 MPY W4*W5. W7 . Fetch [W8] to W4. .

6]. CORCON<0>. Wyd} {. optionally pre-fetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. Wxd} {. Acc {. as described in Section 4.Section 5. W5*W5. Wxd ∈ [W4 . The ‘i’ bits select the Wx pre-fetch operation. The ‘m’ bits select the operand register Wm for the square. determines if the multiply is fractional or an integer. Wyd} {. SB. W7] Wy ∈ [W10. Wyd ∈ [W4 . 6]. 2. The ‘x’ bits select the pre-fetch Wxd destination. no saturation) W6 W9 ACCA Data 0900 CORCON SR Before Instruction 6500 0900 00 7C80 0908 B865 0000 0000 W6 W9 ACCA Data 0900 CORCON SR After Instruction B865 0902 00 4FB2 0000 B865 0000 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.. W7] (Wm)*(Wm) → Acc(A or B) ([Wx])→ Wxd. Operands Wx. -2.. A. W6*W6. Wxd} {. W11]. Fetch [W9] to W6. The 32-bit result of the signed multiply is sign-extended to 40-bits and stored in the specified accumulator. Wy and Wyd specify optional pre-fetch operations which support indirect and register offset addressing..14. (Wx)+kx→Wx ([Wy])→ Wyd. W7*W7] Acc ∈ [A. The ‘A’ bit selects the accumulator for the result. W6 . ky ∈ [-6. OAB. The ‘j’ bits select the Wy pre-fetch operation. SA.1 “MAC Pre-Fetches”. Advance Information DS70030E-page 5-163 . Wyd} {.B] Wx ∈ [W8.[Wy]+=ky. Post-increment W9 by 2 . Instruction Descriptions MPY Syntax: {label:} MPY Square to Accumulator Wm*Wm. 4. -4. [W9]+=2. Wxd. CORCON = 0x0000 (fractional multiply. -2. Wxd} {. 4.[Wy].[W9+W12]. Words: Cycles: Example 1 1 1 MPY W6*W6.[Wx]-=kx.[Wx]+=kx. OB.[W11+W12]. Wyd} Operands: Wm*Wm ∈ [W4*W4. 2.[Wy]-=ky.[Wx].. Wxd} {. W9]. Note: The IF bit. SAB 1111 00mm A0xx yyii iijj jj01 Operation: Status Affected: Encoding: Description: Square the contents of a working register. (Wy)+ky→Wy OA. kx ∈ [-6. -4. The ‘y’ bits select the pre-fetch Wyd destination. Square W6 and store to ACCA .

W5 . CORCON = 0x0000 (fractional multiply. Fetch [W10] to W5. [W10]+=2. B. Post-increment W10 by 2 . W4. Fetch [W9+W12] to W4 . . Square W4 and store to ACCB . [W9+W12].dsPIC30F Programmer’s Reference Manual Example 2 MPY W4*W4. no saturation) W4 W5 W9 W10 W12 ACCB Data 1600 Data 1B00 CORCON SR Before Instruction E228 9000 1700 1B00 FF00 00 9834 4500 8911 F678 0000 0000 W4 W5 W9 W10 W12 ACCB Data 1600 Data 1B00 CORCON SR After Instruction 8911 F678 1700 1B02 FF00 00 06F5 4C80 8911 F678 0000 0000 DS70030E-page 5-164 Advance Information  2003 Microchip Technology Inc.

2. Advance Information DS70030E-page 5-165 . 6]. W7] -(Wm)*(Wn) → Acc(A or B) ([Wx])→ Wxd. Wyd ∈ [W4 .. The ‘y’ bits select the pre-fetch Wyd destination. -4. Acc {. W4*W7. ky ∈ [-6.N W4*W5. Words: Cycles: Example 1 1 1 MPY. 2. OB. Wxd} {. Wyd} {. 6]. Post-increment W8 by 2 .[Wx]-=kx. 4.[W9+W12]. [W10]+=2. determines if the multiply is fractional or an integer.[Wy]. The ‘A’ bit selects the accumulator for the result. kx ∈ [-6.[Wy]-=ky. The 32-bit result of the signed multiply is sign-extended to 40-bits and stored to the specified accumulator.[Wy]+=ky. Wyd} {.[Wx]+=kx.. CORCON<0>. no saturation) W4 W5 W8 W10 ACCA Data 0B00 Data 2000 CORCON SR Before Instruction 3023 1290 0B00 2000 00 0000 2387 0054 660A 0001 0000 W4 W5 W8 W10 ACCA Data 0B00 Data 2000 CORCON SR After Instruction 0054 660A 0B02 2002 FF FC82 7650 0054 660A 0001 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. The ‘x’ bits select the pre-fetch Wxd destination. The ‘j’ bits select the Wy pre-fetch operation. Instruction Descriptions MPY. A. The ‘i’ bits select the Wx pre-fetch operation. CORCON = 0x0001 (integer multiply. W11]. W5*W6. Wyd} {. W9]. Post-increment W10 by 2 . Wxd} {. (Wx)+kx→Wx ([Wy])→ Wyd. [W8]+=2. Wyd} Operands: Wm*Wn ∈ [W4*W5. -4. (Wy)+ky→Wy OA.. W4*W6. -2. W4. OAB 1100 0mmm A1xx yyii iijj jj11 Operation: Status Affected: Encoding: Description: Multiply the contents of a working register by the negative of the contents of another working register. Multiply W4*W5.N Syntax: {label:} MPY. Fetch [W10] to W5. W5 . negate the result and store to ACCA . Note: The IF bit. 4. optionally pre-fetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. Wxd} {.B] Wx ∈ [W8. Wxd} {. W7] Wy ∈ [W10.[Wx]. The ‘m’ bits select the operand registers Wm and Wn for the multiply. Wxd ∈ [W4 . Fetch [W8] to W4.N Multiply -Wm by Wn to Accumulator Wm*Wn. W6*W7] Acc ∈ [A.[W11+W12]..Section 5. W5*W7. -2.

no saturation) W4 W5 W8 W10 ACCA Data 0B00 Data 2000 CORCON SR Before Instruction 3023 1290 0B00 2000 00 0000 2387 0054 660A 0000 0000 W4 W5 W8 W10 ACCA Data 0B00 Data 2000 CORCON SR After Instruction 0054 660A 0B02 2002 FF F904 ECA0 0054 660A 0000 0000 DS70030E-page 5-166 Advance Information  2003 Microchip Technology Inc. Fetch [W10] to W5. W5 . negate the result and store to ACCA .N W4*W5. . W4. Fetch [W8] to W4. Post-increment W8 by 2 . CORCON = 0x0000 (fractional multiply. A.dsPIC30F Programmer’s Reference Manual Example 2 MPY. [W8]+=2. [W10]+=2. Multiply W4*W5. Post-increment W10 by 2 .

-2. W4*W6.. Wxd} {.[W9+W12]. kx ∈ [-6.AWB} {. Advance Information DS70030E-page 5-167 . W5*W7. -4. determines if the multiply is fractional or an integer.[Wy]+=ky. Words: Cycles: 1 1 5 Instruction Descriptions  2003 Microchip Technology Inc. The ‘y’ bits select the pre-fetch Wyd destination. 2. ky ∈ [-6. Wxd} {. Wyd} {. The ‘m’ bits select the operand registers Wm and Wn for the multiply. [W13]+=2] (Acc(A or B)) − (Wm)*(Wn) → Acc(A or B) ([Wx])→ Wxd. Wxd ∈ [W4 . SB. W6*W7] Acc ∈ [A.. The ‘A’ bit selects the accumulator for the result. Wyd} {. OB.. 4.14.1 “MAC Pre-Fetches”. SA.[Wx]-=kx. Wyd} {.4 “MAC Write Back”. 6]. Wxd} {. The ‘j’ bits select the Wy pre-fetch operation. -2. Acc {. The ‘a’ bits select the accumulator write back destination. CORCON<0>.[Wy]-=ky. W7] AWB ∈ [W13. The ‘x’ bits select the pre-fetch Wxd destination. Operand AWB specifies the optional store of the “other” accumulator as described in Section 4. 4. -4.[Wx]+=kx.[W11+W12]. Wy and Wyd specify optional pre-fetch operations which support indirect and register offset addressing as described in Section 4. OAB. Wxd} {. SAB 1100 0mmm A1xx yyii iijj jjaa Operation: Status Affected: Encoding: Description: Multiply the contents of two working registers.Section 5. Wyd} Operands: Wm*Wn ∈ [W4*W5. optionally pre-fetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. Note: The IF bit. Operands Wx. W11]. 2. W5*W6.. W4*W7. The ‘i’ bits select the Wx pre-fetch operation.14. Wxd. 6].[Wy]. (Wy)+ky→Wy (Acc(B or A)) rounded → AWB OA. W7] Wy ∈ [W10.[Wx]. Wyd ∈ [W4 . Instruction Descriptions MSC Syntax: {label:} MSC Multiply and Subtract from Accumulator Wm*Wn.B] Wx ∈ [W8. The 32-bit result of the signed multiply is sign-extended to 40-bits and subtracted from the specified accumulator. W9]. (Wx)+kx→Wx ([Wy])→ Wyd.

Post-decrement W8 by 4 . Write Back ACCB to W13 . no saturation) W4 W5 W11 W12 W13 ACCA ACCB Data 2000 CORCON SR Before Instruction 0500 2000 1800 0800 6233 00 3738 5ED0 00 1000 0000 3579 0000 0000 W4 W5 W11 W12 W13 ACCA ACCB Data 2000 CORCON SR After Instruction 0500 3579 1800 0800 3738 00 3738 5ED0 00 0EC0 0000 3579 0000 0000 DS70030E-page 5-168 Advance Information  2003 Microchip Technology Inc. W6. . [W11+W12]. [W8]-=4. Fetch [W11+W12] to W5 . A. CORCON = 0x0000 (fractional multiply. no saturation) W6 W7 W8 W10 ACCA Data 0C00 Data 1C00 CORCON SR Example 2 Before Instruction 9051 7230 0C00 1C00 00 0567 8000 D309 100B 0001 0000 W6 W7 W8 W10 ACCA Data 0C00 Data 1C00 CORCON SR After Instruction D309 100B 0BFC 1BFC 00 3738 5ED0 D309 100B 0001 0000 MSC W4*W5. [W10]-=4. W5. Multiply W4*W5 and subtract the result from ACCA .dsPIC30F Programmer’s Reference Manual Example 1 MSC W6*W7. Multiply W6*W7 and subtract the result from ACCA . B. Post-decrement W10 by 4 . W7 . W13 . Fetch [W8] to W6. Fetch [W10] to W7. CORCON = 0x0001 (integer multiply.

. the 16-bit result is stored in W2. the Most Significant Word of the 32-bit result is stored in W3. Multiply (0x800)*WREG (Byte mode) Before Instruction WREG (W0) 9823 W2 FFFF W3 FFFF Data 0800 2690 SR 0000 Example 2 MUL TMR1 After Instruction WREG (W0) 9823 W2 13B0 W3 FFFF Data 0800 2690 SR 0000 . 1 for byte). 3: The IF bit. CORCON<0>. Instruction Descriptions MUL Syntax: Operands: Operation: {label:} Integer Unsigned Multiply f and WREG MUL{. has no effect on this operation.B 0x800 . 4: This is the only instruction which provides for an 8-bit multiply. You may use a . and the Least Significant Word of the 32-bit result is stored in W2.B} f f ∈ [0 . 2: The WREG is set to working register W0. Note 1: The extension .Section 5. 8191] For byte operation: (WREG)<7:0> * (f)<7:0> → W2 For word operation: (WREG) * (f) → W2:W3 None 1011 1100 0B0f ffff ffff ffff Status Affected: Encoding: Description: Multiply the default working register WREG with the specified file register and place the result in the W2:W3 register pair. but it is not required. In Word mode.W extension to denote a word operation. If this instruction is executed in Byte mode. The ‘f’ bits select the address of the file register. Words: Cycles: Example 1 1 1 MUL.B in the instruction denotes a byte operation rather than a word operation. Advance Information DS70030E-page 5-169 . Both operands and the result are interpreted as unsigned integers. Multiply (TMR1)*WREG (Word mode) Before Instruction WREG (W0) F001 W2 0000 W3 0000 TMR1 3287 SR 0000 After Instruction WREG (W0) F001 W2 C287 W3 2F5E TMR1 3287 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. The ‘B’ bit selects byte or word operation (0 for word..

2: Since the product of the multiplication is 32-bits. Note 1: This instruction operates in Word mode only.SS W0. W15] Wnd ∈ [W0. has no effect on this operation. W12 . [Ws++].. [Ws]. Register direct addressing must be used for Wb and Wnd. Both source operands and the result Wnd are interpreted as two’s complement signed integers. CORCON<0>. The ‘w’ bits select the address of the base register. . Multiply W0*W1 . 4: The IF bit. See Figure 4-2 for information on how double-words are aligned in memory.SS Wb. W15] Ws ∈ [W0 . [--Ws]. since W15<0> is fixed to zero.. W1.dsPIC30F Programmer’s Reference Manual MUL. Words: Cycles: Example 1 1 1 MUL. [Ws--]. Ws.. The ‘d’ bits select the address of the lower destination register. W2. The ‘p’ bits select the source Address mode. and the Most Significant Word of the result is stored in Wnd+1. 3: Wnd may not be W14.SS Syntax: {label:} Integer 16x16-bit Signed Multiply MUL. The ‘s’ bits select the address of the source register. The Least Significant Word of the result is stored in Wnd (which must be an even numbered working register).. Wnd Operands: Wb ∈ [W0 .. Store the result to W12:W13 Before Instruction W0 9823 W1 67DC W12 FFFF W13 FFFF SR 0000 After Instruction W0 9823 W1 67DC W12 D314 W13 D5DC SR 0000 DS70030E-page 5-170 Advance Information  2003 Microchip Technology Inc.. W12] signed (Wb) * signed (Ws) → Wnd:Wnd+1 None 1011 1001 1www wddd dppp ssss Operation: Status Affected: Encoding: Description: Multiply the contents of Wb with the contents of Ws. and store the 32-bit result in two successive working registers. Wnd must be an even working register. Register direct or register indirect addressing may be used for Ws. [++Ws]. W4 .

SS W2. W0 . Instruction Descriptions Example 2 MUL.Section 5. Advance Information DS70030E-page 5-171 . Pre-decrement W4 . Multiply W2*[W4] . [--W4]. Store the result to W0:W1 Before Instruction W0 FFFF W1 FFFF W2 0045 W4 27FE Data 27FC 0098 SR 0000 After Instruction W0 28F8 W1 0000 W2 0045 W4 27FC Data 27FC 0098 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.

.. The Wb operand and the result Wnd are interpreted as a two’s complement signed integer. and store the 32-bit result in two successive working registers. W2. Store the result to W2:W3 Before Instruction W0 C000 W2 1234 W3 C9BA SR 0000 After Instruction W0 C000 W2 4000 W3 FFF8 SR 0000 DS70030E-page 5-172 Advance Information  2003 Microchip Technology Inc. and the Most Significant Word of the result is stored in Wnd+1. Wnd must be an even working register. CORCON<0>. The literal is interpreted as an unsigned integer. 4: The IF bit.SU Syntax: Operands: {label:} Integer 16x16-bit Signed-Unsigned Short Literal Multiply MUL. W2 . 31] Wnd ∈ [W0. Words: Cycles: Example 1 1 1 MUL. . since W15<0> is fixed to zero.dsPIC30F Programmer’s Reference Manual MUL. W15] lit5 ∈ [0 . W4 . The Least Significant Word of the result is stored in Wnd (which must be an even numbered working register). The ‘w’ bits select the address of the base register.. 3: Wnd may not be W14.. Note 1: This instruction operates in Word mode only. #0x1F.SU Wb.. See Figure 4-2 for information on how double-words are aligned in memory. has no effect on this operation. The ‘k’ bits define a 5-bit unsigned integer literal.. Multiply W0 by literal 0x1F . W12] signed (Wb) * unsigned lit5 → Wnd:Wnd+1 None 1011 1001 0www wddd d11k kkkk Operation: Status Affected: Encoding: Description: Multiply the contents of Wb with the 5-bit literal. Wnd Wb ∈ [W0 . 2: Since the product of the multiplication is 32-bits. #lit5.SU W0. The ‘d’ bits select the address of the lower destination register. Register direct addressing must be used for Wb and Wnd.

SU W2. Advance Information DS70030E-page 5-173 . W0 . #0x10. Store the result to W0:W1 Before Instruction W0 ABCD W1 89B3 W2 F240 SR 0000 After Instruction W0 2400 W1 000F W2 F240 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Instruction Descriptions Example 2 MUL.Section 5. Multiply W2 by literal 0x10 .

The Ws operand is interpreted as an unsigned integer. The Wb operand and the result Wnd are interpreted as a two’s complement signed integer. W4 . [Ws++].SU Syntax: {label:} Integer 16x16-bit Signed-Unsigned Multiply MUL.. [Ws--]. [W9]. Store the result to W0:W1 Before Instruction W0 68DC W1 AA40 W8 F000 W9 178C Data 178C F000 SR 0000 After Instruction W0 0000 W1 F100 W8 F000 W9 178C Data 178C F000 SR 0000 DS70030E-page 5-174 Advance Information  2003 Microchip Technology Inc. The ‘s’ bits select the address of the source register. CORCON<0>. Register direct addressing must be used for Wb and Wnd. Wnd must be an even working register. . Wnd Operands: Wb ∈ [W0 .. [++Ws]. The ‘p’ bits select the source Address mode. 4: The IF bit. The Least Significant Word of the result is stored in Wnd (which must be an even numbered working register). See Figure 4-2 for information on how double-words are aligned in memory. The ‘d’ bits select the address of the lower destination register. W15] Ws ∈ [W0 .. The ‘w’ bits select the address of the base register... Words: Cycles: Example 1 1 1 MUL. [Ws]. Note 1: This instruction operates in Word mode only. W2. and store the 32-bit result in two successive working registers. W12] signed (Wb) * unsigned (Ws) → Wnd:Wnd+1 None 1011 1001 0www wddd dppp ssss Operation: Status Affected: Encoding: Description: Multiply the contents of Wb with the contents of Ws. [--Ws]. and the Most Significant Word of the result is stored in Wnd+1. since W15<0> is fixed to zero. 2: Since the product of the multiplication is 32-bits. W15] Wnd ∈ [W0. 3: Wnd may not be W14. Ws. has no effect on this operation.SU Wb. Multiply W8*[W9] . W0 .dsPIC30F Programmer’s Reference Manual MUL..SU W8. Register direct or register indirect addressing may be used for Ws.

Pre-Increment W3 . Store the result to W4:W5 Before Instruction W2 0040 W3 0280 W4 1819 W5 2021 Data 0282 0068 SR 0000 After Instruction W2 0040 W3 0282 W4 1A00 W5 0000 Data 0282 0068 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Instruction Descriptions Example 2 MUL. Advance Information DS70030E-page 5-175 . W4 .Section 5.SU W2. [++W3]. Multiply W2*[W3] .

The ‘p’ bits select the source Address mode. W15] Wnd ∈ [W0. Wnd Operands: Wb ∈ [W0 . The ‘w’ bits select the address of the base register.US Syntax: {label:} Integer 16x16-bit Unsigned-Signed Multiply MUL. [Ws].. The ‘s’ bits select the address of the source register. 4: The IF bit. The ‘d’ bits select the address of the lower destination register.. Note 1: This instruction operates in Word mode only. [Ws++]. W2 .. and the Most Significant Word of the result is stored in Wnd+1.dsPIC30F Programmer’s Reference Manual MUL.. Ws. Wnd must be an even working register. has no effect on this operation. Register direct or register indirect addressing may be used for Ws. [Ws--]. Register direct addressing must be used for Wb and Wnd. [W1]. Multiply W0*[W1] (unsigned-signed) . CORCON<0>. W12] unsigned (Wb) * signed (Ws) → Wnd:Wnd+1 None 1011 1000 1www wddd dppp ssss Operation: Status Affected: Encoding: Description: Multiply the contents of Wb with the contents of Ws. [--Ws].US W0. W4 .US Wb. The Ws operand and the result Wnd are interpreted as a two’s complement signed integer. Words: Cycles: Example 1 1 1 MUL. 3: Wnd may not be W14.. See Figure 4-2 for information on how double-words are aligned in memory. 2: Since the product of the multiplication is 32-bits. and store the 32-bit result in two successive working registers. [++Ws]. Store the result to W2:W3 Before Instruction W0 C000 W1 2300 W2 00DA W3 CC25 Data 2300 F000 SR 0000 After Instruction W0 C000 W1 2300 W2 0000 W3 F400 Data 2300 F000 SR 0000 DS70030E-page 5-176 Advance Information  2003 Microchip Technology Inc. W15] Ws ∈ [W0 . The Wb operand is interpreted as an unsigned integer. . The Least Significant Word of the result is stored in Wnd (which must be an even numbered working register). since W15<0> is fixed to zero. W2..

Advance Information DS70030E-page 5-177 . Mult. W6*[W5] (unsigned-signed) . Store the result to W10:W11 .Section 5. Instruction Descriptions Example 2 MUL.US W6. Post-Increment W5 Before Instruction W5 0C00 W6 FFFF W10 0908 W11 6EEB Data 0C00 7FFF SR 0000 After Instruction W5 0C02 W6 FFFF W10 8001 W11 7FFE Data 0C00 7FFF SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. W10 . [W5++].

The ‘w’ bits select the address of the base register. W12] unsigned (Wb) * unsigned lit5 → Wnd:Wnd+1 None 1011 1000 0www wddd d11k kkkk Operation: Status Affected: Encoding: Description: Multiply the contents of Wb with the 5-bit literal. Multiply W0 by literal 0xF . . and the Most Significant Word of the result is stored in Wnd+1. See Figure 4-2 for information on how double-words are aligned in memory.. 31] Wnd ∈ [W0.. W15] lit5 ∈ [0 . Multiply W7 by literal 0x1F .. Words: Cycles: Example 1 1 1 MUL. W4 . Store the result to W12:W13 Before Instruction W0 2323 W12 4512 W13 7821 SR 0000 Example 2 MUL.UU W0. 4: The IF bit.UU Syntax: Operands: {label:} Integer 16x16-bit Unsigned Short Literal Multiply MUL. W12 . #lit5. CORCON<0>. since W15<0> is fixed to zero. Note 1: This instruction operates in Word mode only. 3: Wnd may not be W14. Wnd must be an even working register. Register direct addressing must be used for Wb and Wnd. Both operands and the result are interpreted as unsigned integers.UU After Instruction W0 2323 W12 0F0D W13 0002 SR 0000 . The ‘k’ bits define a 5-bit unsigned integer literal. W2. and store the 32-bit result in two successive working registers.dsPIC30F Programmer’s Reference Manual MUL. W0 Before Instruction W0 780B W1 3805 W7 F240 SR 0000 After Instruction W0 55C0 W1 001D W7 F240 SR 0000 DS70030E-page 5-178 Advance Information  2003 Microchip Technology Inc.. 2: Since the product of the multiplication is 32-bits. #0xF. Store the result to W0:W1 W7. The ‘d’ bits select the address of the lower destination register.UU Wb. #0x1F... Wnd Wb ∈ [W0 . The Least Significant Word of the result is stored in Wnd (which must be an even numbered working register). has no effect on this operation.

W2. The ‘d’ bits select the address of the lower destination register. and store the 32-bit result in two successive working registers. The ‘w’ bits select the address of the base register. Words: Cycles: Example 1 1 1 MUL. Both source operands and the result are interpreted as unsigned integers. W12] unsigned (Wb) * unsigned (Ws) → Wnd:Wnd+1 None 1011 1000 0www wddd dppp ssss Operation: Status Affected: Encoding: Description: Multiply the contents of Wb with the contents of Ws. W15] Wnd ∈ [W0. The ‘p’ bits select the source Address mode. [Ws--]. [++Ws]. See Figure 4-2 for information on how double-words are aligned in memory. 2: Since the product of the multiplication is 32-bits. since W15<0> is fixed to zero. W0. Note 1: This instruction operates in Word mode only. CORCON<0>.UU Wb... Register direct or indirect addressing may be used for Ws. Ws. and the most Significant Word of the result is stored in Wnd+1.... 3: Wnd may not be W14. W4 . Wnd Operands: Wb ∈ [W0 . Advance Information DS70030E-page 5-179 . Instruction Descriptions MUL.UU Syntax: {label:} Integer 16x16-bit Unsigned Multiply MUL.. [Ws]. W15] Ws ∈ [W0 . W2 .UU W4. [--Ws]. Wnd must be an even working register. The least Significant Word of the result is stored in Wnd (which must be an even numbered working register). has no effect on this operation. [Ws++]. Register direct addressing must be used for Wb and Wnd. Store the result to W2:W3 Before Instruction W0 FFFF W2 2300 W3 00DA W4 FFFF SR 0000 After Instruction W0 FFFF W2 0001 W3 FFFE W4 FFFF SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.Section 5. 4: The IF bit. Multiply W4*W0 (unsigned-unsigned) . The ‘s’ bits select the address of the source register.

W4 . . Mult. [W1++]. Post-Increment W1 Before Instruction W0 1024 W1 2300 W4 9654 W5 BDBC Data 2300 D625 SR 0000 After Instruction W0 1024 W1 2302 W4 6D34 W5 0D80 Data 2300 D625 SR 0000 DS70030E-page 5-180 Advance Information  2003 Microchip Technology Inc.UU W0.dsPIC30F Programmer’s Reference Manual Example 2 MUL. W0*[W1] (unsigned-unsigned) . Store the result to W4:W5 .

Note 1: The extension . but it is not required. N. The ‘B’ bit selects byte or word operation (0 for word.Section 5. The ‘D’ bit selects the destination (0 for WREG. Instruction Descriptions NEG Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Negate f NEG{. The ‘f’ bits select the address of the file register. If WREG is not specified.W extension to denote a word operation. The optional WREG operand determines the destination register.. Advance Information DS70030E-page 5-181 . the result is stored in WREG. Negate (0x880) (Byte mode) . Z. 1 for byte).WREG} f ∈ [0 . 8191] (f) + 1 → destination designated by D DC.B in the instruction denotes a byte operation rather than a word operation.B} f {. Store result to WREG Before Instruction WREG (W0) 9080 Data 0880 2355 SR 0000 Example 2 NEG 0x1200 After Instruction WREG (W0) 90AB Data 0880 2355 SR 0008 (N=1) . the result is stored in the file register.B 0x880. Negate (0x1200) (Word mode) Before Instruction Data 1200 8923 SR 0000 After Instruction Data 1200 76DD SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. WREG . 2: The WREG is set to working register W0. If WREG is specified. Words: Cycles: Example 1 1 1 NEG. 1 for file register). You may use a . C 1110 1110 0BDf ffff ffff ffff Compute the 2’s complement of the contents of the file register and place the result in the destination register. OV..

[Ws]. but it is not required. 1 for byte). [++Ws]. . W15] Wd ∈ [W0 . You may use a . Pre-decrement W4 (Word mode) . Note: The extension . W15] (Ws) + 1 → Wd a`I=kI=lsI=wI=` 1110 1010 0Bqq qddd dppp ssss Compute the 2’s complement of the contents of the source register Ws and place the result in the destination register Wd. [Ws--].B 1 1 W3.B} Ws.W extension to denote a word operation.dsPIC30F Programmer’s Reference Manual NEG Syntax: {label:} Negate Ws NEG{. The ‘q’ bits select the destination Address mode. [Ws++].. [--Ws]. Either register direct or indirect addressing may be used for both Ws and Wd. [--W4] Before Instruction W2 0900 W4 1002 Data 0900 870F Data 1000 5105 SR 0000 After Instruction W2 0902 W4 1000 Data 0900 870F Data 1000 78F1 SR 0000 DS70030E-page 5-182 Advance Information  2003 Microchip Technology Inc. The ‘d’ bits select the address of the destination register. The ‘B’ bit selects byte or word operation (0 for word. The ‘p’ bits select the source Address mode. Negate W3 and store to [W4] (Byte mode) .. Post-increment W2 [W2++]. Negate [W2] and store to [W4] .. Post-increment W4 Before Instruction W3 7839 W4 1005 Data 1004 2355 SR 0000 Example 2 NEG After Instruction W3 7839 W4 1006 Data 1004 C755 SR 0008 (N=1) . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 . Words: Cycles: Example 1 NEG.B in the instruction denotes a byte operation rather than a word operation. The ‘s’ bits select the address of the source register.. [W4++] .

Store result to ACCA . SA. OB. Status Affected: Encoding: Description: Words: Cycles: Example 1 NEG 1 1 A . SB. Negate ACCB . SAB 1100 1011 A001 0000 0000 0000 Compute the 2’s complement of the contents of the specified accumulator. Instruction Descriptions NEG Syntax: Operands: Operation: {label:} Acc ∈ [A. Regardless of the Saturation mode. Store result to ACCB . The ‘A’ bit specifies the selected accumulator. this instruction operates on all 40-bits of the accumulator. OAB. CORCON = 0x00C0 (normal saturation) ACCB CORCON SR Before Instruction FF F230 10DC 00C0 0000 ACCB CORCON SR After Instruction 00 0DCF EF24 00C0 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.B] Negate Accumulator NEG Acc If (Acc = A): -ACCA → ACCA Else: -ACCB → ACCB OA. CORCON = 0x0000 (no saturation) ACCA CORCON SR Example 2 NEG Before Instruction 00 3290 59C8 0000 0000 B ACCA CORCON SR After Instruction FF CD6F A638 0000 0000 . Negate ACCA . Advance Information DS70030E-page 5-183 .Section 5.

execute no operation PC SR Before Instruction 00 08AE 0000 After Instruction PC 00 08B0 SR 0000 DS70030E-page 5-184 Advance Information  2003 Microchip Technology Inc. . The ‘x’ bits can take any value.dsPIC30F Programmer’s Reference Manual NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} None No Operation NOP No Operation None 0000 0000 xxxx xxxx xxxx xxxx No Operation is performed. execute no operation PC SR Example 2 Before Instruction 00 1092 0000 After Instruction PC 00 1094 SR 0000 NOP . Words: Cycles: Example 1 NOP 1 1 .

execute no operation PC SR Before Instruction 00 1466 0000 After Instruction PC 00 1468 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. execute no operation PC SR Example 2 Before Instruction 00 2430 0000 After Instruction PC 00 2432 SR 0000 NOPR . Instruction Descriptions NOPR Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} None No Operation NOPR No Operation None 1111 1111 xxxx xxxx xxxx xxxx No Operation is performed.Section 5. Words: Cycles: Example 1 1 1 NOPR . The ‘x’ bits can take any value. Advance Information DS70030E-page 5-185 .

Pop TOS to 0x1230 Before Instruction W15 1006 Data 1004 A401 Data 1230 2355 SR 0000 Example 2 POP 0x880 After Instruction W15 1004 Data 1004 A401 Data 1230 A401 SR 0000 .dsPIC30F Programmer’s Reference Manual POP Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Pop TOS to f POP f f ∈ [0 . . which may reside anywhere in the lower 32K words of data memory. Pop TOS to 0x880 Before Instruction W15 2000 Data 0880 E3E1 Data 1FFE A090 SR 0000 After Instruction W15 1FFE Data 0880 A090 Data 1FFE A090 SR 0000 DS70030E-page 5-186 Advance Information  2003 Microchip Technology Inc.. Words: Cycles: Example 1 POP 1 1 0x1230 . 65534] (W15)-2 → W15 (TOS) → f None 1111 1001 ffff ffff ffff fff0 The stack pointer (W15) is pre-decremented by 2 and the Top-of-Stack (TOS) word is written to the specified file register. The ‘f’ bits select the address of the file register. Note 1: This instruction operates in Word mode only. 2: The file register address must be word aligned..

W15] (W15)-2 → W15 (TOS) → Wd None 0111 1www w0hh hddd d100 1111 The stack pointer (W15) is pre-decremented by 2 and the Top-of-Stack (TOS) word is written to Wd. Note 1: This instruction operates in Word mode only. The ‘d’ bits select the address of the destination register.. Wd” instruction (MOV [--W15]. The ‘h’ bits select the destination Address mode.. It reverse assembles as MOV. Instruction Descriptions POP Syntax: {label:} Pop TOS to Wd POP Wd [Wd] [Wd++] [Wd--] [--Wd] [++Wd] [Wd+Wb] Operands: Operation: Status Affected: Encoding: Description: Wd ∈ [W0 . Wd). Either register direct or indirect addressing may be used for Wd. Words: Cycles: Example 1 POP 1 1 W4 . W15] Wb ∈ [W0 . Advance Information DS70030E-page 5-187 .. Pop TOS to [W10] Before Instruction W10 0E02 W15 1766 Data 0E04 E3E1 Data 1764 C7B5 SR 0000 After Instruction W10 0E04 W15 1764 Data 0E04 C7B5 Data 1764 C7B5 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Pre-increment W10 .. Pop TOS to W4 Before Instruction W4 EDA8 W15 1008 Data 1006 C45A SR 0000 Example 2 POP [++W10] After Instruction W4 C45A W15 1006 Data 1006 C45A SR 0000 . The ‘w’ bits define the offset register Wb. 2: This instruction is a specific version of the “MOV Ws.Section 5.

Double pop TOS to W0 Before Instruction W0 673E W1 DD23 W15 0BBC Data 0BB8 791C Data 0BBA D400 SR 0000 After Instruction W0 791C W1 D400 W15 0BB8 Data 0BB8 791C Data 0BBA D400 SR 0000 DS70030E-page 5-188 Advance Information  2003 Microchip Technology Inc.D Syntax: Operands: Operation: {label:} Double Pop TOS to Wnd:Wnd+1 POP.D W6 . 2: Wnd must be an even working register. W14] (W15)-2 → W15 (TOS) → Wnd+1 (W15)-2 → W15 (TOS) → Wnd None 1011 1110 0000 0ddd 0100 1111 Status Affected: Encoding: Description: A double-word is popped from the Top-of-Stack (TOS) and stored to Wnd:Wnd+1. See Figure 4-2 for information on how double-words are aligned in memory. Wnd” instruction (MOV. the stack pointer (W15) gets decremented by 4. W2. 3: This instruction is a specific version of the “MOV.. and the Least Significant Word is stored to Wnd. Since a double-word is popped. Note 1: This instruction operates on double-words.D Ws.D W0 After Instruction W6 3210 W7 7654 W15 084C Data 084C 3210 Data 084E 7654 SR 0000 .D [--W15].D Wnd Wnd ∈ [W0. The ‘d’ bits select the address of the destination register pair. . The Most Significant Word is stored to Wnd+1. W4.dsPIC30F Programmer’s Reference Manual POP. Wnd).D. . It reverse assembles as MOV. Double pop TOS to W6 Before Instruction W6 07BB W7 89AE W15 0850 Data 084C 3210 Data 084E 7654 SR 0000 Example 2 POP.. Words: Cycles: Example 1 1 2 POP.

OV.Section 5. The following registers are affected: W0-W3. Z. C=1) After instruction execution. They may only be accessed with PUSH. Z. (See PUSH. Note 1: The shadow registers are not directly accessible. 5 Instruction Descriptions  2003 Microchip Technology Inc. C 1111 1110 1000 0000 0000 0000 The values in the shadow registers are copied into their respective primary registers. OV. 2: The shadow registers are only one-level deep. contents of shadow registers are NOT modified.S Pop shadow registers DC.S Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} None Pop Shadow Registers POP. Words: Cycles: Example 1 1 1 POP. N.S Example 1 for contents of shadows) Before Instruction W0 07BB W1 03FD W2 9610 W3 7249 SR 00E0 (IPL=7) Note: After Instruction W0 0000 W1 1000 W2 2000 W3 3000 SR 00E1 (IPL=7.S and POP. Pop the shadow registers .S . Advance Information DS70030E-page 5-189 . N and DC Status register flags.S. and the C. Instruction Descriptions POP.

2: The file register address must be word aligned. 65534] (f) → (TOS) (W15)+2 → W15 None 1111 1000 ffff ffff ffff fff0 The contents of the specified file register are written to the Top-of-Stack (TOS) location and then the stack pointer (W15) is incremented by 2..dsPIC30F Programmer’s Reference Manual PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Push f to TOS PUSH f f ∈ [0 . Note 1: This instruction operates in Word mode only. The ‘f’ bits select the address of the file register. Words: Cycles: Example 1 PUSH 1 1 0x2004 . Push (0x2004) to TOS Before Instruction W15 0B00 Data 0B00 791C Data 2004 D400 SR 0000 Example 2 PUSH 0xC0E After Instruction W15 0B02 Data 0B00 D400 Data 2004 D400 SR 0000 . Push (0xC0E) to TOS Before Instruction W15 0920 Data 0920 0000 Data 0C0E 67AA SR 0000 After Instruction W15 0922 Data 0920 67AA Data 2004 67AA SR 0000 DS70030E-page 5-190 Advance Information  2003 Microchip Technology Inc. . The file register may reside anywhere in the lower 32K words of data memory..

[W15++]).Section 5. Push [W5+W10] to TOS Before Instruction W5 1200 W10 0044 W15 0806 Data 0806 216F Data 1244 B20A SR 0000 After Instruction W5 1200 W10 0044 W15 0808 Data 0806 B20A Data 1244 B20A SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Advance Information DS70030E-page 5-191 . Note 1: This instruction operates in Word mode only. 2: This instruction is a specific version of the “MOV Ws. The ‘s’ bits select the address of the source register. W15] (Ws) → (TOS) (W15)+2 → W15 None 0111 1www w001 1111 1ggg ssss The contents of Ws are written to the Top-of-Stack (TOS) location and then the stack pointer (W15) is incremented by 2.. W15] Wb ∈ [W0 . The ‘w’ bits define the offset register Wb. Instruction Descriptions PUSH Syntax: {label:} Push Ws to TOS PUSH Ws [Ws] [Ws++] [Ws--] [--Ws] [++Ws] [Ws+Wb] Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 .. Wd” instruction (MOV Ws. Words: Cycles: Example 1 PUSH 1 1 W2 . Push W2 to TOS Before Instruction W2 6889 W15 1566 Data 1566 0000 SR 0000 Example 2 PUSH [W5+W10] After Instruction W2 6889 W15 1568 Data 1566 6889 SR 0000 . The ‘g’ bits select the source Address mode.. It reverse assembles as MOV..

2: Wns must be an even working register. Push W6:W7 to TOS Before Instruction W6 C451 W7 3380 W15 1240 Data 1240 B004 Data 1242 0891 SR 0000 Example 2 PUSH. See Figure 4-2 for information on how double-words are aligned in memory. W2.. Since a double-word is pushed.D Wns Wns ∈ [W0. It reverse assembles as MOV. [W15++]).dsPIC30F Programmer’s Reference Manual PUSH. The ‘s’ bits select the address of the source register pair.. Wd” instruction (MOV. W14] (Wns) → (TOS) (W15)+2 → W15 (Wns+1) → (TOS) (W15)+2 → W15 None 1011 1110 1001 1111 1000 sss0 Status Affected: Encoding: Description: A double-word (Wns:Wns+1) is pushed to the Top-of-Stack (TOS). Words: Cycles: Example 1 1 2 PUSH. Push W10:W11 to TOS Before Instruction W10 80D3 W11 4550 W15 0C08 Data 0C08 79B5 Data 0C0A 008E SR 0000 After Instruction W10 80D3 W11 4550 W15 0C0C Data 0C08 80D3 Data 0C0A 4550 SR 0000 DS70030E-page 5-192 Advance Information  2003 Microchip Technology Inc. and the Most Significant word (Wns+1) is pushed to the TOS last. The Least Significant word (Wns) is pushed to the TOS first.D Wns.D. . W4 .D Syntax: Operands: Operation: {label:} Double Push Wns:Wns+1 to TOS PUSH.D W10 After Instruction W6 C451 W7 3380 W15 1244 Data 1240 C451 Data 1242 3380 SR 0000 . Note 1: This instruction operates on double-words.D Wns.D W6 . 3: This instruction is a specific version of the “MOV. the stack pointer (W15) gets incremented by 4.

N and DC Status register flags. The following registers are shadowed: W0-W3. Instruction Descriptions PUSH. contents of the shadow registers are updated. 5 Instruction Descriptions  2003 Microchip Technology Inc. Z.S. OV. and the C. Note 1: The shadow registers are not directly accessible. 2: The shadow registers are only one-level deep.S . Words: Cycles: Example 1 1 1 PUSH. Advance Information DS70030E-page 5-193 . Push primary registers into shadow registers Before Instruction W0 0000 W1 1000 W2 2000 W3 3000 SR 0001 (C=1) Note: After Instruction W0 0000 W1 1000 W2 2000 W3 3000 SR 0001 (C=1) After an instruction execution.S Push shadow registers None 1111 1110 1010 0000 0000 0000 The contents of the primary registers are copied into their respective shadow registers.Section 5. They may only be accessed with PUSH.S Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} None Push Shadow Registers PUSH.S and POP.

Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 PWRSAV #0 . 4: If awakened from a Watchdog Time-out. SLEEP and IDLE flags of the Reset System and Control (RCON) register are reset. If lit1 = 0. SLEEP (RCON<3>) is set to ‘1’ and the clock source is started. it is also shutdown. . IDLE (RCON<2>) is set to ‘1’ and the clock source is applied to the CPU. the clock to the CPU and peripherals are shutdown. Enter IDLE mode Before Instruction SR 0020 (IPL=1) After Instruction SR 0020 (IPL=1) DS70030E-page 5-194 Advance Information  2003 Microchip Technology Inc. Note 1: The processor will exit from IDLE or SLEEP through an interrupt. Enter SLEEP mode Before Instruction SR 0040 (IPL=2) Example 2 PWRSAV #1 After Instruction SR 0040 (IPL=2) . but the clock source remains active and the peripherals continue to operate. If lit1 = 1. This instruction resets the Watchdog Timer Count register and the Prescaler Count registers.dsPIC30F Programmer’s Reference Manual PWRSAV Syntax: Operands: Operation: {label:} lit1 ∈ [0. See the dsPIC30F Data Sheet for details. 2: If awakened from IDLE mode. 3: If awakened from SLEEP mode. SLEEP mode is entered. the clock to the CPU shuts down.1] Enter Power Saving Mode PWRSAV #lit1 0 → WDT count register 0 → WDT prescaler A count 0 → WDT prescaler B count 0 → WDTO (RCON<4>) 0 → SLEEP (RCON<3>) 0 → IDLE (RCON<2>) If (lit1 = 0): Enter SLEEP mode Else: Enter IDLE mode None 1111 1110 0100 0000 0000 000k Place the processor into the specified Power Saving mode. If an on-chip oscillator is being used. WDTO (RCON<4>) is set to ‘1’. In addition. In IDLE mode. processor RESET or Watchdog Time-out. the WDTO. IDLE mode is entered. In SLEEP mode.

W3 ... _Task1 W0. After the return address is stacked. The ‘n’ bits are a signed literal that specifies the size of the relative call (in program words) from (PC+2). where Slit16 ∈ [-32768 .. (PC) + 2 → PC (PC<15:0>) → (TOS) (W15) + 2 → W15 (PC<22:16>) → (TOS) (W15) + 2 → W15 (PC) + (2 * Slit16) → PC NOP → Instruction Register None 0000 0111 nnnn nnnn nnnn nnnn Relative subroutine call with a range of 32K program words forward or back from the current PC.. W2. W1. Before the call is made. Expr is resolved by the linker to a Slit16.. label or expression. 007000 _Init: 007002 _Init W0. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 2 012004 012006 . 32767].. [W4++] W2 . Call _Task1 .. Note: When possible. W2 W0. Call _Init 00620E 006210 . the sign-extended 17-bit value (2 * Slit16) is added to the contents of the PC and the result is stored in the PC. . 012458 _Task1: 01245A RCALL ADD . CLR . the return address (PC+2) is pushed onto the stack... since it only consumes one word of program memory. Instruction Descriptions RCALL Syntax: Operands: Operation: {label:} Relative Call RCALL Expr Expr may be an absolute address. .. _Init subroutine 5 Instruction Descriptions PC W15 Data 0C50 Data 0C52 SR Before Instruction 00 620E 0C50 FFFF FFFF 0000 After Instruction PC 00 7000 W15 0C54 Data 0C50 6210 Data 0C52 0000 SR 0000  2003 Microchip Technology Inc. ... PC W15 Data 0810 Data 0812 SR After Instruction 01 2458 0814 2006 0001 0000 . Advance Information DS70030E-page 5-195 . SUB .. this instruction should be used instead of CALL. .. _Task1 subroutine PC W15 Data 0810 Data 0812 SR Example 2 Before Instruction 01 2004 0810 FFFF FFFF 0000 RCALL MOV .Section 5.

W15] (PC) + 2 → PC (PC<15:0>) → (TOS) (W15) + 2 → W15 (PC<22:16>) → (TOS) (W15) + 2 → W15 (PC) + (2 * (Wn)) → PC NOP → Instruction Register None 0000 0001 0010 0000 0000 ssss Computed. The ‘s’ bits select the address of the source register. [W10] .. . RCALL with W6 PC W6 W15 Data 1004 Data 1006 SR Example 2 Before Instruction 01 000A FFC0 1004 98FF 2310 0000 RCALL FF1L . . . RCALL with W2 000302 000304 ... After Instruction PC 00 FF8C W6 FFC0 W15 1008 Data 1004 000C Data 1006 0001 SR 0000 W2 W0. 000450 000452 EX2: W2 . Before the call is made. the sign-extended 17-bit value (2 * (Wn)) is added to the contents of the PC and the result is stored in the PC.. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 2 00FF8C 00FF8E .. Destination of RCALL PC W2 W15 Data 1004 Data 1006 SR Before Instruction 00 0302 00A6 1004 32BB 901A 0000 After Instruction PC 00 0450 W2 00A6 W15 1008 Data 1004 0304 Data 1006 0000 SR 0000 DS70030E-page 5-196 Advance Information  2003 Microchip Technology Inc.. After the return address is stacked.. W1 . 010008 01000A 01000C EX1: INC . . Register direct addressing must be used for Wn.. Destination of RCALL W6 W4..dsPIC30F Programmer’s Reference Manual RCALL Syntax: Operands: Operation: {label:} Computed Relative Call RCALL Wn Wn ∈ [W0 . ... RCALL MOVE W2. relative subroutine call specified by the working register Wn. . The range of the call is 32K program words forward or back from the current PC. CLR .. W3 .. the return address (PC+2) is pushed onto the stack..

Clear the scratch space 00089E 0008A0 5 Instruction Descriptions PC RCOUNT SR Before Instruction 00 089E 0000 0000 After Instruction PC 00 08A0 RCOUNT 03FF SR 0010 (RA=1)  2003 Microchip Technology Inc. PWRSAV. Note: The REPEAT and target instruction are interruptible. W1.. Execute CLR 1024 times . and then normal instruction execution continues with the instruction following the target instruction. When RCOUNT equals zero. Special Features. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 000452 000454 REPEAT #9 ADD [W0++]. The ‘k’ bits are an unsigned literal that specifies the loop count. Restrictions: 1. LNK.D. DISI. RCOUNT is decremented with each execution of the target instruction. The target REPEAT instruction can NOT be: • an instruction that changes program flow • a DO. 2. the RCOUNT register is loaded with the repeat count value specified in the instruction. Execute ADD 10 times . [W2++] .Section 5. Instruction Descriptions REPEAT Syntax: Operands: Operation: {label:} Repeat Next Instruction ‘lit14+1’ Times REPEAT #lit14 lit14 ∈ [0 . Vector update PC RCOUNT SR Example 2 Before Instruction 00 0452 0000 0000 REPEAT CLR After Instruction PC 00 0454 RCOUNT 0009 SR 0010 (RA=1) #0x3FF [W6++] . The repeated instruction (or target instruction) is held in the instruction register for all iterations and is only fetched once. When the repeat literal is ‘0’. When this instruction executes.. REPEAT or UNLK instruction • a 2-word instruction Unexpected results may occur if these target instructions are used. MOV. the target instruction is executed one more time. Advance Information DS70030E-page 5-197 . REPEAT has the effect of a NOP and the RA bit is not set. 16383] (lit14) → RCOUNT (PC)+2 → PC Enable Code Looping RA 0000 1001 00kk kkkk kkkk kkkk Repeat the instruction immediately following the REPEAT instruction (lit14 + 1) times.

REPEAT or ULNK instruction • a 2-word instruction Unexpected results may occur if these target instructions are used. The target REPEAT instruction can NOT be: • an instruction that changes program flow • a DO. W15] (Wn<13:0>) → RCOUNT (PC)+2 → PC Enable Code Looping RA 0000 1001 1000 0000 0000 ssss Repeat the instruction immediately following the REPEAT instruction (Wn<13:0>) times. . the RCOUNT register is loaded with the lower 14-bits of Wn. Note: The REPEAT and target instruction are interruptible. LNK.. The instruction to be repeated (or target instruction) is held in the instruction register for all iterations and is only fetched once. MOV. The ‘s’ bits specify the Wn register that contains the repeat count.dsPIC30F Programmer’s Reference Manual REPEAT Syntax: Operands: Operation: {label:} Repeat Next Instruction Wn+1 Times REPEAT Wn Wn ∈ [W0 .. Restrictions: 1. Execute COM (W4+1) times . When this instruction executes. the target instruction is executed one more time. Special Features. When (Wn) = 0. DISI. and then normal instruction execution continues with the instruction following the target instruction.D. When RCOUNT equals zero. RCOUNT is decremented with each execution of the target instruction. 2. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 000A26 000A28 REPEAT COM W4 [W0++]. REPEAT has the effect of a NOP and the RA bit is not set. PWRSAV. [W2++] . Vector complement PC W4 RCOUNT SR Before Instruction 00 0A26 0023 0000 0000 PC W4 RCOUNT SR After Instruction 00 0A28 0023 0023 0010 (RA=1) DS70030E-page 5-198 Advance Information  2003 Microchip Technology Inc.

Section 5. Advance Information DS70030E-page 5-199 . Decrement (0x840) PC W10 RCOUNT SR Before Instruction 00 089E 00FF 0000 0000 After Instruction PC 00 08A0 W10 00FF RCOUNT 00FF SR 0010 (RA=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. [W3++] . Execute TBLRD (W10+1) times [W2++]. Instruction Descriptions Example 2 00089E 0008A0 REPEAT TBLRDL W10 .

the location of the RESET GOTO instruction. . SAB. SB. N. RA. The SWR bit. The PC will be set to ‘0’. DA. DC.dsPIC30F Programmer’s Reference Manual RESET Syntax: Operands: Operation: {label:} None Reset RESET Force all registers that are affected by a MCLR Reset to their RESET condition. C=1) SR 0000 DS70030E-page 5-200 Advance Information  2003 Microchip Technology Inc. will be set to ‘1’ to indicate that the RESET instruction was executed. OAB. All core and peripheral registers will take their power-on value. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 00202A RESET . 1 → SWR (RCON<6>) 0 → PC OA. Z. IPL<2:0>. OV. RCON<6>. OB. SA. C 1111 1110 0000 0000 0000 0000 This instruction provides a way to execute a software RESET. Note: Refer to the dsPIC30F MCU Family Reference Manual for the power-on value of all registers. Execute software RESET PC W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 SPLIM TBLPAG PSVPAG CORCON RCON SR Before After Instruction Instruction 00 202A PC 00 0000 8901 W0 0000 08BB W1 0000 B87A W2 0000 872F W3 0000 C98A W4 0000 AAD4 W5 0000 981E W6 0000 1809 W7 0000 C341 W8 0000 90F4 W9 0000 F409 W10 0000 1700 W11 0000 1008 W12 0000 6556 W13 0000 231D W14 0000 1704 W15 0800 1800 SPLIM 0000 007F TBLPAG 0000 0001 PSVPAG 0000 00F0 CORCON 0020 (SATDW=1) 0000 RCON 0040 (SWR=1) 0021 (IPL.

Instruction Descriptions RETFIE Syntax: Operands: Operation: {label:} None Return from Interrupt RETFIE (W15)-2 → W15 (TOS<15:8>) → (SR<7:0>) (TOS<7>) → (IPL3. The stack is popped again. CORCON<3>) (TOS<6:0>) → (PC<22:16>) (W15)-2 → W15 (TOS<15:0>) → (PC<15:0>) NOP → Instruction Register IPL<3:0>. Advance Information DS70030E-page 5-201 . 2: Before RETFIE is executed.Section 5. C=1) 008050 . RA. which loads the low byte of the Status register. OV. which loads the lower 16 bits of the PC. C 0000 0110 0100 0000 0000 0000 Return from Interrupt Service Routine. C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. N. the appropriate interrupt flag must be cleared in software to avoid recursive interrupts. Return from ISR PC W15 Data 0922 Data 0924 CORCON SR Before Instruction 00 8050 0926 7008 0300 0000 0000 PC W15 Data 0922 Data 0924 CORCON SR After Instruction 00 7008 0922 7008 0300 0000 0003 (Z. Z. Note 1: Restoring IPL<3> and the low byte of the Status register restores the Interrupt Priority Level to the level before the execution was processed. Status Affected: Encoding: Description: Words: Cycles: Example 1 1 3 (2 if exception pending) 000A26 RETFIE . Return from ISR PC W15 Data 0830 Data 0832 CORCON SR Example 2 Before Instruction 00 0A26 0834 0230 8101 0001 0000 RETFIE PC W15 Data 0830 Data 0832 CORCON SR After Instruction 01 0230 0830 0230 8101 0001 0081 (IPL=4. The stack is popped. IPL<3> (CORCON<3>) and the Most Significant Byte of the PC.

Wn lit10 ∈ [0 . The software stack is popped twice to restore the PC and the signed literal is stored in Wn.B} #lit10. 1 for byte). Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 3 (2 if exception pending) 000440 RETLW.. 2: For byte operations. the literal must be specified as an unsigned value [0:255]. but it is not required. See Section 4. 1023] for word operation Wn ∈ [W0 .B #0xA. Return with 0xA in W0 PC W0 W15 Data 1984 Data 1986 SR Example 2 Before Instruction 00 0440 9846 1988 7006 0000 0000 RETLW After Instruction PC 00 7006 W0 980A W15 1984 Data 1984 7006 Data 1986 0000 SR 0000 #0x230. 255] for byte operation lit10 ∈ [0 . Since two pops are made. unsigned 10-bit literal stored in Wn. .. The ‘k’ bits specify the value of the literal. W2 . Return with 0x230 in W2 00050A PC W2 W15 Data 11FC Data 11FE SR Before Instruction 00 050A 0993 1200 7008 0001 0000 PC W2 W15 Data 11FC Data 11FE SR After Instruction 01 7008 0230 11FC 7008 0001 0000 DS70030E-page 5-202 Advance Information  2003 Microchip Technology Inc..B in the instruction denotes a byte operation rather than a word operation. W0 .dsPIC30F Programmer’s Reference Manual RETLW Syntax: Operands: {label:} Return with Literal in Wn RETLW{. the stack pointer (W15) is decremented by 4. The ‘d’ bits select the address of the destination register.W extension to denote a word operation.. You may use a .. Note 1: The extension . The ‘B’ bit selects byte or word operation (0 for word.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode.. W15] (W15)-2 → W15 (TOS) → (PC<22:16>) (W15)-2 → W15 (TOS) → (PC<15:0>) lit10 → Wn None 0000 0101 0Bkk kkkk kkkk dddd Return from subroutine with the specified.

The software stack is popped twice to restore the PC. 1 3 (2 if exception pending) 001A06 RETURN . Advance Information DS70030E-page 5-203 . Since two pops are made. Return from subroutine Status Affected: Encoding: Description: Words: Cycles: Example 1 PC W15 Data 1244 Data 1246 SR Example 2 Before Instruction 00 1A06 1248 0004 0001 0000 RETURN PC W15 Data 1244 Data 1246 SR After Instruction 01 0004 1244 0004 0001 0000 005404 .Section 5. Instruction Descriptions RETURN Syntax: Operands: Operation: {label:} None Return RETURN (W15)-2 → W15 (TOS) → (PC<22:16>) (W15)-2 → W15 (TOS) → (PC<15:0>) NOP → Instruction Register None 0000 0110 0000 0000 0000 0000 Return from subroutine. Return from subroutine PC W15 Data 0906 Data 0908 SR Before Instruction 00 5404 090A 0966 0000 0000 PC W15 Data 0906 Data 0908 SR After Instruction 00 0966 0906 0966 0000 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. the stack pointer (W15) is decremented by 4.

B} f {. The ‘D’ bit selects the destination (0 for f.dsPIC30F Programmer’s Reference Manual RLC Syntax: Operands: Operation: {label:} Rotate Left f through Carry RLC{. and it is then overwritten with the Most Significant bit of Ws. If WREG is specified.. 2: The WREG is set to working register W0. 1 for WREG).B in the instruction denotes a byte operation rather than a word operation. You may use a . . The ‘B’ bit selects byte or word operation (0 for word.WREG} f ∈ [0 . the result is stored in WREG. If WREG is not specified. C 1101 0110 1BDf ffff ffff ffff Rotate the contents of the file register f one bit to the left through the Carry flag and place the result in the destination register. The ‘f’ bits select the address of the file register. C=1) . The Carry flag of the Status Register is shifted into the Least Significant bit of the destination. Rotate Left w/ C (0x1233) (Byte mode) Before Instruction Data 1232 E807 SR 0000 Example 2 RLC After Instruction Data 1232 D007 SR 0009 (N. 8191] For byte operation: (C) → Dest<0> (f<6:0>) → Dest<7:1> (f<7>) → C For word operation: (C) → Dest<0> (f<14:0>) → Dest<15:1> (f<15>) → C C Status Affected: Encoding: Description: N. WREG Before After Instruction Instruction WREG (W0) 5601 WREG (W0) 42DD Data 0820 216E Data 0820 216E SR 0001 (C=1) SR 0000 (C=0) DS70030E-page 5-204 Advance Information  2003 Microchip Technology Inc.W extension to denote a word operation.. The optional WREG operand determines the destination register.B 0x1233 . the result is stored in the file register. Store result in WREG 0x820. 1 for byte). but it is not required. Note 1: The extension . Words: Cycles: Example 1 1 1 RLC. Z. Rotate Left w/ C (0x820) (Word mode) .

You may use a .B} Ws. The ‘p’ bits select the source Address mode.B W0. Note: The extension . Rotate Left w/ C (W0) (Byte mode) ..W extension to denote a word operation. The ‘q’ bits select the destination Address mode. [--Ws].. Words: Cycles: Example 1 1 1 RLC. Instruction Descriptions RLC Syntax: {label:} Rotate Left Ws through Carry RLC{. W15] Wd ∈ [W0 . [Ws]. The Carry flag of the Status register is shifted into the Least Significant bit of Wd. W15] For byte operation: (C) → Wd<0> (Ws<6:0>) → Wd<7:1> (Ws<7>) → C For word operation: (C) → Wd<0> (Ws<14:0>) → Wd<15:1> (Ws<15>) → C C Status Affected: Encoding: Description: N. W3 .. The ‘B’ bit selects byte or word operation (0 for word. C 1101 0010 1Bqq qddd dppp ssss Rotate the contents of the source register Ws one bit to the left through the Carry flag and place the result in the destination register Wd. Z. [Ws--]. but it is not required. 1 for byte). [++Ws]. Advance Information DS70030E-page 5-205 . The ‘d’ bits select the address of the destination register. [Ws++]. Store the result in W3 5 Instruction Descriptions Before Instruction W0 9976 W3 5879 SR 0001 (C=1) After Instruction W0 9976 W3 58ED SR 0009 (N=1)  2003 Microchip Technology Inc.B in the instruction denotes a byte operation rather than a word operation. and it is then overwritten with the Most Significant bit of Ws. The ‘s’ bits select the address of the source register. Either register direct or indirect addressing may be used for Ws and Wd.Section 5. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 ..

C=1) DS70030E-page 5-206 Advance Information  2003 Microchip Technology Inc. Store result in [W8] Before After Instruction Instruction W2 2008 W2 200A W8 094E W8 094E Data 094E 3689 Data 094E 8082 Data 2008 C041 Data 2008 C041 SR 0001 (C=1) SR 0009 (N. Post-increment W2 . [W8] .dsPIC30F Programmer’s Reference Manual Example 2 RLC [W2++]. Rotate Left w/ C [W2] (Word mode) . .

Z 1101 0110 0BDf ffff ffff ffff Rotate the contents of the file register f one bit to the left and place the result in the destination register. The ‘B’ bit selects byte or word operation (0 for word. and the Carry flag is not affected.W extension to denote a word operation. Store result in WREG 0x820. The ‘f’ bits select the address of the file register. Note 1: The extension . You may use a . If WREG is not specified. The Most Significant bit of f is stored in the Least Significant bit of the destination.B} f {.B 0x1233 . Words: Cycles: Example 1 1 1 RLNC. Advance Information DS70030E-page 5-207 .WREG} f ∈ [0 . the result is stored in the file register. the result is stored in WREG. WREG Before After Instruction Instruction WREG (W0) 5601 WREG (W0) 42DC Data 0820 216E Data 0820 216E SR 0001 (C=1) SR 0000 (C=0) 5 Instruction Descriptions  2003 Microchip Technology Inc. 2: The WREG is set to working register W0. Rotate Left (0x820) (Word mode) . Instruction Descriptions RLNC Syntax: Operands: Operation: {label:} Rotate Left f without Carry RLNC{. 1 for byte). The optional WREG operand determines the destination register. 8191] For byte operation: (f<6:0>) → Dest<7:1> (f<7>) → Dest<0> For word operation: (f<14:0>) → Dest<15:1> (f<15>) → Dest<0> Status Affected: Encoding: Description: N. 1 for file register). but it is not required.B in the instruction denotes a byte operation rather than a word operation..Section 5. Rotate Left (0x1233) (Byte mode) Before Instruction Data 1232 E807 SR 0000 Example 2 RLNC After Instruction Data 1233 D107 SR 0008 (N=1) .. The ‘D’ bit selects the destination (0 for WREG. If WREG is specified.

W extension to denote a word operation. W3 . You may use a .. W15] Wd ∈ [W0 . Note: The extension . and the Carry flag is not affected.. [--Ws].B} Ws.dsPIC30F Programmer’s Reference Manual RLNC Syntax: {label:} Rotate Left Ws without Carry RLNC{. [++Ws]. [Ws]. The ‘s’ bits select the address of the source register.. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 . The ‘q’ bits select the destination Address mode. The ‘p’ bits select the source Address mode. W15] For byte operation: (Ws<6:0>) → Wd<7:1> (Ws<7>) → Wd<0> For word operation: (Ws<14:0>) → Wd<15:1> (Ws<15>) → Wd<0> Status Affected: Encoding: Description: N. Rotate Left (W0) (Byte mode) . Words: Cycles: Example 1 1 1 RLNC. [Ws++]. Either register direct or indirect addressing may be used for Ws and Wd. The ‘B’ bit selects byte or word operation (0 for byte. The Most Significant bit of Ws is stored in the Least Significant bit of Wd. The ‘d’ bits select the address of the destination register.. C=1) DS70030E-page 5-208 Advance Information  2003 Microchip Technology Inc.B W0. but it is not required. [Ws--]. Store the result in W3 Before Instruction W0 9976 W3 5879 SR 0001 (C=1) After Instruction W0 9976 W3 58EC SR 0009 (N.B in the instruction denotes a byte operation rather than a word operation. 1 for word). . Z 1101 0010 0Bqq qddd dppp ssss Rotate the contents of the source register Ws one bit to the left and place the result in the destination register Wd.

Section 5. [W8] . Advance Information DS70030E-page 5-209 . Instruction Descriptions Example 2 RLNC [W2++]. Post-increment W2 . Rotate Left [W2] (Word mode) . C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Store result in [W8] Before After Instruction Instruction W2 2008 W2 200A W8 094E W8 094E Data 094E 3689 Data 094E 8083 Data 2008 C041 Data 2008 C041 SR 0001 (C=1) SR 0009 (N.

1 for file register).dsPIC30F Programmer’s Reference Manual RRC Syntax: Operands: Operation: {label:} Rotate Right f through Carry RRC{. C 1101 0111 1BDf ffff ffff ffff Rotate the contents of the file register f one bit to the right through the Carry flag and place the result in the destination register.B in the instruction denotes a byte operation rather than a word operation. . Store result in WREG 0x820. 8191] For byte operation: (C) → Dest<7> (f<7:1>) → Dest<6:0> (f<0>) → C For word operation: (C) → Dest<15> (f<15:1>) → Dest<14:0> (f<0>) → C C Status Affected: Encoding: Description: N. but it is not required.B} f {. Rotate Right w/ C (0x820) (Word mode) .WREG} f ∈ [0 . and it is then overwritten with the Least Significant bit of Ws. If WREG is specified. If WREG is not specified. the result is stored in the file register. the result is stored in WREG. 1 for word).B 0x1233 .W extension to denote a word operation. Z. 2: The WREG is set to working register W0. The ‘B’ bit selects byte or word operation (0 for byte. You may use a . Words: Cycles: Example 1 1 1 RRC.. The ‘D’ bit selects the destination (0 for WREG. Note 1: The extension . The Carry flag of the Status Register is shifted into the Most Significant bit of the destination. The optional WREG operand determines the destination register. Rotate Right w/ C (0x1233) (Byte mode) Before Instruction Data 1232 E807 SR 0000 Example 2 RRC After Instruction Data 1232 7407 SR 0000 . The ‘f’ bits select the address of the file register. WREG Before After Instruction Instruction WREG (W0) 5601 WREG (W0) 90B7 Data 0820 216E Data 0820 216E SR 0001 (C=1) SR 0008 (N=1) DS70030E-page 5-210 Advance Information  2003 Microchip Technology Inc..

and it is then overwritten with the Least Significant bit of Ws. You may use a . Rotate Right w/ C (W0) (Byte mode) . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 . W3 . [--Ws].B} Ws. The Carry flag of the Status Register is shifted into the Most Significant bit of Wd. [Ws++]. The ‘s’ bits select the address of the source register.Section 5. Instruction Descriptions RRC Syntax: {label:} Rotate Right Ws through Carry RRC{. The ‘q’ bits select the destination Address mode. Either register direct or indirect addressing may be used for Ws and Wd. Words: Cycles: Example 1 1 1 RRC.. [Ws--]. W15] Wd ∈ [W0 .B in the instruction denotes a byte operation rather than a word operation. Store the result in W3 Before Instruction W0 9976 W3 5879 SR 0001 (C=1) After Instruction W0 9976 W3 58BB SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. The ‘p’ bits select the source Address mode. [++Ws]. W15] For byte operation: (C) → Wd<7> (Ws<7:1>) → Wd<6:0> (Ws<0>) → C For word operation: (C) → Wd<15> (Ws<15:1>) → Wd<14:0> (Ws<0>) → C C Status Affected: Encoding: Description: N. The ‘B’ bit selects byte or word operation (0 for word. Advance Information DS70030E-page 5-211 . 1 for byte). Z. The ‘d’ bits select the address of the destination register.B W0... Note: The extension . but it is not required.. [Ws].W extension to denote a word operation. C 1101 0011 1Bqq qddd dppp ssss Rotate the contents of the source register Ws one bit to the right through the Carry flag and place the result in the destination register Wd.

C=1) DS70030E-page 5-212 Advance Information  2003 Microchip Technology Inc. Store result in [W8] Before After Instruction Instruction W2 2008 W2 200A W8 094E W8 094E Data 094E 3689 Data 094E E020 Data 2008 C041 Data 2008 C041 SR 0001 (C=1) SR 0009 (N.dsPIC30F Programmer’s Reference Manual Example 2 RRC [W2++]. Rotate Right w/ C [W2] (Word mode) . Post-increment W2 . . [W8] .

Rotate Right (0x820) (Word mode) . The Least Significant bit of f is stored in the Most Significant bit of the destination. Advance Information DS70030E-page 5-213 .. Words: Cycles: Example 1 1 1 RRNC. You may use a . The ‘D’ bit selects the destination (0 for WREG.. Store result in WREG 0x820. and the Carry flag is not affected. 8191] For byte operation: (f<7:1>) → Dest<6:0> (f<0>) → Dest<7> For word operation: (f<15:1>) → Dest<14:0> (f<0>) → Dest<15> Status Affected: Encoding: Description: N. The optional WREG operand determines the destination register. 1 for byte). the result is stored in WREG.B} f {. Note 1: The extension . The ‘f’ bits select the address of the file register.Section 5.B 0x1233 .W extension to denote a word operation. If WREG is specified.WREG} f ∈ [0 .B in the instruction denotes a byte operation rather than a word operation. 1 for file register). Instruction Descriptions RRNC Syntax: Operands: Operation: {label:} Rotate Right f without Carry RRNC{. WREG Before After Instruction Instruction WREG (W0) 5601 WREG (W0) 10B7 Data 0820 216E Data 0820 216E SR 0001 (C=1) SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Rotate Right (0x1233) (Byte mode) Before Instruction Data 1232 E807 SR 0000 Example 2 RRNC After Instruction Data 1232 7407 SR 0000 . 2: The WREG is set to working register W0. Z 1101 0111 0BDf ffff ffff ffff Rotate the contents of the file register f one bit to the right and place the result in the destination register. but it is not required. the result is stored in the file register. The ‘B’ bit selects byte or word operation (0 for word. If WREG is not specified.

[Ws--].dsPIC30F Programmer’s Reference Manual RRNC Syntax: {label:} Rotate Right Ws without Carry RRNC{. Words: Cycles: Example 1 1 1 RRNC.B in the instruction denotes a byte operation rather than a word operation. but it is not required. [++Ws]. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 ... The Least Significant bit of Ws is stored in the Most Significant bit of Wd. and the Carry flag is not affected.W extension to denote a word operation. 1 for byte). Rotate Right (W0) (Byte mode) . You may use a . The ‘s’ bits select the address of the source register. [Ws].B W0. Either register direct or indirect addressing may be used for Ws and Wd. . W15] Wd ∈ [W0 .. Store the result in W3 Before Instruction W0 9976 W3 5879 SR 0001 (C=1) After Instruction W0 9976 W3 583B SR 0001 (C=1) DS70030E-page 5-214 Advance Information  2003 Microchip Technology Inc. The ‘d’ bits select the address of the destination register.. Z 1101 0011 0Bqq qddd dppp ssss Rotate the contents of the source register Ws one bit to the right and place the result in the destination register Wd.B} Ws. [Ws++]. The ‘p’ bits select the source Address mode. [--Ws]. Note: The extension . The ‘q’ bits select the destination Address mode. The ‘B’ bit selects byte or word operation (0 for word. W15] For byte operation: (Ws<7:1>) → Wd<6:0> (Ws<0>) → Wd<7> For word operation: (Ws<15:1>) → Wd<14:0> (Ws<0>) → Wd<15> Status Affected: Encoding: Description: N. W3 .

Rotate Right [W2] (Word mode) . Instruction Descriptions Example 2 RRNC [W2++]. Store result in [W8] Before Instruction W2 2008 W8 094E Data 094E 3689 Data 2008 C041 SR 0000 After Instruction W2 200A W8 094E Data 094E E020 Data 2008 C041 SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Post-increment W2 .Section 5. [W8] . Advance Information DS70030E-page 5-215 .

{#Slit4.} Wd [Wd] [Wd++] [Wd--] [--Wd] [++Wd] [Wd+Wb] Operands: Acc ∈ [A. CORCON<5>.R may be used to store the rounded accumulator contents. Note 1: This instruction does not modify the contents of Acc. The ‘d’ bits specify the destination register Wd. The ‘r’ bits encode the optional accumulator pre-shift. The ‘w’ bits specify the offset register Wb. 3: If Data Write saturation is enabled (SATDW. 2: This instruction stores the truncated contents of Acc. Either register direct or indirect addressing may be used for Wd. +7] Wb.. #4. where a negative operand indicates an arithmetic left shift and a positive operand indicates an arithmetic right shift. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 SAC A.. The instruction SAC.. The ‘h’ bits select the destination Address mode. the value stored to Wd is subject to saturation after the optional shift is performed. CORCON = 0x0010 (SATDW = 1) W5 ACCA CORCON SR Before Instruction B900 00 120F FF00 0010 0000 W5 ACCA CORCON SR After Instruction 0120 00 120F FF00 0010 0000 DS70030E-page 5-216 Advance Information  2003 Microchip Technology Inc. = 1). signed 4-bit shift of the specified accumulator. The shift range is -8:7. W5 . .. then store the shifted contents of AccH (Acc[31:16]) to Wd.B] Slit4 ∈ [-8 . Store result to W5 . W15] ShiftSlit4(Acc) (optional) (Acc[31:16]) → Wd None 1100 1100 Awww wrrr rhhh dddd Perform an optional. Right shift ACCA by 4 .dsPIC30F Programmer’s Reference Manual SAC Syntax: {label:} Store Accumulator SAC Acc. The ‘A’ bit specifies the source accumulator. Wd ∈ [W0 .

Advance Information DS70030E-page 5-217 . Instruction Descriptions Example 2 SAC B. Left shift ACCB by 4 . CORCON = 0x0010 (SATDW = 1) W5 ACCB Data 2000 CORCON SR Before Instruction 2000 FF C891 8F4C 5BBE 0010 0000 W5 ACCB Data 2000 CORCON SR After Instruction 2002 FF C891 1F4C 8000 0010 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Post-increment W5 . Store result to [W5]. [W5++] .Section 5. #-4.

signed 4-bit shift of the specified accumulator. CORCON<5>. W5 . The ‘w’ bits specify the offset register Wb. Note 1: This instruction does not modify the contents of the Acc. Right shift ACCA by 4 ..B] Slit4 ∈ [-8 . The ‘A’ bit specifies the source accumulator. The ‘r’ bits encode the optional accumulator pre-shift..R Acc. where a negative operand indicates an arithmetic left shift and a positive operand indicates an arithmetic right shift. The instruction SAC may be used to store the truncated accumulator contents. . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 SAC. then store the rounded contents of AccH (Acc[31:16]) to Wd. 2: This instruction stores the rounded contents of Acc. CORCON = 0x0010 (SATDW = 1) W5 ACCA CORCON SR Before Instruction B900 00 120F FF00 0010 0000 W5 ACCA CORCON SR After Instruction 0121 00 120F FF00 0010 0000 DS70030E-page 5-218 Advance Information  2003 Microchip Technology Inc. CORCON<1>.} Wd [Wd] [Wd++] [Wd--] [--Wd] [++Wd] [Wd+Wb] Operands: Acc ∈ [A. = 1).dsPIC30F Programmer’s Reference Manual SAC. +7] Wb ∈ [W0 . Store rounded result to W5 . W15] ShiftSlit4(Acc) (optional) Round(Acc) (Acc[31:16]) → Wd None 1100 1101 Awww wrrr rhhh dddd Perform an optional.. Either register direct or indirect addressing may be used for Wd.. W15] Wd ∈ [W0 . The Rounding mode (Conventional or Convergent) is set by the RND bit. The shift range is -8:7.R Syntax: {label:} Store Rounded Accumulator SAC. The ‘d’ bits specify the destination register Wd. The ‘h’ bits select the destination Address mode. {#Slit4. #4.. the value stored to Wd is subject to saturation after the optional shift is performed. 3: If Data Write saturation is enabled (SATDW.R A..

Left shift ACCB by 4 . [W5++] . Post-increment W5 .R B. Advance Information DS70030E-page 5-219 .Section 5. CORCON = 0x0010 (SATDW = 1) W5 ACCB Data 2000 CORCON SR Before Instruction 2000 FF F891 8F4C 5BBE 0010 0000 W5 ACCB Data 2000 CORCON SR After Instruction 2002 FF F891 8F4C 8919 0010 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Store rounded result to [W5]. Instruction Descriptions Example 2 SAC. #-4.

. so any address modification is by ‘1’. W15] Wnd ∈ [W0 .. and register direct addressing must be used for Wnd. The ‘p’ bits select the source Address mode. and it uses no .dsPIC30F Programmer’s Reference Manual SE Syntax: {label:} Sign-Extend Ws SE Ws. Z. 2: The source Ws is addressed as a byte operand. Status Affected: Encoding: Description: Words: Cycles: Example 1 SE 1 1 W3. The ‘s’ bits select the address of the source register. W12 After Instruction W3 7839 W4 0039 SR 0001 (C=1) . [Ws--]. The ‘d’ bits select the address of the destination register. [Ws++]..B or . . [++Ws]. [Ws]. The C flag is set to the complement of the N flag. W15] Ws<7:0> → Wnd<7:0> If (Ws<7> = 1): 0xFF → Wnd<15:8> Else: 0 → Wnd<15:8> N. Wnd Operands: Operation: Ws ∈ [W0 . C 1111 1011 0000 0ddd dppp ssss Sign-extend the byte in Ws and store the 16-bit result in Wnd. Either register direct or indirect addressing may be used for Ws. Post-increment W2 Before Instruction W2 0900 W12 1002 Data 0900 008F SR 0000 After Instruction W2 0901 W12 FF8F Data 0900 008F SR 0008 (N=1) DS70030E-page 5-220 Advance Information  2003 Microchip Technology Inc.. Sign-extend W3 and store to W4 Before Instruction W3 7839 W4 1005 SR 0000 Example 2 SE [W2++]. Sign-extend [W2] and store to W12 .W extension. W4 . Note 1: This operation converts a byte to a word. [--Ws].

the bits of the specified file register are set. 1 for byte). The ‘B’ bit selects byte or word operation (0 for word. Set WREG (Word mode) Before Instruction WREG (W0) 0900 SR 0000 After Instruction WREG (W0) FFFF SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Instruction Descriptions SETM Syntax: {label:} Set f or WREG SETM{. the bits of WREG are set.B in the instruction denotes a byte operation rather than a word operation. 1 for file register). Otherwise. Note 1: The extension . The ‘D’ bit selects the destination (0 for WREG. You may use a ..W extension to denote a word operation. Status Affected: Encoding: Description: Words: Cycles: Example 1 SETM.Section 5. Advance Information DS70030E-page 5-221 . Set 0x891 (Byte mode) Before Instruction Data 0890 2739 SR 0000 Example 2 SETM WREG After Instruction Data 0890 FF39 SR 0000 . but it is not required..B} f WREG Operands: Operation: f ∈ [0 . 8191] For byte operation: 0xFF → destination designated by D For word operation: 0xFFFF → destination designated by D None 1110 1111 1BDf ffff ffff ffff All the bits of the specified register are set to ‘1’. The ‘f’ bits select the address of the file register. If WREG is specified.B 1 1 0x891 . 2: The WREG is set to working register W0.

Set W13 (Byte mode) Before Instruction W13 2739 SR 0000 Example 2 SETM [--W6] After Instruction W13 27FF SR 0000 .dsPIC30F Programmer’s Reference Manual SETM Syntax: {label:} Set Ws SETM{. . Note: The extension .B in the instruction denotes a byte operation rather than a word operation.. The ‘q’ bits select the destination Address mode. The ‘d’ bits select the address of the destination register.. Pre-decrement W6 (Word mode) . You may use a .B 1 1 W13 . W15] For byte operation: 0xFF → Wd for byte operation For word operation: 0xFFFF → Wd for word operation None 1110 1011 1Bqq qddd d000 0000 All the bits of the specified register are set to ‘1’. 1 for byte). The ‘B’ bits selects byte or word operation (0 for word. Status Affected: Encoding: Description: Words: Cycles: Example 1 SETM. Either register direct or indirect addressing may be used for Wd. Set [W6] Before Instruction W6 1250 Data 124E 3CD9 SR 0000 After Instruction W6 124E Data 124E FFFF SR 0000 DS70030E-page 5-222 Advance Information  2003 Microchip Technology Inc. but it is not required.W extension to denote a word operation.B} Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Wd ∈ [W0 .

#-10 . The shift range is -16:16. #Slit6 Acc ∈ [A. CORCON = 0x0040 (SATB = 1) ACCB CORCON SR Before Instruction FF FFF1 8F4C 0040 0000 ACCB CORCON SR After Instruction FF C63D 3000 0040 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. OAB. #12 . SA.Section 5. Arithmetic right shift ACCA by 12 . 16] Shiftk(Acc) → Acc OA. Store result to ACCB . where a negative operand indicates a left shift and a positive operand indicates a right shift. OB. Arithmetic left shift ACCB by 10 . 2: If the shift amount is greater than 16 or less than -16. and an arithmetic trap will occur. CORCON<7>). CORCON = 0x0080 (SATA = 1) ACCA CORCON SR Example 2 Before Instruction 00 120F FF00 0080 0000 ACCA CORCON SR After Instruction 00 0001 20FF 0080 0000 SFTAC B.. Instruction Descriptions SFTAC Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Arithmetic Shift Accumulator by Slit6 SFTAC Acc. Note 1: If saturation is enabled for the target accumulator (SATA. 6-bit literal and store the result back into the accumulator. the value stored to the accumulator is subject to saturation. The ‘k’ bits determine the number of bits to be shifted. SAB 1100 1000 A000 0000 01kk kkkk Arithmetic shift the 40-bit contents of the specified accumulator by the signed. Advance Information DS70030E-page 5-223 . Store result to ACCA . SB. Any bits which are shifted out of the accumulator are lost..B] Slit6 ∈ [-16 . no modification will be made to the accumulator. Words: Cycles: Example 1 1 1 SFTAC A. CORCON<6> or SATB. The ‘A’ bit selects the accumulator for the result.

Arithmetic shift ACCB by (W12) . Words: Cycles: Example 1 1 1 SFTAC A. Note 1: If saturation is enabled for the target accumulator (SATA.dsPIC30F Programmer’s Reference Manual SFTAC Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Arithmetic Shift Accumulator by Wb SFTAC Acc. no modification will be made to the accumulator.. Wb Acc ∈ [A. Store result to ACCB . CORCON = 0x0000 (saturation disabled) W0 ACCA CORCON SR Example 2 Before Instruction FFFC 00 320F AB09 0000 0000 W0 ACCA CORCON SR After Instruction FFFC 03 20FA B090 0000 8800 (OA. where a negative value indicates a left shift and a positive value indicates a right shift.B] Wb ∈ [W0 . W15] Shift(Wb)(Acc) → Acc OA. and an arithmetic trap will occur. The ‘A’ bit selects the accumulator for the source/destination. SAB 1100 1000 A000 0000 0000 ssss Arithmetic shift the 40-bit contents of the specified accumulator and store the result back into the accumulator. the value stored to the accumulator is subject to saturation. SB. The ‘s’ bits select the address of the shift count register. CORCON<6> or SATB. SA. Any bits which are shifted out of the accumulator are lost. W0 . CORCON = 0x0040 (SATB = 1) W12 ACCB CORCON SR Before Instruction 000F FF FFF1 8F4C 0040 0000 W12 ACCB CORCON SR After Instruction 000F FF FFFF FFE3 0040 0000 DS70030E-page 5-224 Advance Information  2003 Microchip Technology Inc. . OAB. OAB=1) SFTAC B. Arithmetic shift ACCA by (W0) . W12 . The shift range is -16:16. 2: If the shift amount is greater than 16 or less than -16.. Store result to ACCA . CORCON<7>). OB. The Least Significant 6 bits of Wb are used to specify the shift amount.

Advance Information DS70030E-page 5-225 . If WREG is specified. 1 for file register).B 1 1 0x909 . Instruction Descriptions SL Syntax: Operands: Operation: {label:} Shift Left f SL{. WREG 5 Instruction Descriptions Before Instruction WREG (W0) 0900 Data 1650 4065 SR 0000 After Instruction WREG (W0) 80CA Data 1650 4065 SR 0008 (N=1)  2003 Microchip Technology Inc.. 8191] For byte operation: (f<7>) → (C) (f<6:0>) → Dest<7:1> 0 → Dest<0> For word operation: (f<15>) → (C) (f<14:0>) → Dest<15:1> 0 → Dest<0> C 0 Status Affected: Encoding: Description: N.W extension to denote a word operation. 2: The WREG is set to working register W0. C 1101 0100 0BDf ffff ffff ffff Shift the contents of the file register one bit to the left and place the result in the destination register.B in the instruction denotes a byte operation rather than a word operation. The ‘D’ bit selects the destination (0 for WREG. Note 1: The extension . The Most Significant bit of the file register is shifted into the Carry bit of the Status register. The optional WREG operand determines the destination register. The ‘B’ bit selects byte or word operation (0 for word. Store result in WREG 0x1650. The ‘f’ bits select the address of the file register. Shift left (0x1650) (Word mode) . the result is stored in the file register. and zero is shifted into the Least Significant bit of the destination register. Shift left (0x909) (Byte mode) Before Instruction Data 0908 9439 SR 0000 Example 2 SL After Instruction Data 0908 0839 SR 0001 (C=1) . Words: Cycles: Example 1 SL. 1 for byte).WREG} f ∈ [0. Z. You may use a . If WREG is not specified. the result is stored in WREG..Section 5.B} f {. but it is not required.

and 0 is shifted into the Least Significant bit of Wd. W15] Wd ∈ [W0 .. but it is not required. The ‘d’ bits select the address of the destination register. [Ws--]. Either register direct or indirect addressing may be used for Ws and Wd. You may use a .. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 . [Ws++]. W4 . The ‘B’ bit selects byte or word operation (0 for word. [--Ws].. W15] For byte operation: (Ws<7>) → C (Ws<6:0>) → Wd<7:1> 0 → Wd<0> For word operation: (Ws<15>) → C (Ws<14:0>) → Wd<15:1> 0 → Wd<0> C 0 Status Affected: Encoding: Description: N.. Note: The extension . The ‘q’ bits select the destination Address mode. [++Ws]. The Most Significant bit of Ws is shifted into the Carry bit of the Status register. C 1101 0000 0Bqq qddd dppp ssss Shift the contents of the source register Ws one bit to the left and place the result in the destination register Wd.B} Ws. Shift left W3 (Byte mode) .B in the instruction denotes a byte operation rather than a word operation. Store result to W4 Before Instruction W3 78A9 W4 1005 SR 0000 After Instruction W3 78A9 W4 1052 SR 0001 (C=1) DS70030E-page 5-226 Advance Information  2003 Microchip Technology Inc.B 1 1 W3. . [Ws].W extension to denote a word operation. The ‘s’ bits select the address of the source register.dsPIC30F Programmer’s Reference Manual SL Syntax: {label:} Shift Left Ws SL{. 1 for byte). The ‘p’ bits select the source Address mode. Z. Words: Cycles: Example 1 SL.

Shift left [W2] (Word mode) .Section 5. [W12] . Store result to [W12] . Advance Information DS70030E-page 5-227 . Post-increment W2 Before Instruction W2 0900 W12 1002 Data 0900 800F Data 1002 6722 SR 0000 After Instruction W2 0902 W12 1002 Data 0900 800F Data 1002 001E SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Instruction Descriptions Example 2 SL [W2++].

15] Wnd ∈ [W0 . The ‘w’ bits select the address of the base register.. #lit4. Shift left W3 by 12 . W8 After Instruction W2 8A90 SR 0008 (N=1) . Wnd Wb ∈ [W0 . The ‘k’ bits provide the literal operand. The ‘d’ bits select the address of the destination register. #12... Store result to W8 Before Instruction W3 0912 W8 1002 SR 0000 After Instruction W3 0912 W8 2000 SR 0000 DS70030E-page 5-228 Advance Information  2003 Microchip Technology Inc. W15] lit4<3:0> → Shift_Val Wnd<15:Shift_Val> = Wb<15-Shift_Val:0> Wd<Shift_Val-1:0> = 0 N.. #4. Direct addressing must be used for Wb and Wnd. . a five-bit integer number. Any bits shifted out of the source register are lost. Z 1101 1101 0www wddd d100 kkkk Shift left the contents of the source register Wb by the 4-bit unsigned literal and store the result in the destination register Wnd. Store result to W2 Before Instruction W2 78A9 SR 0000 Example 2 SL W3. W2 .. W15] lit4 ∈ [0. Shift left W2 by 4 ..dsPIC30F Programmer’s Reference Manual SL Syntax: Operands: {label:} Shift Left by Short Literal SL Wb. Note: This instruction operates in Word mode only. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SL 1 1 W2.

Z 1101 1101 0www wddd d000 ssss Shift left the contents of the source register Wb by the 5 Least Significant bits of Wns (only up to 15 positions) and store the result in the destination register Wnd. Register direct addressing must be used for Wb. 2: If Wns is greater than 15.. Wns. W15] Wns<4:0> → Shift_Val Wnd<15:Shift_Val> = Wb<15-Shift_Val:0> Wd<Shift_Val-1:0> = 0 N. The ‘d’ bits select the address of the destination register.. Store result to W2 Before Instruction W0 09A4 W1 8903 W2 78A9 SR 0000 Example 2 SL W4. Note 1: This instruction operates in Word mode only.. Wnd Wb ∈ [W0 . Store result to W6 Before Instruction W4 A409 W5 FF01 W6 0883 SR 0000 After Instruction W4 A409 W5 FF01 W6 4812 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SL 1 1 W0.. W1. Advance Information DS70030E-page 5-229 . Wnd will be loaded with 0x0. The ‘w’ bits select the address of the base register. Wns and Wnd. Shift left W4 by W5<0:4> . W5. W15] Wns ∈ [W0 .Section 5. W2 ..W15] Wnd ∈ [W0 . W6 After Instruction W0 09A4 W1 8903 W2 4D20 SR 0000 . Any bits shifted out of the source register are lost. Instruction Descriptions SL Syntax: Operands: {label:} Shift Left by Wns SL Wb. Shift left W0 by W1<0:4> .. The ‘s’ bits select the address of the source register.

.B in the instruction denotes a byte operation rather than a word operation. N. The ‘D’ bit selects the destination (0 for WREG. Sub. OV.W extension to denote a word operation.B} f {. The optional WREG operand determines the destination register. If WREG is not specified. WREG from (0xA04) (Word mode) . The ‘B’ bit selects byte or word operation (0 for word. C=1) . If WREG is specified. the result is stored in the file register. and place the result in the destination register. Note 1: The extension .B 0x1FFF . the result is stored in WREG. 2: The WREG is set to working register W0. Store result to 0x1FFF Before Instruction WREG (W0) 7804 Data 1FFE 9439 SR 0000 Example 2 SUB After Instruction WREG (W0) 7804 Data 1FFE 9039 SR 0009 (N. WREG from (0x1FFF) (Byte mode) . The ‘f’ bits select the address of the file register.dsPIC30F Programmer’s Reference Manual SUB Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Subtract WREG from f SUB{. Sub. 1 for file register).. WREG Before Instruction WREG (W0) 6234 Data 0A04 4523 SR 0000 After Instruction WREG (W0) E2EF Data 0A04 4523 SR 0008 (N=1) DS70030E-page 5-230 Advance Information  2003 Microchip Technology Inc. You may use a .WREG} f ∈ [0 . Store result to WREG 0xA04. Z. 1 for byte). but it is not required. C 1011 0101 0BDf ffff ffff ffff Subtract the contents of the default working register WREG from the contents of the specified file register.. Words: Cycles: Example 1 1 1 SUB. 8191] (f) – (WREG) → destination designated by D DC.

. 0x23 from W0 (Byte mode) . 1023] for word operation Wn ∈ [W0 .B in the instruction denotes a byte operation rather than a word operation. OV. Register direct addressing must be used for Wn.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode..Section 5. The ‘B’ bit selects byte or word operation.. the literal must be specified as an unsigned value [0:255]. You may use a . but it is not required. Store result to W0 Before Instruction W0 7804 SR 0000 Example 2 SUB #0x108. Z. The ‘d’ bits select the address of the working register. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SUB. Instruction Descriptions SUB Syntax: Operands: {label:} Subtract Literal from Wn SUB{. 255] for byte operation lit10 ∈ [0 . Note 1: The extension . Advance Information DS70030E-page 5-231 . The ‘k’ bits specify the literal operand. Sub.. C 1011 0001 0Bkk kkkk kkkk dddd Subtract the 10-bit unsigned literal operand from the contents of the working register Wn.B 1 1 #0x23. W4 After Instruction W0 78E1 SR 0008 (N=1) . 0x108 from W4 (Word mode) . N. W15] (Wn) – lit10 → Wn DC. W0 . and store the result back in the working register Wn.B} #lit10. Sub.. Wn lit10 ∈ [0 . 2: For byte operations. See Section 4. Store result to W4 Before Instruction W4 6234 SR 0000 After Instruction W4 612C SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc..W extension to denote a word operation.

#0x8. Store result to [W2] . The ‘B’ bit selects byte or word operation (0 for word. 0x8 from W0 (Word mode) . Z. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 ..dsPIC30F Programmer’s Reference Manual SUB Syntax: {label:} Subtract Short Literal from Wb SUB{. 1 for byte). Note: The extension . .W extension to denote a word operation. C=1) DS70030E-page 5-232 Advance Information  2003 Microchip Technology Inc. 31] Wd ∈ [W0 . Sub.B} Wb. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SUB.. Store result to W5 Before Instruction W4 1782 W5 7804 SR 0000 Example 2 SUB After Instruction W4 1782 W5 7872 SR 0005 (OV.. The ‘d’ bits select the address of the destination register. The ‘q’ bits select the destination Address mode.B in the instruction denotes a byte operation rather than a word operation... Register direct or indirect addressing must be used for Wd. W15] (Wb) – lit5 → Wd DC. [W2++] Before Instruction W0 F230 W2 2004 Data 2004 A557 SR 0000 After Instruction W0 F230 W2 2006 Data 2004 F228 SR 0009 (N. You may use a . N. but it is not required. #lit5.. 0x10 from W4 (Byte mode) . C 0101 0www wBqq qddd d11k kkkk Subtract the 5-bit unsigned literal operand from the contents of the base register Wb. Register direct addressing must be used for Wb.B 1 1 W4. W15] lit5 ∈ [0 . The ‘w’ bits select the address of the base register. The ‘k’ bits provide the literal operand. Post-increment W2 W0. and place the result in the destination register Wd. Sub. OV. C=1) . #0x10. W5 . a five-bit integer number.

[Ws--]. N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Either register direct or indirect addressing may be used for Ws and Wd. The ‘s’ bits select the address of the source register. [Ws++]. Register direct addressing must be used for Wb.B 1 1 W0. but it is not required.W extension to denote a word operation.. The ‘p’ bits select the source Address mode. You may use a . [Ws]. Sub. Store result to W0 Before Instruction W0 1732 W1 7844 SR 0000 After Instruction W0 17EE W1 7844 SR 0108 (DC. The ‘d’ bits select the address of the destination register. Note: The extension . N. The ‘q’ bits select the destination Address mode. Z.Section 5. Ws. 1 for byte). The ‘w’ bits select the address of the base register.. W15] Ws ∈ [W0 .. [--Ws].B} Wb. Advance Information DS70030E-page 5-233 . W1.. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SUB. Instruction Descriptions SUB Syntax: {label:} Subtract Ws from Wb SUB{. [++Ws]. W0 . The ‘B’ bit selects byte or word operation (0 for word.. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . W1 from W0 (Byte mode) . OV. C 0101 0www wBqq qddd dppp ssss Subtract the contents of the source register Ws from the contents of the base register Wb and place the result in the destination register Wd.. W15] (Wb) – (Ws) → Wd DC. W15] Wd ∈ [W0 .B in the instruction denotes a byte operation rather than a word operation.

. OV=1) DS70030E-page 5-234 Advance Information  2003 Microchip Technology Inc. [W8++]. . [W8] from W7 (Word mode) Store result to [W9] Post-increment W8 Post-increment W9 Before Instruction W7 2450 W8 1808 W9 2020 Data 1808 92E4 Data 2022 A557 SR 0000 After Instruction W7 2450 W8 180A W9 2022 Data 1808 92E4 Data 2022 916C SR 010C (DC. .dsPIC30F Programmer’s Reference Manual Example 2 SUB W7. [W9++] . N. Sub. .

OAB. This instruction performs a 40-bit subtraction. Store the result to ACCB . SA. Status Affected: Encoding: Description: Words: Cycles: Example 1 SUB 1 1 A . OB=1) . Store the result to ACCA . Subtract ACCA from ACCB . and store the result back into Acc. Instruction Descriptions SUB Syntax: Operands: Operation: {label:} Acc ∈ [A. OB. SB. Advance Information DS70030E-page 5-235 .Section 5. CORCON = 0x0000 (no saturation) ACCA ACCB CORCON SR Example 2 SUB Before Instruction 76 120F 098A 23 F312 BC17 0000 0000 B ACCA ACCB CORCON SR After Instruction 52 1EFC 4D73 23 F312 BC17 0000 1100 (OA. CORCON = 0x0040 (SATB = 1) ACCA ACCB CORCON SR Before Instruction FF 9022 2EE1 00 2456 8F4C 0040 0000 ACCA ACCB CORCON SR After Instruction FF 9022 2EE1 00 7FFF FFFF 0040 1400 (SB. Subtract ACCB from ACCA . SAB 1100 1011 A011 0000 0000 0000 Subtract the contents of the unspecified accumulator from the contents of Acc. The ‘A’ bit specifies the destination accumulator.B] Subtract Accumulators SUB Acc If (Acc = A): ACCA – ACCB → ACCA Else: ACCB – ACCA → ACCB OA. SAB=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.

OV.B} f {. Store result to WREG SUBB 0xA04. You may use a . WREG and C from (0xA04) (Word mode) . C) from the contents of the specified file register and place the result in the destination register. CPB. WREG and C from (0x1FFF) (Byte mode) . the result is stored in the file register The ‘B’ bit selects byte or word operation (0 for word. . 1 for file register). The ‘f’ bits select the address of the file register. If WREG is not specified. 8191] (f) – (WREG) – (C) → destination designated by D DC. 2: The WREG is set to working register W0. The optional WREG operand determines the destination register. The ‘D’ bit selects the destination (0 for WREG. Sub. 1 for byte). Store result to 0x1FFF Before Instruction WREG (W0) 7804 Data 1FFE 9439 SR 0000 Example 2 After Instruction WREG (W0) 7804 Data 1FFE 8F39 SR 0008 (N=1) . These instructions can only clear Z. 3: The Z flag is “sticky” for ADDC. N.. but it is not required.WREG} f ∈ [0 . Note 1: The extension .B 0x1FFF . WREG Before Instruction WREG (W0) 6234 Data 0A04 6235 SR 0000 After Instruction WREG (W0) 0000 Data 0A04 6235 SR 0001 (C=1) DS70030E-page 5-236 Advance Information  2003 Microchip Technology Inc. SUBB and SUBBR. C 1011 0101 1BDf ffff ffff ffff Subtract the contents of the default working register WREG and the Borrow flag (Carry flag inverse. Words: Cycles: Example 1 1 1 SUBB..dsPIC30F Programmer’s Reference Manual SUBB Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Subtract WREG and Carry bit from f SUBB{.B in the instruction denotes a byte operation rather than a word operation. If WREG is specified. Z.W extension to denote a word operation. Sub. the result is stored in WREG.

Section 5. W4 After Instruction W0 78E0 SR 0108 (DC. Register direct addressing must be used for Wn. 0x108 and C from W4 (Word mode) . Store result to W4 Before Instruction W4 6234 SR 0001 (C=1) After Instruction W4 612C SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. 255] for byte operation lit10 ∈ [0 . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SUBB. Instruction Descriptions SUBB Syntax: Operands: {label:} Subtract Wn from Literal with Borrow SUBB{. You may use a . C 1011 0001 1Bkk kkkk kkkk dddd Subtract the unsigned 10-bit literal operand and the Borrow flag (Carry flag inverse. W15] (Wn) – lit10 – (C) → Wn DC.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode. 1 for byte).. N. W0 .B 1 1 #0x23. Z. and store the result back in the working register Wn.. Wn lit10 ∈ [0 . C) from the contents of the working register Wn.B} #lit10.w extension to denote a word operation. 3: The Z flag is “sticky” for ADDC. These instructions can only clear Z. 1023] for word operation Wn ∈ [W0 . OV. The ‘B’ bit selects byte or word operation (0 for word. the literal must be specified as an unsigned value [0:255]. 0x23 and C from W0 (Byte mode) . SUBB and SUBBR. See Section 4. Store result to W0 Before Instruction W0 7804 SR 0000 Example 2 SUBB #0x108. The ‘d’ bits select the address of the working register.B in the instruction denotes a byte operation rather than a word operation. N=1) ... 2: For byte operations.. Advance Information DS70030E-page 5-237 . Note 1: The extension . Sub. The ‘k’ bits specify the literal operand. Sub. but it is not required. CPB..

CPB. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SUBB.. The ‘k’ bits provide the literal operand.. [W2++] After Instruction W4 1782 W5 7871 SR 0005 (OV.B in the instruction denotes a byte operation rather than a word operation. #0x10. W15] (Wb) – lit5 – (C) → Wd DC. The ‘d’ bits select the address of the destination register. but it is not required. The ‘q’ bits select the destination Address mode. SUBB and SUBBR. #lit5. W5 ...W extension to denote a word operation. C 0101 1www wBqq qddd d11k kkkk Subtract the 5-bit unsigned literal operand and the Borrow flag (Carry flag inverse. #0x8. 1 for byte). 0x8 and C from W0 (Word mode) . The ‘w’ bits select the address of the base register. Sub. Post-increment W2 Before After Instruction Instruction W0 0009 W0 0009 W2 2004 W2 2006 Data 2004 A557 Data 2004 0000 SR 0020 (Z=1) SR 0103 (DC.B 1 1 W4.dsPIC30F Programmer’s Reference Manual SUBB Syntax: {label:} Subtract Short Literal from Wb with Borrow SUBB{. Register direct addressing must be used for Wb. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . 31] Wd ∈ [W0 . These instructions can only clear Z. Sub. a five-bit integer number. N. Note 1: The extension . C=1) . W15] lit5 ∈ [0 . You may use a . C=1) DS70030E-page 5-238 Advance Information  2003 Microchip Technology Inc. Store result to W5 Before Instruction W4 1782 W5 7804 SR 0000 Example 2 SUBB W0. Z..B} Wb. The ‘B’ bit selects byte or word operation (0 for word. 0x10 and C from W4 (Byte mode) . Z. OV. . C) from the contents of the base register Wb and place the result in the destination register Wd. Store result to [W2] .. 2: The Z flag is “sticky” for ADDC. Either register direct or indirect addressing may be used for Wd.

1 for byte).W extension to denote a word operation. The ‘w’ bits select the address of the base register. Register direct addressing must be used for Wb. [--Ws]. [Ws--]. [Ws++]. and place the result in the destination register Wd. The ‘s’ bits select the address of the source register.. The ‘d’ bits select the address of the destination register. Instruction Descriptions SUBB Syntax: {label:} Subtract Ws from Wb with Borrow SUBB{. Note 1: The extension . Store result to W0 Before Instruction W0 1732 W1 7844 SR 0000 After Instruction W0 17ED W1 7844 SR 0108 (DC. N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc.B} Wb.B 1 1 W0.Section 5. W1 and C from W0 (Byte mode) . SUBB and SUBBR. W15] Wd ∈ [W0 . OV.. C) from the contents of the base register Wb. N. The ‘q’ bits select the destination Address mode. but it is not required.. Ws. [Ws]. W1. Advance Information DS70030E-page 5-239 . W0 . These instructions can only clear Z. C 0101 1www wBqq qddd dppp ssss Subtract the contents of the source register Ws and the Borrow flag (Carry flag inverse. W15] Ws ∈ [W0 .. Register direct or indirect addressing may be used for Ws and Wd. [++Ws].. Sub. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . W15] (Wb) – (Ws) – (C) → Wd DC..B in the instruction denotes a byte operation rather than a word operation. CPB. Z. The ‘B’ bit selects byte or word operation (0 for word. The ‘p’ bits select the source Address mode. You may use a . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SUBB. 2: The Z flag is “sticky” for ADDC.

[W8++]. . .dsPIC30F Programmer’s Reference Manual Example 2 SUBB W7. . [W8] and C from W7 (Word mode) Store result to [W9] Post-increment W8 Post-increment W9 Before Instruction W7 2450 W8 1808 W9 2022 Data 1808 92E4 Data 2022 A557 SR 0000 After Instruction W7 2450 W8 180A W9 2024 Data 1808 92E4 Data 2022 916C SR 010C (DC. OV=1) DS70030E-page 5-240 Advance Information  2003 Microchip Technology Inc. Sub. .[W9++] . N.

CPB. Sub. Words: Cycles: Example 1 1 1 SUBBR. If WREG is not specified. 1 for file register).WREG} f ∈ [0 . SUBB and SUBBR. You may use a . Advance Information DS70030E-page 5-241 . Instruction Descriptions SUBBR Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Subtract f from WREG with Borrow SUBBR{.B in the instruction denotes a byte operation rather than a word operation. but it is not required.. and place the result in the destination register. Store result to WREG Before Instruction WREG (W0) 6234 Data 0A04 6235 SR 0000 After Instruction WREG (W0) FFFE Data 0A04 6235 SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. the result is stored in the file register.W extension to denote a word operation. (0x803) and C from WREG (Byte mode) . Note 1: The extension . The ‘D’ bit selects the destination (0 for WREG. C 1011 1101 1BDf ffff ffff ffff Subtract the contents of the specified file register f and the Borrow flag (Carry flag inverse. the result is stored in WREG. The optional WREG operand determines the destination register. WREG .B 0x803 . C) from the contents of WREG. N. Store result to 0x803 Before After Instruction Instruction WREG (W0) 7804 WREG (W0) 7804 Data 0802 9439 Data 0802 6F39 SR 0002 (Z=1) SR 0000 Example 2 SUBBR 0xA04. 3: The Z flag is “sticky” for ADDC. Sub. (0xA04) and C from WREG (Word mode) . The ‘f’ bits select the address of the file register..Section 5. 1 for byte). 8191] (WREG) – (f) – (C) → destination designated by D DC. If WREG is specified. Z. The ‘B’ bit selects byte or word operation (0 for word. OV. These instructions can only clear Z.B} f {. 2: The WREG is set to working register W0.

W extension to denote a word operation. #lit5. W15] lit5 – (Wb) – (C) → Wd DC. 1 for byte). W1 .. The ‘d’ bits select the address of the destination register. The ‘w’ bits select the address of the base register. #0x8. N=1) DS70030E-page 5-242 Advance Information  2003 Microchip Technology Inc. C=1) Example 2 SUBBR After Instruction W0 F310 W1 7800 SR 0103 (DC. Sub. Z. N. You may use a . a five-bit integer number. OV. .B in the instruction denotes a byte operation rather than a word operation. Register direct addressing must be used for Wb. The ‘k’ bits provide the literal operand.. Post-increment W2 Before After Instruction Instruction W0 0009 W0 0009 W2 2004 W2 2006 Data 2004 A557 Data 2004 FFFE SR 0020 (Z=1) SR 0108 (DC. The ‘q’ bits select the destination Address mode. C) from the 5-bit unsigned literal and place the result in the destination register Wd. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 SUBBR. Store result to [W2] . but it is not required.. Note 1: The extension . W0 and C from 0x10 (Byte mode) .B W0. Register direct or indirect addressing must be used for Wd. These instructions can only clear Z. W15] lit5 ∈ [0 . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . 31] Wd ∈ [W0 . SUBB and SUBBR. [W2++] ... W0 and C from 0x8 (Word mode) .B} Wb.. 2: The Z flag is “sticky” for ADDC. #0x10. The ‘B’ bit selects byte or word operation (0 for word. CPB.dsPIC30F Programmer’s Reference Manual SUBBR Syntax: {label:} Subtract Wb from Short Literal with Borrow SUBBR{. C 0001 1www wBqq qddd d11k kkkk Subtract the contents of the base register Wb and the Borrow flag (Carry flag inverse. Store result to W1 Before Instruction W0 F310 W1 786A SR 0003 (Z. C=1) W0. Sub. Z.

Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 SUBBR. 2: The Z flag is “sticky” for ADDC. The ‘d’ bits select the address of the destination register. Note 1: The extension . [Ws--]. but it is not required. W15] (Ws) – (Wb) – (C) → Wd DC. Sub. Store result to W0 Before Instruction W0 1732 W1 7844 SR 0000 After Instruction W0 1711 W1 7844 SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. W15] Wd ∈ [W0 . C 0001 1www wBqq qddd dppp ssss Subtract the contents of the base register Wb and the Borrow flag (Carry flag inverse. OV. CPB. Register direct or indirect addressing may be used for Ws and Wd. W0 .B in the instruction denotes a byte operation rather than a word operation. SUBB and SUBBR. The ‘s’ bits select the address of the source register.. 1 for byte). W0 and C from W1 (Byte mode) . W15] Ws ∈ [W0 . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . [++Ws].. Instruction Descriptions SUBBR Syntax: {label:} Subtract Wb from Ws with Borrow SUBBR{.Section 5. Register direct addressing must be used for Wb. [Ws]...W extension to denote a word operation. The ‘q’ bits select the destination Address mode. [Ws++].. [--Ws]. N. C) from the contents of the source register Ws and place the result in the destination register Wd..B} Wb. These instructions can only clear Z. The ‘B’ bit selects byte or word operation (0 for word. You may use a . W1. Advance Information DS70030E-page 5-243 . Ws. The ‘p’ bits select the source Address mode. The ‘w’ bits select the address of the base register. Z.B W0.

[W9++] .[W8++].dsPIC30F Programmer’s Reference Manual Example 2 SUBBR W7. . . . W7 and C from [W8] (Word mode) Store result to [W9] Post-increment W8 Post-increment W9 Before Instruction W7 2450 W8 1808 W9 2022 Data 1808 92E4 Data 2022 A557 SR 0000 After Instruction W7 2450 W8 180A W9 2024 Data 1808 92E4 Data 2022 6E93 SR 0005 (OV. C=1) DS70030E-page 5-244 Advance Information  2003 Microchip Technology Inc. . Sub.

but it is not required. Sub.WREG} f ∈ [0 . 1 for file register). and place the result in the destination register.B 1 1 0x1FFF . 1 for byte). The ‘f’ bits select the address of the file register. Store result to 0x1FFF Before Instruction WREG (W0) 7804 Data 1FFE 9439 SR 0000 Example 2 SUBR After Instruction WREG (W0) 7804 Data 1FFE 7039 SR 0000 .W extension to denote a word operation.. 8191] (WREG) – (f) → destination designated by D DC. Z.. WREG Before Instruction WREG (W0) 6234 Data 0A04 6235 SR 0000 After Instruction WREG (W0) FFFF Data 0A04 6235 SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. If WREG is specified.Section 5. the result is stored in WREG. 2: The WREG is set to working register W0. (0xA04) from WREG (Word mode) . (0x1FFF) from WREG (Byte mode) . C 1011 1101 0BDf ffff ffff ffff Subtract the contents of the specified file register from the contents of the default working register WREG. Note 1: The extension . Instruction Descriptions SUBR Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Subtract f from WREG SUBR{. The optional WREG operand determines the destination register. You may use a . Sub.B in the instruction denotes a byte operation rather than a word operation. OV. Words: Cycles: Example 1 SUBR. The ‘D’ bit selects the destination (0 for WREG.B} f {. the result is stored in the file register The ‘B’ bit selects byte or word operation (0 for word. N. Advance Information DS70030E-page 5-245 . Store result to WREG 0xA04. If WREG is not specified.

Store result to W1 Before Instruction W0 F310 W1 786A SR 0000 Example 2 SUBR After Instruction W0 F310 W1 7800 SR 0103 (DC. C=1) ..dsPIC30F Programmer’s Reference Manual SUBR Syntax: {label:} Subtract Wb from Short Literal SUBR{.B} Wb.. Sub. W0 from 0x8 (Word mode) . . Store result to [W2] . N. The ‘q’ bits select the destination Address mode. The ‘k’ bits provide the literal operand. C 0001 0www wBqq qddd d11k kkkk Subtract the contents of the base register Wb from the unsigned 5-bit literal operand. OV. Sub. Either register direct or indirect addressing may be used for Wd. Post-increment W2 W0. 1 for byte). and place the result in the destination register Wd.. 31] Wd ∈ [W0 . The ‘B’ bit selects byte or word operation (0 for word.. [W2++] Before Instruction W0 0009 W2 2004 Data 2004 A557 SR 0000 After Instruction W0 0009 W2 2006 Data 2004 FFFF SR 0108 (DC. W15] lit5 – (Wb) → Wd DC. Z. W15] lit5 ∈ [0 . #lit5 Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . Register direct addressing must be used for Wb. N=1) DS70030E-page 5-246 Advance Information  2003 Microchip Technology Inc.B 1 1 W0. Note: The extension . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SUBR.W extension to denote a word operation. Z. The ‘d’ bits select the address of the destination register. W1 . W0 from 0x10 (Byte mode) . a five-bit integer number. #0x10. You may use a . The ‘w’ bits select the address of the base register.. #0x8. but it is not required..B in the instruction denotes a byte operation rather than a word operation.

W15] Ws ∈ [W0 . [Ws++]. OV. Ws. Note: The extension .B} Wb. C 0001 0www wBqq qddd dppp ssss Subtract the contents of the base register Wb from the contents of the source register Ws and place the result in the destination register Wd.. but it is not required. Register direct addressing must be used for Wb. [--Ws]. The ‘B’ bit selects byte or word operation (0 for word. The ‘q’ bits select the destination Address mode. Sub.B in the instruction denotes a byte operation rather than a word operation. You may use a . The ‘w’ bits select the address of the base register. The ‘d’ bits select the address of the destination register. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . W0 from W1 (Byte mode) . Instruction Descriptions SUBR Syntax: {label:} Subtract Wb from Ws SUBR{. W15] (Ws) – (Wb) → Wd DC.Section 5. Store result to W0 Before Instruction W0 1732 W1 7844 SR 0000 After Instruction W0 1712 W1 7844 SR 0001 (C=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. The ‘s’ bits select the address of the source register. W1. [Ws]. 1 for byte). W15] Wd ∈ [W0 .. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 SUBR.. Advance Information DS70030E-page 5-247 .. Either register direct or indirect addressing may be used for Ws and Wd.. Z..W extension to denote a word operation. W0 . The ‘p’ bits select the source Address mode. [++Ws]. [Ws--]. N.B 1 1 W0.

W7 from [W8] (Word mode) Store result to [W9] Post-increment W8 Post-increment W9 Before Instruction W7 2450 W8 1808 W9 2022 Data 1808 92E4 Data 2022 A557 SR 0000 After Instruction W7 2450 W8 180A W9 2024 Data 1808 92E4 Data 2022 6E94 SR 0005 (OV. . C=1) DS70030E-page 5-248 Advance Information  2003 Microchip Technology Inc. [W9++] . . [W8++]. Sub.dsPIC30F Programmer’s Reference Manual Example 2 SUBR W7. . .

The ‘s’ bits select the address of the working register.B in the instruction denotes a byte operation rather than a word operation. 1 for byte). In Byte mode. The ‘B’ bit selects byte or word operation (0 for word. and the Most Significant Byte of Wn is unchanged. Note: The extension . In Word mode. the two nibbles of the Least Significant Byte of Wn are swapped. Nibble swap (0x1021) Before Instruction Data 1020 AB87 SR 0000 Example 2 SWAP 0x1760 After Instruction Data 1020 BA87 SR 0000 . Status Affected: Encoding: Description: Words: Cycles: Example 1 SWAP. but it is not required.B} Wn Wn ∈ [W0 . W15] For byte operation: (Wn)<7:4> ↔ (Wn)<3:0> For word operation: (Wn)<15:8> ↔ (Wn)<7:0> None 1111 1101 1B00 0000 0000 ssss Swap the contents of the working register Wn.B 1 1 0x1021 . Byte swap (0x1760) Before Instruction Data 1760 8095 SR 0000 After Instruction Data 1760 9580 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.Section 5... Advance Information DS70030E-page 5-249 . Instruction Descriptions SWAP Syntax: Operands: Operation: {label:} Byte or Nibble Swap Wn SWAP{. Register direct addressing must be used for Wn.W extension to denote a word operation. the two bytes of Wn are swapped. You may use a .

but it is not required. Status Affected: Encoding: Description: Words: Cycles: 1 2 DS70030E-page 5-250 Advance Information  2003 Microchip Technology Inc. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 .(Ws)] <23:16> → Wd For word operation: Program Mem [(TBLPAG). The ‘p’ bits select the source Address mode. The ‘q’ bits select the destination Address mode. Note: The extension . the source address depends on the contents of Ws. with the effective address specified by Ws. [Ws++]. You may use a .. W15] Wd ∈ [W0 .. W15] For byte operation: If (LSB(Ws) = 1) 0 → Wd Else Program Mem [(TBLPAG). The ‘d’ bits select the address of the destination (data) register. [++Ws].W extension to denote a word move. In Byte mode. If Ws is not word aligned. 1 for byte). zero is stored to the Most Significant Byte of the destination register (due to non-existent program memory) and the third program memory byte (PM<23:16>) at the specified program memory address is stored to the Least Significant Byte of the destination register. The ‘B’ bit selects byte or word operation (0 for word. [--Ws]. [Ws--]. In Word mode. and either register direct or indirect addressing may be used for Wd.B in the instruction denotes a byte move rather than a word move. zero is stored to the destination register (due to non-existent program memory). Indirect addressing must be used for Ws. The target word address of program memory is formed by concatenating the 8-bit Table Pointer register.. . the third program memory byte (PM<23:16>) at the specified program memory address is stored to the destination register.B} [Ws].dsPIC30F Programmer’s Reference Manual TBLRDH Syntax: {label:} Table Read High TBLRDH{.. TBLPAG<7:0>. The ‘s’ bits select the address of the source (address) register. If Ws is word aligned.(Ws)] <23:16> → Wd <7:0> 0 → Wd <15:8> None 1011 1010 1Bqq qddd dppp ssss Read the contents of the Most Significant Word of program memory and store it to the destination register Wd.

Read PM (TBLPAG:[W6]) (Word mode) . W8 W6 W8 Program 00 3406 TBLPAG SR Before Instruction 3406 65B1 29 2E40 0000 0000 After Instruction W6 3408 W8 0029 Program 00 3406 29 2E40 TBLPAG 0000 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc.Section 5. Post-increment W1 W0 W1 Data 0F70 Program 01 0812 TBLPAG SR Example 2 Before Instruction 0812 0F71 0944 EF 2042 0001 0000 After Instruction W0 0812 W1 0F72 Data 0F70 EF44 Program 01 0812 EF 2042 TBLPAG 0001 SR 0000 . Instruction Descriptions Example 1 TBLRDH. Post-increment W6 TBLRDH [W6++]. Read PM (TBLPAG:[W0]) (Byte mode) .B [W0]. Store to W8 . Advance Information DS70030E-page 5-251 . Store to [W1] . [W1++] .

the first byte of the program memory word (PM<7:0>) is stored to the destination register. the second byte of the program memory word (PM<15:7>) is stored to the destination register.. Status Affected: Encoding: Description: Words: Cycles: 1 2 DS70030E-page 5-252 Advance Information  2003 Microchip Technology Inc. If Ws is not word aligned.. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 . The ‘q’ bits select the destination Address mode. The target word address of program memory is formed by concatenating the 8-bit Table Pointer register. W15] For byte operation: If (LSB(Ws) = 1) Program Mem [(TBLPAG). [Ws++]. The ‘B’ bit selects byte or word operation (0 for word mode.B} [Ws]. the source address depends on the contents of Ws. but it is not required. TBLPAG<7:0>. [Ws--]. and either register direct or indirect addressing may be used for Wd. Note: The extension . with the effective address specified by Ws. The ‘d’ bits select the address of the destination (data) register. In Word mode.(Ws)] <7:0> → Wd For word operation: Program Mem [(TBLPAG).B in the instruction denotes a byte move rather than a word move.W extension to denote a word move. In Byte mode. [--Ws]. The ‘s’ bits select the address of the source (address) register.. If Ws is word aligned. Indirect addressing must be used for Ws. W15] Wd ∈ [W0 .(Ws)] <15:0> → Wd None 1011 1010 0Bqq qddd dppp ssss Read the contents of the Least Significant Word of program memory and store it to the destination register Wd. 1 for byte).. [++Ws]. the lower 2 bytes of program memory are stored to the destination register. You may use a . . The ‘p’ bits select the source Address mode.dsPIC30F Programmer’s Reference Manual TBLRDL Syntax: {label:} Table Read Low TBLRDL{.(Ws)] <15:8> → Wd Else Program Mem [(TBLPAG).

Read PM (TBLPAG:[W6]) (Word mode) . Post-increment W0 W0 W1 Data 0F70 Program 01 0812 TBLPAG SR Example 2 Before Instruction 0813 0F71 0944 EF 2042 0001 0000 After Instruction W0 0814 W1 0F20 Data 0F70 EF44 Program 01 0812 EF 2042 TBLPAG 0001 SR 0000 .B [W0++].Section 5. Post-increment W8 TBLRDL [W6]. Advance Information DS70030E-page 5-253 . W1 . Instruction Descriptions Example 1 TBLRDL. Store to W1 . Store to W8 . [W8++] W6 W8 Data 1202 Program 00 3406 TBLPAG SR Before Instruction 3406 1202 658B 29 2E40 0000 0000 After Instruction W6 3408 W8 1204 Data 1202 2E40 Program 00 3406 29 2E40 TBLPAG 0000 SR 0000 5 Instruction Descriptions  2003 Microchip Technology Inc. Read PM (TBLPAG:[W0]) (Byte mode) .

1 for byte). The ‘d’ bits select the address of the destination (address) register. this instruction can only write to the upper byte of program memory (PM<23:16>). Since program memory is 24-bits wide.B} Ws. . [Ws]. The destination word address of program memory is formed by concatenating the 8-bit Table Pointer register.(Wd)]<23:16> For word operation: (Ws)<7:0> → Program Mem [(TBLPAG). The ‘p’ bits select the source Address mode.. but it is not required. with the effective address specified by Wd.dsPIC30F Programmer’s Reference Manual TBLWTH Syntax: {label:} Table Write High TBLWTH{. and indirect addressing must be used for Wd. [++Ws]. W15] For byte operation: If (LSB(Wd) = 1) NOP Else (Ws) → Program Mem [(TBLPAG). Either direct or indirect addressing may be used for Ws... The ‘s’ bits select the address of the source (data) register.W extension to denote a word move. The ‘q’ bits select the destination Address mode. W15] Wd ∈ [W0 . no operation is performed. You may use a . [Ws++]. The ‘B’ bit selects byte or word operation (0 for word. TBLPAG<7:0>. [--Ws].B in the instruction denotes a byte move rather than a word move. Note: The extension . [Ws--]. [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 . If Byte mode is used with a Wd that is not word aligned.. This may be performed using a Wd that is word aligned in Byte mode or Word mode.(Wd)] <23:16> None 1011 1011 1Bqq qddd dppp ssss Store the contents of the working source register Ws to the Most Significant Word of program memory. Status Affected: Encoding: Description: Words: Cycles: 1 2 DS70030E-page 5-254 Advance Information  2003 Microchip Technology Inc.

5 Instruction Descriptions  2003 Microchip Technology Inc... to PM Latch High (TBLPAG:[W1]) . Write [W0].. [W8++] . Write W6. Instruction Descriptions Example 1 TBLWTH. Post-increment W0 W0 W1 Data 0812 Program 01 0F70 TBLPAG SR Note: Before Instruction 0812 0F70 0944 EF 2042 0001 0000 After Instruction W0 0812 W1 0F70 Data 0812 EF44 Program 01 0F70 44 2042 TBLPAG 0001 SR 0000 Only the Program Latch is written to. [W1] . The contents of program memory are not updated until the FLASH memory is programmed using the procedure described in the dsPIC30F Family Reference Manual. to PM Latch High (TBLPAG:[W8]) . Post-increment W8 Example 2 TBLWTH W6 W8 Program 00 0870 TBLPAG SR Note: Before Instruction 0026 0870 22 3551 0000 0000 After Instruction W6 0026 W8 0872 Program 00 0870 26 3551 TBLPAG 0000 SR 0000 Only the Program Latch is written to.B [W0++]. (Byte mode) . The contents of program memory are not updated until the FLASH memory is programmed using the procedure described in the dsPIC30F Family Reference Manual.. (Word mode) . W6. Advance Information DS70030E-page 5-255 .Section 5.

and indirect addressing must be used for Wd. W15] Wd ∈ [W0 .. The ‘s’ bits select the address of the source (data) register.. Ws is stored to the second byte of program memory (PM<15:8>). [Ws]. If Wd is not word aligned. but it is not required. Note: The extension . You may use a . The ‘q’ bits select the destination Address mode. [--Ws]. In Byte mode.(Wd)] <7:0> For word operation: (Ws) → Program Mem [(TBLPAG).B in the instruction denotes a byte move rather than a word move. The ‘p’ bits select the source Address mode. the Least Significant bit of Wd determines the destination byte. Either direct or indirect addressing may be used for Ws. 1 for byte). . [Ws--]. with the effective address specified by Wd. Ws is stored to the first byte of program memory (PM<7:0>). [++Ws]. In Word mode.(Wd)] <15:0> None 1011 1011 0Bqq qddd dppp ssss Store the contents of the working source register Ws to the Least Significant Word of program memory. The destination word address of program memory is formed by concatenating the 8-bit Table Pointer register.. The ‘B’ bit selects byte or word operation (0 for word. Status Affected: Encoding: Description: Words: Cycles: 1 2 DS70030E-page 5-256 Advance Information  2003 Microchip Technology Inc.W extension to denote a word move. Ws is stored to the lower 2 bytes of program memory. If Wd is word aligned. TBLPAG<7:0>. W15] For byte operation: If (LSB(Wd)=1) (Ws) → Program Mem [(TBLPAG).. The ‘d’ bits select the address of the destination (address) register. [Ws++].dsPIC30F Programmer’s Reference Manual TBLWTL Syntax: {label:} Table Write Low TBLWTL{.B} Ws.(Wd)] <15:8> Else (Ws) → Program Mem [(TBLPAG). [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Operation: Ws ∈ [W0 .

[W8] . to PM Latch Low (TBLPAG:[W8]) . The contents of program memory are not updated until the FLASH memory is programmed using the procedure described in the dsPIC30F Family Reference Manual. Write W0. 5 Instruction Descriptions  2003 Microchip Technology Inc. to PM Latch Low (TBLPAG:[W1]) . Instruction Descriptions Example 1 TBLWTL... Post-increment W1 W0 W1 Program 00 1224 TBLPAG SR Note: Before Instruction 6628 1225 78 0080 0000 0000 After Instruction W0 6628 W1 1226 Program 01 1224 78 2880 TBLPAG 0000 SR 0000 Only the Program Latch is written to.B W0.Section 5. [W6]. (Byte mode) . Post-increment W8 Example 2 TBLWTL W6 W8 Data 1600 Program 01 7208 TBLPAG SR Note: Before Instruction 1600 7208 0130 09 0002 0001 0000 After Instruction W6 1600 W8 7208 Data 1600 0130 Program 01 7208 09 0130 TBLPAG 0001 SR 0000 Only the Program Latch is written to... (Word mode) . Advance Information DS70030E-page 5-257 . Write [W6]. The contents of program memory are not updated until the FLASH memory is programmed using the procedure described in the dsPIC30F Family Reference Manual. [W1++] .

1 1 ULNK . Unlink the stack frame Words: Cycles: Example 1 Before Instruction W14 2002 W15 20A2 Data 2000 2000 SR 0000 Example 2 ULNK After Instruction W14 2000 W15 2000 Data 2000 2000 SR 0000 . Unlink the stack frame Before Instruction W14 0802 W15 0812 Data 0800 0800 SR 0000 After Instruction W14 0800 W15 0800 Data 0800 0800 SR 0000 DS70030E-page 5-258 Advance Information  2003 Microchip Technology Inc. and then popping the stack to reset the frame pointer (W14). .dsPIC30F Programmer’s Reference Manual ULNK Syntax: Operands: Operation: {label:} None De-allocate Stack Frame ULNK W14 → W15 (W15)-2 → W15 (TOS) → W14 None 1111 1010 1000 0000 0000 0000 Status Affected: Encoding: Description: This instruction de-allocates a stack frame for a subroutine calling sequence. The stack frame is de-allocated by setting the stack pointer (W15) equal to the frame pointer (W14).

WREG} f ∈ [0 . If WREG is specified. 8191] (f). XOR (0x1FFF) and WREG (Byte mode) . Z 1011 0110 1BDf ffff ffff ffff Compute the logical exclusive OR operation of the contents of the default working register WREG and the contents of the specified file register and place the result in the destination register. If WREG is not specified. the result is stored in WREG.W extension to denote a word operation. 2: The WREG is set to working register W0.Section 5.B 1 1 0x1FFF . but it is not required.XOR. XOR (0xA04) and WREG (Word mode) . The ‘B’ bit selects byte or word operation (0 for word. Advance Information DS70030E-page 5-259 .(WREG) → destination designated by D N. The ‘D’ bit selects the destination (0 for WREG.. 1 for file register). The optional WREG operand determines the destination register.. Store result to WREG 0xA04. The ‘f’ bits select the address of the file register.B} f {. Words: Cycles: Example 1 XOR. the result is stored in the file register.B in the instruction denotes a byte operation rather than a word operation. WREG Before Instruction WREG (W0) 6234 Data 0A04 A053 SR 0000 After Instruction WREG (W0) C267 Data 0A04 A053 SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. 1 for byte). Note 1: The extension . You may use a . Instruction Descriptions XOR Syntax: Operands: Operation: Status Affected: Encoding: Description: {label:} Exclusive OR f and WREG XOR{. Store result to 0x1FFF Before Instruction WREG (W0) 7804 Data 1FFE 9439 SR 0000 Example 2 XOR After Instruction WREG (W0) 7804 Data 1FFE 9039 SR 0008 (N=1) .

XOR 0x23 and W0 (Byte mode) . You may use a . The ‘B’ bit selects byte or word operation (0 for word.B in the instruction denotes a byte operation rather than a word operation.. 255] for byte operation lit10 ∈ [0 . W15] lit10. the literal must be specified as an unsigned value [0:255].B 1 1 #0x23. 2: For byte operations..6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode. W4 After Instruction W0 7827 SR 0000 . See Section 4.. Store result to W4 Before Instruction W4 6134 SR 0000 After Instruction W4 603C SR 0000 DS70030E-page 5-260 Advance Information  2003 Microchip Technology Inc. XOR 0x108 and W4 (Word mode) . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 XOR. Z 1011 0010 1Bkk kkkk kkkk dddd Compute the logical exclusive OR operation of the unsigned 10-bit literal operand and the contents of the working register Wn and store the result back in the working register Wn. Store result to W0 Before Instruction W0 7804 SR 0000 Example 2 XOR #0x108.dsPIC30F Programmer’s Reference Manual XOR Syntax: Operands: {label:} Exclusive OR Literal and Wn XOR{. 1 for byte). Note 1: The extension . Register direct addressing must be used for Wn. W0 . The ‘k’ bits specify the literal operand. .(Wn) → Wn N. 1023] for word operation Wn ∈ [W0 . Wn lit10 ∈ [0 .B} #lit10. The ‘d’ bits select the address of the working register..W extension to denote a word operation.. but it is not required.XOR..

W5 . 31] Wd ∈ [W0 .lit5 → Wd N.B} Wb.. Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . The ‘B’ bit selects byte or word operation (0 for word. XOR W2 by 0x1F (Word mode) . but it is not required. W15] (Wb).B W4.Section 5.. Store result to W5 Before Instruction W4 C822 W5 1200 SR 0000 Example 2 XOR After Instruction W4 C822 W5 1234 SR 0000 . Z 0110 1www wBqq qddd d11k kkkk Compute the logical exclusive OR operation of the contents of the base register Wb and the unsigned 5-bit literal operand and place the result in the destination register Wd..B in the instruction denotes a byte operation rather than a word operation. Post-increment W8 W2. a 5-bit integer number... The ‘k’ bits provide the literal operand. You may use a .XOR. Store result to [W8] . The ‘q’ bits select the destination Address mode. Instruction Descriptions XOR Syntax: {label:} Exclusive OR Wb and Short Literal XOR{. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Wd. #lit5. XOR W4 and 0x14 (Byte mode) . 1 for byte). The ‘w’ bits select the address of the base register. #0x16. The ‘d’ bits select the address of the destination register. #0x1F.. Note: The extension . Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 XOR.W extension to denote a word operation. W15] lit5 ∈ [0 . [W8++] Before Instruction W2 8505 W8 1004 Data 1004 6628 SR 0000 After Instruction W2 8505 W8 1006 Data 1004 851A SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. Advance Information DS70030E-page 5-261 .

Either register direct or indirect addressing may be used for Ws and Wd.B in the instruction denotes a byte operation rather than a word operation. Operation: Status Affected: Encoding: Description: Words: Cycles: Example 1 1 1 XOR.B W1. [W9++] . The ‘s’ bits select the address of the source register.. The ‘q’ bits select the destination Address mode. and place the result in the destination register Wd.. Register direct addressing must be used for Wb. The ‘B’ bit selects byte or word operation (0 for word. [--Ws]. [Ws++]. You may use a .W extension to denote a word operation. but it is not required.. [W5++]. Post-increment W5 and W9 Before Instruction W1 AAAA W5 2000 W9 2600 Data 2000 115A Data 2600 0000 SR 0000 After Instruction W1 AAAA W5 2001 W9 2601 Data 2000 115A Data 2600 00F0 SR 0008 (N=1) DS70030E-page 5-262 Advance Information  2003 Microchip Technology Inc... Note: The extension . Wd [Wd] [Wd++] [Wd--] [++Wd] [--Wd] Operands: Wb ∈ [W0 . [Ws]. [++Ws]. The ‘p’ bits select the source Address mode. The ‘w’ bits select the address of the base register. . Z 0110 1www wBqq qddd dppp ssss Compute the logical exclusive OR operation of the contents of the source register Ws and the contents of the base register Wb. Ws. W15] Wd ∈ [W0 . [Ws--]. The ‘d’ bits select the address of the destination register. Store result to [W9] .(Ws) → Wd N.B} Wb. W15] (Wb). XOR W1 and [W5] (Byte mode) .dsPIC30F Programmer’s Reference Manual XOR Syntax: {label:} Exclusive OR Wb and Ws XOR{. 1 for byte).XOR.. W15] Ws ∈ [W0 .

W9 . Instruction Descriptions Example 2 XOR W1. Store the result to W9 Before Instruction W1 FEDC W5 1234 W9 A34D SR 0000 After Instruction W1 FEDC W5 1234 W9 ECE8 SR 0008 (N=1) 5 Instruction Descriptions  2003 Microchip Technology Inc. W5. Advance Information DS70030E-page 5-263 .Section 5. XOR W1 and W5 (Word mode) .

W15] Ws<7:0> → Wnd<7:0> 0 → Wnd<15:8> N. The ‘q’ bits select the destination Address mode. Post-increment W2 Before Instruction W2 0900 W12 1002 Data 0900 268F SR 0000 After Instruction W2 0901 W12 008F Data 0900 268F SR 0001 (C=1) DS70030E-page 5-264 Advance Information  2003 Microchip Technology Inc. The ‘s’ bits select the address of the source register. [++Ws]. Wnd Operands: Operation: Status Affected: Encoding: Description: Ws ∈ [W0 .B or . . so any address modification is by 1. W4 . because the zero-extended word is always positive. Zero-extend [W2] . [--Ws]. Note 1: This operation converts a byte to a word. C 1111 1011 10qq qddd dppp ssss Zero-extend the Least Significant Byte in source working register Ws to a 16-bit value and store the result in the destination working register Wnd. Words: Cycles: Example 1 ZE 1 1 W3.W extension. and it uses no . [Ws]..dsPIC30F Programmer’s Reference Manual ZE Syntax: {label:} Zero-Extend Wn ZE Ws. The N flag is cleared and the C flag is set. W12 After Instruction W3 7839 W4 0039 SR 0001 (C=1) . Either register direct or indirect addressing may be used for Ws... Store to W12 . The ‘d’ bits select the address of the destination register. 2: The source Ws is addressed as a byte operand. [Ws++]. and register direct addressing must be used for Wnd. zero-extend W3 . W15] Wnd ∈ [W0 . Store result to W4 Before Instruction W3 7839 W4 1005 SR 0000 Example 2 ZE [W2++]. Z. [Ws--]. The ‘p’ bits select the source Address mode..

...4 6..3 6.......................................................................................6 Reference Section 6..................... 6-3 Program Memory Map ................................. Reference HIGHLIGHTS This section of the manual contains reference information for the dsPIC30F............................................................................................2 6........................................................................................... 6-6 Instruction Bit Map ....1 6.......................... 6-7 Instruction Set Summary Table ............ Advance Information DS70030E-page 6-1 ................ It consists of the following sections: 6..... 6-2 Core Special Function Register Map ..............................................5 Data Memory Map ........... 6-9  2003 Microchip Technology Inc................................

The data space boundaries indicated here are for example purposes only. 2: Refer to Section 4. Refer to the appropriate device data sheet for further details. DS70030E-page 6-2 Advance Information  2003 Microchip Technology Inc. performing byte accesses and word alignment requirements. 3: Refer to the dsPIC30F MCU Family Reference Manual for information on accessing program memory through data address space. .dsPIC30F Programmer’s Reference Manual 6. Figure 6-1: Data Memory Map MS Byte Address MSB 0x0001 0x07FF 0x0801 Near RAM 0x17FF 0x1801 0x1FFF 0x27FF 0x2801 16-bits LSB SFR Space LS Byte Address 0x0000 0x07FE 0x0800 X Data RAM 0x17FE 0x1800 Y Data RAM 0x27FE 0x2800 0x8001 0x8000 X Data RAM Unimplemented Provides Program Space Visibility 0xFFFF 0xFFFE Note 1: The partition between the X and Y data spaces is device specific.1 Data Memory Map A sample dsPIC30F data memory map is shown in Figure 6-1. “Instruction Set Details” for information on Data Addressing modes.

Please refer to the dsPIC30F Data Sheet for complete register descriptions and the memory map of the remaining special function registers. Reference  2003 Microchip Technology Inc.Section 6. Reference 6 6. Advance Information DS70030E-page 6-3 .2 Core Special Function Register Map The Core Special Function Register Map is shown in Table 6-1.

Table 6-1: Bit 13 W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 SPLIM ACCAL ACCAH Sign-extension of ACCA<39> ACCBL ACCBH Sign-extension of ACCB<39> PCL — — — — — — — — — — — — — — — RCOUNT DCOUNT DOSTARTL — — — — — — — — DOENDL — — — — — — — — — DOENDH — DOSTARTH — — — — — — — PCH TBLPAG PSVPAG ACCBU ACCAU Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET State dsPIC30F Core Register Map 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 00xx xxxx xxxx xxxx xxxx xxxx 0000 0000 00xx xxxx Name Addr Bit 15 Bit 14 W0 0000 DS70030E-page 6-4 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 0016 W12 0018 W13 001A W14 001C W15 001E SPLIM 0020 ACCAL 0022 dsPIC30F Programmer’s Reference Manual Advance Information ACCAH 0024 ACCAU 0026 ACCBL 0028 ACCBH 002A ACCBU 002C PCL 002E PCH 0030 — TBLPAG 0032 — PSVPAG 0034 — RCOUNT 0036 DCOUNT 0038 DOSTARTL 003A DOSTARTH 003C — DOENDL 003E  2003 Microchip Technology Inc. DOENDH 0040 — .

YMODEND 004E XBREV 0050 BREN DISICNT 0052 — Reserved 0054 007E — Advance Information Section 6. Reference DS70030E-page 6-5 6 .Table 6-1: Bit 13 SA — — XMODSRT<15:0> XMODEND<15:0> YMODSRT<15:0> YMODEND<15:0> XBREV<14:0> — — — — — — — — — — — — — — DISICNT<13:0> — — — BWM<3:0> YWM<3:0> XWM<3:0> US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OB — dsPIC30F Core Register Map (Continued) RESET State 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 Name Addr Bit 15 Bit 14 SR 0042 OA CORCON 0044 — MODCON 0046 XMODEN YMODEN XMODSRT 0048 XMODEND 004A YMODSRT 004C Reference © 2003 Microchip Technology Inc.

GOTO Instruction RESET . Fail Trap Vector Stack Error Trap Vector Address Error Trap Vector Arithmetic Warn. Figure 6-2: Program Space Memory Map RESET . .3 Program Memory Map A sample dsPIC30F program memory map is shown in Figure 6-2. Trap Vector Software Trap Reserved Vector Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector 000000 000002 000004 000014 Vector Tables User Memory Space Interrupt 52 Vector Interrupt 53 Vector Alternate Vector Table User FLASH Program Memory (48K instructions) 00007E 000080 0000FE 000100 Reserved (Read 0’s) Data FLASH (4 Kbytes) 017FFE 018000 7FEFFE 7FF000 7FFFFE 800000 Reserved 8005BE 8005C0 8005FE 800600 UNITID Configuration Memory Space Reserved Fuse Configuration Registers F7FFFE F80000 F8000E F80010 Reserved FEFFFE FF0000 FFFFFE DEVID DS70030E-page 6-6 Advance Information  2003 Microchip Technology Inc.dsPIC30F Programmer’s Reference Manual 6.Target Address Osc.

This table contains the encoding for the Most Significant Byte of each instruction. the Most Significant Byte of the PUSH instruction (last row. and the first row of the table represents bits 19:16 of the opcode.4 Instruction Bit Map Instruction encoding for the dsPIC30F is summarized in Table 6-2. Note: The complete opcode for each instruction may be determined by the instruction descriptions in Section 5. Reference  2003 Microchip Technology Inc. The first byte of the opcode is formed by taking the first column bit value and appending the first row bit value. using Table 5. The first column in the table represents bits 23:20 of the opcode. Reference 6 6. ninth column) is encoded with 11111000b (0xF8).2 through Table 5-12.Section 6. Advance Information DS70030E-page 6-7 . “Instruction Descriptions”. For instance.

S DIV.R BTSS MOV.U INC INC2 PUSH DIVF DEC DEC2 POP — — BTSTS MUL SAC BSW SUB SUBB SAC.N MSC 1101 SL ASR LSR 1110 CP0 CP CPB  2003 Microchip Technology Inc.S PUSH.UU BTST BTSTS BTST BTSS BTSC BSET BCLR MUL.S RESET FBCL CLR SETM NOPR 0000 NOP BRA CALL GOTO RCALL 0001 0010 0011 BRA (OV) BRA (C) 0100 0101 0110 0111 1000 1001 1010 BSET BCLR 1011 ADD ADDC SUB SUBB dsPIC30F Programmer’s Reference Manual Advance Information 1100 MAC MPY MPY.SS MUL.N MSC SL — — — — — CPSGT CPSLT ASR LSR RLC RLNC RRC RRNC CPSEQ CPSNE — MOVSAC SFTAC IOR MOV ADD ADDC SUB SUBB AND XOR IOR MOV MUL.Table 6-2: 0010 CALL — GOTO RETLW RETFIE RETURN RCALL DO REPEAT BRA (OA) BRA (OB) BRA (SA) — — 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 BRA (SB) dsPIC30F Instruction Encoding bit 23 bit 19 0000 0001 DS70030E-page 6-8 SUBR MOV BRA (Z) ADD SUB AND IOR MOV MOV BTG AND XOR CLRAC MAC MPY MPY.US MUL.SU ADD BTG TBLRDH TBLRDL LAC BTST TBLWTH TBLWTL ADD NEG SUB DIV.D — BTSC MOV FF1L FF1R ADDC SUBB XOR MOV BRA (N) BRA (LE) BRA (LT) BRA (LEU) BRA BRA (NOV) BRA (NC) BRA (NZ) BRA (NN) BRA (GT) BRA (GE) BRA (GTU) — SUBBR RLC RLNC CP0 CP CPB RRC RRNC — SL COM NEG LNK ULNK CLR SETM SE ZE INC INC2 DISI DEC DEC2 DAW EXCH SWAP ASR LSR COM NEG CLRWDT PWRSAV POP. 1111 ED EDAC MAC MPY .

Section 6. description. execution time (in instruction cycles). affected status bits and the page number in which the detailed description can be found. It includes instruction assembly syntax. Table 1-2 identifies the symbols which are used in the Instruction Set Summary Table. size (in 24-bit words). Reference  2003 Microchip Technology Inc. Reference 6 6. Advance Information DS70030E-page 6-9 .5 Instruction Set Summary Table The complete dsPIC30F instruction set is summarized in Table 6-3. This table contains an alphabetized listing of the instruction set.

Wd ADD Wb.Wn AND Wb.Ws.Ws. but never cleared.#bit4 BRA Expr BRA Wn BRA C.#lit4. may be cleared.WREG} ASR Ws.Expr BRA LT. ‘1’ always set.Wd ADD Acc ADD Ws.Wd ASR Wb.Operands ADD f {. Wn Wd = Wb .WREG} ADD #lit10.AND.Wn ADDC Wb. lit5 Wd = Wb .Expr iÉÖÉåÇW set or cleared.Wd AND Wb.Wd AND f {.Expr BRA GTU.WREG} ADDC #lit10.Expr BRA N.AND.Wnd BCLR f.Expr BRA GEU.Expr BRA NC.  2003 Microchip Technology Inc. Ws Destination = arithmetic right shift f Wd = arithmetic right shift Ws Wnd = arithmetic right shift Wb by lit4 Wnd = arithmetic right shift Wb by Wns Bit clear f Bit clear Ws Branch unconditionally Computed branch Branch if Carry Branch if greater than or equal Branch if Carry Branch if greater than Branch if unsigned greater than Branch if less than or equal Branch if unsigned less than or equal Branch if less than Branch if not Carry Branch if Negative Branch if not Carry Branch if not Negative 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 2 1 1 1 1 — — — — — — — — — — — — — — — — 1 1 — — — — — — — — — — — — — — — — — — 1 1 — — 1 1 — — — — — — — — — — — — — — — — — — — — — 1 1 — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — unchanged 1 1 — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 — — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — 1 1 — — — — 1 1 — — — — — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — — — — — Words Cycles OA OB SA SB OAB SAB DC N OV Z C dsPIC30F Instruction Set Summary Table Page # 5-7 5-8 5-9 5-10 5-11 5-12 5-14 5-15 5-16 5-17 5-19 5-20 5-21 5-22 5-24 5-25 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 Assembly Syntax Mnemonic.Expr BRA GE.Expr BRA LE.Wd ADDC Wb.Wn DS70030E-page 6-10 may be set. ‘0’ always cleared.AND.#Slit4.Expr BRA NN.Table 6-3: Description Destination = f + WREG Wn = lit10 + Wn Wd = Wb + lit5 Wd = Wb + Ws Add accumulators 16-bit signed add to accumulator Destination = f + WREG + (C) Wn = lit10 + Wn + (C) Wd = Wb + lit5 + (C) Wd = Wb + Ws + (C) Destination = f . WREG Wn = lit10 .Wnd ASR Wb.AND.Acc ADDC f {.#lit5.WREG} AND #lit10.#lit5. but never set. SB and SAB are only modified if the corresponding saturation is enabled.Expr BRA GT.Wd ASR f {.Expr BRA LTU. .Expr BRA LEU. ADD Wb. otherwise unchanged.Wns.#lit5.Ws.#bit4 dsPIC30F Programmer’s Reference Manual Advance Information BCLR Ws. Note: SA.

6 .#bit4 BTG Ws. BRA SB.Wd iÉÖÉåÇW set or cleared.Expr BRA OB. 1 1 (2 or 3) — — 1 1 (2 or 3) — — — — — — — — — — — — — — — — — 0 — — — 1 1 (2 or 3) — — — 1 1 (2 or 3) — — — — — — — — — — — — — — — — — — — — 0 — — — — unchanged 1 1 — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — 0 — — — 1 1 — — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — 0 — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 (2) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 (2) — — — — — — — 1 1 (2) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 (2) — — — — — — — — 1 1 (2) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 (2) — — — — — — — — — 1 1 (2) — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 (2) — — — — — — — — — — Words Cycles OA OB SA SB OAB SAB DC N OV Z C — — — — — — — — — — — — — — — — — — — dsPIC30F Instruction Set Summary Table (Continued) Page # 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 5-55 5-56 5-56 5-58 5-59 5-60 5-62 5-64 5-65 5-67 5-68 5-68 5-69 5-69 5-71 5-72 5-72 5-73 5-74 5-75 5-75 5-76 5-77 5-79 5-80 5-81 Assembly Syntax Mnemonic.Wyd. but never cleared.Wx.#bit4 BTSC Ws. ‘0’ always cleared.Expr BRA Z.WREG} COM Ws.Operands BRA NOV.#bit4 Advance Information BTST.#bit4 BTSC f.#bit4 CALL Expr CALL Wn CLR f CLR WREG CLR Wd CLR Acc. may be cleared.#bit4 BTST.#bit4 BTST f.Z Ws.Expr BRA OV. skip if set Bit test f Bit test Ws to C Bit test Ws to Z Bit test Ws<Wb> to C Bit test Ws<Wb> to Z Bit test then set f Bit test Ws to C then set Bit test Ws to Z then set Call subroutine Call indirect subroutine f = 0x0000 WREG = 0x0000 Wd = 0 Clear Accumulator Clear Watchdog Timer Destination = f Wd = Ws 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 — — — — — — — — — — — 0 — — — 1 1 — 1 1 — — — — — — — — — — — — — — 0 — — — may be set.Wy. Section 6.C Ws.#bit4 BTSS f.Table 6-3: Description Branch if not Overflow Branch if not Zero Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch if Zero Bit set f Bit set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit toggle f Bit toggle Ws Bit test f.C Ws.Expr BRA NZ.#bit4 BTST.Wb BTG f.#bit4 BSET Ws. but never set.Expr BRA OA.C Ws.Wb BSW.Expr Reference © 2003 Microchip Technology Inc. skip if clear Bit test f.AWB CLRWDT COM f {.#bit4 BTSS Ws.Wxd.Z Ws.Expr BSET f.#bit4 BTSTS.Z Ws. Reference DS70030E-page 6-11 Note: SA.Wb BTSTS f. SB and SAB are only modified if the corresponding saturation is enabled. skip if set Bit test Ws. skip if clear Bit test Ws.Z Ws. otherwise unchanged.C Ws.#bit4 BSW. ‘1’ always set.Wb BTST.#bit4 BTSTS.Expr BRA SA.

skip if < Signed Compare (Wb with Wn). Wn CPSGT Wb.UD Wm.Wd DISI #lit14 DIV. SB and SAB are only modified if the corresponding saturation is enabled. but never cleared. ‘1’ always set. Wn DIVF Wm.Ws CP0 f CP0 Ws CPB f CPB Wb. skip if ≠ 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 2 1 18 18 2 2 1 1 1 1 1 1 2 2 — — — — — — — — — — — — — — — — — — — — — — — — — unchanged — — — — — — — — — — — — 18 18 — — — — — — 0 18 — 1 — — — — — — — — — 0 1 — — 1 — — — — — — — — — — — — — 1 — — — — — — — — — — — — — — — 1 — — — — 1 — — — — — — — — — — — — — — — — — 0 1 (2 or 3) — — — — — Wn = decimal adjust Wn Destination = f – 1 Wd = Ws – 1 Destination = f – 2 Wd = Ws – 2 Disable interrupts for lit14 instruction cycles Signed 16/16-bit integer divide Signed 32/16-bit integer divide Unsigned 16/16-bit integer divide Unsigned 32/16-bit integer divide Signed 16/16-bit fractional divide Do code to PC+Expr. . skip if > Signed Compare (Wb with Wn). Note: SA.Wy.Table 6-3: Description Compare (f – WREG) Compare (Wb – lit5) Compare (Wb – Ws) Compare (f – 0x0000) Compare (Ws – 0x0000) Compare with borrow (f – WREG – C) Compare with borrow (Wb – lit5 – C) Compare with borrow (Wb – Ws – C) Compare (Wb with Wn).Wx. Wn DIV.#lit5 DS70030E-page 6-12 may be set. but never set.  2003 Microchip Technology Inc. Wn DAW.Wd DEC2 f {.Wnd FF1L Ws. otherwise unchanged.Wxd EXCH Wns.S Wm.Wnd GOTO Expr GOTO Wn iÉÖÉåÇW set or cleared. Wn CPSNE Wb. ‘0’ always cleared.Wxd EDAC Wm*Wm.Wnd FBCL Ws. Wn dsPIC30F Programmer’s Reference Manual Advance Information DIV. skip if = Signed Compare (Wb with Wn). Wn DO #lit14.SD Wm. Expr ED Wm*Wm.Acc. Expr DO Wn.Ws CPSEQ Wb. CP Wb. (Wn+1) times Euclidean distance (no accumulate) Euclidean distance Swap Wns and Wnd Find bit change from left (MSb) side Find first one from left (MSb) side Find first one from right (LSb) side Go to address Go to address indirectly 1 1 (2 or 3) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0 0 — — — — 1 1 (2 or 3) — — — — — — 1 1 (2 or 3) — — — — — — — — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — — — — — Words Cycles OA OB SA SB OAB SAB DC N OV Z C dsPIC30F Instruction Set Summary Table (Continued) Page # 5-82 5-83 5-84 5-85 5-86 5-87 5-88 5-89 5-91 5-92 5-93 5-94 5-95 5-96 5-97 5-98 5-99 5-100 5-101 5-101 5-103 5-103 5-105 5-107 5-109 5-111 5-113 5-115 5-116 5-118 5-120 5-122 5-123 Assembly Syntax Mnemonic.Acc.Wnd FF1R Ws.WREG} DEC Ws.Operands CP f CP Wb.#lit5 CPB Wb. (lit14+1) times Do code to PC+Expr.Wy.Wx.B Wn DEC f {. may be cleared.WREG} DEC2 Ws. Wn DIV.U Wm. Wn CPSLT Wb.

Ws Load Accumulator Link frame pointer Destination = logical right shift f Wd = logical right shift Ws Wnd = logical right shift Wb by lit4 Wnd = logical right shift Wb by Wns Multiply and accumulate Square and accumulate Move f to destination Move WREG to f Move f to Wnd Move Wns to f Move 8-bit unsigned literal to Wnd Move 16-bit literal to Wnd Move [Wns + Slit10] to Wnd Move Wns to [Wnd + Slit10] Move Ws to Wd Move double Ws to Wnd:Wnd+1 Move double Wns:Wns+1 to Wd Move [Wx] to Wxd. but never cleared. Section 6.Ws. ‘1’ always set.Acc.Wnd} = sign(Wb) * sign(Ws) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 — — — — may be set.Wnd MOV.WREG} Reference © 2003 Microchip Technology Inc.Wd MOV.f MOV. 6 .Wnd LSR Wb.Wxd.Wy.Wx.WREG} INC Ws.Wnd MOV [Wns+Slit10]. lit5 Wd = Wb .AWB MUL f MUL. but never set.IOR.Wn IOR Wb.Wx. may be cleared.WREG} LSR Ws.Wns.f MOV f.#lit5.D Wns.Wxd.Acc. WREG Wn = lit10 .Wnd MAC Wm*Wn.WREG} MOV WREG.[Wnd+Slit10] MOV Ws.IOR.IOR.WREG} INC2 Ws.Wy.Wnd MOV Wns. MOV f {.Wd IOR Wb.Wy.Wd LSR Wb. Reference DS70030E-page 6-13 Note: SA. ‘0’ always cleared. Wn Wd = Wb . Acc LNK #lit14 LSR f {.Wy.Wyd.Wxd.Wxd.N Wm*Wn.SS Wb.Wnd iÉÖÉåÇW set or cleared.Wy. and [Wy] to Wyd Multiply Wn by Wm to accumulator Square to Accumulator -(Multiply Wn by Wm) to Accumulator Multiply and subtract from Accumulator W3:W2 = f * WREG {Wnd+1.Wyd MSC Wm*Wn.Acc.D Ws.Table 6-3: Description Destination = f + 1 Wd = Ws + 1 Destination = f + 2 Wd = Ws + 2 Destination = f .B #lit8.Wyd.Wxd.#Slit4.Wd MOVSAC Acc.Acc.Acc.Wx.Wx.IOR.Wd LAC Ws.AWB MAC Wm*Wm.Wx.Wd INC2 f {.Wy.AWB MPY Wm*Wn.Wnd Advance Information MOV Wns.Wyd.#lit4.Wxd. — — — — — unchanged — — — — 1 1 1 1 1 1 — — — — — — — — — — — 0 0 0 1 1 — — — — — — — — — — — — — 0 0 0 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0 0 0 — — — — — — — — — — — — — — — 1 1 1 1 — — — 1 1 — — — — — 1 1 — — — — 1 1 — — — — — — — — 1 1 — — — — — 1 1 — — — — — 1 1 — — — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 — — — — — — — 1 1 — — — — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — — — — — — Words Cycles OA OB SA SB OAB SAB DC N OV Z C dsPIC30F Instruction Set Summary Table (Continued) Page # 5-124 5-125 5-126 5-127 5-128 5-129 5-130 5-131 5-133 5-135 5-136 5-137 5-139 5-140 5-141 5-143 5-145 5-146 5-147 5-148 5-149 5-150 5-151 5-152 5-153 5-155 5-157 5-159 5-161 5-163 5-165 5-167 5-169 5-170 Assembly Syntax Mnemonic.Operands INC f {.Wx. otherwise unchanged.Wxd. SB and SAB are only modified if the corresponding saturation is enabled.Wx.Acc.Ws.Wyd. IOR #lit10.Wd IOR f {.Wyd MPY Wm*Wm.Wyd MPY.Wy.Wnd MOV #lit16.

Wnd MUL.Wnd} = sign(Wb) * unsign(lit5) {Wnd+1.#lit5.Ws.Wnd} = unsign(Wb) * sign(Ws) {Wnd+1. may be cleared.#lit5.Wd RRC f {.D Wns PUSH.Wd RLNC f {.UU Wb.UU Wb.S PWRSAV #lit1 RCALL Expr RCALL Wn dsPIC30F Programmer’s Reference Manual Advance Information REPEAT #lit14 REPEAT Wn RESET RETFIE RETLW #lit10.Wnd DS70030E-page 6-14 may be set. otherwise unchanged. iÉÖÉåÇW set or cleared.Wn RETURN RLC f {. Note: SA.WREG} RLNC Ws.Wd RRNC f {.Wnd NEG f {. ‘0’ always cleared.WREG} RRC Ws.Ws.D Wnd POP.SU Wb.Ws. MUL.Wd  2003 Microchip Technology Inc.Wnd MUL.WREG} RRNC Ws.Operands MUL. SB and SAB are only modified if the corresponding saturation is enabled.US Wb. but never set.SU Wb.Wnd} = unsign(Wb) * unsign(lit5) {Wnd+1. ‘1’ always set.WREG} RLC Ws.Table 6-3: Description {Wnd+1.Wnd MUL.Wnd} = unsign(Wb) * unsign(Ws) Destination = f + 1 Wd = Ws + 1 Negate Accumulator No operation No operation Pop TOS to f Pop TOS to Wd Pop double from TOS to Wnd:Wnd+1 Pop shadow registers Push f to TOS Push Ws to TOS Push double Wns:Wns+1 to TOS Push shadow registers Enter Power Saving mode Relative call Computed call Repeat next instruction (lit14+1) times Repeat next instruction (Wn+1) times Software device RESET Return from interrupt enable Return with lit10 in Wn Return from subroutine Destination = rotate left through Carry f Wd = rotate left through Carry Ws Destination = rotate left (no Carry) f Wd = rotate left (no Carry) Ws Destination = rotate right through Carry f Wd = rotate right through Carry Ws Destination = rotate right (no Carry) f Wd = rotate right (no Carry) Ws 1 1 1 1 1 1 1 1 1 1 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 — — — — — — — — — — — — — — 1 2 — 1 2 — — — — — — — — — — — — — — — — — 1 1 — — 1 1 — — — — — — — — — — — — — — — — — — — — 1 2 — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — unchanged 1 1 — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — 1 2 — — — — — 1 1 — — — — — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 — — — — — — 1 1 — — — — — — — — — — — 1 1 — 1 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 — — — — — — 1 1 — — — — — — — — — 1 1 — — — — — — — — — 1 1 — — — — — — — — — — — — 1 1 — — — — — — — — — — 1 1 — — — — — — — — — — — — — — — Words Cycles OA OB SA SB OAB SAB DC N OV Z C dsPIC30F Instruction Set Summary Table (Continued) Page # 5-172 5-174 5-176 5-178 5-179 5-181 5-182 5-183 5-184 5-185 5-186 5-187 5-188 5-189 5-190 5-191 5-192 5-193 5-194 5-195 5-196 5-197 5-198 5-200 5-201 5-202 5-203 5-204 5-205 5-207 5-208 5-210 5-211 5-213 5-214 Assembly Syntax Mnemonic.WREG} NEG Ws.S PUSH f PUSH Ws PUSH. . but never cleared.Wd NEG Acc NOP NOPR POP f POP Wd POP.Wnd} = sign(Wb) * unsign(Ws) {Wnd+1.

Wnd SUB f {.Wd SUBBR Wb. — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — unchanged — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — f = 0xFFFF WREG = 0xFFFF Ws = 0xFFFF Arithmetic shift accumulator by Slit6 Arithmetic shift accumulator by (Wn) Destination = arithmetic left shift f Wd = arithmetic left shift Ws Wnd = left shift Wb by lit4 Wnd = left shift Wb by Wns Destination = f – WREG Wn = Wn – lit10 Wd = Wb – lit5 Wd = Wb – Ws Subtract Accumulators destination = f – WREG – (C) Wn = Wn – lit10 – (C) Wd = Wb – lit5 – (C) Wd = Wb – Ws – (C) Destination = WREG – f – (C) Wd = lit5 – Wb – (C) 1 1 Wd = Ws – Wb – (C) Destination = WREG – f Wd = lit5 – Wb Wd = Ws – Wb Wn = byte or nibble swap Wn Read high program word to Wd Read low program word to Wd Write Ws to high program word Write Ws to low program word Unlink frame pointer 1 1 1 1 1 1 1 1 1 1 1 1 1 — — 1 1 — — — 1 1 — — — — 1 1 — — — — 1 1 — — — — 1 1 — — — — — 1 1 — — — — — — 1 1 — — — — — — 1 1 — 1 1 — 1 1 — — — — — — — 1 1 — — — — — — — 1 1 — — — — — — — 1 1 — — — — — — — 1 1 — — — — — — — — — — 1 1 — — — — — — — — — — Words Cycles OA OB SA SB OAB SAB DC N OV Z C — — dsPIC30F Instruction Set Summary Table (Continued) Page # 5-216 5-218 5-220 5-221 5-221 5-222 5-223 5-224 5-225 5-226 5-228 5-229 5-230 5-231 5-232 5-233 5-235 5-236 5-237 5-238 5-239 5-241 5-242 5-243 5-245 5-246 5-247 5-249 5-250 5-252 5-254 5-256 5-258 Assembly Syntax Mnemonic.Wd SE Ws.Wns.Wd SETM f SETM WREG SETM Ws Reference © 2003 Microchip Technology Inc. Reference DS70030E-page 6-15 Note: SA.WREG} SUBB #lit10.Wd TBLRDL Ws.WREG} SUBBR Wb. may be cleared.#Slit4.Wn Advance Information SUBB Wb.Operands SAC Acc. ‘1’ always set. Section 6.Wd SUB Wb.Wd SUBR f {.Ws. 6 .R Acc.Wd SUBR Wb.#lit5.Wd SWAP Wn TBLRDH Ws.#lit5.Wd SL Wb.#Slit6 SFTAC Acc.#lit5.Wnd SL Wb.Wn SUB Wb. SFTAC Acc. but never set.Ws.Wd SAC.WREG} SUB #lit10.WREG} SUBR Wb. otherwise unchanged.Wd SUBBR f {.Wd SUB Acc SUBB f {. SB and SAB are only modified if the corresponding saturation is enabled.Wn SL f {.Wd SUBB Wb. ‘0’ always cleared.#lit4.Ws.#lit5. but never cleared.Wd TBLWTL Ws.Ws.#Slit4.WREG} SL Ws.Wd TBLWTH Ws.Table 6-3: Description Store Accumulator Store rounded Accumulator Wd = sign-extended Ws — — — — — — — — — — — — — — — — — — — — — — — — — — 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — may be set.Wd ULNK iÉÖÉåÇW set or cleared.

Wn Wd = Wb .Table 6-3: Description Destination = f .XOR. .WREG} XOR #lit10.Wn DS70030E-page 6-16 XOR Wb. Ws Wd = zero-extended Ws may be set.Ws. Note: SA. WREG Wn = lit10 . dsPIC30F Programmer’s Reference Manual Advance Information  2003 Microchip Technology Inc.Operands XOR f {. — unchanged 1 1 — — — — — — — 1 1 — — — — — — — 1 1 — — — — — — — 1 1 — — — — — — — — 1 1 — — — — — — — — — — — — 1 Words Cycles OA OB SA SB OAB SAB DC N OV Z C dsPIC30F Instruction Set Summary Table (Continued) Page # 5-259 5-260 5-261 5-262 5-264 Assembly Syntax Mnemonic. SB and SAB are only modified if the corresponding saturation is enabled.#lit5.Wd iÉÖÉåÇW set or cleared. lit5 — — 0 — Wd = Wb . otherwise unchanged.Wd ZE Ws.XOR.XOR.Wd XOR Wb.XOR. ‘0’ always cleared. but never set. ‘1’ always set. may be cleared. but never cleared.

Skip if Clear) KKKKKKKKKKKKKKKKKKKKKKKKKKKK RJSO BTSS (Bit Test f.B (Bit Clear f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOV BRA (Branch Unconditionally) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJPN BRA (Computed Branch) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJPO BRA C (Branch if Carry) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJPP BRA GE (Branch if Signed Greater Than or Equal) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJPR BRA GEU (Branch if Unsigned Greater Than or Equal) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJPS BRA GT (Branch if Signed Greater Than) KKKKKKKKKKKKKKK RJPT BRA GTU (Branch if Unsigned Greater Than) KKKKKKKK RJPU BRA LE (Branch if Signed Less Than or Equal) KKKKKK RJPV BRA LEU (Branch if Unsigned Less Than or Equal) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJQM BRA LT (Branch if Signed Less Than) KKKKKKKKKKKKKKKKKKKK RJQN BRA LTU (Branch if Not Carry) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJQQ BRA LTU (Branch if Unsigned Less Than) KKKKKKKKKKKKKK RJQO BRA N (Branch if Negative) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJQP BRA NN (Branch if Not Negative)KKKKKKKKKKKKKKKKKKKKKKKKKKKK RJQR BRA NOV (Branch if Not Overflow) KKKKKKKKKKKKKKKKKKKKKKKKK RJQS BRA NZ (Branch if Not Zero) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJQT BRA OA (Branch if Overflow Accumulator A) KKKKKKKKKK RJQU BRA OB (Branch if Overflow Accumulator B) KKKKKKKKKK RJQV BRA OV (Branch if Overflow) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJRM BRA SA (Branch if Saturation Accumulator A) KKKKKKKK RJRN BRA SB (Branch if Saturation Accumulator B) KKKKKKKK RJRO BRA Z (Branch if Zero) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJRP BSET (Bit Set f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJRQ BSET (Bit Set in Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJRR BSW (Bit Write in Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJRS BTG (Bit Toggle f)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJRU BTG (Bit Toggle in Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJRV BTSC (Bit Test f. Skip if Clear) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJSM BTSC (Bit Test Ws. Accumulator B KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJR Accumulator Access KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPP Accumulator Usage KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPO Addressing Modes for Wd Destination Register KKKKKKKKKKKKKKKK RJP Addressing Modes for Ws Source Register KKKKKKKKKKKKKKKKKKKKKKK RJP Assigned Working Register Usage KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJOT I Immediate Addressing KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJV Operands in the Instruction Set KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJV Implied DSP Operands KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJOT Implied Frame and Stack Pointer KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJOT Instruction Bit Map KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SJT Instruction Description Example KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJS Instruction Descriptions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJT ADD (16-bit Signed Add to Accumulator) KKKKKKKKKKKKKKKK RJNO ADD (Add Accumulators) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNN ADD (Add f to WREG) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJT ADD (Add Literal to Wn) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJU ADD (Add Wb to Short Literal) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJV ADD (Add Wb to Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNM ADDC (Add f to WREG with Carry) KKKKKKKKKKKKKKKKKKKKKKKKK RJNQ ADDC (Add Literal to Wn with Carry) KKKKKKKKKKKKKKKKKKKKKK RJNR ADDC (Add Wb to Short Literal with Carry)KKKKKKKKKKKKK RJNS ADDC (Add Wb to Ws with Carry) KKKKKKKKKKKKKKKKKKKKKKKKKKK RJNT AND (AND f and WREG) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNV AND (AND Literal and Wd) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOM AND (AND Wb and Short Literal) KKKKKKKKKKKKKKKKKKKKKKKKKKKK RJON AND (AND Wb and Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOO ASR (Arithmetic Shift Right by Short Literal) KKKKKKKKKKK RJOT ASR (Arithmetic Shift Right by Wns) KKKKKKKKKKKKKKKKKKKKKKK RJOU ASR (Arithmetic Shift Right f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOQ ASR (Arithmetic Shift Right Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOR BCLR (Bit Clear in Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJPM BCLR. Advance Information DS70030E-page 1 . Skip if Set) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJSQ BTSS (Bit Test Ws.Index INDEX A Accumulator A. Skip if Set) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJSR BTST (Bit Test f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJST BTST (Bit Test in Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJSUI=RJSV B Byte Operations KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNP C Code Examples ‘Z’ Status bit Operation for 32-bit Addition KKKKKKKKKKKKKKK QJOS Base MAC Syntax KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPR File Register Addressing KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJP File Register Addressing and WREGKKKKKKKKKKKKKKKKKKKKKKKKK QJP Frame Pointer Usage KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJOP Illegal Word Move OperationsKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNU Immediate Addressing KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNM Indirect Addressing with Effective Address Update KKK QJS Indirect Addressing with Register Offset KKKKKKKKKKKKKKKKKKKK QJT Legal Word Move Operations KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNT MAC Accumulator WB Syntax KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPS MAC Pre-Fetch Syntax KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPR Move with Literal Offset Instructions KKKKKKKKKKKKKKKKKKKKKKKKKK QJT MSC Instruction with Two Pre-Fetches and Accumulator Write Back KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPS Normalizing with FBCL KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPV Register Direct Addressing KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJQ Sample Byte Math Operations KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNR Sample Byte Move Operations KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNQ Scaling with FBCLKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPU Stack Pointer Usage KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJON Unsigned f and WREG Multiply (Legacy MULWF Instruction) KKKKKKKKKKKKKKKKKKKKKKKKKKK QJOV Using 10-bit Literals for Byte Operands KKKKKKKKKKKKKKKKKKK QJNV Using the Default Working Register WREGKKKKKKKKKKKKK QJOU Conditional Branch Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJOR Core Control Register KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJV Core Special Function Register Map KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SJP Index D Data Addressing Mode Tree KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNM Data Addressing Modes KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJO Data Memory Map KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SJO DCOUNT Register KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJS Default Working Register (WREG) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJP Default Working Register WREG KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJOU Development Support KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJO DOEND Register KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJS DOSTART Register KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJS DSP Accumulator Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPT DSP Data Formats KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPM DSP MAC Indirect Addressing Modes KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJU DSP MAC Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPP dsPIC30F Overview KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJO F File Register Addressing KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJO  2003 Microchip Technology Inc.

dsPIC30F Programmer’s Reference Manual BTSTS (Bit Test/Set f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJTN BTSTS (Bit Test/Set in Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJTO CALL (Call Indirect Subroutine) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJTQ CALL (Call Subroutine) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJTP CLR (Clear Accumulator.SS (Integer 16x16-bit Signed Multiply)KKKKKKKKKK RJNTM MUL. Skip if Not Equal) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJVQ DAW. Set Status Flags) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJUV CPSEQ (Compare Wb with Wn.B (Decimal Adjust Wn) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJVR DEC (Decrement f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJVS DEC (Decrement Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJVT DEC2 (Decrement f by 2) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJVU DEC2 (Decrement Ws by 2) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJVV DISI (Disable Interrupts Temporarily) KKKKKKKKKKKKKKKKKKKKRJNMM DIV. Set Status Flags) KKKKKKKKKRJUQ CP0 (Compare f with 0x0. Set Status Flags) KKKKKKKKKKKRJUR CP0 (Compare Ws with 0x0.B (Move 8-bit Literal to Wnd) KKKKKKKKKKKKKKKKKKKKKKKK RJNQV MOV. No Accumulate) KKKKKKKKKKKKKRJNNN EDAC (Euclidean Distance) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNNP EXCH (Exchange Wns and Wnd) KKKKKKKKKKKKKKKKKKKKKKKKKKRJNNR FBCL (Find First Bit Change from Left) KKKKKKKKKKKKKKKKKRJNNS FF1L (Find First One from Left) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNNU FF1R (Find First One from Right) KKKKKKKKKKKKKKKKKKKKKKKKKKRJNOM GOTO (Unconditional Indirect Jump) KKKKKKKKKKKKKKKKKKKKKRJNOP GOTO (Unconditional Jump) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNOO INC (Increment f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNOQ INC (Increment Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNOR INC2 (Increment f by 2) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNOS INC2 (Increment Ws by 2) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNOT IOR (Inclusive OR f and WREG) KKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNOU IOR (Inclusive OR Literal and Wn) KKKKKKKKKKKKKKKKKKKKKKKKKRJNOV IOR (Inclusive OR Wb and Short Literal) KKKKKKKKKKKKKKKRJNPM IOR (Inclusive OR Wb and Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNPN LAC (Load Accumulator) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNPP LNK (Allocate Stack Frame) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNPR LSR (Logical Shift Right by Short Literal) KKKKKKKKKKKKKKRJNPV LSR (Logical Shift Right by Wns) KKKKKKKKKKKKKKKKKKKKKKKKKKKRJNQM LSR (Logical Shift Right f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNPS LSR (Logical Shift Right Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNPT MAC (Multiply and Accumulate) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNQN MAC (Square and Accumulate) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNQP MOV (Move 16-bit Literal to Wn) KKKKKKKKKKKKKKKKKKKKKKKKKKKRJNRM MOV (Move f to Destination) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNQR MOV (Move f to Wnd) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNQT MOV (Move Wns to [Wd with offset]) KKKKKKKKKKKKKKKKKKKKKRJNRO MOV (Move Wns to f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNQU MOV (Move WREG to f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNQS MOV (Move Ws to Wd) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNRP MOV (Move Ws with offset to Wnd)KKKKKKKKKKKKKKKKKKKKKKK RJNRN MOV.D (Double-Word Move from Wns to Destination) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNRT MOVSAC (Pre-Fetch Operands and Store Accumulator) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNRV MPY (Multiply Wm by Wn to Accumulator) KKKKKKKKKKKK RJNSN MPY (Square to Accumulator) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNSP MPY.N (Multiply -Wm by Wn to Accumulator) KKKKKKK RJNSR MSC (Multiply and Subtract from Accumulator)KKKKK RJNST MUL (Integer Unsigned Multiply f and WREG) KKKKKK RJNSV MUL. Set Status Flags) KKKKKKKKRJUO CP (Compare Wb with lit5.UU (Integer 16x16-bit Unsigned Short Literal Multiply) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNTU NEG (Negate Accumulator) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUP NEG (Negate f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUN NEG (Negate Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUO NOP (No Operation) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUQ NOPR (No Operation)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUR POP (Pop TOS to f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUS POP (Pop TOS to Wd)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUT POP. . Set Status Flags) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJUU CPB (Compare Ws with Wb using Borrow.S (Pop Shadow Registers) KKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUV PUSH (Push f to TOS) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNVM PUSH (Push Ws to TOS)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNVN PUSH.D (Double Push Wns/ tåëHN=íç=qlpFKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNVO PUSH.D (Double Pop TOS to Wnd/ tåÇHNF KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNUU POP.U (Unsigned Integer Divide) KKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNMP DIVF (Fractional Divide) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNMR DO (Initialize Hardware Loop Literal) KKKKKKKKKKKKKKKKKKKKKRJNMT DO (Initialize Hardware Loop Wn) KKKKKKKKKKKKKKKKKKKKKKKKKRJNMV ED (Euclidean Distance.UU (Integer 16x16-bit Unsigned Multiply) KKKKK RJNTV MUL. Pre-Fetch Operands) KKKKKKRJTT CLR (Clear f or WREG) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJTR CLR (Clear Wd) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJTS CLRWDT (Clear Watchdog Timer) KKKKKKKKKKKKKKKKKKKKKKKKKKRJTV COM (Complement f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJUM COM (Complement Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJUN CP (Compare f with WREG.US (Integer 16x16-bit Unsigned-Signed Multiply)KKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNTS MUL.S (Signed Integer Divide) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJNMN DIV.SU (Integer 16x16-bit Signed-Unsigned Short Literal Multiply) KKKKKKKK RJNTO MUL. Skip if Less Than) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJVP CPSNE (Signed Compare Wb with Wn.S (Push Shadow Registers)KKKKKKKKKKKKKKKKKKKKKKKK RJNVP PWRSAV (Enter Power Saving Mode) KKKKKKKKKKKKKKKKKK RJNVQ RCALL (Computed Relative Call) KKKKKKKKKKKKKKKKKKKKKKKKKK RJNVS RCALL (Relative Call)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNVR REPEAT (Repeat Next Instruction ‘lit14’ Times) KKK RJNVT REPEAT (Repeat Next Instruction Wn Times) KKKKKK RJNVU RESET (Reset) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOMM RETFIE (Return from Interrupt) KKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOMN RETLW (Return with Literal in Wn)KKKKKKKKKKKKKKKKKKKKKKKK RJOMO RETURN (Return)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOMP RLC (Rotate Left f through Carry)KKKKKKKKKKKKKKKKKKKKKKKKKK RJOMQ RLC (Rotate Left Ws through Carry) KKKKKKKKKKKKKKKKKKKKK RJOMR RLNC (Rotate Left f without Carry) KKKKKKKKKKKKKKKKKKKKKKKK RJOMT RLNC (Rotate Left Ws without Carry)KKKKKKKKKKKKKKKKKKKK RJOMU RRC (Rotate Right f through Carry)KKKKKKKKKKKKKKKKKKKKKKK RJONM RRC (Rotate Right Ws through Carry) KKKKKKKKKKKKKKKKKK RJONN RRNC (Rotate Right f without Carry) KKKKKKKKKKKKKKKKKKKKK RJONP RRNC (Rotate Right Ws without Carry)KKKKKKKKKKKKKKKKK RJONQ SAC (Store Accumulator) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJONS SAC.D (Double-Word Move from Source to Wnd) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNRR MOV. Set Status Flags) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJUT CPB (Compare Wb with lit5 using Borrow. Set Status Flags) KKKKKKKKKKRJUP CP (Compare Wb with Ws. Skip if Equal) KKKKKKKKRJVN CPSGT (Signed Compare Wb with Wn. Skip if Greater Than)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKRJVO CPSLT (Signed Compare Wb with Wn.SU (Integer 16x16-bit Signed-Unsigned Multiply)KKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJNTQ MUL. Set Status Flags) KKKKKKKRJUS CPB (Compare f with WREG using Borrow.R (Store Rounded Accumulator) KKKKKKKKKKKKKKKKKKK RJONU SE (Sign-Extend Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOOM SETM (Set f or WREG)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOON SETM (Set Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOOO SFTAC (Arithmetic Shift Accumulator by Slit6)KKKKKK RJOOP SFTAC (Arithmetic Shift Accumulator by Wb) KKKKKKK RJOOQ SL (Shift Left by Short Literal)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOOU SL (Shift Left by Wns) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOOV DS70030E-page 2 Advance Information  2003 Microchip Technology Inc.

Index SL (Shift Left f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOOR SL (Shift Left Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOOS SUB (Subtract Accumulators) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOPR SUB (Subtract Literal from Wn) KKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOPN SUB (Subtract Short Literal from Wb) KKKKKKKKKKKKKKKKKKKK RJOPO SUB (Subtract WREG from f) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOPM SUB (Subtract Ws from Wb) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOPP SUBB (Subtract Short Literal from Wb with Borrow) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOPU SUBB (Subtract Wn from Literal with Borrow) KKKKKKK RJOPT SUBB (Subtract WREG and Carry bit from f) KKKKKKKK RJOPS SUBB (Subtract Ws from Wb with Borrow) KKKKKKKKKKKK RJOPV SUBBR (Subtract f from WREG with Borrow)KKKKKKKK RJOQN SUBBR (Subtract Wb from Short Literal with Borrow) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOQO SUBBR (Subtract Wb from Ws with Borrow) KKKKKKKKK RJOQP SUBR (Subtract f from WREG) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOQR SUBR (Subtract Wb from Short Literal) KKKKKKKKKKKKKKKKK RJOQS SUBR (Subtract Wb from Ws) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOQT SWAP (Byte or Nibble Swap Wn) KKKKKKKKKKKKKKKKKKKKKKKKKK RJOQV TBLRDH (Table Read High) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJORM TBLRDL (Table Read Low)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJORO TBLWTH (Table Write High) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJORQ TBLWTL (Table Write Low) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJORS ULNK (De-allocate Stack Frame) KKKKKKKKKKKKKKKKKKKKKKKKKK RJORU XOR (Exclusive OR f and WREG) KKKKKKKKKKKKKKKKKKKKKKKKK RJORV XOR (Exclusive OR Literal and Wn) KKKKKKKKKKKKKKKKKKKKKK RJOSM XOR (Exclusive OR Wb and Short Literal) KKKKKKKKKKKK RJOSN XOR (Exclusive OR Wb and Ws)KKKKKKKKKKKKKKKKKKKKKKKKKKK RJOSO ZE (Zero-Extend Wn) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJOSQ Instruction Encoding Field Descriptors Introduction KKKKKKKKKKK RJO Instruction Set Overview KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJO Bit Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJT Compare/Skip Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJU Control Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJNM DSP Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJNM dsPIC30F Instruction GroupsKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJO Logic Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJR Math InstructionsKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJQ Move Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJP Program Flow Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJV Rotate/Shift Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJS Shadow/Stack InstructionsKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJNM Instruction Set Summary Table KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SJV Instruction Set Symbols KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ #text KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ (text) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ <n:m> KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ [text] KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ { }KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ {label:} KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Acc KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ AWB KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ bit4 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ ExprKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ f KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ lit1 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ lit10 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ lit14 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ lit16 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ lit23 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ lit4 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ lit5 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ lit8 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Slit10 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Slit16 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Slit4 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Slit5KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ TOS KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wb KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wd KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wm*Wm KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wm*Wn KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wm. Advance Information DS70030E-page 3 . Wn KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wn KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wnd KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wns KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ WREG KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Ws KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wx KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wxd KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wy KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Wyd KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJQ Instruction Stalls KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNO DO/REPEAT Loops KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNP Exceptions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNP Instructions that Change Program Flow KKKKKKKKKKKKKKKKKK QJNP PSV KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNP RAW Dependency Detection KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNO Instruction Symbols KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJO Integer and Fractional Data KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPM Representation KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPN Interrupt Priority LevelKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJU Introduction KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJO Index M MAC Operations KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPQ Pre-Fetch Register Updates KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPQ Pre-Fetches KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPP SyntaxKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPQ Write Back KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPQ MAC Accumulator Write Back SelectionKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJR MAC or MPY Source Operands (Different Working Register) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJR MAC or MPY Source Operands (Same Working Register) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJR Manual Objective KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJO Microchip Documentation KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJR Modulo and Bit-Reversed Addressing Modes KKKKKKKKKKKKKKKKKKK QJU Multi-Cycle InstructionsKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJO Multi-Word Instructions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK PJP N Normalizing the Accumulator with the FBCL Instruction KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJPV O Offset Addressing Modes for Wd Destination Register (with Register Offset) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJP Offset Addressing Modes for Ws Source Register (with Register Offset) KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJP P PICmicro® Microcontroller Compatibility KKKKKKKKKKKKKKKKKKKKKKKKK QJOU PRODH PRODL Register Pair KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJOU Program Addressing Modes KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNN Methods of Modifying Flow KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNN Program Counter KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJR Program Memory Map KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SJS  2003 Microchip Technology Inc.

.dsPIC30F Programmer’s Reference Manual Programmer’s Model KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJP Diagram KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJQ Register Descriptions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJP PSVPAG Register KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJR T TBLPAG Register KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJR Third Party Documentation KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK NJR R RCOUNT Register KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJS Register Direct Addressing KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJQ Register Indirect Addressing KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJR Modes KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJR Register Indirect Addressing and the Instruction Set KKKKKKKKKQJU Registers CORCON (Core Control) Register KKKKKKKKKKKKKKKKKKKKKKKKKKKOJNO SR (Status) Register KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJNM Related DocumentsKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKNJR U Using 10-bit Literal Operands KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNV 10-bit Literal CodingKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNV W Word Move Operations KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNS Data Alignment in Memory KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJNS Working Register ArrayKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK OJP X X Data Space Pre-Fetch Destination KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJQ X Data Space Pre-Fetch Operation KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJQ S Scaling Data with the FBCL InstructionKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJPT Scaling Examples KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJPU Shadow Registers KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJV Automatic Usage KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJV Software Stack Frame Pointer KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJPI=QJOO Example KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJOP Overflow KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJOQ Underflow KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJOQ Software Stack PointerKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJRI=QJOM Example KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKQJON Stack Pointer Limit Register (SPLIM)KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJR Status RegisterKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJT DSP ALU Status Bits KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJU Loop Status Bits KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJT MCU ALU Status Bits KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKOJT Style and Symbol Conventions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKNJP Document Conventions KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKNJP Y Y Data Space Pre-Fetch Destination KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJR Y Data Space Pre-Fetch Operation KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK RJQ Z Z Status Bit KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK QJOS DS70030E-page 4 Advance Information  2003 Microchip Technology Inc.

Index NOTES: Index  2003 Microchip Technology Inc. Advance Information DS70030E-page 5 .

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